TargetLowering.cpp revision 5f0c658aa40c6d1475f7c9daa72497362fbee216
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetMachine.h" 16#include "llvm/Target/MRegisterInfo.h" 17#include "llvm/CodeGen/SelectionDAG.h" 18#include "llvm/ADT/StringExtras.h" 19#include "llvm/Support/MathExtras.h" 20using namespace llvm; 21 22TargetLowering::TargetLowering(TargetMachine &tm) 23 : TM(tm), TD(TM.getTargetData()) { 24 assert(ISD::BUILTIN_OP_END <= 128 && 25 "Fixed size array in TargetLowering is not large enough!"); 26 // All operations default to being supported. 27 memset(OpActions, 0, sizeof(OpActions)); 28 29 IsLittleEndian = TD.isLittleEndian(); 30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType()); 31 ShiftAmtHandling = Undefined; 32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 33 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 34 allowUnalignedMemoryAccesses = false; 35 UseUnderscoreSetJmpLongJmp = false; 36 IntDivIsCheap = false; 37 Pow2DivIsCheap = false; 38 StackPointerRegisterToSaveRestore = 0; 39 SchedPreferenceInfo = SchedulingForLatency; 40} 41 42TargetLowering::~TargetLowering() {} 43 44/// setValueTypeAction - Set the action for a particular value type. This 45/// assumes an action has not already been set for this value type. 46static void SetValueTypeAction(MVT::ValueType VT, 47 TargetLowering::LegalizeAction Action, 48 TargetLowering &TLI, 49 MVT::ValueType *TransformToType, 50 TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 51 ValueTypeActions.setTypeAction(VT, Action); 52 if (Action == TargetLowering::Promote) { 53 MVT::ValueType PromoteTo; 54 if (VT == MVT::f32) 55 PromoteTo = MVT::f64; 56 else { 57 unsigned LargerReg = VT+1; 58 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 59 ++LargerReg; 60 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 61 "Nothing to promote to??"); 62 } 63 PromoteTo = (MVT::ValueType)LargerReg; 64 } 65 66 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 67 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 68 "Can only promote from int->int or fp->fp!"); 69 assert(VT < PromoteTo && "Must promote to a larger type!"); 70 TransformToType[VT] = PromoteTo; 71 } else if (Action == TargetLowering::Expand) { 72 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 73 "Cannot expand this type: target must support SOME integer reg!"); 74 // Expand to the next smaller integer type! 75 TransformToType[VT] = (MVT::ValueType)(VT-1); 76 } 77} 78 79 80/// computeRegisterProperties - Once all of the register classes are added, 81/// this allows us to compute derived properties we expose. 82void TargetLowering::computeRegisterProperties() { 83 assert(MVT::LAST_VALUETYPE <= 32 && 84 "Too many value types for ValueTypeActions to hold!"); 85 86 // Everything defaults to one. 87 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 88 NumElementsForVT[i] = 1; 89 90 // Find the largest integer register class. 91 unsigned LargestIntReg = MVT::i128; 92 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 93 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 94 95 // Every integer value type larger than this largest register takes twice as 96 // many registers to represent as the previous ValueType. 97 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 98 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 99 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 100 101 // Inspect all of the ValueType's possible, deciding how to process them. 102 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 103 // If we are expanding this type, expand it! 104 if (getNumElements((MVT::ValueType)IntReg) != 1) 105 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 106 ValueTypeActions); 107 else if (!isTypeLegal((MVT::ValueType)IntReg)) 108 // Otherwise, if we don't have native support, we must promote to a 109 // larger type. 110 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 111 TransformToType, ValueTypeActions); 112 else 113 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 114 115 // If the target does not have native support for F32, promote it to F64. 116 if (!isTypeLegal(MVT::f32)) 117 SetValueTypeAction(MVT::f32, Promote, *this, 118 TransformToType, ValueTypeActions); 119 else 120 TransformToType[MVT::f32] = MVT::f32; 121 122 // Set MVT::Vector to always be Expanded 123 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 124 ValueTypeActions); 125 126 assert(isTypeLegal(MVT::f64) && "Target does not support FP?"); 127 TransformToType[MVT::f64] = MVT::f64; 128} 129 130const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 131 return NULL; 132} 133 134//===----------------------------------------------------------------------===// 135// Optimization Methods 136//===----------------------------------------------------------------------===// 137 138/// ShrinkDemandedConstant - Check to see if the specified operand of the 139/// specified instruction is a constant integer. If so, check to see if there 140/// are any bits set in the constant that are not demanded. If so, shrink the 141/// constant and return true. 142bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 143 uint64_t Demanded) { 144 // FIXME: ISD::SELECT, ISD::SELECT_CC 145 switch(Op.getOpcode()) { 146 default: break; 147 case ISD::AND: 148 case ISD::OR: 149 case ISD::XOR: 150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 151 if ((~Demanded & C->getValue()) != 0) { 152 MVT::ValueType VT = Op.getValueType(); 153 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 154 DAG.getConstant(Demanded & C->getValue(), 155 VT)); 156 return CombineTo(Op, New); 157 } 158 break; 159 } 160 return false; 161} 162 163/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 164/// DemandedMask bits of the result of Op are ever used downstream. If we can 165/// use this information to simplify Op, create a new simplified DAG node and 166/// return true, returning the original and new nodes in Old and New. Otherwise, 167/// analyze the expression and return a mask of KnownOne and KnownZero bits for 168/// the expression (used to simplify the caller). The KnownZero/One bits may 169/// only be accurate for those bits in the DemandedMask. 170bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 171 uint64_t &KnownZero, 172 uint64_t &KnownOne, 173 TargetLoweringOpt &TLO, 174 unsigned Depth) const { 175 KnownZero = KnownOne = 0; // Don't know anything. 176 // Other users may use these bits. 177 if (!Op.Val->hasOneUse()) { 178 if (Depth != 0) { 179 // If not at the root, Just compute the KnownZero/KnownOne bits to 180 // simplify things downstream. 181 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 182 return false; 183 } 184 // If this is the root being simplified, allow it to have multiple uses, 185 // just set the DemandedMask to all bits. 186 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 187 } else if (DemandedMask == 0) { 188 // Not demanding any bits from Op. 189 if (Op.getOpcode() != ISD::UNDEF) 190 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 191 return false; 192 } else if (Depth == 6) { // Limit search depth. 193 return false; 194 } 195 196 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 197 switch (Op.getOpcode()) { 198 case ISD::Constant: 199 // We know all of the bits for a constant! 200 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 201 KnownZero = ~KnownOne & DemandedMask; 202 return false; // Don't fall through, will infinitely loop. 203 case ISD::AND: 204 // If either the LHS or the RHS are Zero, the result is zero. 205 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 206 KnownOne, TLO, Depth+1)) 207 return true; 208 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 209 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 210 KnownZero2, KnownOne2, TLO, Depth+1)) 211 return true; 212 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 213 214 // If all of the demanded bits are known one on one side, return the other. 215 // These bits cannot contribute to the result of the 'and'. 216 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 217 return TLO.CombineTo(Op, Op.getOperand(0)); 218 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 219 return TLO.CombineTo(Op, Op.getOperand(1)); 220 // If all of the demanded bits in the inputs are known zeros, return zero. 221 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 222 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 223 // If the RHS is a constant, see if we can simplify it. 224 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 225 return true; 226 227 // If the RHS is a constant, check to see if the LHS would be zero without 228 // using the bits from the RHS. Above, we used knowledge about the RHS to 229 // simplify the LHS, here we're using information from the LHS to simplify 230 // the RHS. 231 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 232 uint64_t LHSZero, LHSOne; 233 ComputeMaskedBits(Op.getOperand(0), DemandedMask, 234 LHSZero, LHSOne, Depth+1); 235 // If the LHS already has zeros where RHSC does, this and is dead. 236 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 237 return TLO.CombineTo(Op, Op.getOperand(0)); 238 // If any of the set bits in the RHS are known zero on the LHS, shrink 239 // the constant. 240 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 241 return true; 242 } 243 244 // Output known-1 bits are only known if set in both the LHS & RHS. 245 KnownOne &= KnownOne2; 246 // Output known-0 are known to be clear if zero in either the LHS | RHS. 247 KnownZero |= KnownZero2; 248 break; 249 case ISD::OR: 250 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 251 KnownOne, TLO, Depth+1)) 252 return true; 253 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 254 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 255 KnownZero2, KnownOne2, TLO, Depth+1)) 256 return true; 257 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 258 259 // If all of the demanded bits are known zero on one side, return the other. 260 // These bits cannot contribute to the result of the 'or'. 261 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 262 return TLO.CombineTo(Op, Op.getOperand(0)); 263 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 264 return TLO.CombineTo(Op, Op.getOperand(1)); 265 // If all of the potentially set bits on one side are known to be set on 266 // the other side, just use the 'other' side. 267 if ((DemandedMask & (~KnownZero) & KnownOne2) == 268 (DemandedMask & (~KnownZero))) 269 return TLO.CombineTo(Op, Op.getOperand(0)); 270 if ((DemandedMask & (~KnownZero2) & KnownOne) == 271 (DemandedMask & (~KnownZero2))) 272 return TLO.CombineTo(Op, Op.getOperand(1)); 273 // If the RHS is a constant, see if we can simplify it. 274 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 275 return true; 276 277 // Output known-0 bits are only known if clear in both the LHS & RHS. 278 KnownZero &= KnownZero2; 279 // Output known-1 are known to be set if set in either the LHS | RHS. 280 KnownOne |= KnownOne2; 281 break; 282 case ISD::XOR: 283 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 284 KnownOne, TLO, Depth+1)) 285 return true; 286 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 287 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 288 KnownOne2, TLO, Depth+1)) 289 return true; 290 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 291 292 // If all of the demanded bits are known zero on one side, return the other. 293 // These bits cannot contribute to the result of the 'xor'. 294 if ((DemandedMask & KnownZero) == DemandedMask) 295 return TLO.CombineTo(Op, Op.getOperand(0)); 296 if ((DemandedMask & KnownZero2) == DemandedMask) 297 return TLO.CombineTo(Op, Op.getOperand(1)); 298 299 // Output known-0 bits are known if clear or set in both the LHS & RHS. 300 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 301 // Output known-1 are known to be set if set in only one of the LHS, RHS. 302 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 303 304 // If all of the unknown bits are known to be zero on one side or the other 305 // (but not both) turn this into an *inclusive* or. 306 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 307 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut)) 308 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits) 309 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 310 Op.getOperand(0), 311 Op.getOperand(1))); 312 // If all of the demanded bits on one side are known, and all of the set 313 // bits on that side are also known to be set on the other side, turn this 314 // into an AND, as we know the bits will be cleared. 315 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 316 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 317 if ((KnownOne & KnownOne2) == KnownOne) { 318 MVT::ValueType VT = Op.getValueType(); 319 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 320 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 321 ANDC)); 322 } 323 } 324 325 // If the RHS is a constant, see if we can simplify it. 326 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 327 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 328 return true; 329 330 KnownZero = KnownZeroOut; 331 KnownOne = KnownOneOut; 332 break; 333 case ISD::SETCC: 334 // If we know the result of a setcc has the top bits zero, use this info. 335 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 336 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 337 break; 338 case ISD::SELECT: 339 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 340 KnownOne, TLO, Depth+1)) 341 return true; 342 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 343 KnownOne2, TLO, Depth+1)) 344 return true; 345 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 346 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 347 348 // If the operands are constants, see if we can simplify them. 349 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 350 return true; 351 352 // Only known if known in both the LHS and RHS. 353 KnownOne &= KnownOne2; 354 KnownZero &= KnownZero2; 355 break; 356 case ISD::SELECT_CC: 357 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 358 KnownOne, TLO, Depth+1)) 359 return true; 360 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 361 KnownOne2, TLO, Depth+1)) 362 return true; 363 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 364 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 365 366 // If the operands are constants, see if we can simplify them. 367 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 368 return true; 369 370 // Only known if known in both the LHS and RHS. 371 KnownOne &= KnownOne2; 372 KnownZero &= KnownZero2; 373 break; 374 case ISD::SHL: 375 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 376 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 377 KnownZero, KnownOne, TLO, Depth+1)) 378 return true; 379 KnownZero <<= SA->getValue(); 380 KnownOne <<= SA->getValue(); 381 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 382 } 383 break; 384 case ISD::SRL: 385 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 386 MVT::ValueType VT = Op.getValueType(); 387 unsigned ShAmt = SA->getValue(); 388 389 // Compute the new bits that are at the top now. 390 uint64_t HighBits = (1ULL << ShAmt)-1; 391 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 392 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 393 394 if (SimplifyDemandedBits(Op.getOperand(0), 395 (DemandedMask << ShAmt) & TypeMask, 396 KnownZero, KnownOne, TLO, Depth+1)) 397 return true; 398 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 399 KnownZero &= TypeMask; 400 KnownOne &= TypeMask; 401 KnownZero >>= ShAmt; 402 KnownOne >>= ShAmt; 403 KnownZero |= HighBits; // high bits known zero. 404 } 405 break; 406 case ISD::SRA: 407 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 408 MVT::ValueType VT = Op.getValueType(); 409 unsigned ShAmt = SA->getValue(); 410 411 // Compute the new bits that are at the top now. 412 uint64_t HighBits = (1ULL << ShAmt)-1; 413 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 414 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 415 416 if (SimplifyDemandedBits(Op.getOperand(0), 417 (DemandedMask << ShAmt) & TypeMask, 418 KnownZero, KnownOne, TLO, Depth+1)) 419 return true; 420 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 421 KnownZero &= TypeMask; 422 KnownOne &= TypeMask; 423 KnownZero >>= SA->getValue(); 424 KnownOne >>= SA->getValue(); 425 426 // Handle the sign bits. 427 uint64_t SignBit = MVT::getIntVTSignBit(VT); 428 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 429 430 // If the input sign bit is known to be zero, or if none of the top bits 431 // are demanded, turn this into an unsigned shift right. 432 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 433 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 434 Op.getOperand(1))); 435 } else if (KnownOne & SignBit) { // New bits are known one. 436 KnownOne |= HighBits; 437 } 438 } 439 break; 440 case ISD::SIGN_EXTEND_INREG: { 441 MVT::ValueType VT = Op.getValueType(); 442 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 443 444 // Sign extension. Compute the demanded bits in the result that are not 445 // present in the input. 446 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 447 448 // If none of the extended bits are demanded, eliminate the sextinreg. 449 if (NewBits == 0) 450 return TLO.CombineTo(Op, Op.getOperand(0)); 451 452 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 453 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 454 455 // Since the sign extended bits are demanded, we know that the sign 456 // bit is demanded. 457 InputDemandedBits |= InSignBit; 458 459 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 460 KnownZero, KnownOne, TLO, Depth+1)) 461 return true; 462 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 463 464 // If the sign bit of the input is known set or clear, then we know the 465 // top bits of the result. 466 467 // If the input sign bit is known zero, convert this into a zero extension. 468 if (KnownZero & InSignBit) 469 return TLO.CombineTo(Op, 470 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 471 472 if (KnownOne & InSignBit) { // Input sign bit known set 473 KnownOne |= NewBits; 474 KnownZero &= ~NewBits; 475 } else { // Input sign bit unknown 476 KnownZero &= ~NewBits; 477 KnownOne &= ~NewBits; 478 } 479 break; 480 } 481 case ISD::CTTZ: 482 case ISD::CTLZ: 483 case ISD::CTPOP: { 484 MVT::ValueType VT = Op.getValueType(); 485 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 486 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 487 KnownOne = 0; 488 break; 489 } 490 case ISD::ZEXTLOAD: { 491 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 492 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 493 break; 494 } 495 case ISD::ZERO_EXTEND: { 496 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 497 498 // If none of the top bits are demanded, convert this into an any_extend. 499 uint64_t NewBits = (~InMask) & DemandedMask; 500 if (NewBits == 0) 501 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 502 Op.getValueType(), 503 Op.getOperand(0))); 504 505 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 506 KnownZero, KnownOne, TLO, Depth+1)) 507 return true; 508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 509 KnownZero |= NewBits; 510 break; 511 } 512 case ISD::SIGN_EXTEND: { 513 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 514 uint64_t InMask = MVT::getIntVTBitMask(InVT); 515 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 516 uint64_t NewBits = (~InMask) & DemandedMask; 517 518 // If none of the top bits are demanded, convert this into an any_extend. 519 if (NewBits == 0) 520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 521 Op.getOperand(0))); 522 523 // Since some of the sign extended bits are demanded, we know that the sign 524 // bit is demanded. 525 uint64_t InDemandedBits = DemandedMask & InMask; 526 InDemandedBits |= InSignBit; 527 528 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 529 KnownOne, TLO, Depth+1)) 530 return true; 531 532 // If the sign bit is known zero, convert this to a zero extend. 533 if (KnownZero & InSignBit) 534 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 535 Op.getValueType(), 536 Op.getOperand(0))); 537 538 // If the sign bit is known one, the top bits match. 539 if (KnownOne & InSignBit) { 540 KnownOne |= NewBits; 541 KnownZero &= ~NewBits; 542 } else { // Otherwise, top bits aren't known. 543 KnownOne &= ~NewBits; 544 KnownZero &= ~NewBits; 545 } 546 break; 547 } 548 case ISD::ANY_EXTEND: { 549 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 550 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 551 KnownZero, KnownOne, TLO, Depth+1)) 552 return true; 553 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 554 break; 555 } 556 case ISD::AssertZext: { 557 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 558 uint64_t InMask = MVT::getIntVTBitMask(VT); 559 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 560 KnownZero, KnownOne, TLO, Depth+1)) 561 return true; 562 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 563 KnownZero |= ~InMask & DemandedMask; 564 break; 565 } 566 case ISD::ADD: 567 if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 568 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero, 569 KnownOne, TLO, Depth+1)) 570 return true; 571 // Compute the KnownOne/KnownZero masks for the constant, so we can set 572 // KnownZero appropriately if we're adding a constant that has all low 573 // bits cleared. 574 ComputeMaskedBits(Op.getOperand(1), 575 MVT::getIntVTBitMask(Op.getValueType()), 576 KnownZero2, KnownOne2, Depth+1); 577 578 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 579 CountTrailingZeros_64(~KnownZero2)); 580 KnownZero = (1ULL << KnownZeroOut) - 1; 581 KnownOne = 0; 582 583 SDOperand SH = Op.getOperand(0); 584 // fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1) 585 if (KnownZero && SH.getOpcode() == ISD::SHL && SH.Val->hasOneUse() && 586 Op.Val->hasOneUse()) { 587 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(SH.getOperand(1))) { 588 MVT::ValueType VT = Op.getValueType(); 589 unsigned ShiftAmt = SA->getValue(); 590 uint64_t AddAmt = AA->getValue(); 591 uint64_t AddShr = AddAmt >> ShiftAmt; 592 if (AddAmt == (AddShr << ShiftAmt)) { 593 SDOperand ADD = TLO.DAG.getNode(ISD::ADD, VT, SH.getOperand(0), 594 TLO.DAG.getConstant(AddShr, VT)); 595 SDOperand SHL = TLO.DAG.getNode(ISD::SHL, VT, ADD,SH.getOperand(1)); 596 return TLO.CombineTo(Op, SHL); 597 } 598 } 599 } 600 } 601 break; 602 } 603 604 // If we know the value of all of the demanded bits, return this as a 605 // constant. 606 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 607 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 608 609 return false; 610} 611 612/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 613/// this predicate to simplify operations downstream. Mask is known to be zero 614/// for bits that V cannot have. 615bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 616 unsigned Depth) const { 617 uint64_t KnownZero, KnownOne; 618 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 619 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 620 return (KnownZero & Mask) == Mask; 621} 622 623/// ComputeMaskedBits - Determine which of the bits specified in Mask are 624/// known to be either zero or one and return them in the KnownZero/KnownOne 625/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 626/// processing. 627void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 628 uint64_t &KnownZero, uint64_t &KnownOne, 629 unsigned Depth) const { 630 KnownZero = KnownOne = 0; // Don't know anything. 631 if (Depth == 6 || Mask == 0) 632 return; // Limit search depth. 633 634 uint64_t KnownZero2, KnownOne2; 635 636 switch (Op.getOpcode()) { 637 case ISD::Constant: 638 // We know all of the bits for a constant! 639 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 640 KnownZero = ~KnownOne & Mask; 641 return; 642 case ISD::AND: 643 // If either the LHS or the RHS are Zero, the result is zero. 644 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 645 Mask &= ~KnownZero; 646 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 647 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 648 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 649 650 // Output known-1 bits are only known if set in both the LHS & RHS. 651 KnownOne &= KnownOne2; 652 // Output known-0 are known to be clear if zero in either the LHS | RHS. 653 KnownZero |= KnownZero2; 654 return; 655 case ISD::OR: 656 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 657 Mask &= ~KnownOne; 658 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 659 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 660 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 661 662 // Output known-0 bits are only known if clear in both the LHS & RHS. 663 KnownZero &= KnownZero2; 664 // Output known-1 are known to be set if set in either the LHS | RHS. 665 KnownOne |= KnownOne2; 666 return; 667 case ISD::XOR: { 668 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 669 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 670 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 671 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 672 673 // Output known-0 bits are known if clear or set in both the LHS & RHS. 674 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 675 // Output known-1 are known to be set if set in only one of the LHS, RHS. 676 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 677 KnownZero = KnownZeroOut; 678 return; 679 } 680 case ISD::SELECT: 681 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 682 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 683 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 684 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 685 686 // Only known if known in both the LHS and RHS. 687 KnownOne &= KnownOne2; 688 KnownZero &= KnownZero2; 689 return; 690 case ISD::SELECT_CC: 691 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 692 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 693 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 694 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 695 696 // Only known if known in both the LHS and RHS. 697 KnownOne &= KnownOne2; 698 KnownZero &= KnownZero2; 699 return; 700 case ISD::SETCC: 701 // If we know the result of a setcc has the top bits zero, use this info. 702 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 703 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 704 return; 705 case ISD::SHL: 706 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 707 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 708 Mask >>= SA->getValue(); 709 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 710 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 711 KnownZero <<= SA->getValue(); 712 KnownOne <<= SA->getValue(); 713 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 714 } 715 return; 716 case ISD::SRL: 717 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 718 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 719 uint64_t HighBits = (1ULL << SA->getValue())-1; 720 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 721 Mask <<= SA->getValue(); 722 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 723 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 724 KnownZero >>= SA->getValue(); 725 KnownOne >>= SA->getValue(); 726 KnownZero |= HighBits; // high bits known zero. 727 } 728 return; 729 case ISD::SRA: 730 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 731 uint64_t HighBits = (1ULL << SA->getValue())-1; 732 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue(); 733 Mask <<= SA->getValue(); 734 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 735 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 736 KnownZero >>= SA->getValue(); 737 KnownOne >>= SA->getValue(); 738 739 // Handle the sign bits. 740 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1); 741 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask. 742 743 if (KnownZero & SignBit) { // New bits are known zero. 744 KnownZero |= HighBits; 745 } else if (KnownOne & SignBit) { // New bits are known one. 746 KnownOne |= HighBits; 747 } 748 } 749 return; 750 case ISD::SIGN_EXTEND_INREG: { 751 MVT::ValueType VT = Op.getValueType(); 752 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 753 754 // Sign extension. Compute the demanded bits in the result that are not 755 // present in the input. 756 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; 757 758 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 759 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); 760 761 // If the sign extended bits are demanded, we know that the sign 762 // bit is demanded. 763 if (NewBits) 764 InputDemandedBits |= InSignBit; 765 766 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 767 KnownZero, KnownOne, Depth+1); 768 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 769 770 // If the sign bit of the input is known set or clear, then we know the 771 // top bits of the result. 772 if (KnownZero & InSignBit) { // Input sign bit known clear 773 KnownZero |= NewBits; 774 KnownOne &= ~NewBits; 775 } else if (KnownOne & InSignBit) { // Input sign bit known set 776 KnownOne |= NewBits; 777 KnownZero &= ~NewBits; 778 } else { // Input sign bit unknown 779 KnownZero &= ~NewBits; 780 KnownOne &= ~NewBits; 781 } 782 return; 783 } 784 case ISD::CTTZ: 785 case ISD::CTLZ: 786 case ISD::CTPOP: { 787 MVT::ValueType VT = Op.getValueType(); 788 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 789 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 790 KnownOne = 0; 791 return; 792 } 793 case ISD::ZEXTLOAD: { 794 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); 795 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; 796 return; 797 } 798 case ISD::ZERO_EXTEND: { 799 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 800 uint64_t NewBits = (~InMask) & Mask; 801 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 802 KnownOne, Depth+1); 803 KnownZero |= NewBits & Mask; 804 KnownOne &= ~NewBits; 805 return; 806 } 807 case ISD::SIGN_EXTEND: { 808 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 809 unsigned InBits = MVT::getSizeInBits(InVT); 810 uint64_t InMask = MVT::getIntVTBitMask(InVT); 811 uint64_t InSignBit = 1ULL << (InBits-1); 812 uint64_t NewBits = (~InMask) & Mask; 813 uint64_t InDemandedBits = Mask & InMask; 814 815 // If any of the sign extended bits are demanded, we know that the sign 816 // bit is demanded. 817 if (NewBits & Mask) 818 InDemandedBits |= InSignBit; 819 820 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, 821 KnownOne, Depth+1); 822 // If the sign bit is known zero or one, the top bits match. 823 if (KnownZero & InSignBit) { 824 KnownZero |= NewBits; 825 KnownOne &= ~NewBits; 826 } else if (KnownOne & InSignBit) { 827 KnownOne |= NewBits; 828 KnownZero &= ~NewBits; 829 } else { // Otherwise, top bits aren't known. 830 KnownOne &= ~NewBits; 831 KnownZero &= ~NewBits; 832 } 833 return; 834 } 835 case ISD::ANY_EXTEND: { 836 MVT::ValueType VT = Op.getOperand(0).getValueType(); 837 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), 838 KnownZero, KnownOne, Depth+1); 839 return; 840 } 841 case ISD::AssertZext: { 842 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 843 uint64_t InMask = MVT::getIntVTBitMask(VT); 844 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 845 KnownOne, Depth+1); 846 KnownZero |= (~InMask) & Mask; 847 return; 848 } 849 case ISD::ADD: { 850 // If either the LHS or the RHS are Zero, the result is zero. 851 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 852 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 853 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 854 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 855 856 // Output known-0 bits are known if clear or set in both the low clear bits 857 // common to both LHS & RHS; 858 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 859 CountTrailingZeros_64(~KnownZero2)); 860 861 KnownZero = (1ULL << KnownZeroOut) - 1; 862 KnownOne = 0; 863 return; 864 } 865 case ISD::SUB: 866 // We know that the top bits of C-X are clear if X contains less bits 867 // than C (i.e. no wrap-around can happen). For example, 20-X is 868 // positive if we can prove that X is >= 0 and < 16. Remember to update 869 // SimplifyDemandedBits if/when this is implemented. 870 return; 871 default: 872 // Allow the target to implement this method for its nodes. 873 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) 874 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 875 return; 876 } 877} 878 879/// computeMaskedBitsForTargetNode - Determine which of the bits specified 880/// in Mask are known to be either zero or one and return them in the 881/// KnownZero/KnownOne bitsets. 882void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 883 uint64_t Mask, 884 uint64_t &KnownZero, 885 uint64_t &KnownOne, 886 unsigned Depth) const { 887 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END && 888 "Should use MaskedValueIsZero if you don't know whether Op" 889 " is a target node!"); 890 KnownZero = 0; 891 KnownOne = 0; 892} 893 894//===----------------------------------------------------------------------===// 895// Inline Assembler Implementation Methods 896//===----------------------------------------------------------------------===// 897 898TargetLowering::ConstraintType 899TargetLowering::getConstraintType(char ConstraintLetter) const { 900 // FIXME: lots more standard ones to handle. 901 switch (ConstraintLetter) { 902 default: return C_Unknown; 903 case 'r': return C_RegisterClass; 904 case 'm': // memory 905 case 'o': // offsetable 906 case 'V': // not offsetable 907 return C_Memory; 908 case 'i': // Simple Integer or Relocatable Constant 909 case 'n': // Simple Integer 910 case 's': // Relocatable Constant 911 case 'I': // Target registers. 912 case 'J': 913 case 'K': 914 case 'L': 915 case 'M': 916 case 'N': 917 case 'O': 918 case 'P': 919 return C_Other; 920 } 921} 922 923bool TargetLowering::isOperandValidForConstraint(SDOperand Op, 924 char ConstraintLetter) { 925 switch (ConstraintLetter) { 926 default: return false; 927 case 'i': // Simple Integer or Relocatable Constant 928 case 'n': // Simple Integer 929 case 's': // Relocatable Constant 930 return true; // FIXME: not right. 931 } 932} 933 934 935std::vector<unsigned> TargetLowering:: 936getRegClassForInlineAsmConstraint(const std::string &Constraint, 937 MVT::ValueType VT) const { 938 return std::vector<unsigned>(); 939} 940 941 942std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 943getRegForInlineAsmConstraint(const std::string &Constraint, 944 MVT::ValueType VT) const { 945 if (Constraint[0] != '{') 946 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 947 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 948 949 // Remove the braces from around the name. 950 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 951 952 // Figure out which register class contains this reg. 953 const MRegisterInfo *RI = TM.getRegisterInfo(); 954 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 955 E = RI->regclass_end(); RCI != E; ++RCI) { 956 const TargetRegisterClass *RC = *RCI; 957 958 // If none of the the value types for this register class are valid, we 959 // can't use it. For example, 64-bit reg classes on 32-bit targets. 960 bool isLegal = false; 961 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 962 I != E; ++I) { 963 if (isTypeLegal(*I)) { 964 isLegal = true; 965 break; 966 } 967 } 968 969 if (!isLegal) continue; 970 971 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 972 I != E; ++I) { 973 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 974 return std::make_pair(*I, RC); 975 } 976 } 977 978 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 979} 980