TargetLowering.cpp revision 63079f0757785c5c461bafdd3101ee40aeb717fe
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetSubtarget.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetMachine.h" 18#include "llvm/Target/MRegisterInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/Target/TargetAsmInfo.h" 25#include "llvm/CallingConv.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 52 Names[RTLIB::SUB_F32] = "__subsf3"; 53 Names[RTLIB::SUB_F64] = "__subdf3"; 54 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 55 Names[RTLIB::MUL_F32] = "__mulsf3"; 56 Names[RTLIB::MUL_F64] = "__muldf3"; 57 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 58 Names[RTLIB::DIV_F32] = "__divsf3"; 59 Names[RTLIB::DIV_F64] = "__divdf3"; 60 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 61 Names[RTLIB::REM_F32] = "fmodf"; 62 Names[RTLIB::REM_F64] = "fmod"; 63 Names[RTLIB::REM_PPCF128] = "fmodl"; 64 Names[RTLIB::NEG_F32] = "__negsf2"; 65 Names[RTLIB::NEG_F64] = "__negdf2"; 66 Names[RTLIB::POWI_F32] = "__powisf2"; 67 Names[RTLIB::POWI_F64] = "__powidf2"; 68 Names[RTLIB::POWI_F80] = "__powixf2"; 69 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 70 Names[RTLIB::SQRT_F32] = "sqrtf"; 71 Names[RTLIB::SQRT_F64] = "sqrt"; 72 Names[RTLIB::SQRT_F80] = "sqrtl"; 73 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 74 Names[RTLIB::SIN_F32] = "sinf"; 75 Names[RTLIB::SIN_F64] = "sin"; 76 Names[RTLIB::COS_F32] = "cosf"; 77 Names[RTLIB::COS_F64] = "cos"; 78 Names[RTLIB::POW_F32] = "powf"; 79 Names[RTLIB::POW_F64] = "pow"; 80 Names[RTLIB::POW_F80] = "powl"; 81 Names[RTLIB::POW_PPCF128] = "powl"; 82 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 83 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 84 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 85 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 86 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 87 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 88 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 89 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 90 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 91 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 92 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 93 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 94 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 95 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 96 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 97 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 98 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 99 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 100 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 101 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 102 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 103 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 104 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 105 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 106 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 107 Names[RTLIB::OEQ_F32] = "__eqsf2"; 108 Names[RTLIB::OEQ_F64] = "__eqdf2"; 109 Names[RTLIB::UNE_F32] = "__nesf2"; 110 Names[RTLIB::UNE_F64] = "__nedf2"; 111 Names[RTLIB::OGE_F32] = "__gesf2"; 112 Names[RTLIB::OGE_F64] = "__gedf2"; 113 Names[RTLIB::OLT_F32] = "__ltsf2"; 114 Names[RTLIB::OLT_F64] = "__ltdf2"; 115 Names[RTLIB::OLE_F32] = "__lesf2"; 116 Names[RTLIB::OLE_F64] = "__ledf2"; 117 Names[RTLIB::OGT_F32] = "__gtsf2"; 118 Names[RTLIB::OGT_F64] = "__gtdf2"; 119 Names[RTLIB::UO_F32] = "__unordsf2"; 120 Names[RTLIB::UO_F64] = "__unorddf2"; 121 Names[RTLIB::O_F32] = "__unordsf2"; 122 Names[RTLIB::O_F64] = "__unorddf2"; 123} 124 125/// InitCmpLibcallCCs - Set default comparison libcall CC. 126/// 127static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 128 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 129 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 130 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 131 CCs[RTLIB::UNE_F32] = ISD::SETNE; 132 CCs[RTLIB::UNE_F64] = ISD::SETNE; 133 CCs[RTLIB::OGE_F32] = ISD::SETGE; 134 CCs[RTLIB::OGE_F64] = ISD::SETGE; 135 CCs[RTLIB::OLT_F32] = ISD::SETLT; 136 CCs[RTLIB::OLT_F64] = ISD::SETLT; 137 CCs[RTLIB::OLE_F32] = ISD::SETLE; 138 CCs[RTLIB::OLE_F64] = ISD::SETLE; 139 CCs[RTLIB::OGT_F32] = ISD::SETGT; 140 CCs[RTLIB::OGT_F64] = ISD::SETGT; 141 CCs[RTLIB::UO_F32] = ISD::SETNE; 142 CCs[RTLIB::UO_F64] = ISD::SETNE; 143 CCs[RTLIB::O_F32] = ISD::SETEQ; 144 CCs[RTLIB::O_F64] = ISD::SETEQ; 145} 146 147TargetLowering::TargetLowering(TargetMachine &tm) 148 : TM(tm), TD(TM.getTargetData()) { 149 assert(ISD::BUILTIN_OP_END <= 156 && 150 "Fixed size array in TargetLowering is not large enough!"); 151 // All operations default to being supported. 152 memset(OpActions, 0, sizeof(OpActions)); 153 memset(LoadXActions, 0, sizeof(LoadXActions)); 154 memset(&StoreXActions, 0, sizeof(StoreXActions)); 155 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions)); 156 memset(&ConvertActions, 0, sizeof(ConvertActions)); 157 158 // Set default actions for various operations. 159 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 160 // Default all indexed load / store to expand. 161 for (unsigned IM = (unsigned)ISD::PRE_INC; 162 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 163 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 164 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 165 } 166 167 // These operations default to expand. 168 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); 169 } 170 171 IsLittleEndian = TD->isLittleEndian(); 172 UsesGlobalOffsetTable = false; 173 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 174 ShiftAmtHandling = Undefined; 175 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 176 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 177 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 178 allowUnalignedMemoryAccesses = false; 179 UseUnderscoreSetJmp = false; 180 UseUnderscoreLongJmp = false; 181 SelectIsExpensive = false; 182 IntDivIsCheap = false; 183 Pow2DivIsCheap = false; 184 StackPointerRegisterToSaveRestore = 0; 185 ExceptionPointerRegister = 0; 186 ExceptionSelectorRegister = 0; 187 SetCCResultContents = UndefinedSetCCResult; 188 SchedPreferenceInfo = SchedulingForLatency; 189 JumpBufSize = 0; 190 JumpBufAlignment = 0; 191 IfCvtBlockSizeLimit = 2; 192 193 InitLibcallNames(LibcallRoutineNames); 194 InitCmpLibcallCCs(CmpLibcallCCs); 195 196 // Tell Legalize whether the assembler supports DEBUG_LOC. 197 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 198 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 199} 200 201TargetLowering::~TargetLowering() {} 202 203 204SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 205 assert(getSubtarget() && "Subtarget not defined"); 206 SDOperand ChainOp = Op.getOperand(0); 207 SDOperand DestOp = Op.getOperand(1); 208 SDOperand SourceOp = Op.getOperand(2); 209 SDOperand CountOp = Op.getOperand(3); 210 SDOperand AlignOp = Op.getOperand(4); 211 SDOperand AlwaysInlineOp = Op.getOperand(5); 212 213 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 214 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 215 if (Align == 0) Align = 1; 216 217 // If size is unknown, call memcpy. 218 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 219 if (!I) { 220 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 221 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 222 } 223 224 // If not DWORD aligned or if size is more than threshold, then call memcpy. 225 // The libc version is likely to be faster for the following cases. It can 226 // use the address value and run time information about the CPU. 227 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 228 unsigned Size = I->getValue(); 229 if (AlwaysInline || 230 (Size <= getSubtarget()->getMaxInlineSizeThreshold() && 231 (Align & 3) == 0)) 232 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 233 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 234} 235 236 237SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain, 238 SDOperand Dest, 239 SDOperand Source, 240 SDOperand Count, 241 SelectionDAG &DAG) { 242 MVT::ValueType IntPtr = getPointerTy(); 243 TargetLowering::ArgListTy Args; 244 TargetLowering::ArgListEntry Entry; 245 Entry.Ty = getTargetData()->getIntPtrType(); 246 Entry.Node = Dest; Args.push_back(Entry); 247 Entry.Node = Source; Args.push_back(Entry); 248 Entry.Node = Count; Args.push_back(Entry); 249 std::pair<SDOperand,SDOperand> CallResult = 250 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 251 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 252 return CallResult.second; 253} 254 255 256/// computeRegisterProperties - Once all of the register classes are added, 257/// this allows us to compute derived properties we expose. 258void TargetLowering::computeRegisterProperties() { 259 assert(MVT::LAST_VALUETYPE <= 32 && 260 "Too many value types for ValueTypeActions to hold!"); 261 262 // Everything defaults to needing one register. 263 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 264 NumRegistersForVT[i] = 1; 265 RegisterTypeForVT[i] = TransformToType[i] = i; 266 } 267 // ...except isVoid, which doesn't need any registers. 268 NumRegistersForVT[MVT::isVoid] = 0; 269 270 // Find the largest integer register class. 271 unsigned LargestIntReg = MVT::i128; 272 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 273 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 274 275 // Every integer value type larger than this largest register takes twice as 276 // many registers to represent as the previous ValueType. 277 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 278 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 279 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 280 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 281 TransformToType[ExpandedReg] = ExpandedReg - 1; 282 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 283 } 284 285 // Inspect all of the ValueType's smaller than the largest integer 286 // register to see which ones need promotion. 287 MVT::ValueType LegalIntReg = LargestIntReg; 288 for (MVT::ValueType IntReg = LargestIntReg - 1; 289 IntReg >= MVT::i1; --IntReg) { 290 if (isTypeLegal(IntReg)) { 291 LegalIntReg = IntReg; 292 } else { 293 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 294 ValueTypeActions.setTypeAction(IntReg, Promote); 295 } 296 } 297 298 // ppcf128 type is really two f64's. 299 if (!isTypeLegal(MVT::ppcf128)) { 300 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 301 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 302 TransformToType[MVT::ppcf128] = MVT::f64; 303 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 304 } 305 306 // Decide how to handle f64. If the target does not have native f64 support, 307 // expand it to i64 and we will be generating soft float library calls. 308 if (!isTypeLegal(MVT::f64)) { 309 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 310 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 311 TransformToType[MVT::f64] = MVT::i64; 312 ValueTypeActions.setTypeAction(MVT::f64, Expand); 313 } 314 315 // Decide how to handle f32. If the target does not have native support for 316 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 317 if (!isTypeLegal(MVT::f32)) { 318 if (isTypeLegal(MVT::f64)) { 319 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 320 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 321 TransformToType[MVT::f32] = MVT::f64; 322 ValueTypeActions.setTypeAction(MVT::f32, Promote); 323 } else { 324 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 325 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 326 TransformToType[MVT::f32] = MVT::i32; 327 ValueTypeActions.setTypeAction(MVT::f32, Expand); 328 } 329 } 330 331 // Loop over all of the vector value types to see which need transformations. 332 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 333 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 334 if (!isTypeLegal(i)) { 335 MVT::ValueType IntermediateVT, RegisterVT; 336 unsigned NumIntermediates; 337 NumRegistersForVT[i] = 338 getVectorTypeBreakdown(i, 339 IntermediateVT, NumIntermediates, 340 RegisterVT); 341 RegisterTypeForVT[i] = RegisterVT; 342 TransformToType[i] = MVT::Other; // this isn't actually used 343 ValueTypeActions.setTypeAction(i, Expand); 344 } 345 } 346} 347 348const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 349 return NULL; 350} 351 352/// getVectorTypeBreakdown - Vector types are broken down into some number of 353/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 354/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 355/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 356/// 357/// This method returns the number of registers needed, and the VT for each 358/// register. It also returns the VT and quantity of the intermediate values 359/// before they are promoted/expanded. 360/// 361unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 362 MVT::ValueType &IntermediateVT, 363 unsigned &NumIntermediates, 364 MVT::ValueType &RegisterVT) const { 365 // Figure out the right, legal destination reg to copy into. 366 unsigned NumElts = MVT::getVectorNumElements(VT); 367 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 368 369 unsigned NumVectorRegs = 1; 370 371 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 372 // could break down into LHS/RHS like LegalizeDAG does. 373 if (!isPowerOf2_32(NumElts)) { 374 NumVectorRegs = NumElts; 375 NumElts = 1; 376 } 377 378 // Divide the input until we get to a supported size. This will always 379 // end with a scalar if the target doesn't support vectors. 380 while (NumElts > 1 && 381 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 382 NumElts >>= 1; 383 NumVectorRegs <<= 1; 384 } 385 386 NumIntermediates = NumVectorRegs; 387 388 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 389 if (!isTypeLegal(NewVT)) 390 NewVT = EltTy; 391 IntermediateVT = NewVT; 392 393 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 394 RegisterVT = DestVT; 395 if (DestVT < NewVT) { 396 // Value is expanded, e.g. i64 -> i16. 397 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 398 } else { 399 // Otherwise, promotion or legal types use the same number of registers as 400 // the vector decimated to the appropriate level. 401 return NumVectorRegs; 402 } 403 404 return 1; 405} 406 407SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 408 SelectionDAG &DAG) const { 409 if (usesGlobalOffsetTable()) 410 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 411 return Table; 412} 413 414//===----------------------------------------------------------------------===// 415// Optimization Methods 416//===----------------------------------------------------------------------===// 417 418/// ShrinkDemandedConstant - Check to see if the specified operand of the 419/// specified instruction is a constant integer. If so, check to see if there 420/// are any bits set in the constant that are not demanded. If so, shrink the 421/// constant and return true. 422bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 423 uint64_t Demanded) { 424 // FIXME: ISD::SELECT, ISD::SELECT_CC 425 switch(Op.getOpcode()) { 426 default: break; 427 case ISD::AND: 428 case ISD::OR: 429 case ISD::XOR: 430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 431 if ((~Demanded & C->getValue()) != 0) { 432 MVT::ValueType VT = Op.getValueType(); 433 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 434 DAG.getConstant(Demanded & C->getValue(), 435 VT)); 436 return CombineTo(Op, New); 437 } 438 break; 439 } 440 return false; 441} 442 443/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 444/// DemandedMask bits of the result of Op are ever used downstream. If we can 445/// use this information to simplify Op, create a new simplified DAG node and 446/// return true, returning the original and new nodes in Old and New. Otherwise, 447/// analyze the expression and return a mask of KnownOne and KnownZero bits for 448/// the expression (used to simplify the caller). The KnownZero/One bits may 449/// only be accurate for those bits in the DemandedMask. 450bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 451 uint64_t &KnownZero, 452 uint64_t &KnownOne, 453 TargetLoweringOpt &TLO, 454 unsigned Depth) const { 455 KnownZero = KnownOne = 0; // Don't know anything. 456 457 // The masks are not wide enough to represent this type! Should use APInt. 458 if (Op.getValueType() == MVT::i128) 459 return false; 460 461 // Other users may use these bits. 462 if (!Op.Val->hasOneUse()) { 463 if (Depth != 0) { 464 // If not at the root, Just compute the KnownZero/KnownOne bits to 465 // simplify things downstream. 466 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 467 return false; 468 } 469 // If this is the root being simplified, allow it to have multiple uses, 470 // just set the DemandedMask to all bits. 471 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 472 } else if (DemandedMask == 0) { 473 // Not demanding any bits from Op. 474 if (Op.getOpcode() != ISD::UNDEF) 475 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 476 return false; 477 } else if (Depth == 6) { // Limit search depth. 478 return false; 479 } 480 481 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 482 switch (Op.getOpcode()) { 483 case ISD::Constant: 484 // We know all of the bits for a constant! 485 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 486 KnownZero = ~KnownOne & DemandedMask; 487 return false; // Don't fall through, will infinitely loop. 488 case ISD::AND: 489 // If the RHS is a constant, check to see if the LHS would be zero without 490 // using the bits from the RHS. Below, we use knowledge about the RHS to 491 // simplify the LHS, here we're using information from the LHS to simplify 492 // the RHS. 493 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 494 uint64_t LHSZero, LHSOne; 495 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask, 496 LHSZero, LHSOne, Depth+1); 497 // If the LHS already has zeros where RHSC does, this and is dead. 498 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 499 return TLO.CombineTo(Op, Op.getOperand(0)); 500 // If any of the set bits in the RHS are known zero on the LHS, shrink 501 // the constant. 502 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 503 return true; 504 } 505 506 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 507 KnownOne, TLO, Depth+1)) 508 return true; 509 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 510 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 511 KnownZero2, KnownOne2, TLO, Depth+1)) 512 return true; 513 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 514 515 // If all of the demanded bits are known one on one side, return the other. 516 // These bits cannot contribute to the result of the 'and'. 517 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 518 return TLO.CombineTo(Op, Op.getOperand(0)); 519 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 520 return TLO.CombineTo(Op, Op.getOperand(1)); 521 // If all of the demanded bits in the inputs are known zeros, return zero. 522 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 523 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 524 // If the RHS is a constant, see if we can simplify it. 525 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 526 return true; 527 528 // Output known-1 bits are only known if set in both the LHS & RHS. 529 KnownOne &= KnownOne2; 530 // Output known-0 are known to be clear if zero in either the LHS | RHS. 531 KnownZero |= KnownZero2; 532 break; 533 case ISD::OR: 534 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 535 KnownOne, TLO, Depth+1)) 536 return true; 537 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 538 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 539 KnownZero2, KnownOne2, TLO, Depth+1)) 540 return true; 541 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 542 543 // If all of the demanded bits are known zero on one side, return the other. 544 // These bits cannot contribute to the result of the 'or'. 545 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 546 return TLO.CombineTo(Op, Op.getOperand(0)); 547 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 548 return TLO.CombineTo(Op, Op.getOperand(1)); 549 // If all of the potentially set bits on one side are known to be set on 550 // the other side, just use the 'other' side. 551 if ((DemandedMask & (~KnownZero) & KnownOne2) == 552 (DemandedMask & (~KnownZero))) 553 return TLO.CombineTo(Op, Op.getOperand(0)); 554 if ((DemandedMask & (~KnownZero2) & KnownOne) == 555 (DemandedMask & (~KnownZero2))) 556 return TLO.CombineTo(Op, Op.getOperand(1)); 557 // If the RHS is a constant, see if we can simplify it. 558 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 559 return true; 560 561 // Output known-0 bits are only known if clear in both the LHS & RHS. 562 KnownZero &= KnownZero2; 563 // Output known-1 are known to be set if set in either the LHS | RHS. 564 KnownOne |= KnownOne2; 565 break; 566 case ISD::XOR: 567 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 568 KnownOne, TLO, Depth+1)) 569 return true; 570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 571 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 572 KnownOne2, TLO, Depth+1)) 573 return true; 574 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 575 576 // If all of the demanded bits are known zero on one side, return the other. 577 // These bits cannot contribute to the result of the 'xor'. 578 if ((DemandedMask & KnownZero) == DemandedMask) 579 return TLO.CombineTo(Op, Op.getOperand(0)); 580 if ((DemandedMask & KnownZero2) == DemandedMask) 581 return TLO.CombineTo(Op, Op.getOperand(1)); 582 583 // If all of the unknown bits are known to be zero on one side or the other 584 // (but not both) turn this into an *inclusive* or. 585 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 586 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 587 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 588 Op.getOperand(0), 589 Op.getOperand(1))); 590 591 // Output known-0 bits are known if clear or set in both the LHS & RHS. 592 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 593 // Output known-1 are known to be set if set in only one of the LHS, RHS. 594 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 595 596 // If all of the demanded bits on one side are known, and all of the set 597 // bits on that side are also known to be set on the other side, turn this 598 // into an AND, as we know the bits will be cleared. 599 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 600 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 601 if ((KnownOne & KnownOne2) == KnownOne) { 602 MVT::ValueType VT = Op.getValueType(); 603 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 604 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 605 ANDC)); 606 } 607 } 608 609 // If the RHS is a constant, see if we can simplify it. 610 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 611 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 612 return true; 613 614 KnownZero = KnownZeroOut; 615 KnownOne = KnownOneOut; 616 break; 617 case ISD::SETCC: 618 // If we know the result of a setcc has the top bits zero, use this info. 619 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 620 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 621 break; 622 case ISD::SELECT: 623 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 624 KnownOne, TLO, Depth+1)) 625 return true; 626 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 627 KnownOne2, TLO, Depth+1)) 628 return true; 629 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 630 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 631 632 // If the operands are constants, see if we can simplify them. 633 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 634 return true; 635 636 // Only known if known in both the LHS and RHS. 637 KnownOne &= KnownOne2; 638 KnownZero &= KnownZero2; 639 break; 640 case ISD::SELECT_CC: 641 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 642 KnownOne, TLO, Depth+1)) 643 return true; 644 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 645 KnownOne2, TLO, Depth+1)) 646 return true; 647 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 648 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 649 650 // If the operands are constants, see if we can simplify them. 651 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 652 return true; 653 654 // Only known if known in both the LHS and RHS. 655 KnownOne &= KnownOne2; 656 KnownZero &= KnownZero2; 657 break; 658 case ISD::SHL: 659 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 660 unsigned ShAmt = SA->getValue(); 661 SDOperand InOp = Op.getOperand(0); 662 663 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 664 // single shift. We can do this if the bottom bits (which are shifted 665 // out) are never demanded. 666 if (InOp.getOpcode() == ISD::SRL && 667 isa<ConstantSDNode>(InOp.getOperand(1))) { 668 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) { 669 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 670 unsigned Opc = ISD::SHL; 671 int Diff = ShAmt-C1; 672 if (Diff < 0) { 673 Diff = -Diff; 674 Opc = ISD::SRL; 675 } 676 677 SDOperand NewSA = 678 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 679 MVT::ValueType VT = Op.getValueType(); 680 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 681 InOp.getOperand(0), NewSA)); 682 } 683 } 684 685 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt, 686 KnownZero, KnownOne, TLO, Depth+1)) 687 return true; 688 KnownZero <<= SA->getValue(); 689 KnownOne <<= SA->getValue(); 690 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 691 } 692 break; 693 case ISD::SRL: 694 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 695 MVT::ValueType VT = Op.getValueType(); 696 unsigned ShAmt = SA->getValue(); 697 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 698 unsigned VTSize = MVT::getSizeInBits(VT); 699 SDOperand InOp = Op.getOperand(0); 700 701 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 702 // single shift. We can do this if the top bits (which are shifted out) 703 // are never demanded. 704 if (InOp.getOpcode() == ISD::SHL && 705 isa<ConstantSDNode>(InOp.getOperand(1))) { 706 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) { 707 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 708 unsigned Opc = ISD::SRL; 709 int Diff = ShAmt-C1; 710 if (Diff < 0) { 711 Diff = -Diff; 712 Opc = ISD::SHL; 713 } 714 715 SDOperand NewSA = 716 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 717 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 718 InOp.getOperand(0), NewSA)); 719 } 720 } 721 722 // Compute the new bits that are at the top now. 723 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask, 724 KnownZero, KnownOne, TLO, Depth+1)) 725 return true; 726 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 727 KnownZero &= TypeMask; 728 KnownOne &= TypeMask; 729 KnownZero >>= ShAmt; 730 KnownOne >>= ShAmt; 731 732 uint64_t HighBits = (1ULL << ShAmt)-1; 733 HighBits <<= VTSize - ShAmt; 734 KnownZero |= HighBits; // High bits known zero. 735 } 736 break; 737 case ISD::SRA: 738 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 739 MVT::ValueType VT = Op.getValueType(); 740 unsigned ShAmt = SA->getValue(); 741 742 // Compute the new bits that are at the top now. 743 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 744 745 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 746 747 // If any of the demanded bits are produced by the sign extension, we also 748 // demand the input sign bit. 749 uint64_t HighBits = (1ULL << ShAmt)-1; 750 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 751 if (HighBits & DemandedMask) 752 InDemandedMask |= MVT::getIntVTSignBit(VT); 753 754 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 755 KnownZero, KnownOne, TLO, Depth+1)) 756 return true; 757 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 758 KnownZero &= TypeMask; 759 KnownOne &= TypeMask; 760 KnownZero >>= ShAmt; 761 KnownOne >>= ShAmt; 762 763 // Handle the sign bits. 764 uint64_t SignBit = MVT::getIntVTSignBit(VT); 765 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 766 767 // If the input sign bit is known to be zero, or if none of the top bits 768 // are demanded, turn this into an unsigned shift right. 769 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 770 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 771 Op.getOperand(1))); 772 } else if (KnownOne & SignBit) { // New bits are known one. 773 KnownOne |= HighBits; 774 } 775 } 776 break; 777 case ISD::SIGN_EXTEND_INREG: { 778 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 779 780 // Sign extension. Compute the demanded bits in the result that are not 781 // present in the input. 782 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 783 784 // If none of the extended bits are demanded, eliminate the sextinreg. 785 if (NewBits == 0) 786 return TLO.CombineTo(Op, Op.getOperand(0)); 787 788 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 789 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 790 791 // Since the sign extended bits are demanded, we know that the sign 792 // bit is demanded. 793 InputDemandedBits |= InSignBit; 794 795 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 796 KnownZero, KnownOne, TLO, Depth+1)) 797 return true; 798 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 799 800 // If the sign bit of the input is known set or clear, then we know the 801 // top bits of the result. 802 803 // If the input sign bit is known zero, convert this into a zero extension. 804 if (KnownZero & InSignBit) 805 return TLO.CombineTo(Op, 806 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 807 808 if (KnownOne & InSignBit) { // Input sign bit known set 809 KnownOne |= NewBits; 810 KnownZero &= ~NewBits; 811 } else { // Input sign bit unknown 812 KnownZero &= ~NewBits; 813 KnownOne &= ~NewBits; 814 } 815 break; 816 } 817 case ISD::CTTZ: 818 case ISD::CTLZ: 819 case ISD::CTPOP: { 820 MVT::ValueType VT = Op.getValueType(); 821 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 822 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 823 KnownOne = 0; 824 break; 825 } 826 case ISD::LOAD: { 827 if (ISD::isZEXTLoad(Op.Val)) { 828 LoadSDNode *LD = cast<LoadSDNode>(Op); 829 MVT::ValueType VT = LD->getLoadedVT(); 830 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 831 } 832 break; 833 } 834 case ISD::ZERO_EXTEND: { 835 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 836 837 // If none of the top bits are demanded, convert this into an any_extend. 838 uint64_t NewBits = (~InMask) & DemandedMask; 839 if (NewBits == 0) 840 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 841 Op.getValueType(), 842 Op.getOperand(0))); 843 844 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 845 KnownZero, KnownOne, TLO, Depth+1)) 846 return true; 847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 848 KnownZero |= NewBits; 849 break; 850 } 851 case ISD::SIGN_EXTEND: { 852 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 853 uint64_t InMask = MVT::getIntVTBitMask(InVT); 854 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 855 uint64_t NewBits = (~InMask) & DemandedMask; 856 857 // If none of the top bits are demanded, convert this into an any_extend. 858 if (NewBits == 0) 859 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 860 Op.getOperand(0))); 861 862 // Since some of the sign extended bits are demanded, we know that the sign 863 // bit is demanded. 864 uint64_t InDemandedBits = DemandedMask & InMask; 865 InDemandedBits |= InSignBit; 866 867 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 868 KnownOne, TLO, Depth+1)) 869 return true; 870 871 // If the sign bit is known zero, convert this to a zero extend. 872 if (KnownZero & InSignBit) 873 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 874 Op.getValueType(), 875 Op.getOperand(0))); 876 877 // If the sign bit is known one, the top bits match. 878 if (KnownOne & InSignBit) { 879 KnownOne |= NewBits; 880 KnownZero &= ~NewBits; 881 } else { // Otherwise, top bits aren't known. 882 KnownOne &= ~NewBits; 883 KnownZero &= ~NewBits; 884 } 885 break; 886 } 887 case ISD::ANY_EXTEND: { 888 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 889 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 890 KnownZero, KnownOne, TLO, Depth+1)) 891 return true; 892 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 893 break; 894 } 895 case ISD::TRUNCATE: { 896 // Simplify the input, using demanded bit information, and compute the known 897 // zero/one bits live out. 898 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 899 KnownZero, KnownOne, TLO, Depth+1)) 900 return true; 901 902 // If the input is only used by this truncate, see if we can shrink it based 903 // on the known demanded bits. 904 if (Op.getOperand(0).Val->hasOneUse()) { 905 SDOperand In = Op.getOperand(0); 906 switch (In.getOpcode()) { 907 default: break; 908 case ISD::SRL: 909 // Shrink SRL by a constant if none of the high bits shifted in are 910 // demanded. 911 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 912 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 913 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 914 HighBits >>= ShAmt->getValue(); 915 916 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 917 (DemandedMask & HighBits) == 0) { 918 // None of the shifted in bits are needed. Add a truncate of the 919 // shift input, then shift it. 920 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 921 Op.getValueType(), 922 In.getOperand(0)); 923 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 924 NewTrunc, In.getOperand(1))); 925 } 926 } 927 break; 928 } 929 } 930 931 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 932 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 933 KnownZero &= OutMask; 934 KnownOne &= OutMask; 935 break; 936 } 937 case ISD::AssertZext: { 938 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 939 uint64_t InMask = MVT::getIntVTBitMask(VT); 940 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 941 KnownZero, KnownOne, TLO, Depth+1)) 942 return true; 943 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 944 KnownZero |= ~InMask & DemandedMask; 945 break; 946 } 947 case ISD::FGETSIGN: 948 // All bits are zero except the low bit. 949 KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1; 950 break; 951 case ISD::BIT_CONVERT: 952#if 0 953 // If this is an FP->Int bitcast and if the sign bit is the only thing that 954 // is demanded, turn this into a FGETSIGN. 955 if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) && 956 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 957 !MVT::isVector(Op.getOperand(0).getValueType())) { 958 // Only do this xform if FGETSIGN is valid or if before legalize. 959 if (!TLO.AfterLegalize || 960 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 961 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 962 // place. We expect the SHL to be eliminated by other optimizations. 963 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 964 Op.getOperand(0)); 965 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; 966 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 967 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 968 Sign, ShAmt)); 969 } 970 } 971#endif 972 break; 973 case ISD::ADD: 974 case ISD::SUB: 975 case ISD::INTRINSIC_WO_CHAIN: 976 case ISD::INTRINSIC_W_CHAIN: 977 case ISD::INTRINSIC_VOID: 978 // Just use ComputeMaskedBits to compute output bits. 979 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 980 break; 981 } 982 983 // If we know the value of all of the demanded bits, return this as a 984 // constant. 985 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 986 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 987 988 return false; 989} 990 991/// computeMaskedBitsForTargetNode - Determine which of the bits specified 992/// in Mask are known to be either zero or one and return them in the 993/// KnownZero/KnownOne bitsets. 994void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 995 uint64_t Mask, 996 uint64_t &KnownZero, 997 uint64_t &KnownOne, 998 const SelectionDAG &DAG, 999 unsigned Depth) const { 1000 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1001 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1002 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1003 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1004 "Should use MaskedValueIsZero if you don't know whether Op" 1005 " is a target node!"); 1006 KnownZero = 0; 1007 KnownOne = 0; 1008} 1009 1010/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1011/// targets that want to expose additional information about sign bits to the 1012/// DAG Combiner. 1013unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1014 unsigned Depth) const { 1015 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1016 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1017 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1018 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1019 "Should use ComputeNumSignBits if you don't know whether Op" 1020 " is a target node!"); 1021 return 1; 1022} 1023 1024 1025/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1026/// and cc. If it is unable to simplify it, return a null SDOperand. 1027SDOperand 1028TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1029 ISD::CondCode Cond, bool foldBooleans, 1030 DAGCombinerInfo &DCI) const { 1031 SelectionDAG &DAG = DCI.DAG; 1032 1033 // These setcc operations always fold. 1034 switch (Cond) { 1035 default: break; 1036 case ISD::SETFALSE: 1037 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1038 case ISD::SETTRUE: 1039 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1040 } 1041 1042 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1043 uint64_t C1 = N1C->getValue(); 1044 if (isa<ConstantSDNode>(N0.Val)) { 1045 return DAG.FoldSetCC(VT, N0, N1, Cond); 1046 } else { 1047 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1048 // equality comparison, then we're just comparing whether X itself is 1049 // zero. 1050 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1051 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1052 N0.getOperand(1).getOpcode() == ISD::Constant) { 1053 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1054 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1055 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1056 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1057 // (srl (ctlz x), 5) == 0 -> X != 0 1058 // (srl (ctlz x), 5) != 1 -> X != 0 1059 Cond = ISD::SETNE; 1060 } else { 1061 // (srl (ctlz x), 5) != 0 -> X == 0 1062 // (srl (ctlz x), 5) == 1 -> X == 0 1063 Cond = ISD::SETEQ; 1064 } 1065 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1066 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1067 Zero, Cond); 1068 } 1069 } 1070 1071 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1072 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1073 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1074 1075 // If the comparison constant has bits in the upper part, the 1076 // zero-extended value could never match. 1077 if (C1 & (~0ULL << InSize)) { 1078 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1079 switch (Cond) { 1080 case ISD::SETUGT: 1081 case ISD::SETUGE: 1082 case ISD::SETEQ: return DAG.getConstant(0, VT); 1083 case ISD::SETULT: 1084 case ISD::SETULE: 1085 case ISD::SETNE: return DAG.getConstant(1, VT); 1086 case ISD::SETGT: 1087 case ISD::SETGE: 1088 // True if the sign bit of C1 is set. 1089 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); 1090 case ISD::SETLT: 1091 case ISD::SETLE: 1092 // True if the sign bit of C1 isn't set. 1093 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); 1094 default: 1095 break; 1096 } 1097 } 1098 1099 // Otherwise, we can perform the comparison with the low bits. 1100 switch (Cond) { 1101 case ISD::SETEQ: 1102 case ISD::SETNE: 1103 case ISD::SETUGT: 1104 case ISD::SETUGE: 1105 case ISD::SETULT: 1106 case ISD::SETULE: 1107 return DAG.getSetCC(VT, N0.getOperand(0), 1108 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1109 Cond); 1110 default: 1111 break; // todo, be more careful with signed comparisons 1112 } 1113 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1114 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1115 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1116 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1117 MVT::ValueType ExtDstTy = N0.getValueType(); 1118 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1119 1120 // If the extended part has any inconsistent bits, it cannot ever 1121 // compare equal. In other words, they have to be all ones or all 1122 // zeros. 1123 uint64_t ExtBits = 1124 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1125 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1126 return DAG.getConstant(Cond == ISD::SETNE, VT); 1127 1128 SDOperand ZextOp; 1129 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1130 if (Op0Ty == ExtSrcTy) { 1131 ZextOp = N0.getOperand(0); 1132 } else { 1133 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1134 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1135 DAG.getConstant(Imm, Op0Ty)); 1136 } 1137 if (!DCI.isCalledByLegalizer()) 1138 DCI.AddToWorklist(ZextOp.Val); 1139 // Otherwise, make this a use of a zext. 1140 return DAG.getSetCC(VT, ZextOp, 1141 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1142 ExtDstTy), 1143 Cond); 1144 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 1145 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1146 1147 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1148 if (N0.getOpcode() == ISD::SETCC) { 1149 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1150 if (TrueWhenTrue) 1151 return N0; 1152 1153 // Invert the condition. 1154 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1155 CC = ISD::getSetCCInverse(CC, 1156 MVT::isInteger(N0.getOperand(0).getValueType())); 1157 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1158 } 1159 1160 if ((N0.getOpcode() == ISD::XOR || 1161 (N0.getOpcode() == ISD::AND && 1162 N0.getOperand(0).getOpcode() == ISD::XOR && 1163 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1164 isa<ConstantSDNode>(N0.getOperand(1)) && 1165 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1166 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1167 // can only do this if the top bits are known zero. 1168 if (DAG.MaskedValueIsZero(N0, 1169 MVT::getIntVTBitMask(N0.getValueType())-1)){ 1170 // Okay, get the un-inverted input value. 1171 SDOperand Val; 1172 if (N0.getOpcode() == ISD::XOR) 1173 Val = N0.getOperand(0); 1174 else { 1175 assert(N0.getOpcode() == ISD::AND && 1176 N0.getOperand(0).getOpcode() == ISD::XOR); 1177 // ((X^1)&1)^1 -> X & 1 1178 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1179 N0.getOperand(0).getOperand(0), 1180 N0.getOperand(1)); 1181 } 1182 return DAG.getSetCC(VT, Val, N1, 1183 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1184 } 1185 } 1186 } 1187 1188 uint64_t MinVal, MaxVal; 1189 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1190 if (ISD::isSignedIntSetCC(Cond)) { 1191 MinVal = 1ULL << (OperandBitSize-1); 1192 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1193 MaxVal = ~0ULL >> (65-OperandBitSize); 1194 else 1195 MaxVal = 0; 1196 } else { 1197 MinVal = 0; 1198 MaxVal = ~0ULL >> (64-OperandBitSize); 1199 } 1200 1201 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1202 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1203 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1204 --C1; // X >= C0 --> X > (C0-1) 1205 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1206 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1207 } 1208 1209 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1210 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1211 ++C1; // X <= C0 --> X < (C0+1) 1212 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1213 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1214 } 1215 1216 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1217 return DAG.getConstant(0, VT); // X < MIN --> false 1218 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1219 return DAG.getConstant(1, VT); // X >= MIN --> true 1220 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1221 return DAG.getConstant(0, VT); // X > MAX --> false 1222 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1223 return DAG.getConstant(1, VT); // X <= MAX --> true 1224 1225 // Canonicalize setgt X, Min --> setne X, Min 1226 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1227 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1228 // Canonicalize setlt X, Max --> setne X, Max 1229 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1230 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1231 1232 // If we have setult X, 1, turn it into seteq X, 0 1233 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1234 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1235 ISD::SETEQ); 1236 // If we have setugt X, Max-1, turn it into seteq X, Max 1237 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1238 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1239 ISD::SETEQ); 1240 1241 // If we have "setcc X, C0", check to see if we can shrink the immediate 1242 // by changing cc. 1243 1244 // SETUGT X, SINTMAX -> SETLT X, 0 1245 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1246 C1 == (~0ULL >> (65-OperandBitSize))) 1247 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1248 ISD::SETLT); 1249 1250 // FIXME: Implement the rest of these. 1251 1252 // Fold bit comparisons when we can. 1253 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1254 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1255 if (ConstantSDNode *AndRHS = 1256 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1257 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1258 // Perform the xform if the AND RHS is a single bit. 1259 if (isPowerOf2_64(AndRHS->getValue())) { 1260 return DAG.getNode(ISD::SRL, VT, N0, 1261 DAG.getConstant(Log2_64(AndRHS->getValue()), 1262 getShiftAmountTy())); 1263 } 1264 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1265 // (X & 8) == 8 --> (X & 8) >> 3 1266 // Perform the xform if C1 is a single bit. 1267 if (isPowerOf2_64(C1)) { 1268 return DAG.getNode(ISD::SRL, VT, N0, 1269 DAG.getConstant(Log2_64(C1), getShiftAmountTy())); 1270 } 1271 } 1272 } 1273 } 1274 } else if (isa<ConstantSDNode>(N0.Val)) { 1275 // Ensure that the constant occurs on the RHS. 1276 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1277 } 1278 1279 if (isa<ConstantFPSDNode>(N0.Val)) { 1280 // Constant fold or commute setcc. 1281 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1282 if (O.Val) return O; 1283 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1284 // If the RHS of an FP comparison is a constant, simplify it away in 1285 // some cases. 1286 if (CFP->getValueAPF().isNaN()) { 1287 // If an operand is known to be a nan, we can fold it. 1288 switch (ISD::getUnorderedFlavor(Cond)) { 1289 default: assert(0 && "Unknown flavor!"); 1290 case 0: // Known false. 1291 return DAG.getConstant(0, VT); 1292 case 1: // Known true. 1293 return DAG.getConstant(1, VT); 1294 case 2: // undefind. 1295 return DAG.getNode(ISD::UNDEF, VT); 1296 } 1297 } 1298 1299 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1300 // constant if knowing that the operand is non-nan is enough. We prefer to 1301 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1302 // materialize 0.0. 1303 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1304 return DAG.getSetCC(VT, N0, N0, Cond); 1305 } 1306 1307 if (N0 == N1) { 1308 // We can always fold X == X for integer setcc's. 1309 if (MVT::isInteger(N0.getValueType())) 1310 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1311 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1312 if (UOF == 2) // FP operators that are undefined on NaNs. 1313 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1314 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1315 return DAG.getConstant(UOF, VT); 1316 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1317 // if it is not already. 1318 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1319 if (NewCond != Cond) 1320 return DAG.getSetCC(VT, N0, N1, NewCond); 1321 } 1322 1323 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1324 MVT::isInteger(N0.getValueType())) { 1325 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1326 N0.getOpcode() == ISD::XOR) { 1327 // Simplify (X+Y) == (X+Z) --> Y == Z 1328 if (N0.getOpcode() == N1.getOpcode()) { 1329 if (N0.getOperand(0) == N1.getOperand(0)) 1330 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1331 if (N0.getOperand(1) == N1.getOperand(1)) 1332 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1333 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1334 // If X op Y == Y op X, try other combinations. 1335 if (N0.getOperand(0) == N1.getOperand(1)) 1336 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1337 if (N0.getOperand(1) == N1.getOperand(0)) 1338 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1339 } 1340 } 1341 1342 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1343 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1344 // Turn (X+C1) == C2 --> X == C2-C1 1345 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1346 return DAG.getSetCC(VT, N0.getOperand(0), 1347 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1348 N0.getValueType()), Cond); 1349 } 1350 1351 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1352 if (N0.getOpcode() == ISD::XOR) 1353 // If we know that all of the inverted bits are zero, don't bother 1354 // performing the inversion. 1355 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 1356 return DAG.getSetCC(VT, N0.getOperand(0), 1357 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 1358 N0.getValueType()), Cond); 1359 } 1360 1361 // Turn (C1-X) == C2 --> X == C1-C2 1362 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1363 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1364 return DAG.getSetCC(VT, N0.getOperand(1), 1365 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 1366 N0.getValueType()), Cond); 1367 } 1368 } 1369 } 1370 1371 // Simplify (X+Z) == X --> Z == 0 1372 if (N0.getOperand(0) == N1) 1373 return DAG.getSetCC(VT, N0.getOperand(1), 1374 DAG.getConstant(0, N0.getValueType()), Cond); 1375 if (N0.getOperand(1) == N1) { 1376 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1377 return DAG.getSetCC(VT, N0.getOperand(0), 1378 DAG.getConstant(0, N0.getValueType()), Cond); 1379 else if (N0.Val->hasOneUse()) { 1380 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1381 // (Z-X) == X --> Z == X<<1 1382 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1383 N1, 1384 DAG.getConstant(1, getShiftAmountTy())); 1385 if (!DCI.isCalledByLegalizer()) 1386 DCI.AddToWorklist(SH.Val); 1387 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1388 } 1389 } 1390 } 1391 1392 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1393 N1.getOpcode() == ISD::XOR) { 1394 // Simplify X == (X+Z) --> Z == 0 1395 if (N1.getOperand(0) == N0) { 1396 return DAG.getSetCC(VT, N1.getOperand(1), 1397 DAG.getConstant(0, N1.getValueType()), Cond); 1398 } else if (N1.getOperand(1) == N0) { 1399 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1400 return DAG.getSetCC(VT, N1.getOperand(0), 1401 DAG.getConstant(0, N1.getValueType()), Cond); 1402 } else if (N1.Val->hasOneUse()) { 1403 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1404 // X == (Z-X) --> X<<1 == Z 1405 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1406 DAG.getConstant(1, getShiftAmountTy())); 1407 if (!DCI.isCalledByLegalizer()) 1408 DCI.AddToWorklist(SH.Val); 1409 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1410 } 1411 } 1412 } 1413 } 1414 1415 // Fold away ALL boolean setcc's. 1416 SDOperand Temp; 1417 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1418 switch (Cond) { 1419 default: assert(0 && "Unknown integer setcc!"); 1420 case ISD::SETEQ: // X == Y -> (X^Y)^1 1421 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1422 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1423 if (!DCI.isCalledByLegalizer()) 1424 DCI.AddToWorklist(Temp.Val); 1425 break; 1426 case ISD::SETNE: // X != Y --> (X^Y) 1427 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1428 break; 1429 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1430 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1431 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1432 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1433 if (!DCI.isCalledByLegalizer()) 1434 DCI.AddToWorklist(Temp.Val); 1435 break; 1436 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1437 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1438 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1439 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1440 if (!DCI.isCalledByLegalizer()) 1441 DCI.AddToWorklist(Temp.Val); 1442 break; 1443 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1444 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1445 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1446 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1447 if (!DCI.isCalledByLegalizer()) 1448 DCI.AddToWorklist(Temp.Val); 1449 break; 1450 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1451 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1452 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1453 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1454 break; 1455 } 1456 if (VT != MVT::i1) { 1457 if (!DCI.isCalledByLegalizer()) 1458 DCI.AddToWorklist(N0.Val); 1459 // FIXME: If running after legalize, we probably can't do this. 1460 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1461 } 1462 return N0; 1463 } 1464 1465 // Could not fold it. 1466 return SDOperand(); 1467} 1468 1469SDOperand TargetLowering:: 1470PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1471 // Default implementation: no optimization. 1472 return SDOperand(); 1473} 1474 1475//===----------------------------------------------------------------------===// 1476// Inline Assembler Implementation Methods 1477//===----------------------------------------------------------------------===// 1478 1479TargetLowering::ConstraintType 1480TargetLowering::getConstraintType(const std::string &Constraint) const { 1481 // FIXME: lots more standard ones to handle. 1482 if (Constraint.size() == 1) { 1483 switch (Constraint[0]) { 1484 default: break; 1485 case 'r': return C_RegisterClass; 1486 case 'm': // memory 1487 case 'o': // offsetable 1488 case 'V': // not offsetable 1489 return C_Memory; 1490 case 'i': // Simple Integer or Relocatable Constant 1491 case 'n': // Simple Integer 1492 case 's': // Relocatable Constant 1493 case 'X': // Allow ANY value. 1494 case 'I': // Target registers. 1495 case 'J': 1496 case 'K': 1497 case 'L': 1498 case 'M': 1499 case 'N': 1500 case 'O': 1501 case 'P': 1502 return C_Other; 1503 } 1504 } 1505 1506 if (Constraint.size() > 1 && Constraint[0] == '{' && 1507 Constraint[Constraint.size()-1] == '}') 1508 return C_Register; 1509 return C_Unknown; 1510} 1511 1512/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1513/// vector. If it is invalid, don't add anything to Ops. 1514void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1515 char ConstraintLetter, 1516 std::vector<SDOperand> &Ops, 1517 SelectionDAG &DAG) { 1518 switch (ConstraintLetter) { 1519 default: break; 1520 case 'X': // Allows any operand; labels (basic block) use this. 1521 if (Op.getOpcode() == ISD::BasicBlock) { 1522 Ops.push_back(Op); 1523 return; 1524 } 1525 // fall through 1526 case 'i': // Simple Integer or Relocatable Constant 1527 case 'n': // Simple Integer 1528 case 's': { // Relocatable Constant 1529 // These operands are interested in values of the form (GV+C), where C may 1530 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1531 // is possible and fine if either GV or C are missing. 1532 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1533 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1534 1535 // If we have "(add GV, C)", pull out GV/C 1536 if (Op.getOpcode() == ISD::ADD) { 1537 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1538 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1539 if (C == 0 || GA == 0) { 1540 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1541 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1542 } 1543 if (C == 0 || GA == 0) 1544 C = 0, GA = 0; 1545 } 1546 1547 // If we find a valid operand, map to the TargetXXX version so that the 1548 // value itself doesn't get selected. 1549 if (GA) { // Either &GV or &GV+C 1550 if (ConstraintLetter != 'n') { 1551 int64_t Offs = GA->getOffset(); 1552 if (C) Offs += C->getValue(); 1553 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1554 Op.getValueType(), Offs)); 1555 return; 1556 } 1557 } 1558 if (C) { // just C, no GV. 1559 // Simple constants are not allowed for 's'. 1560 if (ConstraintLetter != 's') { 1561 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1562 return; 1563 } 1564 } 1565 break; 1566 } 1567 } 1568} 1569 1570std::vector<unsigned> TargetLowering:: 1571getRegClassForInlineAsmConstraint(const std::string &Constraint, 1572 MVT::ValueType VT) const { 1573 return std::vector<unsigned>(); 1574} 1575 1576 1577std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1578getRegForInlineAsmConstraint(const std::string &Constraint, 1579 MVT::ValueType VT) const { 1580 if (Constraint[0] != '{') 1581 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1582 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1583 1584 // Remove the braces from around the name. 1585 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1586 1587 // Figure out which register class contains this reg. 1588 const MRegisterInfo *RI = TM.getRegisterInfo(); 1589 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1590 E = RI->regclass_end(); RCI != E; ++RCI) { 1591 const TargetRegisterClass *RC = *RCI; 1592 1593 // If none of the the value types for this register class are valid, we 1594 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1595 bool isLegal = false; 1596 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1597 I != E; ++I) { 1598 if (isTypeLegal(*I)) { 1599 isLegal = true; 1600 break; 1601 } 1602 } 1603 1604 if (!isLegal) continue; 1605 1606 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1607 I != E; ++I) { 1608 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1609 return std::make_pair(*I, RC); 1610 } 1611 } 1612 1613 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1614} 1615 1616//===----------------------------------------------------------------------===// 1617// Loop Strength Reduction hooks 1618//===----------------------------------------------------------------------===// 1619 1620/// isLegalAddressingMode - Return true if the addressing mode represented 1621/// by AM is legal for this target, for a load/store of the specified type. 1622bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1623 const Type *Ty) const { 1624 // The default implementation of this implements a conservative RISCy, r+r and 1625 // r+i addr mode. 1626 1627 // Allows a sign-extended 16-bit immediate field. 1628 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1629 return false; 1630 1631 // No global is ever allowed as a base. 1632 if (AM.BaseGV) 1633 return false; 1634 1635 // Only support r+r, 1636 switch (AM.Scale) { 1637 case 0: // "r+i" or just "i", depending on HasBaseReg. 1638 break; 1639 case 1: 1640 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1641 return false; 1642 // Otherwise we have r+r or r+i. 1643 break; 1644 case 2: 1645 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1646 return false; 1647 // Allow 2*r as r+r. 1648 break; 1649 } 1650 1651 return true; 1652} 1653 1654// Magic for divide replacement 1655 1656struct ms { 1657 int64_t m; // magic number 1658 int64_t s; // shift amount 1659}; 1660 1661struct mu { 1662 uint64_t m; // magic number 1663 int64_t a; // add indicator 1664 int64_t s; // shift amount 1665}; 1666 1667/// magic - calculate the magic numbers required to codegen an integer sdiv as 1668/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1669/// or -1. 1670static ms magic32(int32_t d) { 1671 int32_t p; 1672 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1673 const uint32_t two31 = 0x80000000U; 1674 struct ms mag; 1675 1676 ad = abs(d); 1677 t = two31 + ((uint32_t)d >> 31); 1678 anc = t - 1 - t%ad; // absolute value of nc 1679 p = 31; // initialize p 1680 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1681 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1682 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1683 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1684 do { 1685 p = p + 1; 1686 q1 = 2*q1; // update q1 = 2p/abs(nc) 1687 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1688 if (r1 >= anc) { // must be unsigned comparison 1689 q1 = q1 + 1; 1690 r1 = r1 - anc; 1691 } 1692 q2 = 2*q2; // update q2 = 2p/abs(d) 1693 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1694 if (r2 >= ad) { // must be unsigned comparison 1695 q2 = q2 + 1; 1696 r2 = r2 - ad; 1697 } 1698 delta = ad - r2; 1699 } while (q1 < delta || (q1 == delta && r1 == 0)); 1700 1701 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1702 if (d < 0) mag.m = -mag.m; // resulting magic number 1703 mag.s = p - 32; // resulting shift 1704 return mag; 1705} 1706 1707/// magicu - calculate the magic numbers required to codegen an integer udiv as 1708/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1709static mu magicu32(uint32_t d) { 1710 int32_t p; 1711 uint32_t nc, delta, q1, r1, q2, r2; 1712 struct mu magu; 1713 magu.a = 0; // initialize "add" indicator 1714 nc = - 1 - (-d)%d; 1715 p = 31; // initialize p 1716 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1717 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1718 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1719 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1720 do { 1721 p = p + 1; 1722 if (r1 >= nc - r1 ) { 1723 q1 = 2*q1 + 1; // update q1 1724 r1 = 2*r1 - nc; // update r1 1725 } 1726 else { 1727 q1 = 2*q1; // update q1 1728 r1 = 2*r1; // update r1 1729 } 1730 if (r2 + 1 >= d - r2) { 1731 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1732 q2 = 2*q2 + 1; // update q2 1733 r2 = 2*r2 + 1 - d; // update r2 1734 } 1735 else { 1736 if (q2 >= 0x80000000) magu.a = 1; 1737 q2 = 2*q2; // update q2 1738 r2 = 2*r2 + 1; // update r2 1739 } 1740 delta = d - 1 - r2; 1741 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1742 magu.m = q2 + 1; // resulting magic number 1743 magu.s = p - 32; // resulting shift 1744 return magu; 1745} 1746 1747/// magic - calculate the magic numbers required to codegen an integer sdiv as 1748/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1749/// or -1. 1750static ms magic64(int64_t d) { 1751 int64_t p; 1752 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1753 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1754 struct ms mag; 1755 1756 ad = d >= 0 ? d : -d; 1757 t = two63 + ((uint64_t)d >> 63); 1758 anc = t - 1 - t%ad; // absolute value of nc 1759 p = 63; // initialize p 1760 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1761 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1762 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1763 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1764 do { 1765 p = p + 1; 1766 q1 = 2*q1; // update q1 = 2p/abs(nc) 1767 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1768 if (r1 >= anc) { // must be unsigned comparison 1769 q1 = q1 + 1; 1770 r1 = r1 - anc; 1771 } 1772 q2 = 2*q2; // update q2 = 2p/abs(d) 1773 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1774 if (r2 >= ad) { // must be unsigned comparison 1775 q2 = q2 + 1; 1776 r2 = r2 - ad; 1777 } 1778 delta = ad - r2; 1779 } while (q1 < delta || (q1 == delta && r1 == 0)); 1780 1781 mag.m = q2 + 1; 1782 if (d < 0) mag.m = -mag.m; // resulting magic number 1783 mag.s = p - 64; // resulting shift 1784 return mag; 1785} 1786 1787/// magicu - calculate the magic numbers required to codegen an integer udiv as 1788/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1789static mu magicu64(uint64_t d) 1790{ 1791 int64_t p; 1792 uint64_t nc, delta, q1, r1, q2, r2; 1793 struct mu magu; 1794 magu.a = 0; // initialize "add" indicator 1795 nc = - 1 - (-d)%d; 1796 p = 63; // initialize p 1797 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1798 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1799 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1800 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1801 do { 1802 p = p + 1; 1803 if (r1 >= nc - r1 ) { 1804 q1 = 2*q1 + 1; // update q1 1805 r1 = 2*r1 - nc; // update r1 1806 } 1807 else { 1808 q1 = 2*q1; // update q1 1809 r1 = 2*r1; // update r1 1810 } 1811 if (r2 + 1 >= d - r2) { 1812 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1813 q2 = 2*q2 + 1; // update q2 1814 r2 = 2*r2 + 1 - d; // update r2 1815 } 1816 else { 1817 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1818 q2 = 2*q2; // update q2 1819 r2 = 2*r2 + 1; // update r2 1820 } 1821 delta = d - 1 - r2; 1822 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1823 magu.m = q2 + 1; // resulting magic number 1824 magu.s = p - 64; // resulting shift 1825 return magu; 1826} 1827 1828/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1829/// return a DAG expression to select that will generate the same value by 1830/// multiplying by a magic number. See: 1831/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1832SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1833 std::vector<SDNode*>* Created) const { 1834 MVT::ValueType VT = N->getValueType(0); 1835 1836 // Check to see if we can do this. 1837 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1838 return SDOperand(); // BuildSDIV only operates on i32 or i64 1839 1840 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1841 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1842 1843 // Multiply the numerator (operand 0) by the magic value 1844 SDOperand Q; 1845 if (isOperationLegal(ISD::MULHS, VT)) 1846 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1847 DAG.getConstant(magics.m, VT)); 1848 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1849 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1850 N->getOperand(0), 1851 DAG.getConstant(magics.m, VT)).Val, 1); 1852 else 1853 return SDOperand(); // No mulhs or equvialent 1854 // If d > 0 and m < 0, add the numerator 1855 if (d > 0 && magics.m < 0) { 1856 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1857 if (Created) 1858 Created->push_back(Q.Val); 1859 } 1860 // If d < 0 and m > 0, subtract the numerator. 1861 if (d < 0 && magics.m > 0) { 1862 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1863 if (Created) 1864 Created->push_back(Q.Val); 1865 } 1866 // Shift right algebraic if shift value is nonzero 1867 if (magics.s > 0) { 1868 Q = DAG.getNode(ISD::SRA, VT, Q, 1869 DAG.getConstant(magics.s, getShiftAmountTy())); 1870 if (Created) 1871 Created->push_back(Q.Val); 1872 } 1873 // Extract the sign bit and add it to the quotient 1874 SDOperand T = 1875 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1876 getShiftAmountTy())); 1877 if (Created) 1878 Created->push_back(T.Val); 1879 return DAG.getNode(ISD::ADD, VT, Q, T); 1880} 1881 1882/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1883/// return a DAG expression to select that will generate the same value by 1884/// multiplying by a magic number. See: 1885/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1886SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1887 std::vector<SDNode*>* Created) const { 1888 MVT::ValueType VT = N->getValueType(0); 1889 1890 // Check to see if we can do this. 1891 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1892 return SDOperand(); // BuildUDIV only operates on i32 or i64 1893 1894 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1895 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1896 1897 // Multiply the numerator (operand 0) by the magic value 1898 SDOperand Q; 1899 if (isOperationLegal(ISD::MULHU, VT)) 1900 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1901 DAG.getConstant(magics.m, VT)); 1902 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 1903 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 1904 N->getOperand(0), 1905 DAG.getConstant(magics.m, VT)).Val, 1); 1906 else 1907 return SDOperand(); // No mulhu or equvialent 1908 if (Created) 1909 Created->push_back(Q.Val); 1910 1911 if (magics.a == 0) { 1912 return DAG.getNode(ISD::SRL, VT, Q, 1913 DAG.getConstant(magics.s, getShiftAmountTy())); 1914 } else { 1915 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1916 if (Created) 1917 Created->push_back(NPQ.Val); 1918 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1919 DAG.getConstant(1, getShiftAmountTy())); 1920 if (Created) 1921 Created->push_back(NPQ.Val); 1922 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1923 if (Created) 1924 Created->push_back(NPQ.Val); 1925 return DAG.getNode(ISD::SRL, VT, NPQ, 1926 DAG.getConstant(magics.s-1, getShiftAmountTy())); 1927 } 1928} 1929