TargetLowering.cpp revision 64fa4a9584113f63eccc1a650e7e0cc4ddbab3f6
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetLoweringObjectFile.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/Target/TargetSubtarget.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28using namespace llvm; 29 30namespace llvm { 31TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 32 bool isLocal = GV->hasLocalLinkage(); 33 bool isDeclaration = GV->isDeclaration(); 34 // FIXME: what should we do for protected and internal visibility? 35 // For variables, is internal different from hidden? 36 bool isHidden = GV->hasHiddenVisibility(); 37 38 if (reloc == Reloc::PIC_) { 39 if (isLocal || isHidden) 40 return TLSModel::LocalDynamic; 41 else 42 return TLSModel::GeneralDynamic; 43 } else { 44 if (!isDeclaration || isHidden) 45 return TLSModel::LocalExec; 46 else 47 return TLSModel::InitialExec; 48 } 49} 50} 51 52/// InitLibcallNames - Set default libcall names. 53/// 54static void InitLibcallNames(const char **Names) { 55 Names[RTLIB::SHL_I16] = "__ashlhi3"; 56 Names[RTLIB::SHL_I32] = "__ashlsi3"; 57 Names[RTLIB::SHL_I64] = "__ashldi3"; 58 Names[RTLIB::SHL_I128] = "__ashlti3"; 59 Names[RTLIB::SRL_I16] = "__lshrhi3"; 60 Names[RTLIB::SRL_I32] = "__lshrsi3"; 61 Names[RTLIB::SRL_I64] = "__lshrdi3"; 62 Names[RTLIB::SRL_I128] = "__lshrti3"; 63 Names[RTLIB::SRA_I16] = "__ashrhi3"; 64 Names[RTLIB::SRA_I32] = "__ashrsi3"; 65 Names[RTLIB::SRA_I64] = "__ashrdi3"; 66 Names[RTLIB::SRA_I128] = "__ashrti3"; 67 Names[RTLIB::MUL_I8] = "__mulqi3"; 68 Names[RTLIB::MUL_I16] = "__mulhi3"; 69 Names[RTLIB::MUL_I32] = "__mulsi3"; 70 Names[RTLIB::MUL_I64] = "__muldi3"; 71 Names[RTLIB::MUL_I128] = "__multi3"; 72 Names[RTLIB::SDIV_I8] = "__divqi3"; 73 Names[RTLIB::SDIV_I16] = "__divhi3"; 74 Names[RTLIB::SDIV_I32] = "__divsi3"; 75 Names[RTLIB::SDIV_I64] = "__divdi3"; 76 Names[RTLIB::SDIV_I128] = "__divti3"; 77 Names[RTLIB::UDIV_I8] = "__udivqi3"; 78 Names[RTLIB::UDIV_I16] = "__udivhi3"; 79 Names[RTLIB::UDIV_I32] = "__udivsi3"; 80 Names[RTLIB::UDIV_I64] = "__udivdi3"; 81 Names[RTLIB::UDIV_I128] = "__udivti3"; 82 Names[RTLIB::SREM_I8] = "__modqi3"; 83 Names[RTLIB::SREM_I16] = "__modhi3"; 84 Names[RTLIB::SREM_I32] = "__modsi3"; 85 Names[RTLIB::SREM_I64] = "__moddi3"; 86 Names[RTLIB::SREM_I128] = "__modti3"; 87 Names[RTLIB::UREM_I8] = "__umodqi3"; 88 Names[RTLIB::UREM_I16] = "__umodhi3"; 89 Names[RTLIB::UREM_I32] = "__umodsi3"; 90 Names[RTLIB::UREM_I64] = "__umoddi3"; 91 Names[RTLIB::UREM_I128] = "__umodti3"; 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 98 Names[RTLIB::SUB_F32] = "__subsf3"; 99 Names[RTLIB::SUB_F64] = "__subdf3"; 100 Names[RTLIB::SUB_F80] = "__subxf3"; 101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 102 Names[RTLIB::MUL_F32] = "__mulsf3"; 103 Names[RTLIB::MUL_F64] = "__muldf3"; 104 Names[RTLIB::MUL_F80] = "__mulxf3"; 105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 106 Names[RTLIB::DIV_F32] = "__divsf3"; 107 Names[RTLIB::DIV_F64] = "__divdf3"; 108 Names[RTLIB::DIV_F80] = "__divxf3"; 109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 110 Names[RTLIB::REM_F32] = "fmodf"; 111 Names[RTLIB::REM_F64] = "fmod"; 112 Names[RTLIB::REM_F80] = "fmodl"; 113 Names[RTLIB::REM_PPCF128] = "fmodl"; 114 Names[RTLIB::POWI_F32] = "__powisf2"; 115 Names[RTLIB::POWI_F64] = "__powidf2"; 116 Names[RTLIB::POWI_F80] = "__powixf2"; 117 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 118 Names[RTLIB::SQRT_F32] = "sqrtf"; 119 Names[RTLIB::SQRT_F64] = "sqrt"; 120 Names[RTLIB::SQRT_F80] = "sqrtl"; 121 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 122 Names[RTLIB::LOG_F32] = "logf"; 123 Names[RTLIB::LOG_F64] = "log"; 124 Names[RTLIB::LOG_F80] = "logl"; 125 Names[RTLIB::LOG_PPCF128] = "logl"; 126 Names[RTLIB::LOG2_F32] = "log2f"; 127 Names[RTLIB::LOG2_F64] = "log2"; 128 Names[RTLIB::LOG2_F80] = "log2l"; 129 Names[RTLIB::LOG2_PPCF128] = "log2l"; 130 Names[RTLIB::LOG10_F32] = "log10f"; 131 Names[RTLIB::LOG10_F64] = "log10"; 132 Names[RTLIB::LOG10_F80] = "log10l"; 133 Names[RTLIB::LOG10_PPCF128] = "log10l"; 134 Names[RTLIB::EXP_F32] = "expf"; 135 Names[RTLIB::EXP_F64] = "exp"; 136 Names[RTLIB::EXP_F80] = "expl"; 137 Names[RTLIB::EXP_PPCF128] = "expl"; 138 Names[RTLIB::EXP2_F32] = "exp2f"; 139 Names[RTLIB::EXP2_F64] = "exp2"; 140 Names[RTLIB::EXP2_F80] = "exp2l"; 141 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 142 Names[RTLIB::SIN_F32] = "sinf"; 143 Names[RTLIB::SIN_F64] = "sin"; 144 Names[RTLIB::SIN_F80] = "sinl"; 145 Names[RTLIB::SIN_PPCF128] = "sinl"; 146 Names[RTLIB::COS_F32] = "cosf"; 147 Names[RTLIB::COS_F64] = "cos"; 148 Names[RTLIB::COS_F80] = "cosl"; 149 Names[RTLIB::COS_PPCF128] = "cosl"; 150 Names[RTLIB::POW_F32] = "powf"; 151 Names[RTLIB::POW_F64] = "pow"; 152 Names[RTLIB::POW_F80] = "powl"; 153 Names[RTLIB::POW_PPCF128] = "powl"; 154 Names[RTLIB::CEIL_F32] = "ceilf"; 155 Names[RTLIB::CEIL_F64] = "ceil"; 156 Names[RTLIB::CEIL_F80] = "ceill"; 157 Names[RTLIB::CEIL_PPCF128] = "ceill"; 158 Names[RTLIB::TRUNC_F32] = "truncf"; 159 Names[RTLIB::TRUNC_F64] = "trunc"; 160 Names[RTLIB::TRUNC_F80] = "truncl"; 161 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 162 Names[RTLIB::RINT_F32] = "rintf"; 163 Names[RTLIB::RINT_F64] = "rint"; 164 Names[RTLIB::RINT_F80] = "rintl"; 165 Names[RTLIB::RINT_PPCF128] = "rintl"; 166 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 167 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 168 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 169 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 170 Names[RTLIB::FLOOR_F32] = "floorf"; 171 Names[RTLIB::FLOOR_F64] = "floor"; 172 Names[RTLIB::FLOOR_F80] = "floorl"; 173 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 174 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 175 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 176 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 177 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 178 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 179 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 180 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 181 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 182 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 183 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 184 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 185 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 186 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 187 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 188 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 189 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 190 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 191 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 192 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 193 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 194 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 195 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 196 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 197 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 198 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 199 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 200 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 201 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 202 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 203 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 204 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 205 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 206 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 207 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 208 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 209 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 210 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 211 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 212 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 213 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 214 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 215 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 216 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 217 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 218 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 219 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 220 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 221 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 222 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 223 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 224 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 225 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 226 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 227 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 228 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 229 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 230 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 231 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 232 Names[RTLIB::OEQ_F32] = "__eqsf2"; 233 Names[RTLIB::OEQ_F64] = "__eqdf2"; 234 Names[RTLIB::UNE_F32] = "__nesf2"; 235 Names[RTLIB::UNE_F64] = "__nedf2"; 236 Names[RTLIB::OGE_F32] = "__gesf2"; 237 Names[RTLIB::OGE_F64] = "__gedf2"; 238 Names[RTLIB::OLT_F32] = "__ltsf2"; 239 Names[RTLIB::OLT_F64] = "__ltdf2"; 240 Names[RTLIB::OLE_F32] = "__lesf2"; 241 Names[RTLIB::OLE_F64] = "__ledf2"; 242 Names[RTLIB::OGT_F32] = "__gtsf2"; 243 Names[RTLIB::OGT_F64] = "__gtdf2"; 244 Names[RTLIB::UO_F32] = "__unordsf2"; 245 Names[RTLIB::UO_F64] = "__unorddf2"; 246 Names[RTLIB::O_F32] = "__unordsf2"; 247 Names[RTLIB::O_F64] = "__unorddf2"; 248 Names[RTLIB::MEMCPY] = "memcpy"; 249 Names[RTLIB::MEMMOVE] = "memmove"; 250 Names[RTLIB::MEMSET] = "memset"; 251 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 252} 253 254/// InitLibcallCallingConvs - Set default libcall CallingConvs. 255/// 256static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 257 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 258 CCs[i] = CallingConv::C; 259 } 260} 261 262/// getFPEXT - Return the FPEXT_*_* value for the given types, or 263/// UNKNOWN_LIBCALL if there is none. 264RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 265 if (OpVT == MVT::f32) { 266 if (RetVT == MVT::f64) 267 return FPEXT_F32_F64; 268 } 269 return UNKNOWN_LIBCALL; 270} 271 272/// getFPROUND - Return the FPROUND_*_* value for the given types, or 273/// UNKNOWN_LIBCALL if there is none. 274RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 275 if (RetVT == MVT::f32) { 276 if (OpVT == MVT::f64) 277 return FPROUND_F64_F32; 278 if (OpVT == MVT::f80) 279 return FPROUND_F80_F32; 280 if (OpVT == MVT::ppcf128) 281 return FPROUND_PPCF128_F32; 282 } else if (RetVT == MVT::f64) { 283 if (OpVT == MVT::f80) 284 return FPROUND_F80_F64; 285 if (OpVT == MVT::ppcf128) 286 return FPROUND_PPCF128_F64; 287 } 288 return UNKNOWN_LIBCALL; 289} 290 291/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 292/// UNKNOWN_LIBCALL if there is none. 293RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 294 if (OpVT == MVT::f32) { 295 if (RetVT == MVT::i8) 296 return FPTOSINT_F32_I8; 297 if (RetVT == MVT::i16) 298 return FPTOSINT_F32_I16; 299 if (RetVT == MVT::i32) 300 return FPTOSINT_F32_I32; 301 if (RetVT == MVT::i64) 302 return FPTOSINT_F32_I64; 303 if (RetVT == MVT::i128) 304 return FPTOSINT_F32_I128; 305 } else if (OpVT == MVT::f64) { 306 if (RetVT == MVT::i32) 307 return FPTOSINT_F64_I32; 308 if (RetVT == MVT::i64) 309 return FPTOSINT_F64_I64; 310 if (RetVT == MVT::i128) 311 return FPTOSINT_F64_I128; 312 } else if (OpVT == MVT::f80) { 313 if (RetVT == MVT::i32) 314 return FPTOSINT_F80_I32; 315 if (RetVT == MVT::i64) 316 return FPTOSINT_F80_I64; 317 if (RetVT == MVT::i128) 318 return FPTOSINT_F80_I128; 319 } else if (OpVT == MVT::ppcf128) { 320 if (RetVT == MVT::i32) 321 return FPTOSINT_PPCF128_I32; 322 if (RetVT == MVT::i64) 323 return FPTOSINT_PPCF128_I64; 324 if (RetVT == MVT::i128) 325 return FPTOSINT_PPCF128_I128; 326 } 327 return UNKNOWN_LIBCALL; 328} 329 330/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 331/// UNKNOWN_LIBCALL if there is none. 332RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 333 if (OpVT == MVT::f32) { 334 if (RetVT == MVT::i8) 335 return FPTOUINT_F32_I8; 336 if (RetVT == MVT::i16) 337 return FPTOUINT_F32_I16; 338 if (RetVT == MVT::i32) 339 return FPTOUINT_F32_I32; 340 if (RetVT == MVT::i64) 341 return FPTOUINT_F32_I64; 342 if (RetVT == MVT::i128) 343 return FPTOUINT_F32_I128; 344 } else if (OpVT == MVT::f64) { 345 if (RetVT == MVT::i32) 346 return FPTOUINT_F64_I32; 347 if (RetVT == MVT::i64) 348 return FPTOUINT_F64_I64; 349 if (RetVT == MVT::i128) 350 return FPTOUINT_F64_I128; 351 } else if (OpVT == MVT::f80) { 352 if (RetVT == MVT::i32) 353 return FPTOUINT_F80_I32; 354 if (RetVT == MVT::i64) 355 return FPTOUINT_F80_I64; 356 if (RetVT == MVT::i128) 357 return FPTOUINT_F80_I128; 358 } else if (OpVT == MVT::ppcf128) { 359 if (RetVT == MVT::i32) 360 return FPTOUINT_PPCF128_I32; 361 if (RetVT == MVT::i64) 362 return FPTOUINT_PPCF128_I64; 363 if (RetVT == MVT::i128) 364 return FPTOUINT_PPCF128_I128; 365 } 366 return UNKNOWN_LIBCALL; 367} 368 369/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 370/// UNKNOWN_LIBCALL if there is none. 371RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 372 if (OpVT == MVT::i32) { 373 if (RetVT == MVT::f32) 374 return SINTTOFP_I32_F32; 375 else if (RetVT == MVT::f64) 376 return SINTTOFP_I32_F64; 377 else if (RetVT == MVT::f80) 378 return SINTTOFP_I32_F80; 379 else if (RetVT == MVT::ppcf128) 380 return SINTTOFP_I32_PPCF128; 381 } else if (OpVT == MVT::i64) { 382 if (RetVT == MVT::f32) 383 return SINTTOFP_I64_F32; 384 else if (RetVT == MVT::f64) 385 return SINTTOFP_I64_F64; 386 else if (RetVT == MVT::f80) 387 return SINTTOFP_I64_F80; 388 else if (RetVT == MVT::ppcf128) 389 return SINTTOFP_I64_PPCF128; 390 } else if (OpVT == MVT::i128) { 391 if (RetVT == MVT::f32) 392 return SINTTOFP_I128_F32; 393 else if (RetVT == MVT::f64) 394 return SINTTOFP_I128_F64; 395 else if (RetVT == MVT::f80) 396 return SINTTOFP_I128_F80; 397 else if (RetVT == MVT::ppcf128) 398 return SINTTOFP_I128_PPCF128; 399 } 400 return UNKNOWN_LIBCALL; 401} 402 403/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 404/// UNKNOWN_LIBCALL if there is none. 405RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 406 if (OpVT == MVT::i32) { 407 if (RetVT == MVT::f32) 408 return UINTTOFP_I32_F32; 409 else if (RetVT == MVT::f64) 410 return UINTTOFP_I32_F64; 411 else if (RetVT == MVT::f80) 412 return UINTTOFP_I32_F80; 413 else if (RetVT == MVT::ppcf128) 414 return UINTTOFP_I32_PPCF128; 415 } else if (OpVT == MVT::i64) { 416 if (RetVT == MVT::f32) 417 return UINTTOFP_I64_F32; 418 else if (RetVT == MVT::f64) 419 return UINTTOFP_I64_F64; 420 else if (RetVT == MVT::f80) 421 return UINTTOFP_I64_F80; 422 else if (RetVT == MVT::ppcf128) 423 return UINTTOFP_I64_PPCF128; 424 } else if (OpVT == MVT::i128) { 425 if (RetVT == MVT::f32) 426 return UINTTOFP_I128_F32; 427 else if (RetVT == MVT::f64) 428 return UINTTOFP_I128_F64; 429 else if (RetVT == MVT::f80) 430 return UINTTOFP_I128_F80; 431 else if (RetVT == MVT::ppcf128) 432 return UINTTOFP_I128_PPCF128; 433 } 434 return UNKNOWN_LIBCALL; 435} 436 437/// InitCmpLibcallCCs - Set default comparison libcall CC. 438/// 439static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 440 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 441 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 442 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 443 CCs[RTLIB::UNE_F32] = ISD::SETNE; 444 CCs[RTLIB::UNE_F64] = ISD::SETNE; 445 CCs[RTLIB::OGE_F32] = ISD::SETGE; 446 CCs[RTLIB::OGE_F64] = ISD::SETGE; 447 CCs[RTLIB::OLT_F32] = ISD::SETLT; 448 CCs[RTLIB::OLT_F64] = ISD::SETLT; 449 CCs[RTLIB::OLE_F32] = ISD::SETLE; 450 CCs[RTLIB::OLE_F64] = ISD::SETLE; 451 CCs[RTLIB::OGT_F32] = ISD::SETGT; 452 CCs[RTLIB::OGT_F64] = ISD::SETGT; 453 CCs[RTLIB::UO_F32] = ISD::SETNE; 454 CCs[RTLIB::UO_F64] = ISD::SETNE; 455 CCs[RTLIB::O_F32] = ISD::SETEQ; 456 CCs[RTLIB::O_F64] = ISD::SETEQ; 457} 458 459/// NOTE: The constructor takes ownership of TLOF. 460TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) 461 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 462 // All operations default to being supported. 463 memset(OpActions, 0, sizeof(OpActions)); 464 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 465 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 466 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 467 memset(ConvertActions, 0, sizeof(ConvertActions)); 468 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 469 470 // Set default actions for various operations. 471 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 472 // Default all indexed load / store to expand. 473 for (unsigned IM = (unsigned)ISD::PRE_INC; 474 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 475 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 476 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 477 } 478 479 // These operations default to expand. 480 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 481 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 482 } 483 484 // Most targets ignore the @llvm.prefetch intrinsic. 485 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 486 487 // ConstantFP nodes default to expand. Targets can either change this to 488 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 489 // to optimize expansions for certain constants. 490 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 491 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 492 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 493 494 // These library functions default to expand. 495 setOperationAction(ISD::FLOG , MVT::f64, Expand); 496 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 497 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 498 setOperationAction(ISD::FEXP , MVT::f64, Expand); 499 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 500 setOperationAction(ISD::FLOG , MVT::f32, Expand); 501 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 502 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 503 setOperationAction(ISD::FEXP , MVT::f32, Expand); 504 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 505 506 // Default ISD::TRAP to expand (which turns it into abort). 507 setOperationAction(ISD::TRAP, MVT::Other, Expand); 508 509 IsLittleEndian = TD->isLittleEndian(); 510 UsesGlobalOffsetTable = false; 511 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 512 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 513 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 514 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 515 benefitFromCodePlacementOpt = false; 516 UseUnderscoreSetJmp = false; 517 UseUnderscoreLongJmp = false; 518 SelectIsExpensive = false; 519 IntDivIsCheap = false; 520 Pow2DivIsCheap = false; 521 StackPointerRegisterToSaveRestore = 0; 522 ExceptionPointerRegister = 0; 523 ExceptionSelectorRegister = 0; 524 BooleanContents = UndefinedBooleanContent; 525 SchedPreferenceInfo = SchedulingForLatency; 526 JumpBufSize = 0; 527 JumpBufAlignment = 0; 528 IfCvtBlockSizeLimit = 2; 529 IfCvtDupBlockSizeLimit = 0; 530 PrefLoopAlignment = 0; 531 532 InitLibcallNames(LibcallRoutineNames); 533 InitCmpLibcallCCs(CmpLibcallCCs); 534 InitLibcallCallingConvs(LibcallCallingConvs); 535} 536 537TargetLowering::~TargetLowering() { 538 delete &TLOF; 539} 540 541static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 542 unsigned &NumIntermediates, 543 EVT &RegisterVT, 544 TargetLowering* TLI) { 545 // Figure out the right, legal destination reg to copy into. 546 unsigned NumElts = VT.getVectorNumElements(); 547 MVT EltTy = VT.getVectorElementType(); 548 549 unsigned NumVectorRegs = 1; 550 551 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 552 // could break down into LHS/RHS like LegalizeDAG does. 553 if (!isPowerOf2_32(NumElts)) { 554 NumVectorRegs = NumElts; 555 NumElts = 1; 556 } 557 558 // Divide the input until we get to a supported size. This will always 559 // end with a scalar if the target doesn't support vectors. 560 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 561 NumElts >>= 1; 562 NumVectorRegs <<= 1; 563 } 564 565 NumIntermediates = NumVectorRegs; 566 567 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 568 if (!TLI->isTypeLegal(NewVT)) 569 NewVT = EltTy; 570 IntermediateVT = NewVT; 571 572 EVT DestVT = TLI->getRegisterType(NewVT); 573 RegisterVT = DestVT; 574 if (EVT(DestVT).bitsLT(NewVT)) { 575 // Value is expanded, e.g. i64 -> i16. 576 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 577 } else { 578 // Otherwise, promotion or legal types use the same number of registers as 579 // the vector decimated to the appropriate level. 580 return NumVectorRegs; 581 } 582 583 return 1; 584} 585 586/// computeRegisterProperties - Once all of the register classes are added, 587/// this allows us to compute derived properties we expose. 588void TargetLowering::computeRegisterProperties() { 589 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 590 "Too many value types for ValueTypeActions to hold!"); 591 592 // Everything defaults to needing one register. 593 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 594 NumRegistersForVT[i] = 1; 595 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 596 } 597 // ...except isVoid, which doesn't need any registers. 598 NumRegistersForVT[MVT::isVoid] = 0; 599 600 // Find the largest integer register class. 601 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 602 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 603 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 604 605 // Every integer value type larger than this largest register takes twice as 606 // many registers to represent as the previous ValueType. 607 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 608 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 609 if (!ExpandedVT.isInteger()) 610 break; 611 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 612 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 613 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 614 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 615 } 616 617 // Inspect all of the ValueType's smaller than the largest integer 618 // register to see which ones need promotion. 619 unsigned LegalIntReg = LargestIntReg; 620 for (unsigned IntReg = LargestIntReg - 1; 621 IntReg >= (unsigned)MVT::i1; --IntReg) { 622 EVT IVT = (MVT::SimpleValueType)IntReg; 623 if (isTypeLegal(IVT)) { 624 LegalIntReg = IntReg; 625 } else { 626 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 627 (MVT::SimpleValueType)LegalIntReg; 628 ValueTypeActions.setTypeAction(IVT, Promote); 629 } 630 } 631 632 // ppcf128 type is really two f64's. 633 if (!isTypeLegal(MVT::ppcf128)) { 634 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 635 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 636 TransformToType[MVT::ppcf128] = MVT::f64; 637 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 638 } 639 640 // Decide how to handle f64. If the target does not have native f64 support, 641 // expand it to i64 and we will be generating soft float library calls. 642 if (!isTypeLegal(MVT::f64)) { 643 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 644 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 645 TransformToType[MVT::f64] = MVT::i64; 646 ValueTypeActions.setTypeAction(MVT::f64, Expand); 647 } 648 649 // Decide how to handle f32. If the target does not have native support for 650 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 651 if (!isTypeLegal(MVT::f32)) { 652 if (isTypeLegal(MVT::f64)) { 653 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 654 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 655 TransformToType[MVT::f32] = MVT::f64; 656 ValueTypeActions.setTypeAction(MVT::f32, Promote); 657 } else { 658 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 659 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 660 TransformToType[MVT::f32] = MVT::i32; 661 ValueTypeActions.setTypeAction(MVT::f32, Expand); 662 } 663 } 664 665 // Loop over all of the vector value types to see which need transformations. 666 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 667 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 668 MVT VT = (MVT::SimpleValueType)i; 669 if (!isTypeLegal(VT)) { 670 MVT IntermediateVT; 671 EVT RegisterVT; 672 unsigned NumIntermediates; 673 NumRegistersForVT[i] = 674 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 675 RegisterVT, this); 676 RegisterTypeForVT[i] = RegisterVT; 677 678 // Determine if there is a legal wider type. 679 bool IsLegalWiderType = false; 680 EVT EltVT = VT.getVectorElementType(); 681 unsigned NElts = VT.getVectorNumElements(); 682 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 683 EVT SVT = (MVT::SimpleValueType)nVT; 684 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 685 SVT.getVectorNumElements() > NElts) { 686 TransformToType[i] = SVT; 687 ValueTypeActions.setTypeAction(VT, Promote); 688 IsLegalWiderType = true; 689 break; 690 } 691 } 692 if (!IsLegalWiderType) { 693 EVT NVT = VT.getPow2VectorType(); 694 if (NVT == VT) { 695 // Type is already a power of 2. The default action is to split. 696 TransformToType[i] = MVT::Other; 697 ValueTypeActions.setTypeAction(VT, Expand); 698 } else { 699 TransformToType[i] = NVT; 700 ValueTypeActions.setTypeAction(VT, Promote); 701 } 702 } 703 } 704 } 705} 706 707const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 708 return NULL; 709} 710 711 712MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 713 return PointerTy.SimpleTy; 714} 715 716/// getVectorTypeBreakdown - Vector types are broken down into some number of 717/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 718/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 719/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 720/// 721/// This method returns the number of registers needed, and the VT for each 722/// register. It also returns the VT and quantity of the intermediate values 723/// before they are promoted/expanded. 724/// 725unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 726 EVT &IntermediateVT, 727 unsigned &NumIntermediates, 728 EVT &RegisterVT) const { 729 // Figure out the right, legal destination reg to copy into. 730 unsigned NumElts = VT.getVectorNumElements(); 731 EVT EltTy = VT.getVectorElementType(); 732 733 unsigned NumVectorRegs = 1; 734 735 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 736 // could break down into LHS/RHS like LegalizeDAG does. 737 if (!isPowerOf2_32(NumElts)) { 738 NumVectorRegs = NumElts; 739 NumElts = 1; 740 } 741 742 // Divide the input until we get to a supported size. This will always 743 // end with a scalar if the target doesn't support vectors. 744 while (NumElts > 1 && !isTypeLegal( 745 EVT::getVectorVT(Context, EltTy, NumElts))) { 746 NumElts >>= 1; 747 NumVectorRegs <<= 1; 748 } 749 750 NumIntermediates = NumVectorRegs; 751 752 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 753 if (!isTypeLegal(NewVT)) 754 NewVT = EltTy; 755 IntermediateVT = NewVT; 756 757 EVT DestVT = getRegisterType(Context, NewVT); 758 RegisterVT = DestVT; 759 if (DestVT.bitsLT(NewVT)) { 760 // Value is expanded, e.g. i64 -> i16. 761 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 762 } else { 763 // Otherwise, promotion or legal types use the same number of registers as 764 // the vector decimated to the appropriate level. 765 return NumVectorRegs; 766 } 767 768 return 1; 769} 770 771/// getWidenVectorType: given a vector type, returns the type to widen to 772/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 773/// If there is no vector type that we want to widen to, returns MVT::Other 774/// When and where to widen is target dependent based on the cost of 775/// scalarizing vs using the wider vector type. 776EVT TargetLowering::getWidenVectorType(EVT VT) const { 777 assert(VT.isVector()); 778 if (isTypeLegal(VT)) 779 return VT; 780 781 // Default is not to widen until moved to LegalizeTypes 782 return MVT::Other; 783} 784 785/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 786/// function arguments in the caller parameter area. This is the actual 787/// alignment, not its logarithm. 788unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 789 return TD->getCallFrameTypeAlignment(Ty); 790} 791 792SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 793 SelectionDAG &DAG) const { 794 if (usesGlobalOffsetTable()) 795 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 796 return Table; 797} 798 799bool 800TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 801 // Assume that everything is safe in static mode. 802 if (getTargetMachine().getRelocationModel() == Reloc::Static) 803 return true; 804 805 // In dynamic-no-pic mode, assume that known defined values are safe. 806 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 807 GA && 808 !GA->getGlobal()->isDeclaration() && 809 !GA->getGlobal()->isWeakForLinker()) 810 return true; 811 812 // Otherwise assume nothing is safe. 813 return false; 814} 815 816//===----------------------------------------------------------------------===// 817// Optimization Methods 818//===----------------------------------------------------------------------===// 819 820/// ShrinkDemandedConstant - Check to see if the specified operand of the 821/// specified instruction is a constant integer. If so, check to see if there 822/// are any bits set in the constant that are not demanded. If so, shrink the 823/// constant and return true. 824bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 825 const APInt &Demanded) { 826 DebugLoc dl = Op.getDebugLoc(); 827 828 // FIXME: ISD::SELECT, ISD::SELECT_CC 829 switch (Op.getOpcode()) { 830 default: break; 831 case ISD::XOR: 832 case ISD::AND: 833 case ISD::OR: { 834 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 835 if (!C) return false; 836 837 if (Op.getOpcode() == ISD::XOR && 838 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 839 return false; 840 841 // if we can expand it to have all bits set, do it 842 if (C->getAPIntValue().intersects(~Demanded)) { 843 EVT VT = Op.getValueType(); 844 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 845 DAG.getConstant(Demanded & 846 C->getAPIntValue(), 847 VT)); 848 return CombineTo(Op, New); 849 } 850 851 break; 852 } 853 } 854 855 return false; 856} 857 858/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 859/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 860/// cast, but it could be generalized for targets with other types of 861/// implicit widening casts. 862bool 863TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 864 unsigned BitWidth, 865 const APInt &Demanded, 866 DebugLoc dl) { 867 assert(Op.getNumOperands() == 2 && 868 "ShrinkDemandedOp only supports binary operators!"); 869 assert(Op.getNode()->getNumValues() == 1 && 870 "ShrinkDemandedOp only supports nodes with one result!"); 871 872 // Don't do this if the node has another user, which may require the 873 // full value. 874 if (!Op.getNode()->hasOneUse()) 875 return false; 876 877 // Search for the smallest integer type with free casts to and from 878 // Op's type. For expedience, just check power-of-2 integer types. 879 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 880 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 881 if (!isPowerOf2_32(SmallVTBits)) 882 SmallVTBits = NextPowerOf2(SmallVTBits); 883 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 884 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 885 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 886 TLI.isZExtFree(SmallVT, Op.getValueType())) { 887 // We found a type with free casts. 888 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 889 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 890 Op.getNode()->getOperand(0)), 891 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 892 Op.getNode()->getOperand(1))); 893 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 894 return CombineTo(Op, Z); 895 } 896 } 897 return false; 898} 899 900/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 901/// DemandedMask bits of the result of Op are ever used downstream. If we can 902/// use this information to simplify Op, create a new simplified DAG node and 903/// return true, returning the original and new nodes in Old and New. Otherwise, 904/// analyze the expression and return a mask of KnownOne and KnownZero bits for 905/// the expression (used to simplify the caller). The KnownZero/One bits may 906/// only be accurate for those bits in the DemandedMask. 907bool TargetLowering::SimplifyDemandedBits(SDValue Op, 908 const APInt &DemandedMask, 909 APInt &KnownZero, 910 APInt &KnownOne, 911 TargetLoweringOpt &TLO, 912 unsigned Depth) const { 913 unsigned BitWidth = DemandedMask.getBitWidth(); 914 assert(Op.getValueSizeInBits() == BitWidth && 915 "Mask size mismatches value type size!"); 916 APInt NewMask = DemandedMask; 917 DebugLoc dl = Op.getDebugLoc(); 918 919 // Don't know anything. 920 KnownZero = KnownOne = APInt(BitWidth, 0); 921 922 // Other users may use these bits. 923 if (!Op.getNode()->hasOneUse()) { 924 if (Depth != 0) { 925 // If not at the root, Just compute the KnownZero/KnownOne bits to 926 // simplify things downstream. 927 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 928 return false; 929 } 930 // If this is the root being simplified, allow it to have multiple uses, 931 // just set the NewMask to all bits. 932 NewMask = APInt::getAllOnesValue(BitWidth); 933 } else if (DemandedMask == 0) { 934 // Not demanding any bits from Op. 935 if (Op.getOpcode() != ISD::UNDEF) 936 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 937 return false; 938 } else if (Depth == 6) { // Limit search depth. 939 return false; 940 } 941 942 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 943 switch (Op.getOpcode()) { 944 case ISD::Constant: 945 // We know all of the bits for a constant! 946 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 947 KnownZero = ~KnownOne & NewMask; 948 return false; // Don't fall through, will infinitely loop. 949 case ISD::AND: 950 // If the RHS is a constant, check to see if the LHS would be zero without 951 // using the bits from the RHS. Below, we use knowledge about the RHS to 952 // simplify the LHS, here we're using information from the LHS to simplify 953 // the RHS. 954 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 955 APInt LHSZero, LHSOne; 956 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 957 LHSZero, LHSOne, Depth+1); 958 // If the LHS already has zeros where RHSC does, this and is dead. 959 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 960 return TLO.CombineTo(Op, Op.getOperand(0)); 961 // If any of the set bits in the RHS are known zero on the LHS, shrink 962 // the constant. 963 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 964 return true; 965 } 966 967 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 968 KnownOne, TLO, Depth+1)) 969 return true; 970 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 971 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 972 KnownZero2, KnownOne2, TLO, Depth+1)) 973 return true; 974 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 975 976 // If all of the demanded bits are known one on one side, return the other. 977 // These bits cannot contribute to the result of the 'and'. 978 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 979 return TLO.CombineTo(Op, Op.getOperand(0)); 980 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 981 return TLO.CombineTo(Op, Op.getOperand(1)); 982 // If all of the demanded bits in the inputs are known zeros, return zero. 983 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 984 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 985 // If the RHS is a constant, see if we can simplify it. 986 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 987 return true; 988 // If the operation can be done in a smaller type, do so. 989 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 990 return true; 991 992 // Output known-1 bits are only known if set in both the LHS & RHS. 993 KnownOne &= KnownOne2; 994 // Output known-0 are known to be clear if zero in either the LHS | RHS. 995 KnownZero |= KnownZero2; 996 break; 997 case ISD::OR: 998 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 999 KnownOne, TLO, Depth+1)) 1000 return true; 1001 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1002 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1003 KnownZero2, KnownOne2, TLO, Depth+1)) 1004 return true; 1005 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1006 1007 // If all of the demanded bits are known zero on one side, return the other. 1008 // These bits cannot contribute to the result of the 'or'. 1009 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1010 return TLO.CombineTo(Op, Op.getOperand(0)); 1011 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1012 return TLO.CombineTo(Op, Op.getOperand(1)); 1013 // If all of the potentially set bits on one side are known to be set on 1014 // the other side, just use the 'other' side. 1015 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1016 return TLO.CombineTo(Op, Op.getOperand(0)); 1017 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1018 return TLO.CombineTo(Op, Op.getOperand(1)); 1019 // If the RHS is a constant, see if we can simplify it. 1020 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1021 return true; 1022 // If the operation can be done in a smaller type, do so. 1023 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1024 return true; 1025 1026 // Output known-0 bits are only known if clear in both the LHS & RHS. 1027 KnownZero &= KnownZero2; 1028 // Output known-1 are known to be set if set in either the LHS | RHS. 1029 KnownOne |= KnownOne2; 1030 break; 1031 case ISD::XOR: 1032 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1033 KnownOne, TLO, Depth+1)) 1034 return true; 1035 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1036 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1037 KnownOne2, TLO, Depth+1)) 1038 return true; 1039 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1040 1041 // If all of the demanded bits are known zero on one side, return the other. 1042 // These bits cannot contribute to the result of the 'xor'. 1043 if ((KnownZero & NewMask) == NewMask) 1044 return TLO.CombineTo(Op, Op.getOperand(0)); 1045 if ((KnownZero2 & NewMask) == NewMask) 1046 return TLO.CombineTo(Op, Op.getOperand(1)); 1047 // If the operation can be done in a smaller type, do so. 1048 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1049 return true; 1050 1051 // If all of the unknown bits are known to be zero on one side or the other 1052 // (but not both) turn this into an *inclusive* or. 1053 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1054 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1055 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1056 Op.getOperand(0), 1057 Op.getOperand(1))); 1058 1059 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1060 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1061 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1062 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1063 1064 // If all of the demanded bits on one side are known, and all of the set 1065 // bits on that side are also known to be set on the other side, turn this 1066 // into an AND, as we know the bits will be cleared. 1067 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1068 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1069 if ((KnownOne & KnownOne2) == KnownOne) { 1070 EVT VT = Op.getValueType(); 1071 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1072 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1073 Op.getOperand(0), ANDC)); 1074 } 1075 } 1076 1077 // If the RHS is a constant, see if we can simplify it. 1078 // for XOR, we prefer to force bits to 1 if they will make a -1. 1079 // if we can't force bits, try to shrink constant 1080 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1081 APInt Expanded = C->getAPIntValue() | (~NewMask); 1082 // if we can expand it to have all bits set, do it 1083 if (Expanded.isAllOnesValue()) { 1084 if (Expanded != C->getAPIntValue()) { 1085 EVT VT = Op.getValueType(); 1086 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1087 TLO.DAG.getConstant(Expanded, VT)); 1088 return TLO.CombineTo(Op, New); 1089 } 1090 // if it already has all the bits set, nothing to change 1091 // but don't shrink either! 1092 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1093 return true; 1094 } 1095 } 1096 1097 KnownZero = KnownZeroOut; 1098 KnownOne = KnownOneOut; 1099 break; 1100 case ISD::SELECT: 1101 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1102 KnownOne, TLO, Depth+1)) 1103 return true; 1104 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1105 KnownOne2, TLO, Depth+1)) 1106 return true; 1107 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1108 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1109 1110 // If the operands are constants, see if we can simplify them. 1111 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1112 return true; 1113 1114 // Only known if known in both the LHS and RHS. 1115 KnownOne &= KnownOne2; 1116 KnownZero &= KnownZero2; 1117 break; 1118 case ISD::SELECT_CC: 1119 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1120 KnownOne, TLO, Depth+1)) 1121 return true; 1122 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1123 KnownOne2, TLO, Depth+1)) 1124 return true; 1125 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1126 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1127 1128 // If the operands are constants, see if we can simplify them. 1129 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1130 return true; 1131 1132 // Only known if known in both the LHS and RHS. 1133 KnownOne &= KnownOne2; 1134 KnownZero &= KnownZero2; 1135 break; 1136 case ISD::SHL: 1137 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1138 unsigned ShAmt = SA->getZExtValue(); 1139 SDValue InOp = Op.getOperand(0); 1140 1141 // If the shift count is an invalid immediate, don't do anything. 1142 if (ShAmt >= BitWidth) 1143 break; 1144 1145 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1146 // single shift. We can do this if the bottom bits (which are shifted 1147 // out) are never demanded. 1148 if (InOp.getOpcode() == ISD::SRL && 1149 isa<ConstantSDNode>(InOp.getOperand(1))) { 1150 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1151 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1152 unsigned Opc = ISD::SHL; 1153 int Diff = ShAmt-C1; 1154 if (Diff < 0) { 1155 Diff = -Diff; 1156 Opc = ISD::SRL; 1157 } 1158 1159 SDValue NewSA = 1160 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1161 EVT VT = Op.getValueType(); 1162 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1163 InOp.getOperand(0), NewSA)); 1164 } 1165 } 1166 1167 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1168 KnownZero, KnownOne, TLO, Depth+1)) 1169 return true; 1170 KnownZero <<= SA->getZExtValue(); 1171 KnownOne <<= SA->getZExtValue(); 1172 // low bits known zero. 1173 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1174 } 1175 break; 1176 case ISD::SRL: 1177 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1178 EVT VT = Op.getValueType(); 1179 unsigned ShAmt = SA->getZExtValue(); 1180 unsigned VTSize = VT.getSizeInBits(); 1181 SDValue InOp = Op.getOperand(0); 1182 1183 // If the shift count is an invalid immediate, don't do anything. 1184 if (ShAmt >= BitWidth) 1185 break; 1186 1187 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1188 // single shift. We can do this if the top bits (which are shifted out) 1189 // are never demanded. 1190 if (InOp.getOpcode() == ISD::SHL && 1191 isa<ConstantSDNode>(InOp.getOperand(1))) { 1192 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1193 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1194 unsigned Opc = ISD::SRL; 1195 int Diff = ShAmt-C1; 1196 if (Diff < 0) { 1197 Diff = -Diff; 1198 Opc = ISD::SHL; 1199 } 1200 1201 SDValue NewSA = 1202 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1203 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1204 InOp.getOperand(0), NewSA)); 1205 } 1206 } 1207 1208 // Compute the new bits that are at the top now. 1209 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1210 KnownZero, KnownOne, TLO, Depth+1)) 1211 return true; 1212 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1213 KnownZero = KnownZero.lshr(ShAmt); 1214 KnownOne = KnownOne.lshr(ShAmt); 1215 1216 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1217 KnownZero |= HighBits; // High bits known zero. 1218 } 1219 break; 1220 case ISD::SRA: 1221 // If this is an arithmetic shift right and only the low-bit is set, we can 1222 // always convert this into a logical shr, even if the shift amount is 1223 // variable. The low bit of the shift cannot be an input sign bit unless 1224 // the shift amount is >= the size of the datatype, which is undefined. 1225 if (DemandedMask == 1) 1226 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1227 Op.getOperand(0), Op.getOperand(1))); 1228 1229 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1230 EVT VT = Op.getValueType(); 1231 unsigned ShAmt = SA->getZExtValue(); 1232 1233 // If the shift count is an invalid immediate, don't do anything. 1234 if (ShAmt >= BitWidth) 1235 break; 1236 1237 APInt InDemandedMask = (NewMask << ShAmt); 1238 1239 // If any of the demanded bits are produced by the sign extension, we also 1240 // demand the input sign bit. 1241 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1242 if (HighBits.intersects(NewMask)) 1243 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1244 1245 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1246 KnownZero, KnownOne, TLO, Depth+1)) 1247 return true; 1248 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1249 KnownZero = KnownZero.lshr(ShAmt); 1250 KnownOne = KnownOne.lshr(ShAmt); 1251 1252 // Handle the sign bit, adjusted to where it is now in the mask. 1253 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1254 1255 // If the input sign bit is known to be zero, or if none of the top bits 1256 // are demanded, turn this into an unsigned shift right. 1257 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1258 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1259 Op.getOperand(0), 1260 Op.getOperand(1))); 1261 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1262 KnownOne |= HighBits; 1263 } 1264 } 1265 break; 1266 case ISD::SIGN_EXTEND_INREG: { 1267 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1268 1269 // Sign extension. Compute the demanded bits in the result that are not 1270 // present in the input. 1271 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1272 BitWidth - EVT.getSizeInBits()) & 1273 NewMask; 1274 1275 // If none of the extended bits are demanded, eliminate the sextinreg. 1276 if (NewBits == 0) 1277 return TLO.CombineTo(Op, Op.getOperand(0)); 1278 1279 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1280 InSignBit.zext(BitWidth); 1281 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1282 EVT.getSizeInBits()) & 1283 NewMask; 1284 1285 // Since the sign extended bits are demanded, we know that the sign 1286 // bit is demanded. 1287 InputDemandedBits |= InSignBit; 1288 1289 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1290 KnownZero, KnownOne, TLO, Depth+1)) 1291 return true; 1292 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1293 1294 // If the sign bit of the input is known set or clear, then we know the 1295 // top bits of the result. 1296 1297 // If the input sign bit is known zero, convert this into a zero extension. 1298 if (KnownZero.intersects(InSignBit)) 1299 return TLO.CombineTo(Op, 1300 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1301 1302 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1303 KnownOne |= NewBits; 1304 KnownZero &= ~NewBits; 1305 } else { // Input sign bit unknown 1306 KnownZero &= ~NewBits; 1307 KnownOne &= ~NewBits; 1308 } 1309 break; 1310 } 1311 case ISD::ZERO_EXTEND: { 1312 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1313 APInt InMask = NewMask; 1314 InMask.trunc(OperandBitWidth); 1315 1316 // If none of the top bits are demanded, convert this into an any_extend. 1317 APInt NewBits = 1318 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1319 if (!NewBits.intersects(NewMask)) 1320 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1321 Op.getValueType(), 1322 Op.getOperand(0))); 1323 1324 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1325 KnownZero, KnownOne, TLO, Depth+1)) 1326 return true; 1327 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1328 KnownZero.zext(BitWidth); 1329 KnownOne.zext(BitWidth); 1330 KnownZero |= NewBits; 1331 break; 1332 } 1333 case ISD::SIGN_EXTEND: { 1334 EVT InVT = Op.getOperand(0).getValueType(); 1335 unsigned InBits = InVT.getSizeInBits(); 1336 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1337 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1338 APInt NewBits = ~InMask & NewMask; 1339 1340 // If none of the top bits are demanded, convert this into an any_extend. 1341 if (NewBits == 0) 1342 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1343 Op.getValueType(), 1344 Op.getOperand(0))); 1345 1346 // Since some of the sign extended bits are demanded, we know that the sign 1347 // bit is demanded. 1348 APInt InDemandedBits = InMask & NewMask; 1349 InDemandedBits |= InSignBit; 1350 InDemandedBits.trunc(InBits); 1351 1352 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1353 KnownOne, TLO, Depth+1)) 1354 return true; 1355 KnownZero.zext(BitWidth); 1356 KnownOne.zext(BitWidth); 1357 1358 // If the sign bit is known zero, convert this to a zero extend. 1359 if (KnownZero.intersects(InSignBit)) 1360 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1361 Op.getValueType(), 1362 Op.getOperand(0))); 1363 1364 // If the sign bit is known one, the top bits match. 1365 if (KnownOne.intersects(InSignBit)) { 1366 KnownOne |= NewBits; 1367 KnownZero &= ~NewBits; 1368 } else { // Otherwise, top bits aren't known. 1369 KnownOne &= ~NewBits; 1370 KnownZero &= ~NewBits; 1371 } 1372 break; 1373 } 1374 case ISD::ANY_EXTEND: { 1375 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1376 APInt InMask = NewMask; 1377 InMask.trunc(OperandBitWidth); 1378 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1379 KnownZero, KnownOne, TLO, Depth+1)) 1380 return true; 1381 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1382 KnownZero.zext(BitWidth); 1383 KnownOne.zext(BitWidth); 1384 break; 1385 } 1386 case ISD::TRUNCATE: { 1387 // Simplify the input, using demanded bit information, and compute the known 1388 // zero/one bits live out. 1389 APInt TruncMask = NewMask; 1390 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1391 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1392 KnownZero, KnownOne, TLO, Depth+1)) 1393 return true; 1394 KnownZero.trunc(BitWidth); 1395 KnownOne.trunc(BitWidth); 1396 1397 // If the input is only used by this truncate, see if we can shrink it based 1398 // on the known demanded bits. 1399 if (Op.getOperand(0).getNode()->hasOneUse()) { 1400 SDValue In = Op.getOperand(0); 1401 unsigned InBitWidth = In.getValueSizeInBits(); 1402 switch (In.getOpcode()) { 1403 default: break; 1404 case ISD::SRL: 1405 // Shrink SRL by a constant if none of the high bits shifted in are 1406 // demanded. 1407 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1408 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1409 InBitWidth - BitWidth); 1410 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1411 HighBits.trunc(BitWidth); 1412 1413 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1414 // None of the shifted in bits are needed. Add a truncate of the 1415 // shift input, then shift it. 1416 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1417 Op.getValueType(), 1418 In.getOperand(0)); 1419 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1420 Op.getValueType(), 1421 NewTrunc, 1422 In.getOperand(1))); 1423 } 1424 } 1425 break; 1426 } 1427 } 1428 1429 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1430 break; 1431 } 1432 case ISD::AssertZext: { 1433 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1434 APInt InMask = APInt::getLowBitsSet(BitWidth, 1435 VT.getSizeInBits()); 1436 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1437 KnownZero, KnownOne, TLO, Depth+1)) 1438 return true; 1439 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1440 KnownZero |= ~InMask & NewMask; 1441 break; 1442 } 1443 case ISD::BIT_CONVERT: 1444#if 0 1445 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1446 // is demanded, turn this into a FGETSIGN. 1447 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1448 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1449 !MVT::isVector(Op.getOperand(0).getValueType())) { 1450 // Only do this xform if FGETSIGN is valid or if before legalize. 1451 if (!TLO.AfterLegalize || 1452 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1453 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1454 // place. We expect the SHL to be eliminated by other optimizations. 1455 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1456 Op.getOperand(0)); 1457 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1458 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1459 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1460 Sign, ShAmt)); 1461 } 1462 } 1463#endif 1464 break; 1465 case ISD::ADD: 1466 case ISD::MUL: 1467 case ISD::SUB: { 1468 // Add, Sub, and Mul don't demand any bits in positions beyond that 1469 // of the highest bit demanded of them. 1470 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1471 BitWidth - NewMask.countLeadingZeros()); 1472 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1473 KnownOne2, TLO, Depth+1)) 1474 return true; 1475 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1476 KnownOne2, TLO, Depth+1)) 1477 return true; 1478 // See if the operation should be performed at a smaller bit width. 1479 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1480 return true; 1481 } 1482 // FALL THROUGH 1483 default: 1484 // Just use ComputeMaskedBits to compute output bits. 1485 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1486 break; 1487 } 1488 1489 // If we know the value of all of the demanded bits, return this as a 1490 // constant. 1491 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1492 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1493 1494 return false; 1495} 1496 1497/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1498/// in Mask are known to be either zero or one and return them in the 1499/// KnownZero/KnownOne bitsets. 1500void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1501 const APInt &Mask, 1502 APInt &KnownZero, 1503 APInt &KnownOne, 1504 const SelectionDAG &DAG, 1505 unsigned Depth) const { 1506 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1507 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1508 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1509 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1510 "Should use MaskedValueIsZero if you don't know whether Op" 1511 " is a target node!"); 1512 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1513} 1514 1515/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1516/// targets that want to expose additional information about sign bits to the 1517/// DAG Combiner. 1518unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1519 unsigned Depth) const { 1520 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1521 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1522 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1523 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1524 "Should use ComputeNumSignBits if you don't know whether Op" 1525 " is a target node!"); 1526 return 1; 1527} 1528 1529/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1530/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1531/// determine which bit is set. 1532/// 1533static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1534 // A left-shift of a constant one will have exactly one bit set, because 1535 // shifting the bit off the end is undefined. 1536 if (Val.getOpcode() == ISD::SHL) 1537 if (ConstantSDNode *C = 1538 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1539 if (C->getAPIntValue() == 1) 1540 return true; 1541 1542 // Similarly, a right-shift of a constant sign-bit will have exactly 1543 // one bit set. 1544 if (Val.getOpcode() == ISD::SRL) 1545 if (ConstantSDNode *C = 1546 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1547 if (C->getAPIntValue().isSignBit()) 1548 return true; 1549 1550 // More could be done here, though the above checks are enough 1551 // to handle some common cases. 1552 1553 // Fall back to ComputeMaskedBits to catch other known cases. 1554 EVT OpVT = Val.getValueType(); 1555 unsigned BitWidth = OpVT.getSizeInBits(); 1556 APInt Mask = APInt::getAllOnesValue(BitWidth); 1557 APInt KnownZero, KnownOne; 1558 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1559 return (KnownZero.countPopulation() == BitWidth - 1) && 1560 (KnownOne.countPopulation() == 1); 1561} 1562 1563/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1564/// and cc. If it is unable to simplify it, return a null SDValue. 1565SDValue 1566TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1567 ISD::CondCode Cond, bool foldBooleans, 1568 DAGCombinerInfo &DCI, DebugLoc dl) const { 1569 SelectionDAG &DAG = DCI.DAG; 1570 LLVMContext &Context = *DAG.getContext(); 1571 1572 // These setcc operations always fold. 1573 switch (Cond) { 1574 default: break; 1575 case ISD::SETFALSE: 1576 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1577 case ISD::SETTRUE: 1578 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1579 } 1580 1581 if (isa<ConstantSDNode>(N0.getNode())) { 1582 // Ensure that the constant occurs on the RHS, and fold constant 1583 // comparisons. 1584 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1585 } 1586 1587 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1588 const APInt &C1 = N1C->getAPIntValue(); 1589 1590 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1591 // equality comparison, then we're just comparing whether X itself is 1592 // zero. 1593 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1594 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1595 N0.getOperand(1).getOpcode() == ISD::Constant) { 1596 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1597 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1598 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1599 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1600 // (srl (ctlz x), 5) == 0 -> X != 0 1601 // (srl (ctlz x), 5) != 1 -> X != 0 1602 Cond = ISD::SETNE; 1603 } else { 1604 // (srl (ctlz x), 5) != 0 -> X == 0 1605 // (srl (ctlz x), 5) == 1 -> X == 0 1606 Cond = ISD::SETEQ; 1607 } 1608 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1609 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1610 Zero, Cond); 1611 } 1612 } 1613 1614 // If the LHS is '(and load, const)', the RHS is 0, 1615 // the test is for equality or unsigned, and all 1 bits of the const are 1616 // in the same partial word, see if we can shorten the load. 1617 if (DCI.isBeforeLegalize() && 1618 N0.getOpcode() == ISD::AND && C1 == 0 && 1619 N0.getNode()->hasOneUse() && 1620 isa<LoadSDNode>(N0.getOperand(0)) && 1621 N0.getOperand(0).getNode()->hasOneUse() && 1622 isa<ConstantSDNode>(N0.getOperand(1))) { 1623 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1624 uint64_t bestMask = 0; 1625 unsigned bestWidth = 0, bestOffset = 0; 1626 if (!Lod->isVolatile() && Lod->isUnindexed() && 1627 // FIXME: This uses getZExtValue() below so it only works on i64 and 1628 // below. 1629 N0.getValueType().getSizeInBits() <= 64) { 1630 unsigned origWidth = N0.getValueType().getSizeInBits(); 1631 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1632 // 8 bits, but have to be careful... 1633 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1634 origWidth = Lod->getMemoryVT().getSizeInBits(); 1635 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1636 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1637 uint64_t newMask = (1ULL << width) - 1; 1638 for (unsigned offset=0; offset<origWidth/width; offset++) { 1639 if ((newMask & Mask) == Mask) { 1640 if (!TD->isLittleEndian()) 1641 bestOffset = (origWidth/width - offset - 1) * (width/8); 1642 else 1643 bestOffset = (uint64_t)offset * (width/8); 1644 bestMask = Mask >> (offset * (width/8) * 8); 1645 bestWidth = width; 1646 break; 1647 } 1648 newMask = newMask << width; 1649 } 1650 } 1651 } 1652 if (bestWidth) { 1653 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1654 if (newVT.isRound()) { 1655 EVT PtrType = Lod->getOperand(1).getValueType(); 1656 SDValue Ptr = Lod->getBasePtr(); 1657 if (bestOffset != 0) 1658 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1659 DAG.getConstant(bestOffset, PtrType)); 1660 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1661 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1662 Lod->getSrcValue(), 1663 Lod->getSrcValueOffset() + bestOffset, 1664 false, NewAlign); 1665 return DAG.getSetCC(dl, VT, 1666 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1667 DAG.getConstant(bestMask, newVT)), 1668 DAG.getConstant(0LL, newVT), Cond); 1669 } 1670 } 1671 } 1672 1673 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1674 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1675 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1676 1677 // If the comparison constant has bits in the upper part, the 1678 // zero-extended value could never match. 1679 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1680 C1.getBitWidth() - InSize))) { 1681 switch (Cond) { 1682 case ISD::SETUGT: 1683 case ISD::SETUGE: 1684 case ISD::SETEQ: return DAG.getConstant(0, VT); 1685 case ISD::SETULT: 1686 case ISD::SETULE: 1687 case ISD::SETNE: return DAG.getConstant(1, VT); 1688 case ISD::SETGT: 1689 case ISD::SETGE: 1690 // True if the sign bit of C1 is set. 1691 return DAG.getConstant(C1.isNegative(), VT); 1692 case ISD::SETLT: 1693 case ISD::SETLE: 1694 // True if the sign bit of C1 isn't set. 1695 return DAG.getConstant(C1.isNonNegative(), VT); 1696 default: 1697 break; 1698 } 1699 } 1700 1701 // Otherwise, we can perform the comparison with the low bits. 1702 switch (Cond) { 1703 case ISD::SETEQ: 1704 case ISD::SETNE: 1705 case ISD::SETUGT: 1706 case ISD::SETUGE: 1707 case ISD::SETULT: 1708 case ISD::SETULE: { 1709 EVT newVT = N0.getOperand(0).getValueType(); 1710 if (DCI.isBeforeLegalizeOps() || 1711 (isOperationLegal(ISD::SETCC, newVT) && 1712 getCondCodeAction(Cond, newVT)==Legal)) 1713 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1714 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1715 Cond); 1716 break; 1717 } 1718 default: 1719 break; // todo, be more careful with signed comparisons 1720 } 1721 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1722 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1723 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1724 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1725 EVT ExtDstTy = N0.getValueType(); 1726 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1727 1728 // If the extended part has any inconsistent bits, it cannot ever 1729 // compare equal. In other words, they have to be all ones or all 1730 // zeros. 1731 APInt ExtBits = 1732 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1733 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1734 return DAG.getConstant(Cond == ISD::SETNE, VT); 1735 1736 SDValue ZextOp; 1737 EVT Op0Ty = N0.getOperand(0).getValueType(); 1738 if (Op0Ty == ExtSrcTy) { 1739 ZextOp = N0.getOperand(0); 1740 } else { 1741 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1742 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1743 DAG.getConstant(Imm, Op0Ty)); 1744 } 1745 if (!DCI.isCalledByLegalizer()) 1746 DCI.AddToWorklist(ZextOp.getNode()); 1747 // Otherwise, make this a use of a zext. 1748 return DAG.getSetCC(dl, VT, ZextOp, 1749 DAG.getConstant(C1 & APInt::getLowBitsSet( 1750 ExtDstTyBits, 1751 ExtSrcTyBits), 1752 ExtDstTy), 1753 Cond); 1754 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1755 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1756 1757 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1758 if (N0.getOpcode() == ISD::SETCC) { 1759 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1760 if (TrueWhenTrue) 1761 return N0; 1762 1763 // Invert the condition. 1764 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1765 CC = ISD::getSetCCInverse(CC, 1766 N0.getOperand(0).getValueType().isInteger()); 1767 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1768 } 1769 1770 if ((N0.getOpcode() == ISD::XOR || 1771 (N0.getOpcode() == ISD::AND && 1772 N0.getOperand(0).getOpcode() == ISD::XOR && 1773 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1774 isa<ConstantSDNode>(N0.getOperand(1)) && 1775 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1776 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1777 // can only do this if the top bits are known zero. 1778 unsigned BitWidth = N0.getValueSizeInBits(); 1779 if (DAG.MaskedValueIsZero(N0, 1780 APInt::getHighBitsSet(BitWidth, 1781 BitWidth-1))) { 1782 // Okay, get the un-inverted input value. 1783 SDValue Val; 1784 if (N0.getOpcode() == ISD::XOR) 1785 Val = N0.getOperand(0); 1786 else { 1787 assert(N0.getOpcode() == ISD::AND && 1788 N0.getOperand(0).getOpcode() == ISD::XOR); 1789 // ((X^1)&1)^1 -> X & 1 1790 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1791 N0.getOperand(0).getOperand(0), 1792 N0.getOperand(1)); 1793 } 1794 return DAG.getSetCC(dl, VT, Val, N1, 1795 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1796 } 1797 } 1798 } 1799 1800 APInt MinVal, MaxVal; 1801 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1802 if (ISD::isSignedIntSetCC(Cond)) { 1803 MinVal = APInt::getSignedMinValue(OperandBitSize); 1804 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1805 } else { 1806 MinVal = APInt::getMinValue(OperandBitSize); 1807 MaxVal = APInt::getMaxValue(OperandBitSize); 1808 } 1809 1810 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1811 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1812 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1813 // X >= C0 --> X > (C0-1) 1814 return DAG.getSetCC(dl, VT, N0, 1815 DAG.getConstant(C1-1, N1.getValueType()), 1816 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1817 } 1818 1819 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1820 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1821 // X <= C0 --> X < (C0+1) 1822 return DAG.getSetCC(dl, VT, N0, 1823 DAG.getConstant(C1+1, N1.getValueType()), 1824 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1825 } 1826 1827 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1828 return DAG.getConstant(0, VT); // X < MIN --> false 1829 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1830 return DAG.getConstant(1, VT); // X >= MIN --> true 1831 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1832 return DAG.getConstant(0, VT); // X > MAX --> false 1833 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1834 return DAG.getConstant(1, VT); // X <= MAX --> true 1835 1836 // Canonicalize setgt X, Min --> setne X, Min 1837 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1838 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1839 // Canonicalize setlt X, Max --> setne X, Max 1840 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1841 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1842 1843 // If we have setult X, 1, turn it into seteq X, 0 1844 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1845 return DAG.getSetCC(dl, VT, N0, 1846 DAG.getConstant(MinVal, N0.getValueType()), 1847 ISD::SETEQ); 1848 // If we have setugt X, Max-1, turn it into seteq X, Max 1849 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1850 return DAG.getSetCC(dl, VT, N0, 1851 DAG.getConstant(MaxVal, N0.getValueType()), 1852 ISD::SETEQ); 1853 1854 // If we have "setcc X, C0", check to see if we can shrink the immediate 1855 // by changing cc. 1856 1857 // SETUGT X, SINTMAX -> SETLT X, 0 1858 if (Cond == ISD::SETUGT && 1859 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1860 return DAG.getSetCC(dl, VT, N0, 1861 DAG.getConstant(0, N1.getValueType()), 1862 ISD::SETLT); 1863 1864 // SETULT X, SINTMIN -> SETGT X, -1 1865 if (Cond == ISD::SETULT && 1866 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1867 SDValue ConstMinusOne = 1868 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1869 N1.getValueType()); 1870 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1871 } 1872 1873 // Fold bit comparisons when we can. 1874 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1875 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1876 if (ConstantSDNode *AndRHS = 1877 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1878 EVT ShiftTy = DCI.isBeforeLegalize() ? 1879 getPointerTy() : getShiftAmountTy(); 1880 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1881 // Perform the xform if the AND RHS is a single bit. 1882 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1883 return DAG.getNode(ISD::SRL, dl, VT, N0, 1884 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1885 ShiftTy)); 1886 } 1887 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1888 // (X & 8) == 8 --> (X & 8) >> 3 1889 // Perform the xform if C1 is a single bit. 1890 if (C1.isPowerOf2()) { 1891 return DAG.getNode(ISD::SRL, dl, VT, N0, 1892 DAG.getConstant(C1.logBase2(), ShiftTy)); 1893 } 1894 } 1895 } 1896 } 1897 1898 if (isa<ConstantFPSDNode>(N0.getNode())) { 1899 // Constant fold or commute setcc. 1900 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1901 if (O.getNode()) return O; 1902 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1903 // If the RHS of an FP comparison is a constant, simplify it away in 1904 // some cases. 1905 if (CFP->getValueAPF().isNaN()) { 1906 // If an operand is known to be a nan, we can fold it. 1907 switch (ISD::getUnorderedFlavor(Cond)) { 1908 default: llvm_unreachable("Unknown flavor!"); 1909 case 0: // Known false. 1910 return DAG.getConstant(0, VT); 1911 case 1: // Known true. 1912 return DAG.getConstant(1, VT); 1913 case 2: // Undefined. 1914 return DAG.getUNDEF(VT); 1915 } 1916 } 1917 1918 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1919 // constant if knowing that the operand is non-nan is enough. We prefer to 1920 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1921 // materialize 0.0. 1922 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1923 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1924 1925 // If the condition is not legal, see if we can find an equivalent one 1926 // which is legal. 1927 if (!isCondCodeLegal(Cond, N0.getValueType())) { 1928 // If the comparison was an awkward floating-point == or != and one of 1929 // the comparison operands is infinity or negative infinity, convert the 1930 // condition to a less-awkward <= or >=. 1931 if (CFP->getValueAPF().isInfinity()) { 1932 if (CFP->getValueAPF().isNegative()) { 1933 if (Cond == ISD::SETOEQ && 1934 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 1935 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 1936 if (Cond == ISD::SETUEQ && 1937 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 1938 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 1939 if (Cond == ISD::SETUNE && 1940 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 1941 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 1942 if (Cond == ISD::SETONE && 1943 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 1944 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 1945 } else { 1946 if (Cond == ISD::SETOEQ && 1947 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 1948 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 1949 if (Cond == ISD::SETUEQ && 1950 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 1951 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 1952 if (Cond == ISD::SETUNE && 1953 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 1954 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 1955 if (Cond == ISD::SETONE && 1956 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 1957 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 1958 } 1959 } 1960 } 1961 } 1962 1963 if (N0 == N1) { 1964 // We can always fold X == X for integer setcc's. 1965 if (N0.getValueType().isInteger()) 1966 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1967 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1968 if (UOF == 2) // FP operators that are undefined on NaNs. 1969 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1970 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1971 return DAG.getConstant(UOF, VT); 1972 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1973 // if it is not already. 1974 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1975 if (NewCond != Cond) 1976 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1977 } 1978 1979 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1980 N0.getValueType().isInteger()) { 1981 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1982 N0.getOpcode() == ISD::XOR) { 1983 // Simplify (X+Y) == (X+Z) --> Y == Z 1984 if (N0.getOpcode() == N1.getOpcode()) { 1985 if (N0.getOperand(0) == N1.getOperand(0)) 1986 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1987 if (N0.getOperand(1) == N1.getOperand(1)) 1988 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1989 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1990 // If X op Y == Y op X, try other combinations. 1991 if (N0.getOperand(0) == N1.getOperand(1)) 1992 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1993 Cond); 1994 if (N0.getOperand(1) == N1.getOperand(0)) 1995 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1996 Cond); 1997 } 1998 } 1999 2000 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2001 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2002 // Turn (X+C1) == C2 --> X == C2-C1 2003 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2004 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2005 DAG.getConstant(RHSC->getAPIntValue()- 2006 LHSR->getAPIntValue(), 2007 N0.getValueType()), Cond); 2008 } 2009 2010 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2011 if (N0.getOpcode() == ISD::XOR) 2012 // If we know that all of the inverted bits are zero, don't bother 2013 // performing the inversion. 2014 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2015 return 2016 DAG.getSetCC(dl, VT, N0.getOperand(0), 2017 DAG.getConstant(LHSR->getAPIntValue() ^ 2018 RHSC->getAPIntValue(), 2019 N0.getValueType()), 2020 Cond); 2021 } 2022 2023 // Turn (C1-X) == C2 --> X == C1-C2 2024 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2025 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2026 return 2027 DAG.getSetCC(dl, VT, N0.getOperand(1), 2028 DAG.getConstant(SUBC->getAPIntValue() - 2029 RHSC->getAPIntValue(), 2030 N0.getValueType()), 2031 Cond); 2032 } 2033 } 2034 } 2035 2036 // Simplify (X+Z) == X --> Z == 0 2037 if (N0.getOperand(0) == N1) 2038 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2039 DAG.getConstant(0, N0.getValueType()), Cond); 2040 if (N0.getOperand(1) == N1) { 2041 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2042 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2043 DAG.getConstant(0, N0.getValueType()), Cond); 2044 else if (N0.getNode()->hasOneUse()) { 2045 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2046 // (Z-X) == X --> Z == X<<1 2047 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2048 N1, 2049 DAG.getConstant(1, getShiftAmountTy())); 2050 if (!DCI.isCalledByLegalizer()) 2051 DCI.AddToWorklist(SH.getNode()); 2052 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2053 } 2054 } 2055 } 2056 2057 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2058 N1.getOpcode() == ISD::XOR) { 2059 // Simplify X == (X+Z) --> Z == 0 2060 if (N1.getOperand(0) == N0) { 2061 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2062 DAG.getConstant(0, N1.getValueType()), Cond); 2063 } else if (N1.getOperand(1) == N0) { 2064 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2065 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2066 DAG.getConstant(0, N1.getValueType()), Cond); 2067 } else if (N1.getNode()->hasOneUse()) { 2068 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2069 // X == (Z-X) --> X<<1 == Z 2070 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2071 DAG.getConstant(1, getShiftAmountTy())); 2072 if (!DCI.isCalledByLegalizer()) 2073 DCI.AddToWorklist(SH.getNode()); 2074 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2075 } 2076 } 2077 } 2078 2079 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2080 // Note that where y is variable and is known to have at most 2081 // one bit set (for example, if it is z&1) we cannot do this; 2082 // the expressions are not equivalent when y==0. 2083 if (N0.getOpcode() == ISD::AND) 2084 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2085 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2086 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2087 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2088 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2089 } 2090 } 2091 if (N1.getOpcode() == ISD::AND) 2092 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2093 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2094 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2095 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2096 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2097 } 2098 } 2099 } 2100 2101 // Fold away ALL boolean setcc's. 2102 SDValue Temp; 2103 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2104 switch (Cond) { 2105 default: llvm_unreachable("Unknown integer setcc!"); 2106 case ISD::SETEQ: // X == Y -> ~(X^Y) 2107 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2108 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2109 if (!DCI.isCalledByLegalizer()) 2110 DCI.AddToWorklist(Temp.getNode()); 2111 break; 2112 case ISD::SETNE: // X != Y --> (X^Y) 2113 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2114 break; 2115 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2116 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2117 Temp = DAG.getNOT(dl, N0, MVT::i1); 2118 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2119 if (!DCI.isCalledByLegalizer()) 2120 DCI.AddToWorklist(Temp.getNode()); 2121 break; 2122 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2123 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2124 Temp = DAG.getNOT(dl, N1, MVT::i1); 2125 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2126 if (!DCI.isCalledByLegalizer()) 2127 DCI.AddToWorklist(Temp.getNode()); 2128 break; 2129 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2130 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2131 Temp = DAG.getNOT(dl, N0, MVT::i1); 2132 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2133 if (!DCI.isCalledByLegalizer()) 2134 DCI.AddToWorklist(Temp.getNode()); 2135 break; 2136 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2137 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2138 Temp = DAG.getNOT(dl, N1, MVT::i1); 2139 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2140 break; 2141 } 2142 if (VT != MVT::i1) { 2143 if (!DCI.isCalledByLegalizer()) 2144 DCI.AddToWorklist(N0.getNode()); 2145 // FIXME: If running after legalize, we probably can't do this. 2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2147 } 2148 return N0; 2149 } 2150 2151 // Could not fold it. 2152 return SDValue(); 2153} 2154 2155/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2156/// node is a GlobalAddress + offset. 2157bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2158 int64_t &Offset) const { 2159 if (isa<GlobalAddressSDNode>(N)) { 2160 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2161 GA = GASD->getGlobal(); 2162 Offset += GASD->getOffset(); 2163 return true; 2164 } 2165 2166 if (N->getOpcode() == ISD::ADD) { 2167 SDValue N1 = N->getOperand(0); 2168 SDValue N2 = N->getOperand(1); 2169 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2170 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2171 if (V) { 2172 Offset += V->getSExtValue(); 2173 return true; 2174 } 2175 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2176 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2177 if (V) { 2178 Offset += V->getSExtValue(); 2179 return true; 2180 } 2181 } 2182 } 2183 return false; 2184} 2185 2186 2187SDValue TargetLowering:: 2188PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2189 // Default implementation: no optimization. 2190 return SDValue(); 2191} 2192 2193//===----------------------------------------------------------------------===// 2194// Inline Assembler Implementation Methods 2195//===----------------------------------------------------------------------===// 2196 2197 2198TargetLowering::ConstraintType 2199TargetLowering::getConstraintType(const std::string &Constraint) const { 2200 // FIXME: lots more standard ones to handle. 2201 if (Constraint.size() == 1) { 2202 switch (Constraint[0]) { 2203 default: break; 2204 case 'r': return C_RegisterClass; 2205 case 'm': // memory 2206 case 'o': // offsetable 2207 case 'V': // not offsetable 2208 return C_Memory; 2209 case 'i': // Simple Integer or Relocatable Constant 2210 case 'n': // Simple Integer 2211 case 's': // Relocatable Constant 2212 case 'X': // Allow ANY value. 2213 case 'I': // Target registers. 2214 case 'J': 2215 case 'K': 2216 case 'L': 2217 case 'M': 2218 case 'N': 2219 case 'O': 2220 case 'P': 2221 return C_Other; 2222 } 2223 } 2224 2225 if (Constraint.size() > 1 && Constraint[0] == '{' && 2226 Constraint[Constraint.size()-1] == '}') 2227 return C_Register; 2228 return C_Unknown; 2229} 2230 2231/// LowerXConstraint - try to replace an X constraint, which matches anything, 2232/// with another that has more specific requirements based on the type of the 2233/// corresponding operand. 2234const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2235 if (ConstraintVT.isInteger()) 2236 return "r"; 2237 if (ConstraintVT.isFloatingPoint()) 2238 return "f"; // works for many targets 2239 return 0; 2240} 2241 2242/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2243/// vector. If it is invalid, don't add anything to Ops. 2244void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2245 char ConstraintLetter, 2246 bool hasMemory, 2247 std::vector<SDValue> &Ops, 2248 SelectionDAG &DAG) const { 2249 switch (ConstraintLetter) { 2250 default: break; 2251 case 'X': // Allows any operand; labels (basic block) use this. 2252 if (Op.getOpcode() == ISD::BasicBlock) { 2253 Ops.push_back(Op); 2254 return; 2255 } 2256 // fall through 2257 case 'i': // Simple Integer or Relocatable Constant 2258 case 'n': // Simple Integer 2259 case 's': { // Relocatable Constant 2260 // These operands are interested in values of the form (GV+C), where C may 2261 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2262 // is possible and fine if either GV or C are missing. 2263 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2264 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2265 2266 // If we have "(add GV, C)", pull out GV/C 2267 if (Op.getOpcode() == ISD::ADD) { 2268 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2269 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2270 if (C == 0 || GA == 0) { 2271 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2272 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2273 } 2274 if (C == 0 || GA == 0) 2275 C = 0, GA = 0; 2276 } 2277 2278 // If we find a valid operand, map to the TargetXXX version so that the 2279 // value itself doesn't get selected. 2280 if (GA) { // Either &GV or &GV+C 2281 if (ConstraintLetter != 'n') { 2282 int64_t Offs = GA->getOffset(); 2283 if (C) Offs += C->getZExtValue(); 2284 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2285 Op.getValueType(), Offs)); 2286 return; 2287 } 2288 } 2289 if (C) { // just C, no GV. 2290 // Simple constants are not allowed for 's'. 2291 if (ConstraintLetter != 's') { 2292 // gcc prints these as sign extended. Sign extend value to 64 bits 2293 // now; without this it would get ZExt'd later in 2294 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2295 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2296 MVT::i64)); 2297 return; 2298 } 2299 } 2300 break; 2301 } 2302 } 2303} 2304 2305std::vector<unsigned> TargetLowering:: 2306getRegClassForInlineAsmConstraint(const std::string &Constraint, 2307 EVT VT) const { 2308 return std::vector<unsigned>(); 2309} 2310 2311 2312std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2313getRegForInlineAsmConstraint(const std::string &Constraint, 2314 EVT VT) const { 2315 if (Constraint[0] != '{') 2316 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2317 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2318 2319 // Remove the braces from around the name. 2320 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2321 2322 // Figure out which register class contains this reg. 2323 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2324 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2325 E = RI->regclass_end(); RCI != E; ++RCI) { 2326 const TargetRegisterClass *RC = *RCI; 2327 2328 // If none of the the value types for this register class are valid, we 2329 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2330 bool isLegal = false; 2331 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2332 I != E; ++I) { 2333 if (isTypeLegal(*I)) { 2334 isLegal = true; 2335 break; 2336 } 2337 } 2338 2339 if (!isLegal) continue; 2340 2341 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2342 I != E; ++I) { 2343 if (RegName.equals_lower(RI->getName(*I))) 2344 return std::make_pair(*I, RC); 2345 } 2346 } 2347 2348 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2349} 2350 2351//===----------------------------------------------------------------------===// 2352// Constraint Selection. 2353 2354/// isMatchingInputConstraint - Return true of this is an input operand that is 2355/// a matching constraint like "4". 2356bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2357 assert(!ConstraintCode.empty() && "No known constraint!"); 2358 return isdigit(ConstraintCode[0]); 2359} 2360 2361/// getMatchedOperand - If this is an input matching constraint, this method 2362/// returns the output operand it matches. 2363unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2364 assert(!ConstraintCode.empty() && "No known constraint!"); 2365 return atoi(ConstraintCode.c_str()); 2366} 2367 2368 2369/// getConstraintGenerality - Return an integer indicating how general CT 2370/// is. 2371static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2372 switch (CT) { 2373 default: llvm_unreachable("Unknown constraint type!"); 2374 case TargetLowering::C_Other: 2375 case TargetLowering::C_Unknown: 2376 return 0; 2377 case TargetLowering::C_Register: 2378 return 1; 2379 case TargetLowering::C_RegisterClass: 2380 return 2; 2381 case TargetLowering::C_Memory: 2382 return 3; 2383 } 2384} 2385 2386/// ChooseConstraint - If there are multiple different constraints that we 2387/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2388/// This is somewhat tricky: constraints fall into four classes: 2389/// Other -> immediates and magic values 2390/// Register -> one specific register 2391/// RegisterClass -> a group of regs 2392/// Memory -> memory 2393/// Ideally, we would pick the most specific constraint possible: if we have 2394/// something that fits into a register, we would pick it. The problem here 2395/// is that if we have something that could either be in a register or in 2396/// memory that use of the register could cause selection of *other* 2397/// operands to fail: they might only succeed if we pick memory. Because of 2398/// this the heuristic we use is: 2399/// 2400/// 1) If there is an 'other' constraint, and if the operand is valid for 2401/// that constraint, use it. This makes us take advantage of 'i' 2402/// constraints when available. 2403/// 2) Otherwise, pick the most general constraint present. This prefers 2404/// 'm' over 'r', for example. 2405/// 2406static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2407 bool hasMemory, const TargetLowering &TLI, 2408 SDValue Op, SelectionDAG *DAG) { 2409 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2410 unsigned BestIdx = 0; 2411 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2412 int BestGenerality = -1; 2413 2414 // Loop over the options, keeping track of the most general one. 2415 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2416 TargetLowering::ConstraintType CType = 2417 TLI.getConstraintType(OpInfo.Codes[i]); 2418 2419 // If this is an 'other' constraint, see if the operand is valid for it. 2420 // For example, on X86 we might have an 'rI' constraint. If the operand 2421 // is an integer in the range [0..31] we want to use I (saving a load 2422 // of a register), otherwise we must use 'r'. 2423 if (CType == TargetLowering::C_Other && Op.getNode()) { 2424 assert(OpInfo.Codes[i].size() == 1 && 2425 "Unhandled multi-letter 'other' constraint"); 2426 std::vector<SDValue> ResultOps; 2427 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2428 ResultOps, *DAG); 2429 if (!ResultOps.empty()) { 2430 BestType = CType; 2431 BestIdx = i; 2432 break; 2433 } 2434 } 2435 2436 // This constraint letter is more general than the previous one, use it. 2437 int Generality = getConstraintGenerality(CType); 2438 if (Generality > BestGenerality) { 2439 BestType = CType; 2440 BestIdx = i; 2441 BestGenerality = Generality; 2442 } 2443 } 2444 2445 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2446 OpInfo.ConstraintType = BestType; 2447} 2448 2449/// ComputeConstraintToUse - Determines the constraint code and constraint 2450/// type to use for the specific AsmOperandInfo, setting 2451/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2452void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2453 SDValue Op, 2454 bool hasMemory, 2455 SelectionDAG *DAG) const { 2456 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2457 2458 // Single-letter constraints ('r') are very common. 2459 if (OpInfo.Codes.size() == 1) { 2460 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2461 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2462 } else { 2463 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2464 } 2465 2466 // 'X' matches anything. 2467 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2468 // Labels and constants are handled elsewhere ('X' is the only thing 2469 // that matches labels). For Functions, the type here is the type of 2470 // the result, which is not what we want to look at; leave them alone. 2471 Value *v = OpInfo.CallOperandVal; 2472 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2473 OpInfo.CallOperandVal = v; 2474 return; 2475 } 2476 2477 // Otherwise, try to resolve it to something we know about by looking at 2478 // the actual operand type. 2479 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2480 OpInfo.ConstraintCode = Repl; 2481 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2482 } 2483 } 2484} 2485 2486//===----------------------------------------------------------------------===// 2487// Loop Strength Reduction hooks 2488//===----------------------------------------------------------------------===// 2489 2490/// isLegalAddressingMode - Return true if the addressing mode represented 2491/// by AM is legal for this target, for a load/store of the specified type. 2492bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2493 const Type *Ty) const { 2494 // The default implementation of this implements a conservative RISCy, r+r and 2495 // r+i addr mode. 2496 2497 // Allows a sign-extended 16-bit immediate field. 2498 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2499 return false; 2500 2501 // No global is ever allowed as a base. 2502 if (AM.BaseGV) 2503 return false; 2504 2505 // Only support r+r, 2506 switch (AM.Scale) { 2507 case 0: // "r+i" or just "i", depending on HasBaseReg. 2508 break; 2509 case 1: 2510 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2511 return false; 2512 // Otherwise we have r+r or r+i. 2513 break; 2514 case 2: 2515 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2516 return false; 2517 // Allow 2*r as r+r. 2518 break; 2519 } 2520 2521 return true; 2522} 2523 2524/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2525/// return a DAG expression to select that will generate the same value by 2526/// multiplying by a magic number. See: 2527/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2528SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2529 std::vector<SDNode*>* Created) const { 2530 EVT VT = N->getValueType(0); 2531 DebugLoc dl= N->getDebugLoc(); 2532 2533 // Check to see if we can do this. 2534 // FIXME: We should be more aggressive here. 2535 if (!isTypeLegal(VT)) 2536 return SDValue(); 2537 2538 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2539 APInt::ms magics = d.magic(); 2540 2541 // Multiply the numerator (operand 0) by the magic value 2542 // FIXME: We should support doing a MUL in a wider type 2543 SDValue Q; 2544 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2545 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2546 DAG.getConstant(magics.m, VT)); 2547 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2548 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2549 N->getOperand(0), 2550 DAG.getConstant(magics.m, VT)).getNode(), 1); 2551 else 2552 return SDValue(); // No mulhs or equvialent 2553 // If d > 0 and m < 0, add the numerator 2554 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2555 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2556 if (Created) 2557 Created->push_back(Q.getNode()); 2558 } 2559 // If d < 0 and m > 0, subtract the numerator. 2560 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2561 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2562 if (Created) 2563 Created->push_back(Q.getNode()); 2564 } 2565 // Shift right algebraic if shift value is nonzero 2566 if (magics.s > 0) { 2567 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2568 DAG.getConstant(magics.s, getShiftAmountTy())); 2569 if (Created) 2570 Created->push_back(Q.getNode()); 2571 } 2572 // Extract the sign bit and add it to the quotient 2573 SDValue T = 2574 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2575 getShiftAmountTy())); 2576 if (Created) 2577 Created->push_back(T.getNode()); 2578 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2579} 2580 2581/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2582/// return a DAG expression to select that will generate the same value by 2583/// multiplying by a magic number. See: 2584/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2585SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2586 std::vector<SDNode*>* Created) const { 2587 EVT VT = N->getValueType(0); 2588 DebugLoc dl = N->getDebugLoc(); 2589 2590 // Check to see if we can do this. 2591 // FIXME: We should be more aggressive here. 2592 if (!isTypeLegal(VT)) 2593 return SDValue(); 2594 2595 // FIXME: We should use a narrower constant when the upper 2596 // bits are known to be zero. 2597 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2598 APInt::mu magics = N1C->getAPIntValue().magicu(); 2599 2600 // Multiply the numerator (operand 0) by the magic value 2601 // FIXME: We should support doing a MUL in a wider type 2602 SDValue Q; 2603 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2604 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2605 DAG.getConstant(magics.m, VT)); 2606 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2607 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2608 N->getOperand(0), 2609 DAG.getConstant(magics.m, VT)).getNode(), 1); 2610 else 2611 return SDValue(); // No mulhu or equvialent 2612 if (Created) 2613 Created->push_back(Q.getNode()); 2614 2615 if (magics.a == 0) { 2616 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2617 "We shouldn't generate an undefined shift!"); 2618 return DAG.getNode(ISD::SRL, dl, VT, Q, 2619 DAG.getConstant(magics.s, getShiftAmountTy())); 2620 } else { 2621 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2622 if (Created) 2623 Created->push_back(NPQ.getNode()); 2624 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2625 DAG.getConstant(1, getShiftAmountTy())); 2626 if (Created) 2627 Created->push_back(NPQ.getNode()); 2628 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2629 if (Created) 2630 Created->push_back(NPQ.getNode()); 2631 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2632 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2633 } 2634} 2635