TargetLowering.cpp revision 6520e20e4fb31f2e65e25c38b372b19d33a83df4
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I32] = "__ashlsi3"; 33 Names[RTLIB::SHL_I64] = "__ashldi3"; 34 Names[RTLIB::SHL_I128] = "__ashlti3"; 35 Names[RTLIB::SRL_I32] = "__lshrsi3"; 36 Names[RTLIB::SRL_I64] = "__lshrdi3"; 37 Names[RTLIB::SRL_I128] = "__lshrti3"; 38 Names[RTLIB::SRA_I32] = "__ashrsi3"; 39 Names[RTLIB::SRA_I64] = "__ashrdi3"; 40 Names[RTLIB::SRA_I128] = "__ashrti3"; 41 Names[RTLIB::MUL_I32] = "__mulsi3"; 42 Names[RTLIB::MUL_I64] = "__muldi3"; 43 Names[RTLIB::MUL_I128] = "__multi3"; 44 Names[RTLIB::SDIV_I32] = "__divsi3"; 45 Names[RTLIB::SDIV_I64] = "__divdi3"; 46 Names[RTLIB::SDIV_I128] = "__divti3"; 47 Names[RTLIB::UDIV_I32] = "__udivsi3"; 48 Names[RTLIB::UDIV_I64] = "__udivdi3"; 49 Names[RTLIB::UDIV_I128] = "__udivti3"; 50 Names[RTLIB::SREM_I32] = "__modsi3"; 51 Names[RTLIB::SREM_I64] = "__moddi3"; 52 Names[RTLIB::SREM_I128] = "__modti3"; 53 Names[RTLIB::UREM_I32] = "__umodsi3"; 54 Names[RTLIB::UREM_I64] = "__umoddi3"; 55 Names[RTLIB::UREM_I128] = "__umodti3"; 56 Names[RTLIB::NEG_I32] = "__negsi2"; 57 Names[RTLIB::NEG_I64] = "__negdi2"; 58 Names[RTLIB::ADD_F32] = "__addsf3"; 59 Names[RTLIB::ADD_F64] = "__adddf3"; 60 Names[RTLIB::ADD_F80] = "__addxf3"; 61 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 62 Names[RTLIB::SUB_F32] = "__subsf3"; 63 Names[RTLIB::SUB_F64] = "__subdf3"; 64 Names[RTLIB::SUB_F80] = "__subxf3"; 65 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 66 Names[RTLIB::MUL_F32] = "__mulsf3"; 67 Names[RTLIB::MUL_F64] = "__muldf3"; 68 Names[RTLIB::MUL_F80] = "__mulxf3"; 69 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 70 Names[RTLIB::DIV_F32] = "__divsf3"; 71 Names[RTLIB::DIV_F64] = "__divdf3"; 72 Names[RTLIB::DIV_F80] = "__divxf3"; 73 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 74 Names[RTLIB::REM_F32] = "fmodf"; 75 Names[RTLIB::REM_F64] = "fmod"; 76 Names[RTLIB::REM_F80] = "fmodl"; 77 Names[RTLIB::REM_PPCF128] = "fmodl"; 78 Names[RTLIB::POWI_F32] = "__powisf2"; 79 Names[RTLIB::POWI_F64] = "__powidf2"; 80 Names[RTLIB::POWI_F80] = "__powixf2"; 81 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 82 Names[RTLIB::SQRT_F32] = "sqrtf"; 83 Names[RTLIB::SQRT_F64] = "sqrt"; 84 Names[RTLIB::SQRT_F80] = "sqrtl"; 85 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 86 Names[RTLIB::LOG_F32] = "logf"; 87 Names[RTLIB::LOG_F64] = "log"; 88 Names[RTLIB::LOG_F80] = "logl"; 89 Names[RTLIB::LOG_PPCF128] = "logl"; 90 Names[RTLIB::LOG2_F32] = "log2f"; 91 Names[RTLIB::LOG2_F64] = "log2"; 92 Names[RTLIB::LOG2_F80] = "log2l"; 93 Names[RTLIB::LOG2_PPCF128] = "log2l"; 94 Names[RTLIB::LOG10_F32] = "log10f"; 95 Names[RTLIB::LOG10_F64] = "log10"; 96 Names[RTLIB::LOG10_F80] = "log10l"; 97 Names[RTLIB::LOG10_PPCF128] = "log10l"; 98 Names[RTLIB::EXP_F32] = "expf"; 99 Names[RTLIB::EXP_F64] = "exp"; 100 Names[RTLIB::EXP_F80] = "expl"; 101 Names[RTLIB::EXP_PPCF128] = "expl"; 102 Names[RTLIB::EXP2_F32] = "exp2f"; 103 Names[RTLIB::EXP2_F64] = "exp2"; 104 Names[RTLIB::EXP2_F80] = "exp2l"; 105 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 106 Names[RTLIB::SIN_F32] = "sinf"; 107 Names[RTLIB::SIN_F64] = "sin"; 108 Names[RTLIB::SIN_F80] = "sinl"; 109 Names[RTLIB::SIN_PPCF128] = "sinl"; 110 Names[RTLIB::COS_F32] = "cosf"; 111 Names[RTLIB::COS_F64] = "cos"; 112 Names[RTLIB::COS_F80] = "cosl"; 113 Names[RTLIB::COS_PPCF128] = "cosl"; 114 Names[RTLIB::POW_F32] = "powf"; 115 Names[RTLIB::POW_F64] = "pow"; 116 Names[RTLIB::POW_F80] = "powl"; 117 Names[RTLIB::POW_PPCF128] = "powl"; 118 Names[RTLIB::CEIL_F32] = "ceilf"; 119 Names[RTLIB::CEIL_F64] = "ceil"; 120 Names[RTLIB::CEIL_F80] = "ceill"; 121 Names[RTLIB::CEIL_PPCF128] = "ceill"; 122 Names[RTLIB::TRUNC_F32] = "truncf"; 123 Names[RTLIB::TRUNC_F64] = "trunc"; 124 Names[RTLIB::TRUNC_F80] = "truncl"; 125 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 126 Names[RTLIB::RINT_F32] = "rintf"; 127 Names[RTLIB::RINT_F64] = "rint"; 128 Names[RTLIB::RINT_F80] = "rintl"; 129 Names[RTLIB::RINT_PPCF128] = "rintl"; 130 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 131 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 132 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 133 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 134 Names[RTLIB::FLOOR_F32] = "floorf"; 135 Names[RTLIB::FLOOR_F64] = "floor"; 136 Names[RTLIB::FLOOR_F80] = "floorl"; 137 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 138 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 139 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 140 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 141 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 142 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 143 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 144 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 145 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 146 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 147 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 148 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 149 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 150 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 151 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 152 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 153 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 154 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 155 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 156 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 157 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 158 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 159 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 160 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 161 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 162 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 163 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 164 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 165 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 166 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 167 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 168 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 169 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 170 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 171 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 172 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 173 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 174 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 175 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 176 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 177 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 178 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 179 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 180 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 181 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 182 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 183 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 184 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 185 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 186 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 187 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 188 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 189 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 190 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 191 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 192 Names[RTLIB::OEQ_F32] = "__eqsf2"; 193 Names[RTLIB::OEQ_F64] = "__eqdf2"; 194 Names[RTLIB::UNE_F32] = "__nesf2"; 195 Names[RTLIB::UNE_F64] = "__nedf2"; 196 Names[RTLIB::OGE_F32] = "__gesf2"; 197 Names[RTLIB::OGE_F64] = "__gedf2"; 198 Names[RTLIB::OLT_F32] = "__ltsf2"; 199 Names[RTLIB::OLT_F64] = "__ltdf2"; 200 Names[RTLIB::OLE_F32] = "__lesf2"; 201 Names[RTLIB::OLE_F64] = "__ledf2"; 202 Names[RTLIB::OGT_F32] = "__gtsf2"; 203 Names[RTLIB::OGT_F64] = "__gtdf2"; 204 Names[RTLIB::UO_F32] = "__unordsf2"; 205 Names[RTLIB::UO_F64] = "__unorddf2"; 206 Names[RTLIB::O_F32] = "__unordsf2"; 207 Names[RTLIB::O_F64] = "__unorddf2"; 208} 209 210/// getFPEXT - Return the FPEXT_*_* value for the given types, or 211/// UNKNOWN_LIBCALL if there is none. 212RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 213 if (OpVT == MVT::f32) { 214 if (RetVT == MVT::f64) 215 return FPEXT_F32_F64; 216 } 217 return UNKNOWN_LIBCALL; 218} 219 220/// getFPROUND - Return the FPROUND_*_* value for the given types, or 221/// UNKNOWN_LIBCALL if there is none. 222RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 223 if (RetVT == MVT::f32) { 224 if (OpVT == MVT::f64) 225 return FPROUND_F64_F32; 226 if (OpVT == MVT::f80) 227 return FPROUND_F80_F32; 228 if (OpVT == MVT::ppcf128) 229 return FPROUND_PPCF128_F32; 230 } else if (RetVT == MVT::f64) { 231 if (OpVT == MVT::f80) 232 return FPROUND_F80_F64; 233 if (OpVT == MVT::ppcf128) 234 return FPROUND_PPCF128_F64; 235 } 236 return UNKNOWN_LIBCALL; 237} 238 239/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 240/// UNKNOWN_LIBCALL if there is none. 241RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 242 if (OpVT == MVT::f32) { 243 if (RetVT == MVT::i32) 244 return FPTOSINT_F32_I32; 245 if (RetVT == MVT::i64) 246 return FPTOSINT_F32_I64; 247 if (RetVT == MVT::i128) 248 return FPTOSINT_F32_I128; 249 } else if (OpVT == MVT::f64) { 250 if (RetVT == MVT::i32) 251 return FPTOSINT_F64_I32; 252 if (RetVT == MVT::i64) 253 return FPTOSINT_F64_I64; 254 if (RetVT == MVT::i128) 255 return FPTOSINT_F64_I128; 256 } else if (OpVT == MVT::f80) { 257 if (RetVT == MVT::i32) 258 return FPTOSINT_F80_I32; 259 if (RetVT == MVT::i64) 260 return FPTOSINT_F80_I64; 261 if (RetVT == MVT::i128) 262 return FPTOSINT_F80_I128; 263 } else if (OpVT == MVT::ppcf128) { 264 if (RetVT == MVT::i32) 265 return FPTOSINT_PPCF128_I32; 266 if (RetVT == MVT::i64) 267 return FPTOSINT_PPCF128_I64; 268 if (RetVT == MVT::i128) 269 return FPTOSINT_PPCF128_I128; 270 } 271 return UNKNOWN_LIBCALL; 272} 273 274/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 275/// UNKNOWN_LIBCALL if there is none. 276RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 277 if (OpVT == MVT::f32) { 278 if (RetVT == MVT::i32) 279 return FPTOUINT_F32_I32; 280 if (RetVT == MVT::i64) 281 return FPTOUINT_F32_I64; 282 if (RetVT == MVT::i128) 283 return FPTOUINT_F32_I128; 284 } else if (OpVT == MVT::f64) { 285 if (RetVT == MVT::i32) 286 return FPTOUINT_F64_I32; 287 if (RetVT == MVT::i64) 288 return FPTOUINT_F64_I64; 289 if (RetVT == MVT::i128) 290 return FPTOUINT_F64_I128; 291 } else if (OpVT == MVT::f80) { 292 if (RetVT == MVT::i32) 293 return FPTOUINT_F80_I32; 294 if (RetVT == MVT::i64) 295 return FPTOUINT_F80_I64; 296 if (RetVT == MVT::i128) 297 return FPTOUINT_F80_I128; 298 } else if (OpVT == MVT::ppcf128) { 299 if (RetVT == MVT::i32) 300 return FPTOUINT_PPCF128_I32; 301 if (RetVT == MVT::i64) 302 return FPTOUINT_PPCF128_I64; 303 if (RetVT == MVT::i128) 304 return FPTOUINT_PPCF128_I128; 305 } 306 return UNKNOWN_LIBCALL; 307} 308 309/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 310/// UNKNOWN_LIBCALL if there is none. 311RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 312 if (OpVT == MVT::i32) { 313 if (RetVT == MVT::f32) 314 return SINTTOFP_I32_F32; 315 else if (RetVT == MVT::f64) 316 return SINTTOFP_I32_F64; 317 else if (RetVT == MVT::f80) 318 return SINTTOFP_I32_F80; 319 else if (RetVT == MVT::ppcf128) 320 return SINTTOFP_I32_PPCF128; 321 } else if (OpVT == MVT::i64) { 322 if (RetVT == MVT::f32) 323 return SINTTOFP_I64_F32; 324 else if (RetVT == MVT::f64) 325 return SINTTOFP_I64_F64; 326 else if (RetVT == MVT::f80) 327 return SINTTOFP_I64_F80; 328 else if (RetVT == MVT::ppcf128) 329 return SINTTOFP_I64_PPCF128; 330 } else if (OpVT == MVT::i128) { 331 if (RetVT == MVT::f32) 332 return SINTTOFP_I128_F32; 333 else if (RetVT == MVT::f64) 334 return SINTTOFP_I128_F64; 335 else if (RetVT == MVT::f80) 336 return SINTTOFP_I128_F80; 337 else if (RetVT == MVT::ppcf128) 338 return SINTTOFP_I128_PPCF128; 339 } 340 return UNKNOWN_LIBCALL; 341} 342 343/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 344/// UNKNOWN_LIBCALL if there is none. 345RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 346 if (OpVT == MVT::i32) { 347 if (RetVT == MVT::f32) 348 return UINTTOFP_I32_F32; 349 else if (RetVT == MVT::f64) 350 return UINTTOFP_I32_F64; 351 else if (RetVT == MVT::f80) 352 return UINTTOFP_I32_F80; 353 else if (RetVT == MVT::ppcf128) 354 return UINTTOFP_I32_PPCF128; 355 } else if (OpVT == MVT::i64) { 356 if (RetVT == MVT::f32) 357 return UINTTOFP_I64_F32; 358 else if (RetVT == MVT::f64) 359 return UINTTOFP_I64_F64; 360 else if (RetVT == MVT::f80) 361 return UINTTOFP_I64_F80; 362 else if (RetVT == MVT::ppcf128) 363 return UINTTOFP_I64_PPCF128; 364 } else if (OpVT == MVT::i128) { 365 if (RetVT == MVT::f32) 366 return UINTTOFP_I128_F32; 367 else if (RetVT == MVT::f64) 368 return UINTTOFP_I128_F64; 369 else if (RetVT == MVT::f80) 370 return UINTTOFP_I128_F80; 371 else if (RetVT == MVT::ppcf128) 372 return UINTTOFP_I128_PPCF128; 373 } 374 return UNKNOWN_LIBCALL; 375} 376 377/// InitCmpLibcallCCs - Set default comparison libcall CC. 378/// 379static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 380 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 381 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 382 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 383 CCs[RTLIB::UNE_F32] = ISD::SETNE; 384 CCs[RTLIB::UNE_F64] = ISD::SETNE; 385 CCs[RTLIB::OGE_F32] = ISD::SETGE; 386 CCs[RTLIB::OGE_F64] = ISD::SETGE; 387 CCs[RTLIB::OLT_F32] = ISD::SETLT; 388 CCs[RTLIB::OLT_F64] = ISD::SETLT; 389 CCs[RTLIB::OLE_F32] = ISD::SETLE; 390 CCs[RTLIB::OLE_F64] = ISD::SETLE; 391 CCs[RTLIB::OGT_F32] = ISD::SETGT; 392 CCs[RTLIB::OGT_F64] = ISD::SETGT; 393 CCs[RTLIB::UO_F32] = ISD::SETNE; 394 CCs[RTLIB::UO_F64] = ISD::SETNE; 395 CCs[RTLIB::O_F32] = ISD::SETEQ; 396 CCs[RTLIB::O_F64] = ISD::SETEQ; 397} 398 399TargetLowering::TargetLowering(TargetMachine &tm) 400 : TM(tm), TD(TM.getTargetData()) { 401 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 402 "Fixed size array in TargetLowering is not large enough!"); 403 // All operations default to being supported. 404 memset(OpActions, 0, sizeof(OpActions)); 405 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 406 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 407 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 408 memset(ConvertActions, 0, sizeof(ConvertActions)); 409 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 410 411 // Set default actions for various operations. 412 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 413 // Default all indexed load / store to expand. 414 for (unsigned IM = (unsigned)ISD::PRE_INC; 415 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 416 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 417 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 418 } 419 420 // These operations default to expand. 421 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 422 } 423 424 // Most targets ignore the @llvm.prefetch intrinsic. 425 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 426 427 // ConstantFP nodes default to expand. Targets can either change this to 428 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 429 // to optimize expansions for certain constants. 430 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 431 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 432 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 433 434 // These library functions default to expand. 435 setOperationAction(ISD::FLOG , MVT::f64, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 437 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 438 setOperationAction(ISD::FEXP , MVT::f64, Expand); 439 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 440 setOperationAction(ISD::FLOG , MVT::f32, Expand); 441 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 443 setOperationAction(ISD::FEXP , MVT::f32, Expand); 444 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 445 446 // Default ISD::TRAP to expand (which turns it into abort). 447 setOperationAction(ISD::TRAP, MVT::Other, Expand); 448 449 IsLittleEndian = TD->isLittleEndian(); 450 UsesGlobalOffsetTable = false; 451 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 452 ShiftAmtHandling = Undefined; 453 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 454 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 455 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 456 allowUnalignedMemoryAccesses = false; 457 UseUnderscoreSetJmp = false; 458 UseUnderscoreLongJmp = false; 459 SelectIsExpensive = false; 460 IntDivIsCheap = false; 461 Pow2DivIsCheap = false; 462 StackPointerRegisterToSaveRestore = 0; 463 ExceptionPointerRegister = 0; 464 ExceptionSelectorRegister = 0; 465 SetCCResultContents = UndefinedSetCCResult; 466 SchedPreferenceInfo = SchedulingForLatency; 467 JumpBufSize = 0; 468 JumpBufAlignment = 0; 469 IfCvtBlockSizeLimit = 2; 470 IfCvtDupBlockSizeLimit = 0; 471 PrefLoopAlignment = 0; 472 473 InitLibcallNames(LibcallRoutineNames); 474 InitCmpLibcallCCs(CmpLibcallCCs); 475 476 // Tell Legalize whether the assembler supports DEBUG_LOC. 477 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 478 if (!TASM || !TASM->hasDotLocAndDotFile()) 479 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 480} 481 482TargetLowering::~TargetLowering() {} 483 484/// computeRegisterProperties - Once all of the register classes are added, 485/// this allows us to compute derived properties we expose. 486void TargetLowering::computeRegisterProperties() { 487 assert(MVT::LAST_VALUETYPE <= 32 && 488 "Too many value types for ValueTypeActions to hold!"); 489 490 // Everything defaults to needing one register. 491 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 492 NumRegistersForVT[i] = 1; 493 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 494 } 495 // ...except isVoid, which doesn't need any registers. 496 NumRegistersForVT[MVT::isVoid] = 0; 497 498 // Find the largest integer register class. 499 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 500 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 501 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 502 503 // Every integer value type larger than this largest register takes twice as 504 // many registers to represent as the previous ValueType. 505 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 506 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 507 if (!EVT.isInteger()) 508 break; 509 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 510 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 511 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 512 ValueTypeActions.setTypeAction(EVT, Expand); 513 } 514 515 // Inspect all of the ValueType's smaller than the largest integer 516 // register to see which ones need promotion. 517 unsigned LegalIntReg = LargestIntReg; 518 for (unsigned IntReg = LargestIntReg - 1; 519 IntReg >= (unsigned)MVT::i1; --IntReg) { 520 MVT IVT = (MVT::SimpleValueType)IntReg; 521 if (isTypeLegal(IVT)) { 522 LegalIntReg = IntReg; 523 } else { 524 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 525 (MVT::SimpleValueType)LegalIntReg; 526 ValueTypeActions.setTypeAction(IVT, Promote); 527 } 528 } 529 530 // ppcf128 type is really two f64's. 531 if (!isTypeLegal(MVT::ppcf128)) { 532 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 533 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 534 TransformToType[MVT::ppcf128] = MVT::f64; 535 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 536 } 537 538 // Decide how to handle f64. If the target does not have native f64 support, 539 // expand it to i64 and we will be generating soft float library calls. 540 if (!isTypeLegal(MVT::f64)) { 541 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 542 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 543 TransformToType[MVT::f64] = MVT::i64; 544 ValueTypeActions.setTypeAction(MVT::f64, Expand); 545 } 546 547 // Decide how to handle f32. If the target does not have native support for 548 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 549 if (!isTypeLegal(MVT::f32)) { 550 if (isTypeLegal(MVT::f64)) { 551 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 552 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 553 TransformToType[MVT::f32] = MVT::f64; 554 ValueTypeActions.setTypeAction(MVT::f32, Promote); 555 } else { 556 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 557 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 558 TransformToType[MVT::f32] = MVT::i32; 559 ValueTypeActions.setTypeAction(MVT::f32, Expand); 560 } 561 } 562 563 // Loop over all of the vector value types to see which need transformations. 564 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 565 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 566 MVT VT = (MVT::SimpleValueType)i; 567 if (!isTypeLegal(VT)) { 568 MVT IntermediateVT, RegisterVT; 569 unsigned NumIntermediates; 570 NumRegistersForVT[i] = 571 getVectorTypeBreakdown(VT, 572 IntermediateVT, NumIntermediates, 573 RegisterVT); 574 RegisterTypeForVT[i] = RegisterVT; 575 TransformToType[i] = MVT::Other; // this isn't actually used 576 ValueTypeActions.setTypeAction(VT, Expand); 577 } 578 } 579} 580 581const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 582 return NULL; 583} 584 585 586MVT TargetLowering::getSetCCResultType(const SDValue &) const { 587 return getValueType(TD->getIntPtrType()); 588} 589 590 591/// getVectorTypeBreakdown - Vector types are broken down into some number of 592/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 593/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 594/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 595/// 596/// This method returns the number of registers needed, and the VT for each 597/// register. It also returns the VT and quantity of the intermediate values 598/// before they are promoted/expanded. 599/// 600unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 601 MVT &IntermediateVT, 602 unsigned &NumIntermediates, 603 MVT &RegisterVT) const { 604 // Figure out the right, legal destination reg to copy into. 605 unsigned NumElts = VT.getVectorNumElements(); 606 MVT EltTy = VT.getVectorElementType(); 607 608 unsigned NumVectorRegs = 1; 609 610 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 611 // could break down into LHS/RHS like LegalizeDAG does. 612 if (!isPowerOf2_32(NumElts)) { 613 NumVectorRegs = NumElts; 614 NumElts = 1; 615 } 616 617 // Divide the input until we get to a supported size. This will always 618 // end with a scalar if the target doesn't support vectors. 619 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 620 NumElts >>= 1; 621 NumVectorRegs <<= 1; 622 } 623 624 NumIntermediates = NumVectorRegs; 625 626 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 627 if (!isTypeLegal(NewVT)) 628 NewVT = EltTy; 629 IntermediateVT = NewVT; 630 631 MVT DestVT = getTypeToTransformTo(NewVT); 632 RegisterVT = DestVT; 633 if (DestVT.bitsLT(NewVT)) { 634 // Value is expanded, e.g. i64 -> i16. 635 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 636 } else { 637 // Otherwise, promotion or legal types use the same number of registers as 638 // the vector decimated to the appropriate level. 639 return NumVectorRegs; 640 } 641 642 return 1; 643} 644 645/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 646/// function arguments in the caller parameter area. This is the actual 647/// alignment, not its logarithm. 648unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 649 return TD->getCallFrameTypeAlignment(Ty); 650} 651 652SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 653 SelectionDAG &DAG) const { 654 if (usesGlobalOffsetTable()) 655 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 656 return Table; 657} 658 659bool 660TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 661 // Assume that everything is safe in static mode. 662 if (getTargetMachine().getRelocationModel() == Reloc::Static) 663 return true; 664 665 // In dynamic-no-pic mode, assume that known defined values are safe. 666 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 667 GA && 668 !GA->getGlobal()->isDeclaration() && 669 !GA->getGlobal()->mayBeOverridden()) 670 return true; 671 672 // Otherwise assume nothing is safe. 673 return false; 674} 675 676//===----------------------------------------------------------------------===// 677// Optimization Methods 678//===----------------------------------------------------------------------===// 679 680/// ShrinkDemandedConstant - Check to see if the specified operand of the 681/// specified instruction is a constant integer. If so, check to see if there 682/// are any bits set in the constant that are not demanded. If so, shrink the 683/// constant and return true. 684bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 685 const APInt &Demanded) { 686 // FIXME: ISD::SELECT, ISD::SELECT_CC 687 switch(Op.getOpcode()) { 688 default: break; 689 case ISD::AND: 690 case ISD::OR: 691 case ISD::XOR: 692 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 693 if (C->getAPIntValue().intersects(~Demanded)) { 694 MVT VT = Op.getValueType(); 695 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 696 DAG.getConstant(Demanded & 697 C->getAPIntValue(), 698 VT)); 699 return CombineTo(Op, New); 700 } 701 break; 702 } 703 return false; 704} 705 706/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 707/// DemandedMask bits of the result of Op are ever used downstream. If we can 708/// use this information to simplify Op, create a new simplified DAG node and 709/// return true, returning the original and new nodes in Old and New. Otherwise, 710/// analyze the expression and return a mask of KnownOne and KnownZero bits for 711/// the expression (used to simplify the caller). The KnownZero/One bits may 712/// only be accurate for those bits in the DemandedMask. 713bool TargetLowering::SimplifyDemandedBits(SDValue Op, 714 const APInt &DemandedMask, 715 APInt &KnownZero, 716 APInt &KnownOne, 717 TargetLoweringOpt &TLO, 718 unsigned Depth) const { 719 unsigned BitWidth = DemandedMask.getBitWidth(); 720 assert(Op.getValueSizeInBits() == BitWidth && 721 "Mask size mismatches value type size!"); 722 APInt NewMask = DemandedMask; 723 724 // Don't know anything. 725 KnownZero = KnownOne = APInt(BitWidth, 0); 726 727 // Other users may use these bits. 728 if (!Op.getNode()->hasOneUse()) { 729 if (Depth != 0) { 730 // If not at the root, Just compute the KnownZero/KnownOne bits to 731 // simplify things downstream. 732 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 733 return false; 734 } 735 // If this is the root being simplified, allow it to have multiple uses, 736 // just set the NewMask to all bits. 737 NewMask = APInt::getAllOnesValue(BitWidth); 738 } else if (DemandedMask == 0) { 739 // Not demanding any bits from Op. 740 if (Op.getOpcode() != ISD::UNDEF) 741 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 742 return false; 743 } else if (Depth == 6) { // Limit search depth. 744 return false; 745 } 746 747 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 748 switch (Op.getOpcode()) { 749 case ISD::Constant: 750 // We know all of the bits for a constant! 751 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 752 KnownZero = ~KnownOne & NewMask; 753 return false; // Don't fall through, will infinitely loop. 754 case ISD::AND: 755 // If the RHS is a constant, check to see if the LHS would be zero without 756 // using the bits from the RHS. Below, we use knowledge about the RHS to 757 // simplify the LHS, here we're using information from the LHS to simplify 758 // the RHS. 759 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 760 APInt LHSZero, LHSOne; 761 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 762 LHSZero, LHSOne, Depth+1); 763 // If the LHS already has zeros where RHSC does, this and is dead. 764 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 765 return TLO.CombineTo(Op, Op.getOperand(0)); 766 // If any of the set bits in the RHS are known zero on the LHS, shrink 767 // the constant. 768 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 769 return true; 770 } 771 772 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 773 KnownOne, TLO, Depth+1)) 774 return true; 775 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 776 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 777 KnownZero2, KnownOne2, TLO, Depth+1)) 778 return true; 779 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 780 781 // If all of the demanded bits are known one on one side, return the other. 782 // These bits cannot contribute to the result of the 'and'. 783 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 784 return TLO.CombineTo(Op, Op.getOperand(0)); 785 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 786 return TLO.CombineTo(Op, Op.getOperand(1)); 787 // If all of the demanded bits in the inputs are known zeros, return zero. 788 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 789 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 790 // If the RHS is a constant, see if we can simplify it. 791 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 792 return true; 793 794 // Output known-1 bits are only known if set in both the LHS & RHS. 795 KnownOne &= KnownOne2; 796 // Output known-0 are known to be clear if zero in either the LHS | RHS. 797 KnownZero |= KnownZero2; 798 break; 799 case ISD::OR: 800 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 801 KnownOne, TLO, Depth+1)) 802 return true; 803 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 804 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 805 KnownZero2, KnownOne2, TLO, Depth+1)) 806 return true; 807 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 808 809 // If all of the demanded bits are known zero on one side, return the other. 810 // These bits cannot contribute to the result of the 'or'. 811 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 812 return TLO.CombineTo(Op, Op.getOperand(0)); 813 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 814 return TLO.CombineTo(Op, Op.getOperand(1)); 815 // If all of the potentially set bits on one side are known to be set on 816 // the other side, just use the 'other' side. 817 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 818 return TLO.CombineTo(Op, Op.getOperand(0)); 819 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 820 return TLO.CombineTo(Op, Op.getOperand(1)); 821 // If the RHS is a constant, see if we can simplify it. 822 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 823 return true; 824 825 // Output known-0 bits are only known if clear in both the LHS & RHS. 826 KnownZero &= KnownZero2; 827 // Output known-1 are known to be set if set in either the LHS | RHS. 828 KnownOne |= KnownOne2; 829 break; 830 case ISD::XOR: 831 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 832 KnownOne, TLO, Depth+1)) 833 return true; 834 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 835 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 836 KnownOne2, TLO, Depth+1)) 837 return true; 838 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 839 840 // If all of the demanded bits are known zero on one side, return the other. 841 // These bits cannot contribute to the result of the 'xor'. 842 if ((KnownZero & NewMask) == NewMask) 843 return TLO.CombineTo(Op, Op.getOperand(0)); 844 if ((KnownZero2 & NewMask) == NewMask) 845 return TLO.CombineTo(Op, Op.getOperand(1)); 846 847 // If all of the unknown bits are known to be zero on one side or the other 848 // (but not both) turn this into an *inclusive* or. 849 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 850 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 851 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 852 Op.getOperand(0), 853 Op.getOperand(1))); 854 855 // Output known-0 bits are known if clear or set in both the LHS & RHS. 856 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 857 // Output known-1 are known to be set if set in only one of the LHS, RHS. 858 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 859 860 // If all of the demanded bits on one side are known, and all of the set 861 // bits on that side are also known to be set on the other side, turn this 862 // into an AND, as we know the bits will be cleared. 863 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 864 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 865 if ((KnownOne & KnownOne2) == KnownOne) { 866 MVT VT = Op.getValueType(); 867 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 868 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 869 ANDC)); 870 } 871 } 872 873 // If the RHS is a constant, see if we can simplify it. 874 // for XOR, we prefer to force bits to 1 if they will make a -1. 875 // if we can't force bits, try to shrink constant 876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 877 APInt Expanded = C->getAPIntValue() | (~NewMask); 878 // if we can expand it to have all bits set, do it 879 if (Expanded.isAllOnesValue()) { 880 if (Expanded != C->getAPIntValue()) { 881 MVT VT = Op.getValueType(); 882 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 883 TLO.DAG.getConstant(Expanded, VT)); 884 return TLO.CombineTo(Op, New); 885 } 886 // if it already has all the bits set, nothing to change 887 // but don't shrink either! 888 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 889 return true; 890 } 891 } 892 893 KnownZero = KnownZeroOut; 894 KnownOne = KnownOneOut; 895 break; 896 case ISD::SELECT: 897 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 898 KnownOne, TLO, Depth+1)) 899 return true; 900 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 901 KnownOne2, TLO, Depth+1)) 902 return true; 903 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 904 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 905 906 // If the operands are constants, see if we can simplify them. 907 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 908 return true; 909 910 // Only known if known in both the LHS and RHS. 911 KnownOne &= KnownOne2; 912 KnownZero &= KnownZero2; 913 break; 914 case ISD::SELECT_CC: 915 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 916 KnownOne, TLO, Depth+1)) 917 return true; 918 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 919 KnownOne2, TLO, Depth+1)) 920 return true; 921 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 922 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 923 924 // If the operands are constants, see if we can simplify them. 925 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 926 return true; 927 928 // Only known if known in both the LHS and RHS. 929 KnownOne &= KnownOne2; 930 KnownZero &= KnownZero2; 931 break; 932 case ISD::SHL: 933 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 934 unsigned ShAmt = SA->getZExtValue(); 935 SDValue InOp = Op.getOperand(0); 936 937 // If the shift count is an invalid immediate, don't do anything. 938 if (ShAmt >= BitWidth) 939 break; 940 941 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 942 // single shift. We can do this if the bottom bits (which are shifted 943 // out) are never demanded. 944 if (InOp.getOpcode() == ISD::SRL && 945 isa<ConstantSDNode>(InOp.getOperand(1))) { 946 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 947 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 948 unsigned Opc = ISD::SHL; 949 int Diff = ShAmt-C1; 950 if (Diff < 0) { 951 Diff = -Diff; 952 Opc = ISD::SRL; 953 } 954 955 SDValue NewSA = 956 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 957 MVT VT = Op.getValueType(); 958 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 959 InOp.getOperand(0), NewSA)); 960 } 961 } 962 963 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 964 KnownZero, KnownOne, TLO, Depth+1)) 965 return true; 966 KnownZero <<= SA->getZExtValue(); 967 KnownOne <<= SA->getZExtValue(); 968 // low bits known zero. 969 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 970 } 971 break; 972 case ISD::SRL: 973 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 974 MVT VT = Op.getValueType(); 975 unsigned ShAmt = SA->getZExtValue(); 976 unsigned VTSize = VT.getSizeInBits(); 977 SDValue InOp = Op.getOperand(0); 978 979 // If the shift count is an invalid immediate, don't do anything. 980 if (ShAmt >= BitWidth) 981 break; 982 983 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 984 // single shift. We can do this if the top bits (which are shifted out) 985 // are never demanded. 986 if (InOp.getOpcode() == ISD::SHL && 987 isa<ConstantSDNode>(InOp.getOperand(1))) { 988 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 989 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 990 unsigned Opc = ISD::SRL; 991 int Diff = ShAmt-C1; 992 if (Diff < 0) { 993 Diff = -Diff; 994 Opc = ISD::SHL; 995 } 996 997 SDValue NewSA = 998 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 999 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 1000 InOp.getOperand(0), NewSA)); 1001 } 1002 } 1003 1004 // Compute the new bits that are at the top now. 1005 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1006 KnownZero, KnownOne, TLO, Depth+1)) 1007 return true; 1008 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1009 KnownZero = KnownZero.lshr(ShAmt); 1010 KnownOne = KnownOne.lshr(ShAmt); 1011 1012 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1013 KnownZero |= HighBits; // High bits known zero. 1014 } 1015 break; 1016 case ISD::SRA: 1017 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1018 MVT VT = Op.getValueType(); 1019 unsigned ShAmt = SA->getZExtValue(); 1020 1021 // If the shift count is an invalid immediate, don't do anything. 1022 if (ShAmt >= BitWidth) 1023 break; 1024 1025 APInt InDemandedMask = (NewMask << ShAmt); 1026 1027 // If any of the demanded bits are produced by the sign extension, we also 1028 // demand the input sign bit. 1029 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1030 if (HighBits.intersects(NewMask)) 1031 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1032 1033 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1034 KnownZero, KnownOne, TLO, Depth+1)) 1035 return true; 1036 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1037 KnownZero = KnownZero.lshr(ShAmt); 1038 KnownOne = KnownOne.lshr(ShAmt); 1039 1040 // Handle the sign bit, adjusted to where it is now in the mask. 1041 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1042 1043 // If the input sign bit is known to be zero, or if none of the top bits 1044 // are demanded, turn this into an unsigned shift right. 1045 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1046 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 1047 Op.getOperand(1))); 1048 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1049 KnownOne |= HighBits; 1050 } 1051 } 1052 break; 1053 case ISD::SIGN_EXTEND_INREG: { 1054 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1055 1056 // Sign extension. Compute the demanded bits in the result that are not 1057 // present in the input. 1058 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1059 BitWidth - EVT.getSizeInBits()) & 1060 NewMask; 1061 1062 // If none of the extended bits are demanded, eliminate the sextinreg. 1063 if (NewBits == 0) 1064 return TLO.CombineTo(Op, Op.getOperand(0)); 1065 1066 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1067 InSignBit.zext(BitWidth); 1068 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1069 EVT.getSizeInBits()) & 1070 NewMask; 1071 1072 // Since the sign extended bits are demanded, we know that the sign 1073 // bit is demanded. 1074 InputDemandedBits |= InSignBit; 1075 1076 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1077 KnownZero, KnownOne, TLO, Depth+1)) 1078 return true; 1079 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1080 1081 // If the sign bit of the input is known set or clear, then we know the 1082 // top bits of the result. 1083 1084 // If the input sign bit is known zero, convert this into a zero extension. 1085 if (KnownZero.intersects(InSignBit)) 1086 return TLO.CombineTo(Op, 1087 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1088 1089 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1090 KnownOne |= NewBits; 1091 KnownZero &= ~NewBits; 1092 } else { // Input sign bit unknown 1093 KnownZero &= ~NewBits; 1094 KnownOne &= ~NewBits; 1095 } 1096 break; 1097 } 1098 case ISD::ZERO_EXTEND: { 1099 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1100 APInt InMask = NewMask; 1101 InMask.trunc(OperandBitWidth); 1102 1103 // If none of the top bits are demanded, convert this into an any_extend. 1104 APInt NewBits = 1105 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1106 if (!NewBits.intersects(NewMask)) 1107 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1108 Op.getValueType(), 1109 Op.getOperand(0))); 1110 1111 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1112 KnownZero, KnownOne, TLO, Depth+1)) 1113 return true; 1114 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1115 KnownZero.zext(BitWidth); 1116 KnownOne.zext(BitWidth); 1117 KnownZero |= NewBits; 1118 break; 1119 } 1120 case ISD::SIGN_EXTEND: { 1121 MVT InVT = Op.getOperand(0).getValueType(); 1122 unsigned InBits = InVT.getSizeInBits(); 1123 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1124 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1125 APInt NewBits = ~InMask & NewMask; 1126 1127 // If none of the top bits are demanded, convert this into an any_extend. 1128 if (NewBits == 0) 1129 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1130 Op.getOperand(0))); 1131 1132 // Since some of the sign extended bits are demanded, we know that the sign 1133 // bit is demanded. 1134 APInt InDemandedBits = InMask & NewMask; 1135 InDemandedBits |= InSignBit; 1136 InDemandedBits.trunc(InBits); 1137 1138 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1139 KnownOne, TLO, Depth+1)) 1140 return true; 1141 KnownZero.zext(BitWidth); 1142 KnownOne.zext(BitWidth); 1143 1144 // If the sign bit is known zero, convert this to a zero extend. 1145 if (KnownZero.intersects(InSignBit)) 1146 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1147 Op.getValueType(), 1148 Op.getOperand(0))); 1149 1150 // If the sign bit is known one, the top bits match. 1151 if (KnownOne.intersects(InSignBit)) { 1152 KnownOne |= NewBits; 1153 KnownZero &= ~NewBits; 1154 } else { // Otherwise, top bits aren't known. 1155 KnownOne &= ~NewBits; 1156 KnownZero &= ~NewBits; 1157 } 1158 break; 1159 } 1160 case ISD::ANY_EXTEND: { 1161 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1162 APInt InMask = NewMask; 1163 InMask.trunc(OperandBitWidth); 1164 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1165 KnownZero, KnownOne, TLO, Depth+1)) 1166 return true; 1167 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1168 KnownZero.zext(BitWidth); 1169 KnownOne.zext(BitWidth); 1170 break; 1171 } 1172 case ISD::TRUNCATE: { 1173 // Simplify the input, using demanded bit information, and compute the known 1174 // zero/one bits live out. 1175 APInt TruncMask = NewMask; 1176 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1177 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1178 KnownZero, KnownOne, TLO, Depth+1)) 1179 return true; 1180 KnownZero.trunc(BitWidth); 1181 KnownOne.trunc(BitWidth); 1182 1183 // If the input is only used by this truncate, see if we can shrink it based 1184 // on the known demanded bits. 1185 if (Op.getOperand(0).getNode()->hasOneUse()) { 1186 SDValue In = Op.getOperand(0); 1187 unsigned InBitWidth = In.getValueSizeInBits(); 1188 switch (In.getOpcode()) { 1189 default: break; 1190 case ISD::SRL: 1191 // Shrink SRL by a constant if none of the high bits shifted in are 1192 // demanded. 1193 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1194 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1195 InBitWidth - BitWidth); 1196 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1197 HighBits.trunc(BitWidth); 1198 1199 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1200 // None of the shifted in bits are needed. Add a truncate of the 1201 // shift input, then shift it. 1202 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1203 Op.getValueType(), 1204 In.getOperand(0)); 1205 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1206 NewTrunc, In.getOperand(1))); 1207 } 1208 } 1209 break; 1210 } 1211 } 1212 1213 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1214 break; 1215 } 1216 case ISD::AssertZext: { 1217 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1218 APInt InMask = APInt::getLowBitsSet(BitWidth, 1219 VT.getSizeInBits()); 1220 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1221 KnownZero, KnownOne, TLO, Depth+1)) 1222 return true; 1223 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1224 KnownZero |= ~InMask & NewMask; 1225 break; 1226 } 1227 case ISD::BIT_CONVERT: 1228#if 0 1229 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1230 // is demanded, turn this into a FGETSIGN. 1231 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1232 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1233 !MVT::isVector(Op.getOperand(0).getValueType())) { 1234 // Only do this xform if FGETSIGN is valid or if before legalize. 1235 if (!TLO.AfterLegalize || 1236 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1237 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1238 // place. We expect the SHL to be eliminated by other optimizations. 1239 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1240 Op.getOperand(0)); 1241 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1242 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1243 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1244 Sign, ShAmt)); 1245 } 1246 } 1247#endif 1248 break; 1249 default: 1250 // Just use ComputeMaskedBits to compute output bits. 1251 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1252 break; 1253 } 1254 1255 // If we know the value of all of the demanded bits, return this as a 1256 // constant. 1257 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1258 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1259 1260 return false; 1261} 1262 1263/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1264/// in Mask are known to be either zero or one and return them in the 1265/// KnownZero/KnownOne bitsets. 1266void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1267 const APInt &Mask, 1268 APInt &KnownZero, 1269 APInt &KnownOne, 1270 const SelectionDAG &DAG, 1271 unsigned Depth) const { 1272 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1273 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1274 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1275 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1276 "Should use MaskedValueIsZero if you don't know whether Op" 1277 " is a target node!"); 1278 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1279} 1280 1281/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1282/// targets that want to expose additional information about sign bits to the 1283/// DAG Combiner. 1284unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1285 unsigned Depth) const { 1286 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1287 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1288 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1289 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1290 "Should use ComputeNumSignBits if you don't know whether Op" 1291 " is a target node!"); 1292 return 1; 1293} 1294 1295 1296/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1297/// and cc. If it is unable to simplify it, return a null SDValue. 1298SDValue 1299TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1300 ISD::CondCode Cond, bool foldBooleans, 1301 DAGCombinerInfo &DCI) const { 1302 SelectionDAG &DAG = DCI.DAG; 1303 1304 // These setcc operations always fold. 1305 switch (Cond) { 1306 default: break; 1307 case ISD::SETFALSE: 1308 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1309 case ISD::SETTRUE: 1310 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1311 } 1312 1313 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1314 const APInt &C1 = N1C->getAPIntValue(); 1315 if (isa<ConstantSDNode>(N0.getNode())) { 1316 return DAG.FoldSetCC(VT, N0, N1, Cond); 1317 } else { 1318 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1319 // equality comparison, then we're just comparing whether X itself is 1320 // zero. 1321 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1322 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1323 N0.getOperand(1).getOpcode() == ISD::Constant) { 1324 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1325 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1326 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1327 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1328 // (srl (ctlz x), 5) == 0 -> X != 0 1329 // (srl (ctlz x), 5) != 1 -> X != 0 1330 Cond = ISD::SETNE; 1331 } else { 1332 // (srl (ctlz x), 5) != 0 -> X == 0 1333 // (srl (ctlz x), 5) == 1 -> X == 0 1334 Cond = ISD::SETEQ; 1335 } 1336 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1337 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1338 Zero, Cond); 1339 } 1340 } 1341 1342 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1343 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1344 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1345 1346 // If the comparison constant has bits in the upper part, the 1347 // zero-extended value could never match. 1348 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1349 C1.getBitWidth() - InSize))) { 1350 switch (Cond) { 1351 case ISD::SETUGT: 1352 case ISD::SETUGE: 1353 case ISD::SETEQ: return DAG.getConstant(0, VT); 1354 case ISD::SETULT: 1355 case ISD::SETULE: 1356 case ISD::SETNE: return DAG.getConstant(1, VT); 1357 case ISD::SETGT: 1358 case ISD::SETGE: 1359 // True if the sign bit of C1 is set. 1360 return DAG.getConstant(C1.isNegative(), VT); 1361 case ISD::SETLT: 1362 case ISD::SETLE: 1363 // True if the sign bit of C1 isn't set. 1364 return DAG.getConstant(C1.isNonNegative(), VT); 1365 default: 1366 break; 1367 } 1368 } 1369 1370 // Otherwise, we can perform the comparison with the low bits. 1371 switch (Cond) { 1372 case ISD::SETEQ: 1373 case ISD::SETNE: 1374 case ISD::SETUGT: 1375 case ISD::SETUGE: 1376 case ISD::SETULT: 1377 case ISD::SETULE: 1378 return DAG.getSetCC(VT, N0.getOperand(0), 1379 DAG.getConstant(APInt(C1).trunc(InSize), 1380 N0.getOperand(0).getValueType()), 1381 Cond); 1382 default: 1383 break; // todo, be more careful with signed comparisons 1384 } 1385 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1386 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1387 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1388 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1389 MVT ExtDstTy = N0.getValueType(); 1390 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1391 1392 // If the extended part has any inconsistent bits, it cannot ever 1393 // compare equal. In other words, they have to be all ones or all 1394 // zeros. 1395 APInt ExtBits = 1396 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1397 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1398 return DAG.getConstant(Cond == ISD::SETNE, VT); 1399 1400 SDValue ZextOp; 1401 MVT Op0Ty = N0.getOperand(0).getValueType(); 1402 if (Op0Ty == ExtSrcTy) { 1403 ZextOp = N0.getOperand(0); 1404 } else { 1405 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1406 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1407 DAG.getConstant(Imm, Op0Ty)); 1408 } 1409 if (!DCI.isCalledByLegalizer()) 1410 DCI.AddToWorklist(ZextOp.getNode()); 1411 // Otherwise, make this a use of a zext. 1412 return DAG.getSetCC(VT, ZextOp, 1413 DAG.getConstant(C1 & APInt::getLowBitsSet( 1414 ExtDstTyBits, 1415 ExtSrcTyBits), 1416 ExtDstTy), 1417 Cond); 1418 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1419 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1420 1421 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1422 if (N0.getOpcode() == ISD::SETCC) { 1423 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1424 if (TrueWhenTrue) 1425 return N0; 1426 1427 // Invert the condition. 1428 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1429 CC = ISD::getSetCCInverse(CC, 1430 N0.getOperand(0).getValueType().isInteger()); 1431 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1432 } 1433 1434 if ((N0.getOpcode() == ISD::XOR || 1435 (N0.getOpcode() == ISD::AND && 1436 N0.getOperand(0).getOpcode() == ISD::XOR && 1437 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1438 isa<ConstantSDNode>(N0.getOperand(1)) && 1439 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1440 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1441 // can only do this if the top bits are known zero. 1442 unsigned BitWidth = N0.getValueSizeInBits(); 1443 if (DAG.MaskedValueIsZero(N0, 1444 APInt::getHighBitsSet(BitWidth, 1445 BitWidth-1))) { 1446 // Okay, get the un-inverted input value. 1447 SDValue Val; 1448 if (N0.getOpcode() == ISD::XOR) 1449 Val = N0.getOperand(0); 1450 else { 1451 assert(N0.getOpcode() == ISD::AND && 1452 N0.getOperand(0).getOpcode() == ISD::XOR); 1453 // ((X^1)&1)^1 -> X & 1 1454 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1455 N0.getOperand(0).getOperand(0), 1456 N0.getOperand(1)); 1457 } 1458 return DAG.getSetCC(VT, Val, N1, 1459 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1460 } 1461 } 1462 } 1463 1464 APInt MinVal, MaxVal; 1465 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1466 if (ISD::isSignedIntSetCC(Cond)) { 1467 MinVal = APInt::getSignedMinValue(OperandBitSize); 1468 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1469 } else { 1470 MinVal = APInt::getMinValue(OperandBitSize); 1471 MaxVal = APInt::getMaxValue(OperandBitSize); 1472 } 1473 1474 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1475 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1476 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1477 // X >= C0 --> X > (C0-1) 1478 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1479 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1480 } 1481 1482 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1483 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1484 // X <= C0 --> X < (C0+1) 1485 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1486 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1487 } 1488 1489 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1490 return DAG.getConstant(0, VT); // X < MIN --> false 1491 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1492 return DAG.getConstant(1, VT); // X >= MIN --> true 1493 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1494 return DAG.getConstant(0, VT); // X > MAX --> false 1495 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1496 return DAG.getConstant(1, VT); // X <= MAX --> true 1497 1498 // Canonicalize setgt X, Min --> setne X, Min 1499 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1500 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1501 // Canonicalize setlt X, Max --> setne X, Max 1502 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1503 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1504 1505 // If we have setult X, 1, turn it into seteq X, 0 1506 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1507 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1508 ISD::SETEQ); 1509 // If we have setugt X, Max-1, turn it into seteq X, Max 1510 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1511 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1512 ISD::SETEQ); 1513 1514 // If we have "setcc X, C0", check to see if we can shrink the immediate 1515 // by changing cc. 1516 1517 // SETUGT X, SINTMAX -> SETLT X, 0 1518 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1519 C1 == (~0ULL >> (65-OperandBitSize))) 1520 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1521 ISD::SETLT); 1522 1523 // FIXME: Implement the rest of these. 1524 1525 // Fold bit comparisons when we can. 1526 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1527 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1528 if (ConstantSDNode *AndRHS = 1529 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1530 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1531 // Perform the xform if the AND RHS is a single bit. 1532 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1533 return DAG.getNode(ISD::SRL, VT, N0, 1534 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1535 getShiftAmountTy())); 1536 } 1537 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1538 // (X & 8) == 8 --> (X & 8) >> 3 1539 // Perform the xform if C1 is a single bit. 1540 if (C1.isPowerOf2()) { 1541 return DAG.getNode(ISD::SRL, VT, N0, 1542 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1543 } 1544 } 1545 } 1546 } 1547 } else if (isa<ConstantSDNode>(N0.getNode())) { 1548 // Ensure that the constant occurs on the RHS. 1549 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1550 } 1551 1552 if (isa<ConstantFPSDNode>(N0.getNode())) { 1553 // Constant fold or commute setcc. 1554 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1555 if (O.getNode()) return O; 1556 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1557 // If the RHS of an FP comparison is a constant, simplify it away in 1558 // some cases. 1559 if (CFP->getValueAPF().isNaN()) { 1560 // If an operand is known to be a nan, we can fold it. 1561 switch (ISD::getUnorderedFlavor(Cond)) { 1562 default: assert(0 && "Unknown flavor!"); 1563 case 0: // Known false. 1564 return DAG.getConstant(0, VT); 1565 case 1: // Known true. 1566 return DAG.getConstant(1, VT); 1567 case 2: // Undefined. 1568 return DAG.getNode(ISD::UNDEF, VT); 1569 } 1570 } 1571 1572 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1573 // constant if knowing that the operand is non-nan is enough. We prefer to 1574 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1575 // materialize 0.0. 1576 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1577 return DAG.getSetCC(VT, N0, N0, Cond); 1578 } 1579 1580 if (N0 == N1) { 1581 // We can always fold X == X for integer setcc's. 1582 if (N0.getValueType().isInteger()) 1583 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1584 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1585 if (UOF == 2) // FP operators that are undefined on NaNs. 1586 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1587 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1588 return DAG.getConstant(UOF, VT); 1589 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1590 // if it is not already. 1591 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1592 if (NewCond != Cond) 1593 return DAG.getSetCC(VT, N0, N1, NewCond); 1594 } 1595 1596 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1597 N0.getValueType().isInteger()) { 1598 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1599 N0.getOpcode() == ISD::XOR) { 1600 // Simplify (X+Y) == (X+Z) --> Y == Z 1601 if (N0.getOpcode() == N1.getOpcode()) { 1602 if (N0.getOperand(0) == N1.getOperand(0)) 1603 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1604 if (N0.getOperand(1) == N1.getOperand(1)) 1605 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1606 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1607 // If X op Y == Y op X, try other combinations. 1608 if (N0.getOperand(0) == N1.getOperand(1)) 1609 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1610 if (N0.getOperand(1) == N1.getOperand(0)) 1611 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1612 } 1613 } 1614 1615 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1616 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1617 // Turn (X+C1) == C2 --> X == C2-C1 1618 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1619 return DAG.getSetCC(VT, N0.getOperand(0), 1620 DAG.getConstant(RHSC->getAPIntValue()- 1621 LHSR->getAPIntValue(), 1622 N0.getValueType()), Cond); 1623 } 1624 1625 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1626 if (N0.getOpcode() == ISD::XOR) 1627 // If we know that all of the inverted bits are zero, don't bother 1628 // performing the inversion. 1629 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1630 return 1631 DAG.getSetCC(VT, N0.getOperand(0), 1632 DAG.getConstant(LHSR->getAPIntValue() ^ 1633 RHSC->getAPIntValue(), 1634 N0.getValueType()), 1635 Cond); 1636 } 1637 1638 // Turn (C1-X) == C2 --> X == C1-C2 1639 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1640 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1641 return 1642 DAG.getSetCC(VT, N0.getOperand(1), 1643 DAG.getConstant(SUBC->getAPIntValue() - 1644 RHSC->getAPIntValue(), 1645 N0.getValueType()), 1646 Cond); 1647 } 1648 } 1649 } 1650 1651 // Simplify (X+Z) == X --> Z == 0 1652 if (N0.getOperand(0) == N1) 1653 return DAG.getSetCC(VT, N0.getOperand(1), 1654 DAG.getConstant(0, N0.getValueType()), Cond); 1655 if (N0.getOperand(1) == N1) { 1656 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1657 return DAG.getSetCC(VT, N0.getOperand(0), 1658 DAG.getConstant(0, N0.getValueType()), Cond); 1659 else if (N0.getNode()->hasOneUse()) { 1660 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1661 // (Z-X) == X --> Z == X<<1 1662 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1663 N1, 1664 DAG.getConstant(1, getShiftAmountTy())); 1665 if (!DCI.isCalledByLegalizer()) 1666 DCI.AddToWorklist(SH.getNode()); 1667 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1668 } 1669 } 1670 } 1671 1672 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1673 N1.getOpcode() == ISD::XOR) { 1674 // Simplify X == (X+Z) --> Z == 0 1675 if (N1.getOperand(0) == N0) { 1676 return DAG.getSetCC(VT, N1.getOperand(1), 1677 DAG.getConstant(0, N1.getValueType()), Cond); 1678 } else if (N1.getOperand(1) == N0) { 1679 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1680 return DAG.getSetCC(VT, N1.getOperand(0), 1681 DAG.getConstant(0, N1.getValueType()), Cond); 1682 } else if (N1.getNode()->hasOneUse()) { 1683 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1684 // X == (Z-X) --> X<<1 == Z 1685 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1686 DAG.getConstant(1, getShiftAmountTy())); 1687 if (!DCI.isCalledByLegalizer()) 1688 DCI.AddToWorklist(SH.getNode()); 1689 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1690 } 1691 } 1692 } 1693 } 1694 1695 // Fold away ALL boolean setcc's. 1696 SDValue Temp; 1697 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1698 switch (Cond) { 1699 default: assert(0 && "Unknown integer setcc!"); 1700 case ISD::SETEQ: // X == Y -> (X^Y)^1 1701 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1702 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1703 if (!DCI.isCalledByLegalizer()) 1704 DCI.AddToWorklist(Temp.getNode()); 1705 break; 1706 case ISD::SETNE: // X != Y --> (X^Y) 1707 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1708 break; 1709 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1710 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1711 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1712 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1713 if (!DCI.isCalledByLegalizer()) 1714 DCI.AddToWorklist(Temp.getNode()); 1715 break; 1716 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1717 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1718 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1719 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1720 if (!DCI.isCalledByLegalizer()) 1721 DCI.AddToWorklist(Temp.getNode()); 1722 break; 1723 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1724 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1725 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1726 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1727 if (!DCI.isCalledByLegalizer()) 1728 DCI.AddToWorklist(Temp.getNode()); 1729 break; 1730 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1731 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1732 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1733 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1734 break; 1735 } 1736 if (VT != MVT::i1) { 1737 if (!DCI.isCalledByLegalizer()) 1738 DCI.AddToWorklist(N0.getNode()); 1739 // FIXME: If running after legalize, we probably can't do this. 1740 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1741 } 1742 return N0; 1743 } 1744 1745 // Could not fold it. 1746 return SDValue(); 1747} 1748 1749/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1750/// node is a GlobalAddress + offset. 1751bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1752 int64_t &Offset) const { 1753 if (isa<GlobalAddressSDNode>(N)) { 1754 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1755 GA = GASD->getGlobal(); 1756 Offset += GASD->getOffset(); 1757 return true; 1758 } 1759 1760 if (N->getOpcode() == ISD::ADD) { 1761 SDValue N1 = N->getOperand(0); 1762 SDValue N2 = N->getOperand(1); 1763 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1764 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1765 if (V) { 1766 Offset += V->getSExtValue(); 1767 return true; 1768 } 1769 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1770 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1771 if (V) { 1772 Offset += V->getSExtValue(); 1773 return true; 1774 } 1775 } 1776 } 1777 return false; 1778} 1779 1780 1781/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1782/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1783/// location that the 'Base' load is loading from. 1784bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1785 unsigned Bytes, int Dist, 1786 const MachineFrameInfo *MFI) const { 1787 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1788 return false; 1789 MVT VT = LD->getValueType(0); 1790 if (VT.getSizeInBits() / 8 != Bytes) 1791 return false; 1792 1793 SDValue Loc = LD->getOperand(1); 1794 SDValue BaseLoc = Base->getOperand(1); 1795 if (Loc.getOpcode() == ISD::FrameIndex) { 1796 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1797 return false; 1798 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1799 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1800 int FS = MFI->getObjectSize(FI); 1801 int BFS = MFI->getObjectSize(BFI); 1802 if (FS != BFS || FS != (int)Bytes) return false; 1803 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1804 } 1805 1806 GlobalValue *GV1 = NULL; 1807 GlobalValue *GV2 = NULL; 1808 int64_t Offset1 = 0; 1809 int64_t Offset2 = 0; 1810 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1811 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1812 if (isGA1 && isGA2 && GV1 == GV2) 1813 return Offset1 == (Offset2 + Dist*Bytes); 1814 return false; 1815} 1816 1817 1818SDValue TargetLowering:: 1819PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1820 // Default implementation: no optimization. 1821 return SDValue(); 1822} 1823 1824//===----------------------------------------------------------------------===// 1825// Inline Assembler Implementation Methods 1826//===----------------------------------------------------------------------===// 1827 1828 1829TargetLowering::ConstraintType 1830TargetLowering::getConstraintType(const std::string &Constraint) const { 1831 // FIXME: lots more standard ones to handle. 1832 if (Constraint.size() == 1) { 1833 switch (Constraint[0]) { 1834 default: break; 1835 case 'r': return C_RegisterClass; 1836 case 'm': // memory 1837 case 'o': // offsetable 1838 case 'V': // not offsetable 1839 return C_Memory; 1840 case 'i': // Simple Integer or Relocatable Constant 1841 case 'n': // Simple Integer 1842 case 's': // Relocatable Constant 1843 case 'X': // Allow ANY value. 1844 case 'I': // Target registers. 1845 case 'J': 1846 case 'K': 1847 case 'L': 1848 case 'M': 1849 case 'N': 1850 case 'O': 1851 case 'P': 1852 return C_Other; 1853 } 1854 } 1855 1856 if (Constraint.size() > 1 && Constraint[0] == '{' && 1857 Constraint[Constraint.size()-1] == '}') 1858 return C_Register; 1859 return C_Unknown; 1860} 1861 1862/// LowerXConstraint - try to replace an X constraint, which matches anything, 1863/// with another that has more specific requirements based on the type of the 1864/// corresponding operand. 1865const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 1866 if (ConstraintVT.isInteger()) 1867 return "r"; 1868 if (ConstraintVT.isFloatingPoint()) 1869 return "f"; // works for many targets 1870 return 0; 1871} 1872 1873/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1874/// vector. If it is invalid, don't add anything to Ops. 1875void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1876 char ConstraintLetter, 1877 bool hasMemory, 1878 std::vector<SDValue> &Ops, 1879 SelectionDAG &DAG) const { 1880 switch (ConstraintLetter) { 1881 default: break; 1882 case 'X': // Allows any operand; labels (basic block) use this. 1883 if (Op.getOpcode() == ISD::BasicBlock) { 1884 Ops.push_back(Op); 1885 return; 1886 } 1887 // fall through 1888 case 'i': // Simple Integer or Relocatable Constant 1889 case 'n': // Simple Integer 1890 case 's': { // Relocatable Constant 1891 // These operands are interested in values of the form (GV+C), where C may 1892 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1893 // is possible and fine if either GV or C are missing. 1894 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1895 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1896 1897 // If we have "(add GV, C)", pull out GV/C 1898 if (Op.getOpcode() == ISD::ADD) { 1899 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1900 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1901 if (C == 0 || GA == 0) { 1902 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1903 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1904 } 1905 if (C == 0 || GA == 0) 1906 C = 0, GA = 0; 1907 } 1908 1909 // If we find a valid operand, map to the TargetXXX version so that the 1910 // value itself doesn't get selected. 1911 if (GA) { // Either &GV or &GV+C 1912 if (ConstraintLetter != 'n') { 1913 int64_t Offs = GA->getOffset(); 1914 if (C) Offs += C->getZExtValue(); 1915 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1916 Op.getValueType(), Offs)); 1917 return; 1918 } 1919 } 1920 if (C) { // just C, no GV. 1921 // Simple constants are not allowed for 's'. 1922 if (ConstraintLetter != 's') { 1923 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), 1924 Op.getValueType())); 1925 return; 1926 } 1927 } 1928 break; 1929 } 1930 } 1931} 1932 1933std::vector<unsigned> TargetLowering:: 1934getRegClassForInlineAsmConstraint(const std::string &Constraint, 1935 MVT VT) const { 1936 return std::vector<unsigned>(); 1937} 1938 1939 1940std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1941getRegForInlineAsmConstraint(const std::string &Constraint, 1942 MVT VT) const { 1943 if (Constraint[0] != '{') 1944 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1945 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1946 1947 // Remove the braces from around the name. 1948 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1949 1950 // Figure out which register class contains this reg. 1951 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1952 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1953 E = RI->regclass_end(); RCI != E; ++RCI) { 1954 const TargetRegisterClass *RC = *RCI; 1955 1956 // If none of the the value types for this register class are valid, we 1957 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1958 bool isLegal = false; 1959 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1960 I != E; ++I) { 1961 if (isTypeLegal(*I)) { 1962 isLegal = true; 1963 break; 1964 } 1965 } 1966 1967 if (!isLegal) continue; 1968 1969 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1970 I != E; ++I) { 1971 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1972 return std::make_pair(*I, RC); 1973 } 1974 } 1975 1976 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1977} 1978 1979//===----------------------------------------------------------------------===// 1980// Constraint Selection. 1981 1982/// isMatchingInputConstraint - Return true of this is an input operand that is 1983/// a matching constraint like "4". 1984bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 1985 assert(!ConstraintCode.empty() && "No known constraint!"); 1986 return isdigit(ConstraintCode[0]); 1987} 1988 1989/// getMatchedOperand - If this is an input matching constraint, this method 1990/// returns the output operand it matches. 1991unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 1992 assert(!ConstraintCode.empty() && "No known constraint!"); 1993 return atoi(ConstraintCode.c_str()); 1994} 1995 1996 1997/// getConstraintGenerality - Return an integer indicating how general CT 1998/// is. 1999static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2000 switch (CT) { 2001 default: assert(0 && "Unknown constraint type!"); 2002 case TargetLowering::C_Other: 2003 case TargetLowering::C_Unknown: 2004 return 0; 2005 case TargetLowering::C_Register: 2006 return 1; 2007 case TargetLowering::C_RegisterClass: 2008 return 2; 2009 case TargetLowering::C_Memory: 2010 return 3; 2011 } 2012} 2013 2014/// ChooseConstraint - If there are multiple different constraints that we 2015/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2016/// This is somewhat tricky: constraints fall into four classes: 2017/// Other -> immediates and magic values 2018/// Register -> one specific register 2019/// RegisterClass -> a group of regs 2020/// Memory -> memory 2021/// Ideally, we would pick the most specific constraint possible: if we have 2022/// something that fits into a register, we would pick it. The problem here 2023/// is that if we have something that could either be in a register or in 2024/// memory that use of the register could cause selection of *other* 2025/// operands to fail: they might only succeed if we pick memory. Because of 2026/// this the heuristic we use is: 2027/// 2028/// 1) If there is an 'other' constraint, and if the operand is valid for 2029/// that constraint, use it. This makes us take advantage of 'i' 2030/// constraints when available. 2031/// 2) Otherwise, pick the most general constraint present. This prefers 2032/// 'm' over 'r', for example. 2033/// 2034static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2035 bool hasMemory, const TargetLowering &TLI, 2036 SDValue Op, SelectionDAG *DAG) { 2037 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2038 unsigned BestIdx = 0; 2039 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2040 int BestGenerality = -1; 2041 2042 // Loop over the options, keeping track of the most general one. 2043 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2044 TargetLowering::ConstraintType CType = 2045 TLI.getConstraintType(OpInfo.Codes[i]); 2046 2047 // If this is an 'other' constraint, see if the operand is valid for it. 2048 // For example, on X86 we might have an 'rI' constraint. If the operand 2049 // is an integer in the range [0..31] we want to use I (saving a load 2050 // of a register), otherwise we must use 'r'. 2051 if (CType == TargetLowering::C_Other && Op.getNode()) { 2052 assert(OpInfo.Codes[i].size() == 1 && 2053 "Unhandled multi-letter 'other' constraint"); 2054 std::vector<SDValue> ResultOps; 2055 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2056 ResultOps, *DAG); 2057 if (!ResultOps.empty()) { 2058 BestType = CType; 2059 BestIdx = i; 2060 break; 2061 } 2062 } 2063 2064 // This constraint letter is more general than the previous one, use it. 2065 int Generality = getConstraintGenerality(CType); 2066 if (Generality > BestGenerality) { 2067 BestType = CType; 2068 BestIdx = i; 2069 BestGenerality = Generality; 2070 } 2071 } 2072 2073 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2074 OpInfo.ConstraintType = BestType; 2075} 2076 2077/// ComputeConstraintToUse - Determines the constraint code and constraint 2078/// type to use for the specific AsmOperandInfo, setting 2079/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2080void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2081 SDValue Op, 2082 bool hasMemory, 2083 SelectionDAG *DAG) const { 2084 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2085 2086 // Single-letter constraints ('r') are very common. 2087 if (OpInfo.Codes.size() == 1) { 2088 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2089 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2090 } else { 2091 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2092 } 2093 2094 // 'X' matches anything. 2095 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2096 // Labels and constants are handled elsewhere ('X' is the only thing 2097 // that matches labels). 2098 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2099 isa<ConstantInt>(OpInfo.CallOperandVal)) 2100 return; 2101 2102 // Otherwise, try to resolve it to something we know about by looking at 2103 // the actual operand type. 2104 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2105 OpInfo.ConstraintCode = Repl; 2106 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2107 } 2108 } 2109} 2110 2111//===----------------------------------------------------------------------===// 2112// Loop Strength Reduction hooks 2113//===----------------------------------------------------------------------===// 2114 2115/// isLegalAddressingMode - Return true if the addressing mode represented 2116/// by AM is legal for this target, for a load/store of the specified type. 2117bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2118 const Type *Ty) const { 2119 // The default implementation of this implements a conservative RISCy, r+r and 2120 // r+i addr mode. 2121 2122 // Allows a sign-extended 16-bit immediate field. 2123 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2124 return false; 2125 2126 // No global is ever allowed as a base. 2127 if (AM.BaseGV) 2128 return false; 2129 2130 // Only support r+r, 2131 switch (AM.Scale) { 2132 case 0: // "r+i" or just "i", depending on HasBaseReg. 2133 break; 2134 case 1: 2135 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2136 return false; 2137 // Otherwise we have r+r or r+i. 2138 break; 2139 case 2: 2140 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2141 return false; 2142 // Allow 2*r as r+r. 2143 break; 2144 } 2145 2146 return true; 2147} 2148 2149// Magic for divide replacement 2150 2151struct ms { 2152 int64_t m; // magic number 2153 int64_t s; // shift amount 2154}; 2155 2156struct mu { 2157 uint64_t m; // magic number 2158 int64_t a; // add indicator 2159 int64_t s; // shift amount 2160}; 2161 2162/// magic - calculate the magic numbers required to codegen an integer sdiv as 2163/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2164/// or -1. 2165static ms magic32(int32_t d) { 2166 int32_t p; 2167 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2168 const uint32_t two31 = 0x80000000U; 2169 struct ms mag; 2170 2171 ad = abs(d); 2172 t = two31 + ((uint32_t)d >> 31); 2173 anc = t - 1 - t%ad; // absolute value of nc 2174 p = 31; // initialize p 2175 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2176 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2177 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2178 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2179 do { 2180 p = p + 1; 2181 q1 = 2*q1; // update q1 = 2p/abs(nc) 2182 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2183 if (r1 >= anc) { // must be unsigned comparison 2184 q1 = q1 + 1; 2185 r1 = r1 - anc; 2186 } 2187 q2 = 2*q2; // update q2 = 2p/abs(d) 2188 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2189 if (r2 >= ad) { // must be unsigned comparison 2190 q2 = q2 + 1; 2191 r2 = r2 - ad; 2192 } 2193 delta = ad - r2; 2194 } while (q1 < delta || (q1 == delta && r1 == 0)); 2195 2196 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2197 if (d < 0) mag.m = -mag.m; // resulting magic number 2198 mag.s = p - 32; // resulting shift 2199 return mag; 2200} 2201 2202/// magicu - calculate the magic numbers required to codegen an integer udiv as 2203/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2204static mu magicu32(uint32_t d) { 2205 int32_t p; 2206 uint32_t nc, delta, q1, r1, q2, r2; 2207 struct mu magu; 2208 magu.a = 0; // initialize "add" indicator 2209 nc = - 1 - (-d)%d; 2210 p = 31; // initialize p 2211 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2212 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2213 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2214 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2215 do { 2216 p = p + 1; 2217 if (r1 >= nc - r1 ) { 2218 q1 = 2*q1 + 1; // update q1 2219 r1 = 2*r1 - nc; // update r1 2220 } 2221 else { 2222 q1 = 2*q1; // update q1 2223 r1 = 2*r1; // update r1 2224 } 2225 if (r2 + 1 >= d - r2) { 2226 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2227 q2 = 2*q2 + 1; // update q2 2228 r2 = 2*r2 + 1 - d; // update r2 2229 } 2230 else { 2231 if (q2 >= 0x80000000) magu.a = 1; 2232 q2 = 2*q2; // update q2 2233 r2 = 2*r2 + 1; // update r2 2234 } 2235 delta = d - 1 - r2; 2236 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2237 magu.m = q2 + 1; // resulting magic number 2238 magu.s = p - 32; // resulting shift 2239 return magu; 2240} 2241 2242/// magic - calculate the magic numbers required to codegen an integer sdiv as 2243/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2244/// or -1. 2245static ms magic64(int64_t d) { 2246 int64_t p; 2247 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2248 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2249 struct ms mag; 2250 2251 ad = d >= 0 ? d : -d; 2252 t = two63 + ((uint64_t)d >> 63); 2253 anc = t - 1 - t%ad; // absolute value of nc 2254 p = 63; // initialize p 2255 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2256 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2257 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2258 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2259 do { 2260 p = p + 1; 2261 q1 = 2*q1; // update q1 = 2p/abs(nc) 2262 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2263 if (r1 >= anc) { // must be unsigned comparison 2264 q1 = q1 + 1; 2265 r1 = r1 - anc; 2266 } 2267 q2 = 2*q2; // update q2 = 2p/abs(d) 2268 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2269 if (r2 >= ad) { // must be unsigned comparison 2270 q2 = q2 + 1; 2271 r2 = r2 - ad; 2272 } 2273 delta = ad - r2; 2274 } while (q1 < delta || (q1 == delta && r1 == 0)); 2275 2276 mag.m = q2 + 1; 2277 if (d < 0) mag.m = -mag.m; // resulting magic number 2278 mag.s = p - 64; // resulting shift 2279 return mag; 2280} 2281 2282/// magicu - calculate the magic numbers required to codegen an integer udiv as 2283/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2284static mu magicu64(uint64_t d) 2285{ 2286 int64_t p; 2287 uint64_t nc, delta, q1, r1, q2, r2; 2288 struct mu magu; 2289 magu.a = 0; // initialize "add" indicator 2290 nc = - 1 - (-d)%d; 2291 p = 63; // initialize p 2292 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2293 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2294 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2295 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2296 do { 2297 p = p + 1; 2298 if (r1 >= nc - r1 ) { 2299 q1 = 2*q1 + 1; // update q1 2300 r1 = 2*r1 - nc; // update r1 2301 } 2302 else { 2303 q1 = 2*q1; // update q1 2304 r1 = 2*r1; // update r1 2305 } 2306 if (r2 + 1 >= d - r2) { 2307 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2308 q2 = 2*q2 + 1; // update q2 2309 r2 = 2*r2 + 1 - d; // update r2 2310 } 2311 else { 2312 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2313 q2 = 2*q2; // update q2 2314 r2 = 2*r2 + 1; // update r2 2315 } 2316 delta = d - 1 - r2; 2317 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2318 magu.m = q2 + 1; // resulting magic number 2319 magu.s = p - 64; // resulting shift 2320 return magu; 2321} 2322 2323/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2324/// return a DAG expression to select that will generate the same value by 2325/// multiplying by a magic number. See: 2326/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2327SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2328 std::vector<SDNode*>* Created) const { 2329 MVT VT = N->getValueType(0); 2330 2331 // Check to see if we can do this. 2332 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2333 return SDValue(); // BuildSDIV only operates on i32 or i64 2334 2335 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue(); 2336 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2337 2338 // Multiply the numerator (operand 0) by the magic value 2339 SDValue Q; 2340 if (isOperationLegal(ISD::MULHS, VT)) 2341 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2342 DAG.getConstant(magics.m, VT)); 2343 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 2344 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2345 N->getOperand(0), 2346 DAG.getConstant(magics.m, VT)).getNode(), 1); 2347 else 2348 return SDValue(); // No mulhs or equvialent 2349 // If d > 0 and m < 0, add the numerator 2350 if (d > 0 && magics.m < 0) { 2351 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2352 if (Created) 2353 Created->push_back(Q.getNode()); 2354 } 2355 // If d < 0 and m > 0, subtract the numerator. 2356 if (d < 0 && magics.m > 0) { 2357 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2358 if (Created) 2359 Created->push_back(Q.getNode()); 2360 } 2361 // Shift right algebraic if shift value is nonzero 2362 if (magics.s > 0) { 2363 Q = DAG.getNode(ISD::SRA, VT, Q, 2364 DAG.getConstant(magics.s, getShiftAmountTy())); 2365 if (Created) 2366 Created->push_back(Q.getNode()); 2367 } 2368 // Extract the sign bit and add it to the quotient 2369 SDValue T = 2370 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2371 getShiftAmountTy())); 2372 if (Created) 2373 Created->push_back(T.getNode()); 2374 return DAG.getNode(ISD::ADD, VT, Q, T); 2375} 2376 2377/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2378/// return a DAG expression to select that will generate the same value by 2379/// multiplying by a magic number. See: 2380/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2381SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2382 std::vector<SDNode*>* Created) const { 2383 MVT VT = N->getValueType(0); 2384 2385 // Check to see if we can do this. 2386 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2387 return SDValue(); // BuildUDIV only operates on i32 or i64 2388 2389 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2390 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2391 2392 // Multiply the numerator (operand 0) by the magic value 2393 SDValue Q; 2394 if (isOperationLegal(ISD::MULHU, VT)) 2395 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2396 DAG.getConstant(magics.m, VT)); 2397 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2398 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2399 N->getOperand(0), 2400 DAG.getConstant(magics.m, VT)).getNode(), 1); 2401 else 2402 return SDValue(); // No mulhu or equvialent 2403 if (Created) 2404 Created->push_back(Q.getNode()); 2405 2406 if (magics.a == 0) { 2407 return DAG.getNode(ISD::SRL, VT, Q, 2408 DAG.getConstant(magics.s, getShiftAmountTy())); 2409 } else { 2410 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2411 if (Created) 2412 Created->push_back(NPQ.getNode()); 2413 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2414 DAG.getConstant(1, getShiftAmountTy())); 2415 if (Created) 2416 Created->push_back(NPQ.getNode()); 2417 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2418 if (Created) 2419 Created->push_back(NPQ.getNode()); 2420 return DAG.getNode(ISD::SRL, VT, NPQ, 2421 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2422 } 2423} 2424