TargetLowering.cpp revision 78d12644b905dc54cf6cf984af02a49d30d29744
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28using namespace llvm; 29 30namespace llvm { 31TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 32 bool isLocal = GV->hasLocalLinkage(); 33 bool isDeclaration = GV->isDeclaration(); 34 // FIXME: what should we do for protected and internal visibility? 35 // For variables, is internal different from hidden? 36 bool isHidden = GV->hasHiddenVisibility(); 37 38 if (reloc == Reloc::PIC_) { 39 if (isLocal || isHidden) 40 return TLSModel::LocalDynamic; 41 else 42 return TLSModel::GeneralDynamic; 43 } else { 44 if (!isDeclaration || isHidden) 45 return TLSModel::LocalExec; 46 else 47 return TLSModel::InitialExec; 48 } 49} 50} 51 52/// InitLibcallNames - Set default libcall names. 53/// 54static void InitLibcallNames(const char **Names) { 55 Names[RTLIB::SHL_I16] = "__ashlhi3"; 56 Names[RTLIB::SHL_I32] = "__ashlsi3"; 57 Names[RTLIB::SHL_I64] = "__ashldi3"; 58 Names[RTLIB::SHL_I128] = "__ashlti3"; 59 Names[RTLIB::SRL_I16] = "__lshrhi3"; 60 Names[RTLIB::SRL_I32] = "__lshrsi3"; 61 Names[RTLIB::SRL_I64] = "__lshrdi3"; 62 Names[RTLIB::SRL_I128] = "__lshrti3"; 63 Names[RTLIB::SRA_I16] = "__ashrhi3"; 64 Names[RTLIB::SRA_I32] = "__ashrsi3"; 65 Names[RTLIB::SRA_I64] = "__ashrdi3"; 66 Names[RTLIB::SRA_I128] = "__ashrti3"; 67 Names[RTLIB::MUL_I16] = "__mulhi3"; 68 Names[RTLIB::MUL_I32] = "__mulsi3"; 69 Names[RTLIB::MUL_I64] = "__muldi3"; 70 Names[RTLIB::MUL_I128] = "__multi3"; 71 Names[RTLIB::SDIV_I16] = "__divhi3"; 72 Names[RTLIB::SDIV_I32] = "__divsi3"; 73 Names[RTLIB::SDIV_I64] = "__divdi3"; 74 Names[RTLIB::SDIV_I128] = "__divti3"; 75 Names[RTLIB::UDIV_I16] = "__udivhi3"; 76 Names[RTLIB::UDIV_I32] = "__udivsi3"; 77 Names[RTLIB::UDIV_I64] = "__udivdi3"; 78 Names[RTLIB::UDIV_I128] = "__udivti3"; 79 Names[RTLIB::SREM_I16] = "__modhi3"; 80 Names[RTLIB::SREM_I32] = "__modsi3"; 81 Names[RTLIB::SREM_I64] = "__moddi3"; 82 Names[RTLIB::SREM_I128] = "__modti3"; 83 Names[RTLIB::UREM_I16] = "__umodhi3"; 84 Names[RTLIB::UREM_I32] = "__umodsi3"; 85 Names[RTLIB::UREM_I64] = "__umoddi3"; 86 Names[RTLIB::UREM_I128] = "__umodti3"; 87 Names[RTLIB::NEG_I32] = "__negsi2"; 88 Names[RTLIB::NEG_I64] = "__negdi2"; 89 Names[RTLIB::ADD_F32] = "__addsf3"; 90 Names[RTLIB::ADD_F64] = "__adddf3"; 91 Names[RTLIB::ADD_F80] = "__addxf3"; 92 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 93 Names[RTLIB::SUB_F32] = "__subsf3"; 94 Names[RTLIB::SUB_F64] = "__subdf3"; 95 Names[RTLIB::SUB_F80] = "__subxf3"; 96 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 97 Names[RTLIB::MUL_F32] = "__mulsf3"; 98 Names[RTLIB::MUL_F64] = "__muldf3"; 99 Names[RTLIB::MUL_F80] = "__mulxf3"; 100 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 101 Names[RTLIB::DIV_F32] = "__divsf3"; 102 Names[RTLIB::DIV_F64] = "__divdf3"; 103 Names[RTLIB::DIV_F80] = "__divxf3"; 104 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 105 Names[RTLIB::REM_F32] = "fmodf"; 106 Names[RTLIB::REM_F64] = "fmod"; 107 Names[RTLIB::REM_F80] = "fmodl"; 108 Names[RTLIB::REM_PPCF128] = "fmodl"; 109 Names[RTLIB::POWI_F32] = "__powisf2"; 110 Names[RTLIB::POWI_F64] = "__powidf2"; 111 Names[RTLIB::POWI_F80] = "__powixf2"; 112 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 113 Names[RTLIB::SQRT_F32] = "sqrtf"; 114 Names[RTLIB::SQRT_F64] = "sqrt"; 115 Names[RTLIB::SQRT_F80] = "sqrtl"; 116 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 117 Names[RTLIB::LOG_F32] = "logf"; 118 Names[RTLIB::LOG_F64] = "log"; 119 Names[RTLIB::LOG_F80] = "logl"; 120 Names[RTLIB::LOG_PPCF128] = "logl"; 121 Names[RTLIB::LOG2_F32] = "log2f"; 122 Names[RTLIB::LOG2_F64] = "log2"; 123 Names[RTLIB::LOG2_F80] = "log2l"; 124 Names[RTLIB::LOG2_PPCF128] = "log2l"; 125 Names[RTLIB::LOG10_F32] = "log10f"; 126 Names[RTLIB::LOG10_F64] = "log10"; 127 Names[RTLIB::LOG10_F80] = "log10l"; 128 Names[RTLIB::LOG10_PPCF128] = "log10l"; 129 Names[RTLIB::EXP_F32] = "expf"; 130 Names[RTLIB::EXP_F64] = "exp"; 131 Names[RTLIB::EXP_F80] = "expl"; 132 Names[RTLIB::EXP_PPCF128] = "expl"; 133 Names[RTLIB::EXP2_F32] = "exp2f"; 134 Names[RTLIB::EXP2_F64] = "exp2"; 135 Names[RTLIB::EXP2_F80] = "exp2l"; 136 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 137 Names[RTLIB::SIN_F32] = "sinf"; 138 Names[RTLIB::SIN_F64] = "sin"; 139 Names[RTLIB::SIN_F80] = "sinl"; 140 Names[RTLIB::SIN_PPCF128] = "sinl"; 141 Names[RTLIB::COS_F32] = "cosf"; 142 Names[RTLIB::COS_F64] = "cos"; 143 Names[RTLIB::COS_F80] = "cosl"; 144 Names[RTLIB::COS_PPCF128] = "cosl"; 145 Names[RTLIB::POW_F32] = "powf"; 146 Names[RTLIB::POW_F64] = "pow"; 147 Names[RTLIB::POW_F80] = "powl"; 148 Names[RTLIB::POW_PPCF128] = "powl"; 149 Names[RTLIB::CEIL_F32] = "ceilf"; 150 Names[RTLIB::CEIL_F64] = "ceil"; 151 Names[RTLIB::CEIL_F80] = "ceill"; 152 Names[RTLIB::CEIL_PPCF128] = "ceill"; 153 Names[RTLIB::TRUNC_F32] = "truncf"; 154 Names[RTLIB::TRUNC_F64] = "trunc"; 155 Names[RTLIB::TRUNC_F80] = "truncl"; 156 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 157 Names[RTLIB::RINT_F32] = "rintf"; 158 Names[RTLIB::RINT_F64] = "rint"; 159 Names[RTLIB::RINT_F80] = "rintl"; 160 Names[RTLIB::RINT_PPCF128] = "rintl"; 161 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 162 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 163 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 164 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 165 Names[RTLIB::FLOOR_F32] = "floorf"; 166 Names[RTLIB::FLOOR_F64] = "floor"; 167 Names[RTLIB::FLOOR_F80] = "floorl"; 168 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 169 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 170 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 171 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 172 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 173 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 174 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 175 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 176 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 177 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 178 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 179 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 180 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 181 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 182 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 183 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 184 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 185 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 186 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 187 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 188 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 189 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 190 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 191 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 192 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 193 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 194 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 195 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 196 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 197 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 198 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 199 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 200 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 201 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 202 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 203 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 204 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 205 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 206 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 207 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 208 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 209 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 210 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 211 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 212 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 213 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 214 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 215 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 216 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 217 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 218 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 219 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 220 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 221 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 222 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 223 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 224 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 225 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 226 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 227 Names[RTLIB::OEQ_F32] = "__eqsf2"; 228 Names[RTLIB::OEQ_F64] = "__eqdf2"; 229 Names[RTLIB::UNE_F32] = "__nesf2"; 230 Names[RTLIB::UNE_F64] = "__nedf2"; 231 Names[RTLIB::OGE_F32] = "__gesf2"; 232 Names[RTLIB::OGE_F64] = "__gedf2"; 233 Names[RTLIB::OLT_F32] = "__ltsf2"; 234 Names[RTLIB::OLT_F64] = "__ltdf2"; 235 Names[RTLIB::OLE_F32] = "__lesf2"; 236 Names[RTLIB::OLE_F64] = "__ledf2"; 237 Names[RTLIB::OGT_F32] = "__gtsf2"; 238 Names[RTLIB::OGT_F64] = "__gtdf2"; 239 Names[RTLIB::UO_F32] = "__unordsf2"; 240 Names[RTLIB::UO_F64] = "__unorddf2"; 241 Names[RTLIB::O_F32] = "__unordsf2"; 242 Names[RTLIB::O_F64] = "__unorddf2"; 243 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 244} 245 246/// getFPEXT - Return the FPEXT_*_* value for the given types, or 247/// UNKNOWN_LIBCALL if there is none. 248RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 249 if (OpVT == MVT::f32) { 250 if (RetVT == MVT::f64) 251 return FPEXT_F32_F64; 252 } 253 return UNKNOWN_LIBCALL; 254} 255 256/// getFPROUND - Return the FPROUND_*_* value for the given types, or 257/// UNKNOWN_LIBCALL if there is none. 258RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 259 if (RetVT == MVT::f32) { 260 if (OpVT == MVT::f64) 261 return FPROUND_F64_F32; 262 if (OpVT == MVT::f80) 263 return FPROUND_F80_F32; 264 if (OpVT == MVT::ppcf128) 265 return FPROUND_PPCF128_F32; 266 } else if (RetVT == MVT::f64) { 267 if (OpVT == MVT::f80) 268 return FPROUND_F80_F64; 269 if (OpVT == MVT::ppcf128) 270 return FPROUND_PPCF128_F64; 271 } 272 return UNKNOWN_LIBCALL; 273} 274 275/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 276/// UNKNOWN_LIBCALL if there is none. 277RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 278 if (OpVT == MVT::f32) { 279 if (RetVT == MVT::i8) 280 return FPTOSINT_F32_I8; 281 if (RetVT == MVT::i16) 282 return FPTOSINT_F32_I16; 283 if (RetVT == MVT::i32) 284 return FPTOSINT_F32_I32; 285 if (RetVT == MVT::i64) 286 return FPTOSINT_F32_I64; 287 if (RetVT == MVT::i128) 288 return FPTOSINT_F32_I128; 289 } else if (OpVT == MVT::f64) { 290 if (RetVT == MVT::i32) 291 return FPTOSINT_F64_I32; 292 if (RetVT == MVT::i64) 293 return FPTOSINT_F64_I64; 294 if (RetVT == MVT::i128) 295 return FPTOSINT_F64_I128; 296 } else if (OpVT == MVT::f80) { 297 if (RetVT == MVT::i32) 298 return FPTOSINT_F80_I32; 299 if (RetVT == MVT::i64) 300 return FPTOSINT_F80_I64; 301 if (RetVT == MVT::i128) 302 return FPTOSINT_F80_I128; 303 } else if (OpVT == MVT::ppcf128) { 304 if (RetVT == MVT::i32) 305 return FPTOSINT_PPCF128_I32; 306 if (RetVT == MVT::i64) 307 return FPTOSINT_PPCF128_I64; 308 if (RetVT == MVT::i128) 309 return FPTOSINT_PPCF128_I128; 310 } 311 return UNKNOWN_LIBCALL; 312} 313 314/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 315/// UNKNOWN_LIBCALL if there is none. 316RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 317 if (OpVT == MVT::f32) { 318 if (RetVT == MVT::i8) 319 return FPTOUINT_F32_I8; 320 if (RetVT == MVT::i16) 321 return FPTOUINT_F32_I16; 322 if (RetVT == MVT::i32) 323 return FPTOUINT_F32_I32; 324 if (RetVT == MVT::i64) 325 return FPTOUINT_F32_I64; 326 if (RetVT == MVT::i128) 327 return FPTOUINT_F32_I128; 328 } else if (OpVT == MVT::f64) { 329 if (RetVT == MVT::i32) 330 return FPTOUINT_F64_I32; 331 if (RetVT == MVT::i64) 332 return FPTOUINT_F64_I64; 333 if (RetVT == MVT::i128) 334 return FPTOUINT_F64_I128; 335 } else if (OpVT == MVT::f80) { 336 if (RetVT == MVT::i32) 337 return FPTOUINT_F80_I32; 338 if (RetVT == MVT::i64) 339 return FPTOUINT_F80_I64; 340 if (RetVT == MVT::i128) 341 return FPTOUINT_F80_I128; 342 } else if (OpVT == MVT::ppcf128) { 343 if (RetVT == MVT::i32) 344 return FPTOUINT_PPCF128_I32; 345 if (RetVT == MVT::i64) 346 return FPTOUINT_PPCF128_I64; 347 if (RetVT == MVT::i128) 348 return FPTOUINT_PPCF128_I128; 349 } 350 return UNKNOWN_LIBCALL; 351} 352 353/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 354/// UNKNOWN_LIBCALL if there is none. 355RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 356 if (OpVT == MVT::i32) { 357 if (RetVT == MVT::f32) 358 return SINTTOFP_I32_F32; 359 else if (RetVT == MVT::f64) 360 return SINTTOFP_I32_F64; 361 else if (RetVT == MVT::f80) 362 return SINTTOFP_I32_F80; 363 else if (RetVT == MVT::ppcf128) 364 return SINTTOFP_I32_PPCF128; 365 } else if (OpVT == MVT::i64) { 366 if (RetVT == MVT::f32) 367 return SINTTOFP_I64_F32; 368 else if (RetVT == MVT::f64) 369 return SINTTOFP_I64_F64; 370 else if (RetVT == MVT::f80) 371 return SINTTOFP_I64_F80; 372 else if (RetVT == MVT::ppcf128) 373 return SINTTOFP_I64_PPCF128; 374 } else if (OpVT == MVT::i128) { 375 if (RetVT == MVT::f32) 376 return SINTTOFP_I128_F32; 377 else if (RetVT == MVT::f64) 378 return SINTTOFP_I128_F64; 379 else if (RetVT == MVT::f80) 380 return SINTTOFP_I128_F80; 381 else if (RetVT == MVT::ppcf128) 382 return SINTTOFP_I128_PPCF128; 383 } 384 return UNKNOWN_LIBCALL; 385} 386 387/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 388/// UNKNOWN_LIBCALL if there is none. 389RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 390 if (OpVT == MVT::i32) { 391 if (RetVT == MVT::f32) 392 return UINTTOFP_I32_F32; 393 else if (RetVT == MVT::f64) 394 return UINTTOFP_I32_F64; 395 else if (RetVT == MVT::f80) 396 return UINTTOFP_I32_F80; 397 else if (RetVT == MVT::ppcf128) 398 return UINTTOFP_I32_PPCF128; 399 } else if (OpVT == MVT::i64) { 400 if (RetVT == MVT::f32) 401 return UINTTOFP_I64_F32; 402 else if (RetVT == MVT::f64) 403 return UINTTOFP_I64_F64; 404 else if (RetVT == MVT::f80) 405 return UINTTOFP_I64_F80; 406 else if (RetVT == MVT::ppcf128) 407 return UINTTOFP_I64_PPCF128; 408 } else if (OpVT == MVT::i128) { 409 if (RetVT == MVT::f32) 410 return UINTTOFP_I128_F32; 411 else if (RetVT == MVT::f64) 412 return UINTTOFP_I128_F64; 413 else if (RetVT == MVT::f80) 414 return UINTTOFP_I128_F80; 415 else if (RetVT == MVT::ppcf128) 416 return UINTTOFP_I128_PPCF128; 417 } 418 return UNKNOWN_LIBCALL; 419} 420 421/// InitCmpLibcallCCs - Set default comparison libcall CC. 422/// 423static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 424 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 425 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 426 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 427 CCs[RTLIB::UNE_F32] = ISD::SETNE; 428 CCs[RTLIB::UNE_F64] = ISD::SETNE; 429 CCs[RTLIB::OGE_F32] = ISD::SETGE; 430 CCs[RTLIB::OGE_F64] = ISD::SETGE; 431 CCs[RTLIB::OLT_F32] = ISD::SETLT; 432 CCs[RTLIB::OLT_F64] = ISD::SETLT; 433 CCs[RTLIB::OLE_F32] = ISD::SETLE; 434 CCs[RTLIB::OLE_F64] = ISD::SETLE; 435 CCs[RTLIB::OGT_F32] = ISD::SETGT; 436 CCs[RTLIB::OGT_F64] = ISD::SETGT; 437 CCs[RTLIB::UO_F32] = ISD::SETNE; 438 CCs[RTLIB::UO_F64] = ISD::SETNE; 439 CCs[RTLIB::O_F32] = ISD::SETEQ; 440 CCs[RTLIB::O_F64] = ISD::SETEQ; 441} 442 443TargetLowering::TargetLowering(TargetMachine &tm) 444 : TM(tm), TD(TM.getTargetData()) { 445 // All operations default to being supported. 446 memset(OpActions, 0, sizeof(OpActions)); 447 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 448 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 449 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 450 memset(ConvertActions, 0, sizeof(ConvertActions)); 451 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 452 453 // Set default actions for various operations. 454 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 455 // Default all indexed load / store to expand. 456 for (unsigned IM = (unsigned)ISD::PRE_INC; 457 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 458 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 459 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 460 } 461 462 // These operations default to expand. 463 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 464 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 465 } 466 467 // Most targets ignore the @llvm.prefetch intrinsic. 468 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 469 470 // ConstantFP nodes default to expand. Targets can either change this to 471 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 472 // to optimize expansions for certain constants. 473 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 474 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 475 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 476 477 // These library functions default to expand. 478 setOperationAction(ISD::FLOG , MVT::f64, Expand); 479 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 480 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 481 setOperationAction(ISD::FEXP , MVT::f64, Expand); 482 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 483 setOperationAction(ISD::FLOG , MVT::f32, Expand); 484 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 485 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 486 setOperationAction(ISD::FEXP , MVT::f32, Expand); 487 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 488 489 // Default ISD::TRAP to expand (which turns it into abort). 490 setOperationAction(ISD::TRAP, MVT::Other, Expand); 491 492 IsLittleEndian = TD->isLittleEndian(); 493 UsesGlobalOffsetTable = false; 494 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 495 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 496 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 497 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 498 allowUnalignedMemoryAccesses = false; 499 benefitFromCodePlacementOpt = false; 500 UseUnderscoreSetJmp = false; 501 UseUnderscoreLongJmp = false; 502 SelectIsExpensive = false; 503 IntDivIsCheap = false; 504 Pow2DivIsCheap = false; 505 StackPointerRegisterToSaveRestore = 0; 506 ExceptionPointerRegister = 0; 507 ExceptionSelectorRegister = 0; 508 BooleanContents = UndefinedBooleanContent; 509 SchedPreferenceInfo = SchedulingForLatency; 510 JumpBufSize = 0; 511 JumpBufAlignment = 0; 512 IfCvtBlockSizeLimit = 2; 513 IfCvtDupBlockSizeLimit = 0; 514 PrefLoopAlignment = 0; 515 516 InitLibcallNames(LibcallRoutineNames); 517 InitCmpLibcallCCs(CmpLibcallCCs); 518 519 // Tell Legalize whether the assembler supports DEBUG_LOC. 520 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 521 if (!TASM || !TASM->hasDotLocAndDotFile()) 522 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 523} 524 525TargetLowering::~TargetLowering() {} 526 527/// computeRegisterProperties - Once all of the register classes are added, 528/// this allows us to compute derived properties we expose. 529void TargetLowering::computeRegisterProperties() { 530 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 531 "Too many value types for ValueTypeActions to hold!"); 532 533 // Everything defaults to needing one register. 534 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 535 NumRegistersForVT[i] = 1; 536 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 537 } 538 // ...except isVoid, which doesn't need any registers. 539 NumRegistersForVT[MVT::isVoid] = 0; 540 541 // Find the largest integer register class. 542 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 543 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 544 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 545 546 // Every integer value type larger than this largest register takes twice as 547 // many registers to represent as the previous ValueType. 548 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 549 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 550 if (!EVT.isInteger()) 551 break; 552 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 553 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 554 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 555 ValueTypeActions.setTypeAction(EVT, Expand); 556 } 557 558 // Inspect all of the ValueType's smaller than the largest integer 559 // register to see which ones need promotion. 560 unsigned LegalIntReg = LargestIntReg; 561 for (unsigned IntReg = LargestIntReg - 1; 562 IntReg >= (unsigned)MVT::i1; --IntReg) { 563 MVT IVT = (MVT::SimpleValueType)IntReg; 564 if (isTypeLegal(IVT)) { 565 LegalIntReg = IntReg; 566 } else { 567 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 568 (MVT::SimpleValueType)LegalIntReg; 569 ValueTypeActions.setTypeAction(IVT, Promote); 570 } 571 } 572 573 // ppcf128 type is really two f64's. 574 if (!isTypeLegal(MVT::ppcf128)) { 575 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 576 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 577 TransformToType[MVT::ppcf128] = MVT::f64; 578 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 579 } 580 581 // Decide how to handle f64. If the target does not have native f64 support, 582 // expand it to i64 and we will be generating soft float library calls. 583 if (!isTypeLegal(MVT::f64)) { 584 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 585 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 586 TransformToType[MVT::f64] = MVT::i64; 587 ValueTypeActions.setTypeAction(MVT::f64, Expand); 588 } 589 590 // Decide how to handle f32. If the target does not have native support for 591 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 592 if (!isTypeLegal(MVT::f32)) { 593 if (isTypeLegal(MVT::f64)) { 594 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 595 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 596 TransformToType[MVT::f32] = MVT::f64; 597 ValueTypeActions.setTypeAction(MVT::f32, Promote); 598 } else { 599 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 600 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 601 TransformToType[MVT::f32] = MVT::i32; 602 ValueTypeActions.setTypeAction(MVT::f32, Expand); 603 } 604 } 605 606 // Loop over all of the vector value types to see which need transformations. 607 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 608 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 609 MVT VT = (MVT::SimpleValueType)i; 610 if (!isTypeLegal(VT)) { 611 MVT IntermediateVT, RegisterVT; 612 unsigned NumIntermediates; 613 NumRegistersForVT[i] = 614 getVectorTypeBreakdown(VT, 615 IntermediateVT, NumIntermediates, 616 RegisterVT); 617 RegisterTypeForVT[i] = RegisterVT; 618 619 // Determine if there is a legal wider type. 620 bool IsLegalWiderType = false; 621 MVT EltVT = VT.getVectorElementType(); 622 unsigned NElts = VT.getVectorNumElements(); 623 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 624 MVT SVT = (MVT::SimpleValueType)nVT; 625 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 626 SVT.getVectorNumElements() > NElts) { 627 TransformToType[i] = SVT; 628 ValueTypeActions.setTypeAction(VT, Promote); 629 IsLegalWiderType = true; 630 break; 631 } 632 } 633 if (!IsLegalWiderType) { 634 MVT NVT = VT.getPow2VectorType(); 635 if (NVT == VT) { 636 // Type is already a power of 2. The default action is to split. 637 TransformToType[i] = MVT::Other; 638 ValueTypeActions.setTypeAction(VT, Expand); 639 } else { 640 TransformToType[i] = NVT; 641 ValueTypeActions.setTypeAction(VT, Promote); 642 } 643 } 644 } 645 } 646} 647 648const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 649 return NULL; 650} 651 652 653MVT TargetLowering::getSetCCResultType(MVT VT) const { 654 return getValueType(TD->getIntPtrType()); 655} 656 657 658/// getVectorTypeBreakdown - Vector types are broken down into some number of 659/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 660/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 661/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 662/// 663/// This method returns the number of registers needed, and the VT for each 664/// register. It also returns the VT and quantity of the intermediate values 665/// before they are promoted/expanded. 666/// 667unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 668 MVT &IntermediateVT, 669 unsigned &NumIntermediates, 670 MVT &RegisterVT) const { 671 // Figure out the right, legal destination reg to copy into. 672 unsigned NumElts = VT.getVectorNumElements(); 673 MVT EltTy = VT.getVectorElementType(); 674 675 unsigned NumVectorRegs = 1; 676 677 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 678 // could break down into LHS/RHS like LegalizeDAG does. 679 if (!isPowerOf2_32(NumElts)) { 680 NumVectorRegs = NumElts; 681 NumElts = 1; 682 } 683 684 // Divide the input until we get to a supported size. This will always 685 // end with a scalar if the target doesn't support vectors. 686 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 687 NumElts >>= 1; 688 NumVectorRegs <<= 1; 689 } 690 691 NumIntermediates = NumVectorRegs; 692 693 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 694 if (!isTypeLegal(NewVT)) 695 NewVT = EltTy; 696 IntermediateVT = NewVT; 697 698 MVT DestVT = getRegisterType(NewVT); 699 RegisterVT = DestVT; 700 if (DestVT.bitsLT(NewVT)) { 701 // Value is expanded, e.g. i64 -> i16. 702 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 703 } else { 704 // Otherwise, promotion or legal types use the same number of registers as 705 // the vector decimated to the appropriate level. 706 return NumVectorRegs; 707 } 708 709 return 1; 710} 711 712/// getWidenVectorType: given a vector type, returns the type to widen to 713/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 714/// If there is no vector type that we want to widen to, returns MVT::Other 715/// When and where to widen is target dependent based on the cost of 716/// scalarizing vs using the wider vector type. 717MVT TargetLowering::getWidenVectorType(MVT VT) const { 718 assert(VT.isVector()); 719 if (isTypeLegal(VT)) 720 return VT; 721 722 // Default is not to widen until moved to LegalizeTypes 723 return MVT::Other; 724} 725 726/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 727/// function arguments in the caller parameter area. This is the actual 728/// alignment, not its logarithm. 729unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 730 return TD->getCallFrameTypeAlignment(Ty); 731} 732 733SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 734 SelectionDAG &DAG) const { 735 if (usesGlobalOffsetTable()) 736 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 737 return Table; 738} 739 740bool 741TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 742 // Assume that everything is safe in static mode. 743 if (getTargetMachine().getRelocationModel() == Reloc::Static) 744 return true; 745 746 // In dynamic-no-pic mode, assume that known defined values are safe. 747 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 748 GA && 749 !GA->getGlobal()->isDeclaration() && 750 !GA->getGlobal()->isWeakForLinker()) 751 return true; 752 753 // Otherwise assume nothing is safe. 754 return false; 755} 756 757//===----------------------------------------------------------------------===// 758// Optimization Methods 759//===----------------------------------------------------------------------===// 760 761/// ShrinkDemandedConstant - Check to see if the specified operand of the 762/// specified instruction is a constant integer. If so, check to see if there 763/// are any bits set in the constant that are not demanded. If so, shrink the 764/// constant and return true. 765bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 766 const APInt &Demanded) { 767 DebugLoc dl = Op.getDebugLoc(); 768 769 // FIXME: ISD::SELECT, ISD::SELECT_CC 770 switch (Op.getOpcode()) { 771 default: break; 772 case ISD::XOR: 773 case ISD::AND: 774 case ISD::OR: { 775 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 776 if (!C) return false; 777 778 if (Op.getOpcode() == ISD::XOR && 779 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 780 return false; 781 782 // if we can expand it to have all bits set, do it 783 if (C->getAPIntValue().intersects(~Demanded)) { 784 MVT VT = Op.getValueType(); 785 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 786 DAG.getConstant(Demanded & 787 C->getAPIntValue(), 788 VT)); 789 return CombineTo(Op, New); 790 } 791 792 break; 793 } 794 } 795 796 return false; 797} 798 799/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 800/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 801/// cast, but it could be generalized for targets with other types of 802/// implicit widening casts. 803bool 804TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 805 unsigned BitWidth, 806 const APInt &Demanded, 807 DebugLoc dl) { 808 assert(Op.getNumOperands() == 2 && 809 "ShrinkDemandedOp only supports binary operators!"); 810 assert(Op.getNode()->getNumValues() == 1 && 811 "ShrinkDemandedOp only supports nodes with one result!"); 812 813 // Don't do this if the node has another user, which may require the 814 // full value. 815 if (!Op.getNode()->hasOneUse()) 816 return false; 817 818 // Search for the smallest integer type with free casts to and from 819 // Op's type. For expedience, just check power-of-2 integer types. 820 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 821 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 822 if (!isPowerOf2_32(SmallVTBits)) 823 SmallVTBits = NextPowerOf2(SmallVTBits); 824 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 825 MVT SmallVT = MVT::getIntegerVT(SmallVTBits); 826 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 827 TLI.isZExtFree(SmallVT, Op.getValueType())) { 828 // We found a type with free casts. 829 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 830 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 831 Op.getNode()->getOperand(0)), 832 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 833 Op.getNode()->getOperand(1))); 834 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 835 return CombineTo(Op, Z); 836 } 837 } 838 return false; 839} 840 841/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 842/// DemandedMask bits of the result of Op are ever used downstream. If we can 843/// use this information to simplify Op, create a new simplified DAG node and 844/// return true, returning the original and new nodes in Old and New. Otherwise, 845/// analyze the expression and return a mask of KnownOne and KnownZero bits for 846/// the expression (used to simplify the caller). The KnownZero/One bits may 847/// only be accurate for those bits in the DemandedMask. 848bool TargetLowering::SimplifyDemandedBits(SDValue Op, 849 const APInt &DemandedMask, 850 APInt &KnownZero, 851 APInt &KnownOne, 852 TargetLoweringOpt &TLO, 853 unsigned Depth) const { 854 unsigned BitWidth = DemandedMask.getBitWidth(); 855 assert(Op.getValueSizeInBits() == BitWidth && 856 "Mask size mismatches value type size!"); 857 APInt NewMask = DemandedMask; 858 DebugLoc dl = Op.getDebugLoc(); 859 860 // Don't know anything. 861 KnownZero = KnownOne = APInt(BitWidth, 0); 862 863 // Other users may use these bits. 864 if (!Op.getNode()->hasOneUse()) { 865 if (Depth != 0) { 866 // If not at the root, Just compute the KnownZero/KnownOne bits to 867 // simplify things downstream. 868 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 869 return false; 870 } 871 // If this is the root being simplified, allow it to have multiple uses, 872 // just set the NewMask to all bits. 873 NewMask = APInt::getAllOnesValue(BitWidth); 874 } else if (DemandedMask == 0) { 875 // Not demanding any bits from Op. 876 if (Op.getOpcode() != ISD::UNDEF) 877 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 878 return false; 879 } else if (Depth == 6) { // Limit search depth. 880 return false; 881 } 882 883 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 884 switch (Op.getOpcode()) { 885 case ISD::Constant: 886 // We know all of the bits for a constant! 887 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 888 KnownZero = ~KnownOne & NewMask; 889 return false; // Don't fall through, will infinitely loop. 890 case ISD::AND: 891 // If the RHS is a constant, check to see if the LHS would be zero without 892 // using the bits from the RHS. Below, we use knowledge about the RHS to 893 // simplify the LHS, here we're using information from the LHS to simplify 894 // the RHS. 895 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 896 APInt LHSZero, LHSOne; 897 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 898 LHSZero, LHSOne, Depth+1); 899 // If the LHS already has zeros where RHSC does, this and is dead. 900 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 901 return TLO.CombineTo(Op, Op.getOperand(0)); 902 // If any of the set bits in the RHS are known zero on the LHS, shrink 903 // the constant. 904 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 905 return true; 906 } 907 908 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 909 KnownOne, TLO, Depth+1)) 910 return true; 911 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 912 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 913 KnownZero2, KnownOne2, TLO, Depth+1)) 914 return true; 915 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 916 917 // If all of the demanded bits are known one on one side, return the other. 918 // These bits cannot contribute to the result of the 'and'. 919 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 920 return TLO.CombineTo(Op, Op.getOperand(0)); 921 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 922 return TLO.CombineTo(Op, Op.getOperand(1)); 923 // If all of the demanded bits in the inputs are known zeros, return zero. 924 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 925 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 926 // If the RHS is a constant, see if we can simplify it. 927 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 928 return true; 929 // If the operation can be done in a smaller type, do so. 930 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 931 return true; 932 933 // Output known-1 bits are only known if set in both the LHS & RHS. 934 KnownOne &= KnownOne2; 935 // Output known-0 are known to be clear if zero in either the LHS | RHS. 936 KnownZero |= KnownZero2; 937 break; 938 case ISD::OR: 939 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 940 KnownOne, TLO, Depth+1)) 941 return true; 942 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 943 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 944 KnownZero2, KnownOne2, TLO, Depth+1)) 945 return true; 946 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 947 948 // If all of the demanded bits are known zero on one side, return the other. 949 // These bits cannot contribute to the result of the 'or'. 950 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 951 return TLO.CombineTo(Op, Op.getOperand(0)); 952 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 953 return TLO.CombineTo(Op, Op.getOperand(1)); 954 // If all of the potentially set bits on one side are known to be set on 955 // the other side, just use the 'other' side. 956 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 957 return TLO.CombineTo(Op, Op.getOperand(0)); 958 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 959 return TLO.CombineTo(Op, Op.getOperand(1)); 960 // If the RHS is a constant, see if we can simplify it. 961 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 962 return true; 963 // If the operation can be done in a smaller type, do so. 964 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 965 return true; 966 967 // Output known-0 bits are only known if clear in both the LHS & RHS. 968 KnownZero &= KnownZero2; 969 // Output known-1 are known to be set if set in either the LHS | RHS. 970 KnownOne |= KnownOne2; 971 break; 972 case ISD::XOR: 973 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 974 KnownOne, TLO, Depth+1)) 975 return true; 976 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 977 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 978 KnownOne2, TLO, Depth+1)) 979 return true; 980 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 981 982 // If all of the demanded bits are known zero on one side, return the other. 983 // These bits cannot contribute to the result of the 'xor'. 984 if ((KnownZero & NewMask) == NewMask) 985 return TLO.CombineTo(Op, Op.getOperand(0)); 986 if ((KnownZero2 & NewMask) == NewMask) 987 return TLO.CombineTo(Op, Op.getOperand(1)); 988 // If the operation can be done in a smaller type, do so. 989 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 990 return true; 991 992 // If all of the unknown bits are known to be zero on one side or the other 993 // (but not both) turn this into an *inclusive* or. 994 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 995 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 996 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 997 Op.getOperand(0), 998 Op.getOperand(1))); 999 1000 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1001 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1002 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1003 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1004 1005 // If all of the demanded bits on one side are known, and all of the set 1006 // bits on that side are also known to be set on the other side, turn this 1007 // into an AND, as we know the bits will be cleared. 1008 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1009 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1010 if ((KnownOne & KnownOne2) == KnownOne) { 1011 MVT VT = Op.getValueType(); 1012 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1013 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1014 Op.getOperand(0), ANDC)); 1015 } 1016 } 1017 1018 // If the RHS is a constant, see if we can simplify it. 1019 // for XOR, we prefer to force bits to 1 if they will make a -1. 1020 // if we can't force bits, try to shrink constant 1021 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1022 APInt Expanded = C->getAPIntValue() | (~NewMask); 1023 // if we can expand it to have all bits set, do it 1024 if (Expanded.isAllOnesValue()) { 1025 if (Expanded != C->getAPIntValue()) { 1026 MVT VT = Op.getValueType(); 1027 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1028 TLO.DAG.getConstant(Expanded, VT)); 1029 return TLO.CombineTo(Op, New); 1030 } 1031 // if it already has all the bits set, nothing to change 1032 // but don't shrink either! 1033 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1034 return true; 1035 } 1036 } 1037 1038 KnownZero = KnownZeroOut; 1039 KnownOne = KnownOneOut; 1040 break; 1041 case ISD::SELECT: 1042 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1043 KnownOne, TLO, Depth+1)) 1044 return true; 1045 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1046 KnownOne2, TLO, Depth+1)) 1047 return true; 1048 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1049 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1050 1051 // If the operands are constants, see if we can simplify them. 1052 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1053 return true; 1054 1055 // Only known if known in both the LHS and RHS. 1056 KnownOne &= KnownOne2; 1057 KnownZero &= KnownZero2; 1058 break; 1059 case ISD::SELECT_CC: 1060 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1061 KnownOne, TLO, Depth+1)) 1062 return true; 1063 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1064 KnownOne2, TLO, Depth+1)) 1065 return true; 1066 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1067 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1068 1069 // If the operands are constants, see if we can simplify them. 1070 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1071 return true; 1072 1073 // Only known if known in both the LHS and RHS. 1074 KnownOne &= KnownOne2; 1075 KnownZero &= KnownZero2; 1076 break; 1077 case ISD::SHL: 1078 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1079 unsigned ShAmt = SA->getZExtValue(); 1080 SDValue InOp = Op.getOperand(0); 1081 1082 // If the shift count is an invalid immediate, don't do anything. 1083 if (ShAmt >= BitWidth) 1084 break; 1085 1086 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1087 // single shift. We can do this if the bottom bits (which are shifted 1088 // out) are never demanded. 1089 if (InOp.getOpcode() == ISD::SRL && 1090 isa<ConstantSDNode>(InOp.getOperand(1))) { 1091 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1092 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1093 unsigned Opc = ISD::SHL; 1094 int Diff = ShAmt-C1; 1095 if (Diff < 0) { 1096 Diff = -Diff; 1097 Opc = ISD::SRL; 1098 } 1099 1100 SDValue NewSA = 1101 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1102 MVT VT = Op.getValueType(); 1103 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1104 InOp.getOperand(0), NewSA)); 1105 } 1106 } 1107 1108 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1109 KnownZero, KnownOne, TLO, Depth+1)) 1110 return true; 1111 KnownZero <<= SA->getZExtValue(); 1112 KnownOne <<= SA->getZExtValue(); 1113 // low bits known zero. 1114 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1115 } 1116 break; 1117 case ISD::SRL: 1118 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1119 MVT VT = Op.getValueType(); 1120 unsigned ShAmt = SA->getZExtValue(); 1121 unsigned VTSize = VT.getSizeInBits(); 1122 SDValue InOp = Op.getOperand(0); 1123 1124 // If the shift count is an invalid immediate, don't do anything. 1125 if (ShAmt >= BitWidth) 1126 break; 1127 1128 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1129 // single shift. We can do this if the top bits (which are shifted out) 1130 // are never demanded. 1131 if (InOp.getOpcode() == ISD::SHL && 1132 isa<ConstantSDNode>(InOp.getOperand(1))) { 1133 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1134 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1135 unsigned Opc = ISD::SRL; 1136 int Diff = ShAmt-C1; 1137 if (Diff < 0) { 1138 Diff = -Diff; 1139 Opc = ISD::SHL; 1140 } 1141 1142 SDValue NewSA = 1143 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1144 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1145 InOp.getOperand(0), NewSA)); 1146 } 1147 } 1148 1149 // Compute the new bits that are at the top now. 1150 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1151 KnownZero, KnownOne, TLO, Depth+1)) 1152 return true; 1153 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1154 KnownZero = KnownZero.lshr(ShAmt); 1155 KnownOne = KnownOne.lshr(ShAmt); 1156 1157 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1158 KnownZero |= HighBits; // High bits known zero. 1159 } 1160 break; 1161 case ISD::SRA: 1162 // If this is an arithmetic shift right and only the low-bit is set, we can 1163 // always convert this into a logical shr, even if the shift amount is 1164 // variable. The low bit of the shift cannot be an input sign bit unless 1165 // the shift amount is >= the size of the datatype, which is undefined. 1166 if (DemandedMask == 1) 1167 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1168 Op.getOperand(0), Op.getOperand(1))); 1169 1170 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1171 MVT VT = Op.getValueType(); 1172 unsigned ShAmt = SA->getZExtValue(); 1173 1174 // If the shift count is an invalid immediate, don't do anything. 1175 if (ShAmt >= BitWidth) 1176 break; 1177 1178 APInt InDemandedMask = (NewMask << ShAmt); 1179 1180 // If any of the demanded bits are produced by the sign extension, we also 1181 // demand the input sign bit. 1182 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1183 if (HighBits.intersects(NewMask)) 1184 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1185 1186 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1187 KnownZero, KnownOne, TLO, Depth+1)) 1188 return true; 1189 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1190 KnownZero = KnownZero.lshr(ShAmt); 1191 KnownOne = KnownOne.lshr(ShAmt); 1192 1193 // Handle the sign bit, adjusted to where it is now in the mask. 1194 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1195 1196 // If the input sign bit is known to be zero, or if none of the top bits 1197 // are demanded, turn this into an unsigned shift right. 1198 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1199 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1200 Op.getOperand(0), 1201 Op.getOperand(1))); 1202 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1203 KnownOne |= HighBits; 1204 } 1205 } 1206 break; 1207 case ISD::SIGN_EXTEND_INREG: { 1208 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1209 1210 // Sign extension. Compute the demanded bits in the result that are not 1211 // present in the input. 1212 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1213 BitWidth - EVT.getSizeInBits()) & 1214 NewMask; 1215 1216 // If none of the extended bits are demanded, eliminate the sextinreg. 1217 if (NewBits == 0) 1218 return TLO.CombineTo(Op, Op.getOperand(0)); 1219 1220 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1221 InSignBit.zext(BitWidth); 1222 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1223 EVT.getSizeInBits()) & 1224 NewMask; 1225 1226 // Since the sign extended bits are demanded, we know that the sign 1227 // bit is demanded. 1228 InputDemandedBits |= InSignBit; 1229 1230 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1231 KnownZero, KnownOne, TLO, Depth+1)) 1232 return true; 1233 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1234 1235 // If the sign bit of the input is known set or clear, then we know the 1236 // top bits of the result. 1237 1238 // If the input sign bit is known zero, convert this into a zero extension. 1239 if (KnownZero.intersects(InSignBit)) 1240 return TLO.CombineTo(Op, 1241 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1242 1243 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1244 KnownOne |= NewBits; 1245 KnownZero &= ~NewBits; 1246 } else { // Input sign bit unknown 1247 KnownZero &= ~NewBits; 1248 KnownOne &= ~NewBits; 1249 } 1250 break; 1251 } 1252 case ISD::ZERO_EXTEND: { 1253 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1254 APInt InMask = NewMask; 1255 InMask.trunc(OperandBitWidth); 1256 1257 // If none of the top bits are demanded, convert this into an any_extend. 1258 APInt NewBits = 1259 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1260 if (!NewBits.intersects(NewMask)) 1261 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1262 Op.getValueType(), 1263 Op.getOperand(0))); 1264 1265 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1266 KnownZero, KnownOne, TLO, Depth+1)) 1267 return true; 1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1269 KnownZero.zext(BitWidth); 1270 KnownOne.zext(BitWidth); 1271 KnownZero |= NewBits; 1272 break; 1273 } 1274 case ISD::SIGN_EXTEND: { 1275 MVT InVT = Op.getOperand(0).getValueType(); 1276 unsigned InBits = InVT.getSizeInBits(); 1277 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1278 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1279 APInt NewBits = ~InMask & NewMask; 1280 1281 // If none of the top bits are demanded, convert this into an any_extend. 1282 if (NewBits == 0) 1283 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1284 Op.getValueType(), 1285 Op.getOperand(0))); 1286 1287 // Since some of the sign extended bits are demanded, we know that the sign 1288 // bit is demanded. 1289 APInt InDemandedBits = InMask & NewMask; 1290 InDemandedBits |= InSignBit; 1291 InDemandedBits.trunc(InBits); 1292 1293 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1294 KnownOne, TLO, Depth+1)) 1295 return true; 1296 KnownZero.zext(BitWidth); 1297 KnownOne.zext(BitWidth); 1298 1299 // If the sign bit is known zero, convert this to a zero extend. 1300 if (KnownZero.intersects(InSignBit)) 1301 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1302 Op.getValueType(), 1303 Op.getOperand(0))); 1304 1305 // If the sign bit is known one, the top bits match. 1306 if (KnownOne.intersects(InSignBit)) { 1307 KnownOne |= NewBits; 1308 KnownZero &= ~NewBits; 1309 } else { // Otherwise, top bits aren't known. 1310 KnownOne &= ~NewBits; 1311 KnownZero &= ~NewBits; 1312 } 1313 break; 1314 } 1315 case ISD::ANY_EXTEND: { 1316 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1317 APInt InMask = NewMask; 1318 InMask.trunc(OperandBitWidth); 1319 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1320 KnownZero, KnownOne, TLO, Depth+1)) 1321 return true; 1322 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1323 KnownZero.zext(BitWidth); 1324 KnownOne.zext(BitWidth); 1325 break; 1326 } 1327 case ISD::TRUNCATE: { 1328 // Simplify the input, using demanded bit information, and compute the known 1329 // zero/one bits live out. 1330 APInt TruncMask = NewMask; 1331 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1332 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1333 KnownZero, KnownOne, TLO, Depth+1)) 1334 return true; 1335 KnownZero.trunc(BitWidth); 1336 KnownOne.trunc(BitWidth); 1337 1338 // If the input is only used by this truncate, see if we can shrink it based 1339 // on the known demanded bits. 1340 if (Op.getOperand(0).getNode()->hasOneUse()) { 1341 SDValue In = Op.getOperand(0); 1342 unsigned InBitWidth = In.getValueSizeInBits(); 1343 switch (In.getOpcode()) { 1344 default: break; 1345 case ISD::SRL: 1346 // Shrink SRL by a constant if none of the high bits shifted in are 1347 // demanded. 1348 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1349 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1350 InBitWidth - BitWidth); 1351 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1352 HighBits.trunc(BitWidth); 1353 1354 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1355 // None of the shifted in bits are needed. Add a truncate of the 1356 // shift input, then shift it. 1357 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1358 Op.getValueType(), 1359 In.getOperand(0)); 1360 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1361 Op.getValueType(), 1362 NewTrunc, 1363 In.getOperand(1))); 1364 } 1365 } 1366 break; 1367 } 1368 } 1369 1370 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1371 break; 1372 } 1373 case ISD::AssertZext: { 1374 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1375 APInt InMask = APInt::getLowBitsSet(BitWidth, 1376 VT.getSizeInBits()); 1377 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1378 KnownZero, KnownOne, TLO, Depth+1)) 1379 return true; 1380 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1381 KnownZero |= ~InMask & NewMask; 1382 break; 1383 } 1384 case ISD::BIT_CONVERT: 1385#if 0 1386 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1387 // is demanded, turn this into a FGETSIGN. 1388 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1389 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1390 !MVT::isVector(Op.getOperand(0).getValueType())) { 1391 // Only do this xform if FGETSIGN is valid or if before legalize. 1392 if (!TLO.AfterLegalize || 1393 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1394 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1395 // place. We expect the SHL to be eliminated by other optimizations. 1396 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1397 Op.getOperand(0)); 1398 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1399 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1400 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1401 Sign, ShAmt)); 1402 } 1403 } 1404#endif 1405 break; 1406 case ISD::ADD: 1407 case ISD::MUL: 1408 case ISD::SUB: { 1409 // Add, Sub, and Mul don't demand any bits in positions beyond that 1410 // of the highest bit demanded of them. 1411 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1412 BitWidth - NewMask.countLeadingZeros()); 1413 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1414 KnownOne2, TLO, Depth+1)) 1415 return true; 1416 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1417 KnownOne2, TLO, Depth+1)) 1418 return true; 1419 // See if the operation should be performed at a smaller bit width. 1420 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1421 return true; 1422 } 1423 // FALL THROUGH 1424 default: 1425 // Just use ComputeMaskedBits to compute output bits. 1426 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1427 break; 1428 } 1429 1430 // If we know the value of all of the demanded bits, return this as a 1431 // constant. 1432 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1433 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1434 1435 return false; 1436} 1437 1438/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1439/// in Mask are known to be either zero or one and return them in the 1440/// KnownZero/KnownOne bitsets. 1441void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1442 const APInt &Mask, 1443 APInt &KnownZero, 1444 APInt &KnownOne, 1445 const SelectionDAG &DAG, 1446 unsigned Depth) const { 1447 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1448 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1449 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1450 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1451 "Should use MaskedValueIsZero if you don't know whether Op" 1452 " is a target node!"); 1453 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1454} 1455 1456/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1457/// targets that want to expose additional information about sign bits to the 1458/// DAG Combiner. 1459unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1460 unsigned Depth) const { 1461 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1462 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1463 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1464 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1465 "Should use ComputeNumSignBits if you don't know whether Op" 1466 " is a target node!"); 1467 return 1; 1468} 1469 1470/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1471/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1472/// determine which bit is set. 1473/// 1474static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1475 // A left-shift of a constant one will have exactly one bit set, because 1476 // shifting the bit off the end is undefined. 1477 if (Val.getOpcode() == ISD::SHL) 1478 if (ConstantSDNode *C = 1479 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1480 if (C->getAPIntValue() == 1) 1481 return true; 1482 1483 // Similarly, a right-shift of a constant sign-bit will have exactly 1484 // one bit set. 1485 if (Val.getOpcode() == ISD::SRL) 1486 if (ConstantSDNode *C = 1487 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1488 if (C->getAPIntValue().isSignBit()) 1489 return true; 1490 1491 // More could be done here, though the above checks are enough 1492 // to handle some common cases. 1493 1494 // Fall back to ComputeMaskedBits to catch other known cases. 1495 MVT OpVT = Val.getValueType(); 1496 unsigned BitWidth = OpVT.getSizeInBits(); 1497 APInt Mask = APInt::getAllOnesValue(BitWidth); 1498 APInt KnownZero, KnownOne; 1499 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1500 return (KnownZero.countPopulation() == BitWidth - 1) && 1501 (KnownOne.countPopulation() == 1); 1502} 1503 1504/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1505/// and cc. If it is unable to simplify it, return a null SDValue. 1506SDValue 1507TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1508 ISD::CondCode Cond, bool foldBooleans, 1509 DAGCombinerInfo &DCI, DebugLoc dl) const { 1510 SelectionDAG &DAG = DCI.DAG; 1511 1512 // These setcc operations always fold. 1513 switch (Cond) { 1514 default: break; 1515 case ISD::SETFALSE: 1516 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1517 case ISD::SETTRUE: 1518 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1519 } 1520 1521 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1522 const APInt &C1 = N1C->getAPIntValue(); 1523 if (isa<ConstantSDNode>(N0.getNode())) { 1524 return DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1525 } else { 1526 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1527 // equality comparison, then we're just comparing whether X itself is 1528 // zero. 1529 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1530 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1531 N0.getOperand(1).getOpcode() == ISD::Constant) { 1532 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1533 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1534 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1535 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1536 // (srl (ctlz x), 5) == 0 -> X != 0 1537 // (srl (ctlz x), 5) != 1 -> X != 0 1538 Cond = ISD::SETNE; 1539 } else { 1540 // (srl (ctlz x), 5) != 0 -> X == 0 1541 // (srl (ctlz x), 5) == 1 -> X == 0 1542 Cond = ISD::SETEQ; 1543 } 1544 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1545 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1546 Zero, Cond); 1547 } 1548 } 1549 1550 // If the LHS is '(and load, const)', the RHS is 0, 1551 // the test is for equality or unsigned, and all 1 bits of the const are 1552 // in the same partial word, see if we can shorten the load. 1553 if (DCI.isBeforeLegalize() && 1554 N0.getOpcode() == ISD::AND && C1 == 0 && 1555 N0.getNode()->hasOneUse() && 1556 isa<LoadSDNode>(N0.getOperand(0)) && 1557 N0.getOperand(0).getNode()->hasOneUse() && 1558 isa<ConstantSDNode>(N0.getOperand(1))) { 1559 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1560 uint64_t bestMask = 0; 1561 unsigned bestWidth = 0, bestOffset = 0; 1562 if (!Lod->isVolatile() && Lod->isUnindexed() && 1563 // FIXME: This uses getZExtValue() below so it only works on i64 and 1564 // below. 1565 N0.getValueType().getSizeInBits() <= 64) { 1566 unsigned origWidth = N0.getValueType().getSizeInBits(); 1567 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1568 // 8 bits, but have to be careful... 1569 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1570 origWidth = Lod->getMemoryVT().getSizeInBits(); 1571 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1572 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1573 uint64_t newMask = (1ULL << width) - 1; 1574 for (unsigned offset=0; offset<origWidth/width; offset++) { 1575 if ((newMask & Mask) == Mask) { 1576 if (!TD->isLittleEndian()) 1577 bestOffset = (origWidth/width - offset - 1) * (width/8); 1578 else 1579 bestOffset = (uint64_t)offset * (width/8); 1580 bestMask = Mask >> (offset * (width/8) * 8); 1581 bestWidth = width; 1582 break; 1583 } 1584 newMask = newMask << width; 1585 } 1586 } 1587 } 1588 if (bestWidth) { 1589 MVT newVT = MVT::getIntegerVT(bestWidth); 1590 if (newVT.isRound()) { 1591 MVT PtrType = Lod->getOperand(1).getValueType(); 1592 SDValue Ptr = Lod->getBasePtr(); 1593 if (bestOffset != 0) 1594 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1595 DAG.getConstant(bestOffset, PtrType)); 1596 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1597 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1598 Lod->getSrcValue(), 1599 Lod->getSrcValueOffset() + bestOffset, 1600 false, NewAlign); 1601 return DAG.getSetCC(dl, VT, 1602 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1603 DAG.getConstant(bestMask, newVT)), 1604 DAG.getConstant(0LL, newVT), Cond); 1605 } 1606 } 1607 } 1608 1609 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1610 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1611 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1612 1613 // If the comparison constant has bits in the upper part, the 1614 // zero-extended value could never match. 1615 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1616 C1.getBitWidth() - InSize))) { 1617 switch (Cond) { 1618 case ISD::SETUGT: 1619 case ISD::SETUGE: 1620 case ISD::SETEQ: return DAG.getConstant(0, VT); 1621 case ISD::SETULT: 1622 case ISD::SETULE: 1623 case ISD::SETNE: return DAG.getConstant(1, VT); 1624 case ISD::SETGT: 1625 case ISD::SETGE: 1626 // True if the sign bit of C1 is set. 1627 return DAG.getConstant(C1.isNegative(), VT); 1628 case ISD::SETLT: 1629 case ISD::SETLE: 1630 // True if the sign bit of C1 isn't set. 1631 return DAG.getConstant(C1.isNonNegative(), VT); 1632 default: 1633 break; 1634 } 1635 } 1636 1637 // Otherwise, we can perform the comparison with the low bits. 1638 switch (Cond) { 1639 case ISD::SETEQ: 1640 case ISD::SETNE: 1641 case ISD::SETUGT: 1642 case ISD::SETUGE: 1643 case ISD::SETULT: 1644 case ISD::SETULE: { 1645 MVT newVT = N0.getOperand(0).getValueType(); 1646 if (DCI.isBeforeLegalizeOps() || 1647 (isOperationLegal(ISD::SETCC, newVT) && 1648 getCondCodeAction(Cond, newVT)==Legal)) 1649 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1650 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1651 Cond); 1652 break; 1653 } 1654 default: 1655 break; // todo, be more careful with signed comparisons 1656 } 1657 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1658 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1659 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1660 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1661 MVT ExtDstTy = N0.getValueType(); 1662 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1663 1664 // If the extended part has any inconsistent bits, it cannot ever 1665 // compare equal. In other words, they have to be all ones or all 1666 // zeros. 1667 APInt ExtBits = 1668 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1669 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1670 return DAG.getConstant(Cond == ISD::SETNE, VT); 1671 1672 SDValue ZextOp; 1673 MVT Op0Ty = N0.getOperand(0).getValueType(); 1674 if (Op0Ty == ExtSrcTy) { 1675 ZextOp = N0.getOperand(0); 1676 } else { 1677 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1678 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1679 DAG.getConstant(Imm, Op0Ty)); 1680 } 1681 if (!DCI.isCalledByLegalizer()) 1682 DCI.AddToWorklist(ZextOp.getNode()); 1683 // Otherwise, make this a use of a zext. 1684 return DAG.getSetCC(dl, VT, ZextOp, 1685 DAG.getConstant(C1 & APInt::getLowBitsSet( 1686 ExtDstTyBits, 1687 ExtSrcTyBits), 1688 ExtDstTy), 1689 Cond); 1690 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1691 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1692 1693 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1694 if (N0.getOpcode() == ISD::SETCC) { 1695 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1696 if (TrueWhenTrue) 1697 return N0; 1698 1699 // Invert the condition. 1700 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1701 CC = ISD::getSetCCInverse(CC, 1702 N0.getOperand(0).getValueType().isInteger()); 1703 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1704 } 1705 1706 if ((N0.getOpcode() == ISD::XOR || 1707 (N0.getOpcode() == ISD::AND && 1708 N0.getOperand(0).getOpcode() == ISD::XOR && 1709 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1710 isa<ConstantSDNode>(N0.getOperand(1)) && 1711 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1712 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1713 // can only do this if the top bits are known zero. 1714 unsigned BitWidth = N0.getValueSizeInBits(); 1715 if (DAG.MaskedValueIsZero(N0, 1716 APInt::getHighBitsSet(BitWidth, 1717 BitWidth-1))) { 1718 // Okay, get the un-inverted input value. 1719 SDValue Val; 1720 if (N0.getOpcode() == ISD::XOR) 1721 Val = N0.getOperand(0); 1722 else { 1723 assert(N0.getOpcode() == ISD::AND && 1724 N0.getOperand(0).getOpcode() == ISD::XOR); 1725 // ((X^1)&1)^1 -> X & 1 1726 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1727 N0.getOperand(0).getOperand(0), 1728 N0.getOperand(1)); 1729 } 1730 return DAG.getSetCC(dl, VT, Val, N1, 1731 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1732 } 1733 } 1734 } 1735 1736 APInt MinVal, MaxVal; 1737 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1738 if (ISD::isSignedIntSetCC(Cond)) { 1739 MinVal = APInt::getSignedMinValue(OperandBitSize); 1740 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1741 } else { 1742 MinVal = APInt::getMinValue(OperandBitSize); 1743 MaxVal = APInt::getMaxValue(OperandBitSize); 1744 } 1745 1746 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1747 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1748 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1749 // X >= C0 --> X > (C0-1) 1750 return DAG.getSetCC(dl, VT, N0, 1751 DAG.getConstant(C1-1, N1.getValueType()), 1752 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1753 } 1754 1755 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1756 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1757 // X <= C0 --> X < (C0+1) 1758 return DAG.getSetCC(dl, VT, N0, 1759 DAG.getConstant(C1+1, N1.getValueType()), 1760 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1761 } 1762 1763 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1764 return DAG.getConstant(0, VT); // X < MIN --> false 1765 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1766 return DAG.getConstant(1, VT); // X >= MIN --> true 1767 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1768 return DAG.getConstant(0, VT); // X > MAX --> false 1769 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1770 return DAG.getConstant(1, VT); // X <= MAX --> true 1771 1772 // Canonicalize setgt X, Min --> setne X, Min 1773 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1774 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1775 // Canonicalize setlt X, Max --> setne X, Max 1776 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1777 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1778 1779 // If we have setult X, 1, turn it into seteq X, 0 1780 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1781 return DAG.getSetCC(dl, VT, N0, 1782 DAG.getConstant(MinVal, N0.getValueType()), 1783 ISD::SETEQ); 1784 // If we have setugt X, Max-1, turn it into seteq X, Max 1785 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1786 return DAG.getSetCC(dl, VT, N0, 1787 DAG.getConstant(MaxVal, N0.getValueType()), 1788 ISD::SETEQ); 1789 1790 // If we have "setcc X, C0", check to see if we can shrink the immediate 1791 // by changing cc. 1792 1793 // SETUGT X, SINTMAX -> SETLT X, 0 1794 if (Cond == ISD::SETUGT && 1795 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1796 return DAG.getSetCC(dl, VT, N0, 1797 DAG.getConstant(0, N1.getValueType()), 1798 ISD::SETLT); 1799 1800 // SETULT X, SINTMIN -> SETGT X, -1 1801 if (Cond == ISD::SETULT && 1802 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1803 SDValue ConstMinusOne = 1804 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1805 N1.getValueType()); 1806 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1807 } 1808 1809 // Fold bit comparisons when we can. 1810 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1811 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1812 if (ConstantSDNode *AndRHS = 1813 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1814 MVT ShiftTy = DCI.isBeforeLegalize() ? 1815 getPointerTy() : getShiftAmountTy(); 1816 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1817 // Perform the xform if the AND RHS is a single bit. 1818 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1819 return DAG.getNode(ISD::SRL, dl, VT, N0, 1820 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1821 ShiftTy)); 1822 } 1823 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1824 // (X & 8) == 8 --> (X & 8) >> 3 1825 // Perform the xform if C1 is a single bit. 1826 if (C1.isPowerOf2()) { 1827 return DAG.getNode(ISD::SRL, dl, VT, N0, 1828 DAG.getConstant(C1.logBase2(), ShiftTy)); 1829 } 1830 } 1831 } 1832 } 1833 } else if (isa<ConstantSDNode>(N0.getNode())) { 1834 // Ensure that the constant occurs on the RHS. 1835 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1836 } 1837 1838 if (isa<ConstantFPSDNode>(N0.getNode())) { 1839 // Constant fold or commute setcc. 1840 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1841 if (O.getNode()) return O; 1842 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1843 // If the RHS of an FP comparison is a constant, simplify it away in 1844 // some cases. 1845 if (CFP->getValueAPF().isNaN()) { 1846 // If an operand is known to be a nan, we can fold it. 1847 switch (ISD::getUnorderedFlavor(Cond)) { 1848 default: llvm_unreachable("Unknown flavor!"); 1849 case 0: // Known false. 1850 return DAG.getConstant(0, VT); 1851 case 1: // Known true. 1852 return DAG.getConstant(1, VT); 1853 case 2: // Undefined. 1854 return DAG.getUNDEF(VT); 1855 } 1856 } 1857 1858 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1859 // constant if knowing that the operand is non-nan is enough. We prefer to 1860 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1861 // materialize 0.0. 1862 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1863 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1864 } 1865 1866 if (N0 == N1) { 1867 // We can always fold X == X for integer setcc's. 1868 if (N0.getValueType().isInteger()) 1869 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1870 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1871 if (UOF == 2) // FP operators that are undefined on NaNs. 1872 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1873 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1874 return DAG.getConstant(UOF, VT); 1875 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1876 // if it is not already. 1877 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1878 if (NewCond != Cond) 1879 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1880 } 1881 1882 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1883 N0.getValueType().isInteger()) { 1884 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1885 N0.getOpcode() == ISD::XOR) { 1886 // Simplify (X+Y) == (X+Z) --> Y == Z 1887 if (N0.getOpcode() == N1.getOpcode()) { 1888 if (N0.getOperand(0) == N1.getOperand(0)) 1889 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1890 if (N0.getOperand(1) == N1.getOperand(1)) 1891 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1892 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1893 // If X op Y == Y op X, try other combinations. 1894 if (N0.getOperand(0) == N1.getOperand(1)) 1895 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1896 Cond); 1897 if (N0.getOperand(1) == N1.getOperand(0)) 1898 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1899 Cond); 1900 } 1901 } 1902 1903 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1904 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1905 // Turn (X+C1) == C2 --> X == C2-C1 1906 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1907 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1908 DAG.getConstant(RHSC->getAPIntValue()- 1909 LHSR->getAPIntValue(), 1910 N0.getValueType()), Cond); 1911 } 1912 1913 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1914 if (N0.getOpcode() == ISD::XOR) 1915 // If we know that all of the inverted bits are zero, don't bother 1916 // performing the inversion. 1917 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1918 return 1919 DAG.getSetCC(dl, VT, N0.getOperand(0), 1920 DAG.getConstant(LHSR->getAPIntValue() ^ 1921 RHSC->getAPIntValue(), 1922 N0.getValueType()), 1923 Cond); 1924 } 1925 1926 // Turn (C1-X) == C2 --> X == C1-C2 1927 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1928 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1929 return 1930 DAG.getSetCC(dl, VT, N0.getOperand(1), 1931 DAG.getConstant(SUBC->getAPIntValue() - 1932 RHSC->getAPIntValue(), 1933 N0.getValueType()), 1934 Cond); 1935 } 1936 } 1937 } 1938 1939 // Simplify (X+Z) == X --> Z == 0 1940 if (N0.getOperand(0) == N1) 1941 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1942 DAG.getConstant(0, N0.getValueType()), Cond); 1943 if (N0.getOperand(1) == N1) { 1944 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1945 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1946 DAG.getConstant(0, N0.getValueType()), Cond); 1947 else if (N0.getNode()->hasOneUse()) { 1948 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1949 // (Z-X) == X --> Z == X<<1 1950 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1951 N1, 1952 DAG.getConstant(1, getShiftAmountTy())); 1953 if (!DCI.isCalledByLegalizer()) 1954 DCI.AddToWorklist(SH.getNode()); 1955 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1956 } 1957 } 1958 } 1959 1960 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1961 N1.getOpcode() == ISD::XOR) { 1962 // Simplify X == (X+Z) --> Z == 0 1963 if (N1.getOperand(0) == N0) { 1964 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1965 DAG.getConstant(0, N1.getValueType()), Cond); 1966 } else if (N1.getOperand(1) == N0) { 1967 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1968 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1969 DAG.getConstant(0, N1.getValueType()), Cond); 1970 } else if (N1.getNode()->hasOneUse()) { 1971 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1972 // X == (Z-X) --> X<<1 == Z 1973 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1974 DAG.getConstant(1, getShiftAmountTy())); 1975 if (!DCI.isCalledByLegalizer()) 1976 DCI.AddToWorklist(SH.getNode()); 1977 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1978 } 1979 } 1980 } 1981 1982 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1983 // Note that where y is variable and is known to have at most 1984 // one bit set (for example, if it is z&1) we cannot do this; 1985 // the expressions are not equivalent when y==0. 1986 if (N0.getOpcode() == ISD::AND) 1987 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1988 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1989 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1990 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1991 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1992 } 1993 } 1994 if (N1.getOpcode() == ISD::AND) 1995 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1996 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1997 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1998 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1999 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2000 } 2001 } 2002 } 2003 2004 // Fold away ALL boolean setcc's. 2005 SDValue Temp; 2006 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2007 switch (Cond) { 2008 default: llvm_unreachable("Unknown integer setcc!"); 2009 case ISD::SETEQ: // X == Y -> ~(X^Y) 2010 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2011 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2012 if (!DCI.isCalledByLegalizer()) 2013 DCI.AddToWorklist(Temp.getNode()); 2014 break; 2015 case ISD::SETNE: // X != Y --> (X^Y) 2016 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2017 break; 2018 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2019 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2020 Temp = DAG.getNOT(dl, N0, MVT::i1); 2021 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2022 if (!DCI.isCalledByLegalizer()) 2023 DCI.AddToWorklist(Temp.getNode()); 2024 break; 2025 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2026 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2027 Temp = DAG.getNOT(dl, N1, MVT::i1); 2028 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2029 if (!DCI.isCalledByLegalizer()) 2030 DCI.AddToWorklist(Temp.getNode()); 2031 break; 2032 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2033 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2034 Temp = DAG.getNOT(dl, N0, MVT::i1); 2035 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2036 if (!DCI.isCalledByLegalizer()) 2037 DCI.AddToWorklist(Temp.getNode()); 2038 break; 2039 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2040 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2041 Temp = DAG.getNOT(dl, N1, MVT::i1); 2042 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2043 break; 2044 } 2045 if (VT != MVT::i1) { 2046 if (!DCI.isCalledByLegalizer()) 2047 DCI.AddToWorklist(N0.getNode()); 2048 // FIXME: If running after legalize, we probably can't do this. 2049 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2050 } 2051 return N0; 2052 } 2053 2054 // Could not fold it. 2055 return SDValue(); 2056} 2057 2058/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2059/// node is a GlobalAddress + offset. 2060bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2061 int64_t &Offset) const { 2062 if (isa<GlobalAddressSDNode>(N)) { 2063 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2064 GA = GASD->getGlobal(); 2065 Offset += GASD->getOffset(); 2066 return true; 2067 } 2068 2069 if (N->getOpcode() == ISD::ADD) { 2070 SDValue N1 = N->getOperand(0); 2071 SDValue N2 = N->getOperand(1); 2072 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2073 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2074 if (V) { 2075 Offset += V->getSExtValue(); 2076 return true; 2077 } 2078 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2079 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2080 if (V) { 2081 Offset += V->getSExtValue(); 2082 return true; 2083 } 2084 } 2085 } 2086 return false; 2087} 2088 2089 2090/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 2091/// location that is 'Dist' units away from the location that the 'Base' load 2092/// is loading from. 2093bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, 2094 unsigned Bytes, int Dist, 2095 const MachineFrameInfo *MFI) const { 2096 if (LD->getChain() != Base->getChain()) 2097 return false; 2098 MVT VT = LD->getValueType(0); 2099 if (VT.getSizeInBits() / 8 != Bytes) 2100 return false; 2101 2102 SDValue Loc = LD->getOperand(1); 2103 SDValue BaseLoc = Base->getOperand(1); 2104 if (Loc.getOpcode() == ISD::FrameIndex) { 2105 if (BaseLoc.getOpcode() != ISD::FrameIndex) 2106 return false; 2107 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 2108 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 2109 int FS = MFI->getObjectSize(FI); 2110 int BFS = MFI->getObjectSize(BFI); 2111 if (FS != BFS || FS != (int)Bytes) return false; 2112 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 2113 } 2114 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) { 2115 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1)); 2116 if (V && (V->getSExtValue() == Dist*Bytes)) 2117 return true; 2118 } 2119 2120 GlobalValue *GV1 = NULL; 2121 GlobalValue *GV2 = NULL; 2122 int64_t Offset1 = 0; 2123 int64_t Offset2 = 0; 2124 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 2125 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 2126 if (isGA1 && isGA2 && GV1 == GV2) 2127 return Offset1 == (Offset2 + Dist*Bytes); 2128 return false; 2129} 2130 2131 2132SDValue TargetLowering:: 2133PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2134 // Default implementation: no optimization. 2135 return SDValue(); 2136} 2137 2138//===----------------------------------------------------------------------===// 2139// Inline Assembler Implementation Methods 2140//===----------------------------------------------------------------------===// 2141 2142 2143TargetLowering::ConstraintType 2144TargetLowering::getConstraintType(const std::string &Constraint) const { 2145 // FIXME: lots more standard ones to handle. 2146 if (Constraint.size() == 1) { 2147 switch (Constraint[0]) { 2148 default: break; 2149 case 'r': return C_RegisterClass; 2150 case 'm': // memory 2151 case 'o': // offsetable 2152 case 'V': // not offsetable 2153 return C_Memory; 2154 case 'i': // Simple Integer or Relocatable Constant 2155 case 'n': // Simple Integer 2156 case 's': // Relocatable Constant 2157 case 'X': // Allow ANY value. 2158 case 'I': // Target registers. 2159 case 'J': 2160 case 'K': 2161 case 'L': 2162 case 'M': 2163 case 'N': 2164 case 'O': 2165 case 'P': 2166 return C_Other; 2167 } 2168 } 2169 2170 if (Constraint.size() > 1 && Constraint[0] == '{' && 2171 Constraint[Constraint.size()-1] == '}') 2172 return C_Register; 2173 return C_Unknown; 2174} 2175 2176/// LowerXConstraint - try to replace an X constraint, which matches anything, 2177/// with another that has more specific requirements based on the type of the 2178/// corresponding operand. 2179const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2180 if (ConstraintVT.isInteger()) 2181 return "r"; 2182 if (ConstraintVT.isFloatingPoint()) 2183 return "f"; // works for many targets 2184 return 0; 2185} 2186 2187/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2188/// vector. If it is invalid, don't add anything to Ops. 2189void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2190 char ConstraintLetter, 2191 bool hasMemory, 2192 std::vector<SDValue> &Ops, 2193 SelectionDAG &DAG) const { 2194 switch (ConstraintLetter) { 2195 default: break; 2196 case 'X': // Allows any operand; labels (basic block) use this. 2197 if (Op.getOpcode() == ISD::BasicBlock) { 2198 Ops.push_back(Op); 2199 return; 2200 } 2201 // fall through 2202 case 'i': // Simple Integer or Relocatable Constant 2203 case 'n': // Simple Integer 2204 case 's': { // Relocatable Constant 2205 // These operands are interested in values of the form (GV+C), where C may 2206 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2207 // is possible and fine if either GV or C are missing. 2208 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2209 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2210 2211 // If we have "(add GV, C)", pull out GV/C 2212 if (Op.getOpcode() == ISD::ADD) { 2213 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2214 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2215 if (C == 0 || GA == 0) { 2216 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2217 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2218 } 2219 if (C == 0 || GA == 0) 2220 C = 0, GA = 0; 2221 } 2222 2223 // If we find a valid operand, map to the TargetXXX version so that the 2224 // value itself doesn't get selected. 2225 if (GA) { // Either &GV or &GV+C 2226 if (ConstraintLetter != 'n') { 2227 int64_t Offs = GA->getOffset(); 2228 if (C) Offs += C->getZExtValue(); 2229 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2230 Op.getValueType(), Offs)); 2231 return; 2232 } 2233 } 2234 if (C) { // just C, no GV. 2235 // Simple constants are not allowed for 's'. 2236 if (ConstraintLetter != 's') { 2237 // gcc prints these as sign extended. Sign extend value to 64 bits 2238 // now; without this it would get ZExt'd later in 2239 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2240 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2241 MVT::i64)); 2242 return; 2243 } 2244 } 2245 break; 2246 } 2247 } 2248} 2249 2250std::vector<unsigned> TargetLowering:: 2251getRegClassForInlineAsmConstraint(const std::string &Constraint, 2252 MVT VT) const { 2253 return std::vector<unsigned>(); 2254} 2255 2256 2257std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2258getRegForInlineAsmConstraint(const std::string &Constraint, 2259 MVT VT) const { 2260 if (Constraint[0] != '{') 2261 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2262 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2263 2264 // Remove the braces from around the name. 2265 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2266 2267 // Figure out which register class contains this reg. 2268 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2269 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2270 E = RI->regclass_end(); RCI != E; ++RCI) { 2271 const TargetRegisterClass *RC = *RCI; 2272 2273 // If none of the the value types for this register class are valid, we 2274 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2275 bool isLegal = false; 2276 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2277 I != E; ++I) { 2278 if (isTypeLegal(*I)) { 2279 isLegal = true; 2280 break; 2281 } 2282 } 2283 2284 if (!isLegal) continue; 2285 2286 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2287 I != E; ++I) { 2288 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2289 return std::make_pair(*I, RC); 2290 } 2291 } 2292 2293 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2294} 2295 2296//===----------------------------------------------------------------------===// 2297// Constraint Selection. 2298 2299/// isMatchingInputConstraint - Return true of this is an input operand that is 2300/// a matching constraint like "4". 2301bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2302 assert(!ConstraintCode.empty() && "No known constraint!"); 2303 return isdigit(ConstraintCode[0]); 2304} 2305 2306/// getMatchedOperand - If this is an input matching constraint, this method 2307/// returns the output operand it matches. 2308unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2309 assert(!ConstraintCode.empty() && "No known constraint!"); 2310 return atoi(ConstraintCode.c_str()); 2311} 2312 2313 2314/// getConstraintGenerality - Return an integer indicating how general CT 2315/// is. 2316static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2317 switch (CT) { 2318 default: llvm_unreachable("Unknown constraint type!"); 2319 case TargetLowering::C_Other: 2320 case TargetLowering::C_Unknown: 2321 return 0; 2322 case TargetLowering::C_Register: 2323 return 1; 2324 case TargetLowering::C_RegisterClass: 2325 return 2; 2326 case TargetLowering::C_Memory: 2327 return 3; 2328 } 2329} 2330 2331/// ChooseConstraint - If there are multiple different constraints that we 2332/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2333/// This is somewhat tricky: constraints fall into four classes: 2334/// Other -> immediates and magic values 2335/// Register -> one specific register 2336/// RegisterClass -> a group of regs 2337/// Memory -> memory 2338/// Ideally, we would pick the most specific constraint possible: if we have 2339/// something that fits into a register, we would pick it. The problem here 2340/// is that if we have something that could either be in a register or in 2341/// memory that use of the register could cause selection of *other* 2342/// operands to fail: they might only succeed if we pick memory. Because of 2343/// this the heuristic we use is: 2344/// 2345/// 1) If there is an 'other' constraint, and if the operand is valid for 2346/// that constraint, use it. This makes us take advantage of 'i' 2347/// constraints when available. 2348/// 2) Otherwise, pick the most general constraint present. This prefers 2349/// 'm' over 'r', for example. 2350/// 2351static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2352 bool hasMemory, const TargetLowering &TLI, 2353 SDValue Op, SelectionDAG *DAG) { 2354 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2355 unsigned BestIdx = 0; 2356 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2357 int BestGenerality = -1; 2358 2359 // Loop over the options, keeping track of the most general one. 2360 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2361 TargetLowering::ConstraintType CType = 2362 TLI.getConstraintType(OpInfo.Codes[i]); 2363 2364 // If this is an 'other' constraint, see if the operand is valid for it. 2365 // For example, on X86 we might have an 'rI' constraint. If the operand 2366 // is an integer in the range [0..31] we want to use I (saving a load 2367 // of a register), otherwise we must use 'r'. 2368 if (CType == TargetLowering::C_Other && Op.getNode()) { 2369 assert(OpInfo.Codes[i].size() == 1 && 2370 "Unhandled multi-letter 'other' constraint"); 2371 std::vector<SDValue> ResultOps; 2372 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2373 ResultOps, *DAG); 2374 if (!ResultOps.empty()) { 2375 BestType = CType; 2376 BestIdx = i; 2377 break; 2378 } 2379 } 2380 2381 // This constraint letter is more general than the previous one, use it. 2382 int Generality = getConstraintGenerality(CType); 2383 if (Generality > BestGenerality) { 2384 BestType = CType; 2385 BestIdx = i; 2386 BestGenerality = Generality; 2387 } 2388 } 2389 2390 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2391 OpInfo.ConstraintType = BestType; 2392} 2393 2394/// ComputeConstraintToUse - Determines the constraint code and constraint 2395/// type to use for the specific AsmOperandInfo, setting 2396/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2397void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2398 SDValue Op, 2399 bool hasMemory, 2400 SelectionDAG *DAG) const { 2401 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2402 2403 // Single-letter constraints ('r') are very common. 2404 if (OpInfo.Codes.size() == 1) { 2405 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2406 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2407 } else { 2408 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2409 } 2410 2411 // 'X' matches anything. 2412 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2413 // Labels and constants are handled elsewhere ('X' is the only thing 2414 // that matches labels). For Functions, the type here is the type of 2415 // the result, which is not what we want to look at; leave them alone. 2416 Value *v = OpInfo.CallOperandVal; 2417 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2418 OpInfo.CallOperandVal = v; 2419 return; 2420 } 2421 2422 // Otherwise, try to resolve it to something we know about by looking at 2423 // the actual operand type. 2424 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2425 OpInfo.ConstraintCode = Repl; 2426 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2427 } 2428 } 2429} 2430 2431//===----------------------------------------------------------------------===// 2432// Loop Strength Reduction hooks 2433//===----------------------------------------------------------------------===// 2434 2435/// isLegalAddressingMode - Return true if the addressing mode represented 2436/// by AM is legal for this target, for a load/store of the specified type. 2437bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2438 const Type *Ty) const { 2439 // The default implementation of this implements a conservative RISCy, r+r and 2440 // r+i addr mode. 2441 2442 // Allows a sign-extended 16-bit immediate field. 2443 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2444 return false; 2445 2446 // No global is ever allowed as a base. 2447 if (AM.BaseGV) 2448 return false; 2449 2450 // Only support r+r, 2451 switch (AM.Scale) { 2452 case 0: // "r+i" or just "i", depending on HasBaseReg. 2453 break; 2454 case 1: 2455 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2456 return false; 2457 // Otherwise we have r+r or r+i. 2458 break; 2459 case 2: 2460 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2461 return false; 2462 // Allow 2*r as r+r. 2463 break; 2464 } 2465 2466 return true; 2467} 2468 2469/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2470/// return a DAG expression to select that will generate the same value by 2471/// multiplying by a magic number. See: 2472/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2473SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2474 std::vector<SDNode*>* Created) const { 2475 MVT VT = N->getValueType(0); 2476 DebugLoc dl= N->getDebugLoc(); 2477 2478 // Check to see if we can do this. 2479 // FIXME: We should be more aggressive here. 2480 if (!isTypeLegal(VT)) 2481 return SDValue(); 2482 2483 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2484 APInt::ms magics = d.magic(); 2485 2486 // Multiply the numerator (operand 0) by the magic value 2487 // FIXME: We should support doing a MUL in a wider type 2488 SDValue Q; 2489 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2490 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2491 DAG.getConstant(magics.m, VT)); 2492 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2493 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2494 N->getOperand(0), 2495 DAG.getConstant(magics.m, VT)).getNode(), 1); 2496 else 2497 return SDValue(); // No mulhs or equvialent 2498 // If d > 0 and m < 0, add the numerator 2499 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2500 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2501 if (Created) 2502 Created->push_back(Q.getNode()); 2503 } 2504 // If d < 0 and m > 0, subtract the numerator. 2505 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2506 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2507 if (Created) 2508 Created->push_back(Q.getNode()); 2509 } 2510 // Shift right algebraic if shift value is nonzero 2511 if (magics.s > 0) { 2512 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2513 DAG.getConstant(magics.s, getShiftAmountTy())); 2514 if (Created) 2515 Created->push_back(Q.getNode()); 2516 } 2517 // Extract the sign bit and add it to the quotient 2518 SDValue T = 2519 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2520 getShiftAmountTy())); 2521 if (Created) 2522 Created->push_back(T.getNode()); 2523 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2524} 2525 2526/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2527/// return a DAG expression to select that will generate the same value by 2528/// multiplying by a magic number. See: 2529/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2530SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2531 std::vector<SDNode*>* Created) const { 2532 MVT VT = N->getValueType(0); 2533 DebugLoc dl = N->getDebugLoc(); 2534 2535 // Check to see if we can do this. 2536 // FIXME: We should be more aggressive here. 2537 if (!isTypeLegal(VT)) 2538 return SDValue(); 2539 2540 // FIXME: We should use a narrower constant when the upper 2541 // bits are known to be zero. 2542 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2543 APInt::mu magics = N1C->getAPIntValue().magicu(); 2544 2545 // Multiply the numerator (operand 0) by the magic value 2546 // FIXME: We should support doing a MUL in a wider type 2547 SDValue Q; 2548 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2549 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2550 DAG.getConstant(magics.m, VT)); 2551 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2552 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2553 N->getOperand(0), 2554 DAG.getConstant(magics.m, VT)).getNode(), 1); 2555 else 2556 return SDValue(); // No mulhu or equvialent 2557 if (Created) 2558 Created->push_back(Q.getNode()); 2559 2560 if (magics.a == 0) { 2561 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2562 "We shouldn't generate an undefined shift!"); 2563 return DAG.getNode(ISD::SRL, dl, VT, Q, 2564 DAG.getConstant(magics.s, getShiftAmountTy())); 2565 } else { 2566 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2567 if (Created) 2568 Created->push_back(NPQ.getNode()); 2569 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2570 DAG.getConstant(1, getShiftAmountTy())); 2571 if (Created) 2572 Created->push_back(NPQ.getNode()); 2573 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2574 if (Created) 2575 Created->push_back(NPQ.getNode()); 2576 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2577 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2578 } 2579} 2580 2581/// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET 2582/// node that don't prevent tail call optimization. 2583static SDValue IgnoreHarmlessInstructions(SDValue node) { 2584 // Found call return. 2585 if (node.getOpcode() == ISD::CALL) return node; 2586 // Ignore MERGE_VALUES. Will have at least one operand. 2587 if (node.getOpcode() == ISD::MERGE_VALUES) 2588 return IgnoreHarmlessInstructions(node.getOperand(0)); 2589 // Ignore ANY_EXTEND node. 2590 if (node.getOpcode() == ISD::ANY_EXTEND) 2591 return IgnoreHarmlessInstructions(node.getOperand(0)); 2592 if (node.getOpcode() == ISD::TRUNCATE) 2593 return IgnoreHarmlessInstructions(node.getOperand(0)); 2594 // Any other node type. 2595 return node; 2596} 2597 2598bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall, 2599 SDValue Ret) { 2600 unsigned NumOps = Ret.getNumOperands(); 2601 // ISD::CALL results:(value0, ..., valuen, chain) 2602 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn) 2603 // Value return: 2604 // Check that operand of the RET node sources from the CALL node. The RET node 2605 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the 2606 // value. 2607 // Also we need to check that there is no code in between the call and the 2608 // return. Hence we also check that the incomming chain to the return sources 2609 // from the outgoing chain of the call. 2610 if (NumOps > 1 && 2611 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0) && 2612 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2613 return true; 2614 // void return: The RET node has the chain result value of the CALL node as 2615 // input. 2616 if (NumOps == 1 && 2617 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2618 return true; 2619 2620 return false; 2621} 2622