TargetLowering.cpp revision 7b620afb60382e26ea0c974175b50414f19fc0ff
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29namespace llvm { 30TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 31 bool isLocal = GV->hasLocalLinkage(); 32 bool isDeclaration = GV->isDeclaration(); 33 // FIXME: what should we do for protected and internal visibility? 34 // For variables, is internal different from hidden? 35 bool isHidden = GV->hasHiddenVisibility(); 36 37 if (reloc == Reloc::PIC_) { 38 if (isLocal || isHidden) 39 return TLSModel::LocalDynamic; 40 else 41 return TLSModel::GeneralDynamic; 42 } else { 43 if (!isDeclaration || isHidden) 44 return TLSModel::LocalExec; 45 else 46 return TLSModel::InitialExec; 47 } 48} 49} 50 51/// InitLibcallNames - Set default libcall names. 52/// 53static void InitLibcallNames(const char **Names) { 54 Names[RTLIB::SHL_I16] = "__ashli16"; 55 Names[RTLIB::SHL_I32] = "__ashlsi3"; 56 Names[RTLIB::SHL_I64] = "__ashldi3"; 57 Names[RTLIB::SHL_I128] = "__ashlti3"; 58 Names[RTLIB::SRL_I16] = "__lshri16"; 59 Names[RTLIB::SRL_I32] = "__lshrsi3"; 60 Names[RTLIB::SRL_I64] = "__lshrdi3"; 61 Names[RTLIB::SRL_I128] = "__lshrti3"; 62 Names[RTLIB::SRA_I16] = "__ashri16"; 63 Names[RTLIB::SRA_I32] = "__ashrsi3"; 64 Names[RTLIB::SRA_I64] = "__ashrdi3"; 65 Names[RTLIB::SRA_I128] = "__ashrti3"; 66 Names[RTLIB::MUL_I16] = "__muli16"; 67 Names[RTLIB::MUL_I32] = "__mulsi3"; 68 Names[RTLIB::MUL_I64] = "__muldi3"; 69 Names[RTLIB::MUL_I128] = "__multi3"; 70 Names[RTLIB::SDIV_I32] = "__divsi3"; 71 Names[RTLIB::SDIV_I64] = "__divdi3"; 72 Names[RTLIB::SDIV_I128] = "__divti3"; 73 Names[RTLIB::UDIV_I32] = "__udivsi3"; 74 Names[RTLIB::UDIV_I64] = "__udivdi3"; 75 Names[RTLIB::UDIV_I128] = "__udivti3"; 76 Names[RTLIB::SREM_I32] = "__modsi3"; 77 Names[RTLIB::SREM_I64] = "__moddi3"; 78 Names[RTLIB::SREM_I128] = "__modti3"; 79 Names[RTLIB::UREM_I32] = "__umodsi3"; 80 Names[RTLIB::UREM_I64] = "__umoddi3"; 81 Names[RTLIB::UREM_I128] = "__umodti3"; 82 Names[RTLIB::NEG_I32] = "__negsi2"; 83 Names[RTLIB::NEG_I64] = "__negdi2"; 84 Names[RTLIB::ADD_F32] = "__addsf3"; 85 Names[RTLIB::ADD_F64] = "__adddf3"; 86 Names[RTLIB::ADD_F80] = "__addxf3"; 87 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 88 Names[RTLIB::SUB_F32] = "__subsf3"; 89 Names[RTLIB::SUB_F64] = "__subdf3"; 90 Names[RTLIB::SUB_F80] = "__subxf3"; 91 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 92 Names[RTLIB::MUL_F32] = "__mulsf3"; 93 Names[RTLIB::MUL_F64] = "__muldf3"; 94 Names[RTLIB::MUL_F80] = "__mulxf3"; 95 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 96 Names[RTLIB::DIV_F32] = "__divsf3"; 97 Names[RTLIB::DIV_F64] = "__divdf3"; 98 Names[RTLIB::DIV_F80] = "__divxf3"; 99 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 100 Names[RTLIB::REM_F32] = "fmodf"; 101 Names[RTLIB::REM_F64] = "fmod"; 102 Names[RTLIB::REM_F80] = "fmodl"; 103 Names[RTLIB::REM_PPCF128] = "fmodl"; 104 Names[RTLIB::POWI_F32] = "__powisf2"; 105 Names[RTLIB::POWI_F64] = "__powidf2"; 106 Names[RTLIB::POWI_F80] = "__powixf2"; 107 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 108 Names[RTLIB::SQRT_F32] = "sqrtf"; 109 Names[RTLIB::SQRT_F64] = "sqrt"; 110 Names[RTLIB::SQRT_F80] = "sqrtl"; 111 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 112 Names[RTLIB::LOG_F32] = "logf"; 113 Names[RTLIB::LOG_F64] = "log"; 114 Names[RTLIB::LOG_F80] = "logl"; 115 Names[RTLIB::LOG_PPCF128] = "logl"; 116 Names[RTLIB::LOG2_F32] = "log2f"; 117 Names[RTLIB::LOG2_F64] = "log2"; 118 Names[RTLIB::LOG2_F80] = "log2l"; 119 Names[RTLIB::LOG2_PPCF128] = "log2l"; 120 Names[RTLIB::LOG10_F32] = "log10f"; 121 Names[RTLIB::LOG10_F64] = "log10"; 122 Names[RTLIB::LOG10_F80] = "log10l"; 123 Names[RTLIB::LOG10_PPCF128] = "log10l"; 124 Names[RTLIB::EXP_F32] = "expf"; 125 Names[RTLIB::EXP_F64] = "exp"; 126 Names[RTLIB::EXP_F80] = "expl"; 127 Names[RTLIB::EXP_PPCF128] = "expl"; 128 Names[RTLIB::EXP2_F32] = "exp2f"; 129 Names[RTLIB::EXP2_F64] = "exp2"; 130 Names[RTLIB::EXP2_F80] = "exp2l"; 131 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 132 Names[RTLIB::SIN_F32] = "sinf"; 133 Names[RTLIB::SIN_F64] = "sin"; 134 Names[RTLIB::SIN_F80] = "sinl"; 135 Names[RTLIB::SIN_PPCF128] = "sinl"; 136 Names[RTLIB::COS_F32] = "cosf"; 137 Names[RTLIB::COS_F64] = "cos"; 138 Names[RTLIB::COS_F80] = "cosl"; 139 Names[RTLIB::COS_PPCF128] = "cosl"; 140 Names[RTLIB::POW_F32] = "powf"; 141 Names[RTLIB::POW_F64] = "pow"; 142 Names[RTLIB::POW_F80] = "powl"; 143 Names[RTLIB::POW_PPCF128] = "powl"; 144 Names[RTLIB::CEIL_F32] = "ceilf"; 145 Names[RTLIB::CEIL_F64] = "ceil"; 146 Names[RTLIB::CEIL_F80] = "ceill"; 147 Names[RTLIB::CEIL_PPCF128] = "ceill"; 148 Names[RTLIB::TRUNC_F32] = "truncf"; 149 Names[RTLIB::TRUNC_F64] = "trunc"; 150 Names[RTLIB::TRUNC_F80] = "truncl"; 151 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 152 Names[RTLIB::RINT_F32] = "rintf"; 153 Names[RTLIB::RINT_F64] = "rint"; 154 Names[RTLIB::RINT_F80] = "rintl"; 155 Names[RTLIB::RINT_PPCF128] = "rintl"; 156 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 157 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 158 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 159 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 160 Names[RTLIB::FLOOR_F32] = "floorf"; 161 Names[RTLIB::FLOOR_F64] = "floor"; 162 Names[RTLIB::FLOOR_F80] = "floorl"; 163 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 164 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 165 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 166 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 167 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 168 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 169 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 170 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 171 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 172 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 173 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 174 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 175 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 176 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 177 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 178 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 179 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 180 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 181 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 182 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 183 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 184 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 185 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 186 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 187 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 188 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 189 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 190 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 191 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 192 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 193 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 194 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 195 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 196 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 197 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 198 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 199 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 200 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 201 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 202 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 203 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 204 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 205 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 206 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 207 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 208 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 209 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 210 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 211 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 212 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 213 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 214 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 215 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 216 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 217 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 218 Names[RTLIB::OEQ_F32] = "__eqsf2"; 219 Names[RTLIB::OEQ_F64] = "__eqdf2"; 220 Names[RTLIB::UNE_F32] = "__nesf2"; 221 Names[RTLIB::UNE_F64] = "__nedf2"; 222 Names[RTLIB::OGE_F32] = "__gesf2"; 223 Names[RTLIB::OGE_F64] = "__gedf2"; 224 Names[RTLIB::OLT_F32] = "__ltsf2"; 225 Names[RTLIB::OLT_F64] = "__ltdf2"; 226 Names[RTLIB::OLE_F32] = "__lesf2"; 227 Names[RTLIB::OLE_F64] = "__ledf2"; 228 Names[RTLIB::OGT_F32] = "__gtsf2"; 229 Names[RTLIB::OGT_F64] = "__gtdf2"; 230 Names[RTLIB::UO_F32] = "__unordsf2"; 231 Names[RTLIB::UO_F64] = "__unorddf2"; 232 Names[RTLIB::O_F32] = "__unordsf2"; 233 Names[RTLIB::O_F64] = "__unorddf2"; 234} 235 236/// getFPEXT - Return the FPEXT_*_* value for the given types, or 237/// UNKNOWN_LIBCALL if there is none. 238RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 239 if (OpVT == MVT::f32) { 240 if (RetVT == MVT::f64) 241 return FPEXT_F32_F64; 242 } 243 return UNKNOWN_LIBCALL; 244} 245 246/// getFPROUND - Return the FPROUND_*_* value for the given types, or 247/// UNKNOWN_LIBCALL if there is none. 248RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 249 if (RetVT == MVT::f32) { 250 if (OpVT == MVT::f64) 251 return FPROUND_F64_F32; 252 if (OpVT == MVT::f80) 253 return FPROUND_F80_F32; 254 if (OpVT == MVT::ppcf128) 255 return FPROUND_PPCF128_F32; 256 } else if (RetVT == MVT::f64) { 257 if (OpVT == MVT::f80) 258 return FPROUND_F80_F64; 259 if (OpVT == MVT::ppcf128) 260 return FPROUND_PPCF128_F64; 261 } 262 return UNKNOWN_LIBCALL; 263} 264 265/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 266/// UNKNOWN_LIBCALL if there is none. 267RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 268 if (OpVT == MVT::f32) { 269 if (RetVT == MVT::i32) 270 return FPTOSINT_F32_I32; 271 if (RetVT == MVT::i64) 272 return FPTOSINT_F32_I64; 273 if (RetVT == MVT::i128) 274 return FPTOSINT_F32_I128; 275 } else if (OpVT == MVT::f64) { 276 if (RetVT == MVT::i32) 277 return FPTOSINT_F64_I32; 278 if (RetVT == MVT::i64) 279 return FPTOSINT_F64_I64; 280 if (RetVT == MVT::i128) 281 return FPTOSINT_F64_I128; 282 } else if (OpVT == MVT::f80) { 283 if (RetVT == MVT::i32) 284 return FPTOSINT_F80_I32; 285 if (RetVT == MVT::i64) 286 return FPTOSINT_F80_I64; 287 if (RetVT == MVT::i128) 288 return FPTOSINT_F80_I128; 289 } else if (OpVT == MVT::ppcf128) { 290 if (RetVT == MVT::i32) 291 return FPTOSINT_PPCF128_I32; 292 if (RetVT == MVT::i64) 293 return FPTOSINT_PPCF128_I64; 294 if (RetVT == MVT::i128) 295 return FPTOSINT_PPCF128_I128; 296 } 297 return UNKNOWN_LIBCALL; 298} 299 300/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 301/// UNKNOWN_LIBCALL if there is none. 302RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 303 if (OpVT == MVT::f32) { 304 if (RetVT == MVT::i32) 305 return FPTOUINT_F32_I32; 306 if (RetVT == MVT::i64) 307 return FPTOUINT_F32_I64; 308 if (RetVT == MVT::i128) 309 return FPTOUINT_F32_I128; 310 } else if (OpVT == MVT::f64) { 311 if (RetVT == MVT::i32) 312 return FPTOUINT_F64_I32; 313 if (RetVT == MVT::i64) 314 return FPTOUINT_F64_I64; 315 if (RetVT == MVT::i128) 316 return FPTOUINT_F64_I128; 317 } else if (OpVT == MVT::f80) { 318 if (RetVT == MVT::i32) 319 return FPTOUINT_F80_I32; 320 if (RetVT == MVT::i64) 321 return FPTOUINT_F80_I64; 322 if (RetVT == MVT::i128) 323 return FPTOUINT_F80_I128; 324 } else if (OpVT == MVT::ppcf128) { 325 if (RetVT == MVT::i32) 326 return FPTOUINT_PPCF128_I32; 327 if (RetVT == MVT::i64) 328 return FPTOUINT_PPCF128_I64; 329 if (RetVT == MVT::i128) 330 return FPTOUINT_PPCF128_I128; 331 } 332 return UNKNOWN_LIBCALL; 333} 334 335/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 336/// UNKNOWN_LIBCALL if there is none. 337RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 338 if (OpVT == MVT::i32) { 339 if (RetVT == MVT::f32) 340 return SINTTOFP_I32_F32; 341 else if (RetVT == MVT::f64) 342 return SINTTOFP_I32_F64; 343 else if (RetVT == MVT::f80) 344 return SINTTOFP_I32_F80; 345 else if (RetVT == MVT::ppcf128) 346 return SINTTOFP_I32_PPCF128; 347 } else if (OpVT == MVT::i64) { 348 if (RetVT == MVT::f32) 349 return SINTTOFP_I64_F32; 350 else if (RetVT == MVT::f64) 351 return SINTTOFP_I64_F64; 352 else if (RetVT == MVT::f80) 353 return SINTTOFP_I64_F80; 354 else if (RetVT == MVT::ppcf128) 355 return SINTTOFP_I64_PPCF128; 356 } else if (OpVT == MVT::i128) { 357 if (RetVT == MVT::f32) 358 return SINTTOFP_I128_F32; 359 else if (RetVT == MVT::f64) 360 return SINTTOFP_I128_F64; 361 else if (RetVT == MVT::f80) 362 return SINTTOFP_I128_F80; 363 else if (RetVT == MVT::ppcf128) 364 return SINTTOFP_I128_PPCF128; 365 } 366 return UNKNOWN_LIBCALL; 367} 368 369/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 370/// UNKNOWN_LIBCALL if there is none. 371RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 372 if (OpVT == MVT::i32) { 373 if (RetVT == MVT::f32) 374 return UINTTOFP_I32_F32; 375 else if (RetVT == MVT::f64) 376 return UINTTOFP_I32_F64; 377 else if (RetVT == MVT::f80) 378 return UINTTOFP_I32_F80; 379 else if (RetVT == MVT::ppcf128) 380 return UINTTOFP_I32_PPCF128; 381 } else if (OpVT == MVT::i64) { 382 if (RetVT == MVT::f32) 383 return UINTTOFP_I64_F32; 384 else if (RetVT == MVT::f64) 385 return UINTTOFP_I64_F64; 386 else if (RetVT == MVT::f80) 387 return UINTTOFP_I64_F80; 388 else if (RetVT == MVT::ppcf128) 389 return UINTTOFP_I64_PPCF128; 390 } else if (OpVT == MVT::i128) { 391 if (RetVT == MVT::f32) 392 return UINTTOFP_I128_F32; 393 else if (RetVT == MVT::f64) 394 return UINTTOFP_I128_F64; 395 else if (RetVT == MVT::f80) 396 return UINTTOFP_I128_F80; 397 else if (RetVT == MVT::ppcf128) 398 return UINTTOFP_I128_PPCF128; 399 } 400 return UNKNOWN_LIBCALL; 401} 402 403/// InitCmpLibcallCCs - Set default comparison libcall CC. 404/// 405static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 406 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 407 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 408 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 409 CCs[RTLIB::UNE_F32] = ISD::SETNE; 410 CCs[RTLIB::UNE_F64] = ISD::SETNE; 411 CCs[RTLIB::OGE_F32] = ISD::SETGE; 412 CCs[RTLIB::OGE_F64] = ISD::SETGE; 413 CCs[RTLIB::OLT_F32] = ISD::SETLT; 414 CCs[RTLIB::OLT_F64] = ISD::SETLT; 415 CCs[RTLIB::OLE_F32] = ISD::SETLE; 416 CCs[RTLIB::OLE_F64] = ISD::SETLE; 417 CCs[RTLIB::OGT_F32] = ISD::SETGT; 418 CCs[RTLIB::OGT_F64] = ISD::SETGT; 419 CCs[RTLIB::UO_F32] = ISD::SETNE; 420 CCs[RTLIB::UO_F64] = ISD::SETNE; 421 CCs[RTLIB::O_F32] = ISD::SETEQ; 422 CCs[RTLIB::O_F64] = ISD::SETEQ; 423} 424 425TargetLowering::TargetLowering(TargetMachine &tm) 426 : TM(tm), TD(TM.getTargetData()) { 427 // All operations default to being supported. 428 memset(OpActions, 0, sizeof(OpActions)); 429 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 430 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 431 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 432 memset(ConvertActions, 0, sizeof(ConvertActions)); 433 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 434 435 // Set default actions for various operations. 436 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 437 // Default all indexed load / store to expand. 438 for (unsigned IM = (unsigned)ISD::PRE_INC; 439 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 440 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 441 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 442 } 443 444 // These operations default to expand. 445 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 446 } 447 448 // Most targets ignore the @llvm.prefetch intrinsic. 449 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 450 451 // ConstantFP nodes default to expand. Targets can either change this to 452 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 453 // to optimize expansions for certain constants. 454 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 455 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 456 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 457 458 // These library functions default to expand. 459 setOperationAction(ISD::FLOG , MVT::f64, Expand); 460 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 461 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 462 setOperationAction(ISD::FEXP , MVT::f64, Expand); 463 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 464 setOperationAction(ISD::FLOG , MVT::f32, Expand); 465 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 466 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 467 setOperationAction(ISD::FEXP , MVT::f32, Expand); 468 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 469 470 // Default ISD::TRAP to expand (which turns it into abort). 471 setOperationAction(ISD::TRAP, MVT::Other, Expand); 472 473 IsLittleEndian = TD->isLittleEndian(); 474 UsesGlobalOffsetTable = false; 475 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 476 ShiftAmtHandling = Undefined; 477 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 478 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 479 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 480 allowUnalignedMemoryAccesses = false; 481 UseUnderscoreSetJmp = false; 482 UseUnderscoreLongJmp = false; 483 SelectIsExpensive = false; 484 IntDivIsCheap = false; 485 Pow2DivIsCheap = false; 486 StackPointerRegisterToSaveRestore = 0; 487 ExceptionPointerRegister = 0; 488 ExceptionSelectorRegister = 0; 489 BooleanContents = UndefinedBooleanContent; 490 SchedPreferenceInfo = SchedulingForLatency; 491 JumpBufSize = 0; 492 JumpBufAlignment = 0; 493 IfCvtBlockSizeLimit = 2; 494 IfCvtDupBlockSizeLimit = 0; 495 PrefLoopAlignment = 0; 496 497 InitLibcallNames(LibcallRoutineNames); 498 InitCmpLibcallCCs(CmpLibcallCCs); 499 500 // Tell Legalize whether the assembler supports DEBUG_LOC. 501 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 502 if (!TASM || !TASM->hasDotLocAndDotFile()) 503 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 504} 505 506TargetLowering::~TargetLowering() {} 507 508/// computeRegisterProperties - Once all of the register classes are added, 509/// this allows us to compute derived properties we expose. 510void TargetLowering::computeRegisterProperties() { 511 assert(MVT::LAST_VALUETYPE <= 32 && 512 "Too many value types for ValueTypeActions to hold!"); 513 514 // Everything defaults to needing one register. 515 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 516 NumRegistersForVT[i] = 1; 517 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 518 } 519 // ...except isVoid, which doesn't need any registers. 520 NumRegistersForVT[MVT::isVoid] = 0; 521 522 // Find the largest integer register class. 523 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 524 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 525 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 526 527 // Every integer value type larger than this largest register takes twice as 528 // many registers to represent as the previous ValueType. 529 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 530 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 531 if (!EVT.isInteger()) 532 break; 533 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 534 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 535 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 536 ValueTypeActions.setTypeAction(EVT, Expand); 537 } 538 539 // Inspect all of the ValueType's smaller than the largest integer 540 // register to see which ones need promotion. 541 unsigned LegalIntReg = LargestIntReg; 542 for (unsigned IntReg = LargestIntReg - 1; 543 IntReg >= (unsigned)MVT::i1; --IntReg) { 544 MVT IVT = (MVT::SimpleValueType)IntReg; 545 if (isTypeLegal(IVT)) { 546 LegalIntReg = IntReg; 547 } else { 548 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 549 (MVT::SimpleValueType)LegalIntReg; 550 ValueTypeActions.setTypeAction(IVT, Promote); 551 } 552 } 553 554 // ppcf128 type is really two f64's. 555 if (!isTypeLegal(MVT::ppcf128)) { 556 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 557 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 558 TransformToType[MVT::ppcf128] = MVT::f64; 559 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 560 } 561 562 // Decide how to handle f64. If the target does not have native f64 support, 563 // expand it to i64 and we will be generating soft float library calls. 564 if (!isTypeLegal(MVT::f64)) { 565 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 566 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 567 TransformToType[MVT::f64] = MVT::i64; 568 ValueTypeActions.setTypeAction(MVT::f64, Expand); 569 } 570 571 // Decide how to handle f32. If the target does not have native support for 572 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 573 if (!isTypeLegal(MVT::f32)) { 574 if (isTypeLegal(MVT::f64)) { 575 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 576 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 577 TransformToType[MVT::f32] = MVT::f64; 578 ValueTypeActions.setTypeAction(MVT::f32, Promote); 579 } else { 580 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 581 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 582 TransformToType[MVT::f32] = MVT::i32; 583 ValueTypeActions.setTypeAction(MVT::f32, Expand); 584 } 585 } 586 587 // Loop over all of the vector value types to see which need transformations. 588 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 589 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 590 MVT VT = (MVT::SimpleValueType)i; 591 if (!isTypeLegal(VT)) { 592 MVT IntermediateVT, RegisterVT; 593 unsigned NumIntermediates; 594 NumRegistersForVT[i] = 595 getVectorTypeBreakdown(VT, 596 IntermediateVT, NumIntermediates, 597 RegisterVT); 598 RegisterTypeForVT[i] = RegisterVT; 599 600 // Determine if there is a legal wider type. 601 bool IsLegalWiderType = false; 602 MVT EltVT = VT.getVectorElementType(); 603 unsigned NElts = VT.getVectorNumElements(); 604 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 605 MVT SVT = (MVT::SimpleValueType)nVT; 606 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 607 SVT.getVectorNumElements() > NElts) { 608 TransformToType[i] = SVT; 609 ValueTypeActions.setTypeAction(VT, Promote); 610 IsLegalWiderType = true; 611 break; 612 } 613 } 614 if (!IsLegalWiderType) { 615 MVT NVT = VT.getPow2VectorType(); 616 if (NVT == VT) { 617 // Type is already a power of 2. The default action is to split. 618 TransformToType[i] = MVT::Other; 619 ValueTypeActions.setTypeAction(VT, Expand); 620 } else { 621 TransformToType[i] = NVT; 622 ValueTypeActions.setTypeAction(VT, Promote); 623 } 624 } 625 } 626 } 627} 628 629const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 630 return NULL; 631} 632 633 634MVT TargetLowering::getSetCCResultType(MVT VT) const { 635 return getValueType(TD->getIntPtrType()); 636} 637 638 639/// getVectorTypeBreakdown - Vector types are broken down into some number of 640/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 641/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 642/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 643/// 644/// This method returns the number of registers needed, and the VT for each 645/// register. It also returns the VT and quantity of the intermediate values 646/// before they are promoted/expanded. 647/// 648unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 649 MVT &IntermediateVT, 650 unsigned &NumIntermediates, 651 MVT &RegisterVT) const { 652 // Figure out the right, legal destination reg to copy into. 653 unsigned NumElts = VT.getVectorNumElements(); 654 MVT EltTy = VT.getVectorElementType(); 655 656 unsigned NumVectorRegs = 1; 657 658 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 659 // could break down into LHS/RHS like LegalizeDAG does. 660 if (!isPowerOf2_32(NumElts)) { 661 NumVectorRegs = NumElts; 662 NumElts = 1; 663 } 664 665 // Divide the input until we get to a supported size. This will always 666 // end with a scalar if the target doesn't support vectors. 667 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 668 NumElts >>= 1; 669 NumVectorRegs <<= 1; 670 } 671 672 NumIntermediates = NumVectorRegs; 673 674 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 675 if (!isTypeLegal(NewVT)) 676 NewVT = EltTy; 677 IntermediateVT = NewVT; 678 679 MVT DestVT = getTypeToTransformTo(NewVT); 680 RegisterVT = DestVT; 681 if (DestVT.bitsLT(NewVT)) { 682 // Value is expanded, e.g. i64 -> i16. 683 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 684 } else { 685 // Otherwise, promotion or legal types use the same number of registers as 686 // the vector decimated to the appropriate level. 687 return NumVectorRegs; 688 } 689 690 return 1; 691} 692 693/// getWidenVectorType: given a vector type, returns the type to widen to 694/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 695/// If there is no vector type that we want to widen to, returns MVT::Other 696/// When and where to widen is target dependent based on the cost of 697/// scalarizing vs using the wider vector type. 698MVT TargetLowering::getWidenVectorType(MVT VT) const { 699 assert(VT.isVector()); 700 if (isTypeLegal(VT)) 701 return VT; 702 703 // Default is not to widen until moved to LegalizeTypes 704 return MVT::Other; 705} 706 707/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 708/// function arguments in the caller parameter area. This is the actual 709/// alignment, not its logarithm. 710unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 711 return TD->getCallFrameTypeAlignment(Ty); 712} 713 714SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 715 SelectionDAG &DAG) const { 716 if (usesGlobalOffsetTable()) 717 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 718 return Table; 719} 720 721bool 722TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 723 // Assume that everything is safe in static mode. 724 if (getTargetMachine().getRelocationModel() == Reloc::Static) 725 return true; 726 727 // In dynamic-no-pic mode, assume that known defined values are safe. 728 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 729 GA && 730 !GA->getGlobal()->isDeclaration() && 731 !GA->getGlobal()->mayBeOverridden()) 732 return true; 733 734 // Otherwise assume nothing is safe. 735 return false; 736} 737 738//===----------------------------------------------------------------------===// 739// Optimization Methods 740//===----------------------------------------------------------------------===// 741 742/// ShrinkDemandedConstant - Check to see if the specified operand of the 743/// specified instruction is a constant integer. If so, check to see if there 744/// are any bits set in the constant that are not demanded. If so, shrink the 745/// constant and return true. 746bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 747 const APInt &Demanded) { 748 DebugLoc dl = Op.getDebugLoc(); 749 // FIXME: ISD::SELECT, ISD::SELECT_CC 750 switch (Op.getOpcode()) { 751 default: break; 752 case ISD::AND: 753 case ISD::OR: 754 case ISD::XOR: 755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 756 if (C->getAPIntValue().intersects(~Demanded)) { 757 MVT VT = Op.getValueType(); 758 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 759 DAG.getConstant(Demanded & 760 C->getAPIntValue(), 761 VT)); 762 return CombineTo(Op, New); 763 } 764 break; 765 } 766 return false; 767} 768 769/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 770/// DemandedMask bits of the result of Op are ever used downstream. If we can 771/// use this information to simplify Op, create a new simplified DAG node and 772/// return true, returning the original and new nodes in Old and New. Otherwise, 773/// analyze the expression and return a mask of KnownOne and KnownZero bits for 774/// the expression (used to simplify the caller). The KnownZero/One bits may 775/// only be accurate for those bits in the DemandedMask. 776bool TargetLowering::SimplifyDemandedBits(SDValue Op, 777 const APInt &DemandedMask, 778 APInt &KnownZero, 779 APInt &KnownOne, 780 TargetLoweringOpt &TLO, 781 unsigned Depth) const { 782 unsigned BitWidth = DemandedMask.getBitWidth(); 783 assert(Op.getValueSizeInBits() == BitWidth && 784 "Mask size mismatches value type size!"); 785 APInt NewMask = DemandedMask; 786 DebugLoc dl = Op.getDebugLoc(); 787 788 // Don't know anything. 789 KnownZero = KnownOne = APInt(BitWidth, 0); 790 791 // Other users may use these bits. 792 if (!Op.getNode()->hasOneUse()) { 793 if (Depth != 0) { 794 // If not at the root, Just compute the KnownZero/KnownOne bits to 795 // simplify things downstream. 796 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 797 return false; 798 } 799 // If this is the root being simplified, allow it to have multiple uses, 800 // just set the NewMask to all bits. 801 NewMask = APInt::getAllOnesValue(BitWidth); 802 } else if (DemandedMask == 0) { 803 // Not demanding any bits from Op. 804 if (Op.getOpcode() != ISD::UNDEF) 805 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 806 return false; 807 } else if (Depth == 6) { // Limit search depth. 808 return false; 809 } 810 811 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 812 switch (Op.getOpcode()) { 813 case ISD::Constant: 814 // We know all of the bits for a constant! 815 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 816 KnownZero = ~KnownOne & NewMask; 817 return false; // Don't fall through, will infinitely loop. 818 case ISD::AND: 819 // If the RHS is a constant, check to see if the LHS would be zero without 820 // using the bits from the RHS. Below, we use knowledge about the RHS to 821 // simplify the LHS, here we're using information from the LHS to simplify 822 // the RHS. 823 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 824 APInt LHSZero, LHSOne; 825 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 826 LHSZero, LHSOne, Depth+1); 827 // If the LHS already has zeros where RHSC does, this and is dead. 828 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 829 return TLO.CombineTo(Op, Op.getOperand(0)); 830 // If any of the set bits in the RHS are known zero on the LHS, shrink 831 // the constant. 832 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 833 return true; 834 } 835 836 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 837 KnownOne, TLO, Depth+1)) 838 return true; 839 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 840 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 841 KnownZero2, KnownOne2, TLO, Depth+1)) 842 return true; 843 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 844 845 // If all of the demanded bits are known one on one side, return the other. 846 // These bits cannot contribute to the result of the 'and'. 847 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 848 return TLO.CombineTo(Op, Op.getOperand(0)); 849 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 850 return TLO.CombineTo(Op, Op.getOperand(1)); 851 // If all of the demanded bits in the inputs are known zeros, return zero. 852 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 853 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 854 // If the RHS is a constant, see if we can simplify it. 855 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 856 return true; 857 858 // Output known-1 bits are only known if set in both the LHS & RHS. 859 KnownOne &= KnownOne2; 860 // Output known-0 are known to be clear if zero in either the LHS | RHS. 861 KnownZero |= KnownZero2; 862 break; 863 case ISD::OR: 864 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 865 KnownOne, TLO, Depth+1)) 866 return true; 867 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 868 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 869 KnownZero2, KnownOne2, TLO, Depth+1)) 870 return true; 871 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 872 873 // If all of the demanded bits are known zero on one side, return the other. 874 // These bits cannot contribute to the result of the 'or'. 875 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 876 return TLO.CombineTo(Op, Op.getOperand(0)); 877 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 878 return TLO.CombineTo(Op, Op.getOperand(1)); 879 // If all of the potentially set bits on one side are known to be set on 880 // the other side, just use the 'other' side. 881 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 882 return TLO.CombineTo(Op, Op.getOperand(0)); 883 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 884 return TLO.CombineTo(Op, Op.getOperand(1)); 885 // If the RHS is a constant, see if we can simplify it. 886 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 887 return true; 888 889 // Output known-0 bits are only known if clear in both the LHS & RHS. 890 KnownZero &= KnownZero2; 891 // Output known-1 are known to be set if set in either the LHS | RHS. 892 KnownOne |= KnownOne2; 893 break; 894 case ISD::XOR: 895 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 896 KnownOne, TLO, Depth+1)) 897 return true; 898 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 899 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 900 KnownOne2, TLO, Depth+1)) 901 return true; 902 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 903 904 // If all of the demanded bits are known zero on one side, return the other. 905 // These bits cannot contribute to the result of the 'xor'. 906 if ((KnownZero & NewMask) == NewMask) 907 return TLO.CombineTo(Op, Op.getOperand(0)); 908 if ((KnownZero2 & NewMask) == NewMask) 909 return TLO.CombineTo(Op, Op.getOperand(1)); 910 911 // If all of the unknown bits are known to be zero on one side or the other 912 // (but not both) turn this into an *inclusive* or. 913 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 914 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 915 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 916 Op.getOperand(0), 917 Op.getOperand(1))); 918 919 // Output known-0 bits are known if clear or set in both the LHS & RHS. 920 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 921 // Output known-1 are known to be set if set in only one of the LHS, RHS. 922 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 923 924 // If all of the demanded bits on one side are known, and all of the set 925 // bits on that side are also known to be set on the other side, turn this 926 // into an AND, as we know the bits will be cleared. 927 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 928 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 929 if ((KnownOne & KnownOne2) == KnownOne) { 930 MVT VT = Op.getValueType(); 931 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 932 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 933 Op.getOperand(0), ANDC)); 934 } 935 } 936 937 // If the RHS is a constant, see if we can simplify it. 938 // for XOR, we prefer to force bits to 1 if they will make a -1. 939 // if we can't force bits, try to shrink constant 940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 941 APInt Expanded = C->getAPIntValue() | (~NewMask); 942 // if we can expand it to have all bits set, do it 943 if (Expanded.isAllOnesValue()) { 944 if (Expanded != C->getAPIntValue()) { 945 MVT VT = Op.getValueType(); 946 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 947 TLO.DAG.getConstant(Expanded, VT)); 948 return TLO.CombineTo(Op, New); 949 } 950 // if it already has all the bits set, nothing to change 951 // but don't shrink either! 952 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 953 return true; 954 } 955 } 956 957 KnownZero = KnownZeroOut; 958 KnownOne = KnownOneOut; 959 break; 960 case ISD::SELECT: 961 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 962 KnownOne, TLO, Depth+1)) 963 return true; 964 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 965 KnownOne2, TLO, Depth+1)) 966 return true; 967 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 968 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 969 970 // If the operands are constants, see if we can simplify them. 971 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 972 return true; 973 974 // Only known if known in both the LHS and RHS. 975 KnownOne &= KnownOne2; 976 KnownZero &= KnownZero2; 977 break; 978 case ISD::SELECT_CC: 979 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 980 KnownOne, TLO, Depth+1)) 981 return true; 982 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 983 KnownOne2, TLO, Depth+1)) 984 return true; 985 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 986 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 987 988 // If the operands are constants, see if we can simplify them. 989 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 990 return true; 991 992 // Only known if known in both the LHS and RHS. 993 KnownOne &= KnownOne2; 994 KnownZero &= KnownZero2; 995 break; 996 case ISD::SHL: 997 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 998 unsigned ShAmt = SA->getZExtValue(); 999 SDValue InOp = Op.getOperand(0); 1000 1001 // If the shift count is an invalid immediate, don't do anything. 1002 if (ShAmt >= BitWidth) 1003 break; 1004 1005 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1006 // single shift. We can do this if the bottom bits (which are shifted 1007 // out) are never demanded. 1008 if (InOp.getOpcode() == ISD::SRL && 1009 isa<ConstantSDNode>(InOp.getOperand(1))) { 1010 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1011 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1012 unsigned Opc = ISD::SHL; 1013 int Diff = ShAmt-C1; 1014 if (Diff < 0) { 1015 Diff = -Diff; 1016 Opc = ISD::SRL; 1017 } 1018 1019 SDValue NewSA = 1020 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1021 MVT VT = Op.getValueType(); 1022 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1023 InOp.getOperand(0), NewSA)); 1024 } 1025 } 1026 1027 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1028 KnownZero, KnownOne, TLO, Depth+1)) 1029 return true; 1030 KnownZero <<= SA->getZExtValue(); 1031 KnownOne <<= SA->getZExtValue(); 1032 // low bits known zero. 1033 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1034 } 1035 break; 1036 case ISD::SRL: 1037 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1038 MVT VT = Op.getValueType(); 1039 unsigned ShAmt = SA->getZExtValue(); 1040 unsigned VTSize = VT.getSizeInBits(); 1041 SDValue InOp = Op.getOperand(0); 1042 1043 // If the shift count is an invalid immediate, don't do anything. 1044 if (ShAmt >= BitWidth) 1045 break; 1046 1047 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1048 // single shift. We can do this if the top bits (which are shifted out) 1049 // are never demanded. 1050 if (InOp.getOpcode() == ISD::SHL && 1051 isa<ConstantSDNode>(InOp.getOperand(1))) { 1052 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1053 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1054 unsigned Opc = ISD::SRL; 1055 int Diff = ShAmt-C1; 1056 if (Diff < 0) { 1057 Diff = -Diff; 1058 Opc = ISD::SHL; 1059 } 1060 1061 SDValue NewSA = 1062 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1063 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1064 InOp.getOperand(0), NewSA)); 1065 } 1066 } 1067 1068 // Compute the new bits that are at the top now. 1069 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1070 KnownZero, KnownOne, TLO, Depth+1)) 1071 return true; 1072 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1073 KnownZero = KnownZero.lshr(ShAmt); 1074 KnownOne = KnownOne.lshr(ShAmt); 1075 1076 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1077 KnownZero |= HighBits; // High bits known zero. 1078 } 1079 break; 1080 case ISD::SRA: 1081 // If this is an arithmetic shift right and only the low-bit is set, we can 1082 // always convert this into a logical shr, even if the shift amount is 1083 // variable. The low bit of the shift cannot be an input sign bit unless 1084 // the shift amount is >= the size of the datatype, which is undefined. 1085 if (DemandedMask == 1) 1086 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1087 Op.getOperand(0), Op.getOperand(1))); 1088 1089 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1090 MVT VT = Op.getValueType(); 1091 unsigned ShAmt = SA->getZExtValue(); 1092 1093 // If the shift count is an invalid immediate, don't do anything. 1094 if (ShAmt >= BitWidth) 1095 break; 1096 1097 APInt InDemandedMask = (NewMask << ShAmt); 1098 1099 // If any of the demanded bits are produced by the sign extension, we also 1100 // demand the input sign bit. 1101 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1102 if (HighBits.intersects(NewMask)) 1103 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1104 1105 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1106 KnownZero, KnownOne, TLO, Depth+1)) 1107 return true; 1108 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1109 KnownZero = KnownZero.lshr(ShAmt); 1110 KnownOne = KnownOne.lshr(ShAmt); 1111 1112 // Handle the sign bit, adjusted to where it is now in the mask. 1113 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1114 1115 // If the input sign bit is known to be zero, or if none of the top bits 1116 // are demanded, turn this into an unsigned shift right. 1117 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1118 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1119 Op.getOperand(0), 1120 Op.getOperand(1))); 1121 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1122 KnownOne |= HighBits; 1123 } 1124 } 1125 break; 1126 case ISD::SIGN_EXTEND_INREG: { 1127 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1128 1129 // Sign extension. Compute the demanded bits in the result that are not 1130 // present in the input. 1131 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1132 BitWidth - EVT.getSizeInBits()) & 1133 NewMask; 1134 1135 // If none of the extended bits are demanded, eliminate the sextinreg. 1136 if (NewBits == 0) 1137 return TLO.CombineTo(Op, Op.getOperand(0)); 1138 1139 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1140 InSignBit.zext(BitWidth); 1141 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1142 EVT.getSizeInBits()) & 1143 NewMask; 1144 1145 // Since the sign extended bits are demanded, we know that the sign 1146 // bit is demanded. 1147 InputDemandedBits |= InSignBit; 1148 1149 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1150 KnownZero, KnownOne, TLO, Depth+1)) 1151 return true; 1152 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1153 1154 // If the sign bit of the input is known set or clear, then we know the 1155 // top bits of the result. 1156 1157 // If the input sign bit is known zero, convert this into a zero extension. 1158 if (KnownZero.intersects(InSignBit)) 1159 return TLO.CombineTo(Op, 1160 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1161 1162 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1163 KnownOne |= NewBits; 1164 KnownZero &= ~NewBits; 1165 } else { // Input sign bit unknown 1166 KnownZero &= ~NewBits; 1167 KnownOne &= ~NewBits; 1168 } 1169 break; 1170 } 1171 case ISD::ZERO_EXTEND: { 1172 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1173 APInt InMask = NewMask; 1174 InMask.trunc(OperandBitWidth); 1175 1176 // If none of the top bits are demanded, convert this into an any_extend. 1177 APInt NewBits = 1178 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1179 if (!NewBits.intersects(NewMask)) 1180 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1181 Op.getValueType(), 1182 Op.getOperand(0))); 1183 1184 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1185 KnownZero, KnownOne, TLO, Depth+1)) 1186 return true; 1187 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1188 KnownZero.zext(BitWidth); 1189 KnownOne.zext(BitWidth); 1190 KnownZero |= NewBits; 1191 break; 1192 } 1193 case ISD::SIGN_EXTEND: { 1194 MVT InVT = Op.getOperand(0).getValueType(); 1195 unsigned InBits = InVT.getSizeInBits(); 1196 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1197 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1198 APInt NewBits = ~InMask & NewMask; 1199 1200 // If none of the top bits are demanded, convert this into an any_extend. 1201 if (NewBits == 0) 1202 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1203 Op.getValueType(), 1204 Op.getOperand(0))); 1205 1206 // Since some of the sign extended bits are demanded, we know that the sign 1207 // bit is demanded. 1208 APInt InDemandedBits = InMask & NewMask; 1209 InDemandedBits |= InSignBit; 1210 InDemandedBits.trunc(InBits); 1211 1212 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1213 KnownOne, TLO, Depth+1)) 1214 return true; 1215 KnownZero.zext(BitWidth); 1216 KnownOne.zext(BitWidth); 1217 1218 // If the sign bit is known zero, convert this to a zero extend. 1219 if (KnownZero.intersects(InSignBit)) 1220 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1221 Op.getValueType(), 1222 Op.getOperand(0))); 1223 1224 // If the sign bit is known one, the top bits match. 1225 if (KnownOne.intersects(InSignBit)) { 1226 KnownOne |= NewBits; 1227 KnownZero &= ~NewBits; 1228 } else { // Otherwise, top bits aren't known. 1229 KnownOne &= ~NewBits; 1230 KnownZero &= ~NewBits; 1231 } 1232 break; 1233 } 1234 case ISD::ANY_EXTEND: { 1235 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1236 APInt InMask = NewMask; 1237 InMask.trunc(OperandBitWidth); 1238 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1239 KnownZero, KnownOne, TLO, Depth+1)) 1240 return true; 1241 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1242 KnownZero.zext(BitWidth); 1243 KnownOne.zext(BitWidth); 1244 break; 1245 } 1246 case ISD::TRUNCATE: { 1247 // Simplify the input, using demanded bit information, and compute the known 1248 // zero/one bits live out. 1249 APInt TruncMask = NewMask; 1250 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1251 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1252 KnownZero, KnownOne, TLO, Depth+1)) 1253 return true; 1254 KnownZero.trunc(BitWidth); 1255 KnownOne.trunc(BitWidth); 1256 1257 // If the input is only used by this truncate, see if we can shrink it based 1258 // on the known demanded bits. 1259 if (Op.getOperand(0).getNode()->hasOneUse()) { 1260 SDValue In = Op.getOperand(0); 1261 unsigned InBitWidth = In.getValueSizeInBits(); 1262 switch (In.getOpcode()) { 1263 default: break; 1264 case ISD::SRL: 1265 // Shrink SRL by a constant if none of the high bits shifted in are 1266 // demanded. 1267 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1268 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1269 InBitWidth - BitWidth); 1270 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1271 HighBits.trunc(BitWidth); 1272 1273 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1274 // None of the shifted in bits are needed. Add a truncate of the 1275 // shift input, then shift it. 1276 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1277 Op.getValueType(), 1278 In.getOperand(0)); 1279 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1280 Op.getValueType(), 1281 NewTrunc, 1282 In.getOperand(1))); 1283 } 1284 } 1285 break; 1286 } 1287 } 1288 1289 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1290 break; 1291 } 1292 case ISD::AssertZext: { 1293 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1294 APInt InMask = APInt::getLowBitsSet(BitWidth, 1295 VT.getSizeInBits()); 1296 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1297 KnownZero, KnownOne, TLO, Depth+1)) 1298 return true; 1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1300 KnownZero |= ~InMask & NewMask; 1301 break; 1302 } 1303 case ISD::BIT_CONVERT: 1304#if 0 1305 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1306 // is demanded, turn this into a FGETSIGN. 1307 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1308 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1309 !MVT::isVector(Op.getOperand(0).getValueType())) { 1310 // Only do this xform if FGETSIGN is valid or if before legalize. 1311 if (!TLO.AfterLegalize || 1312 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1313 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1314 // place. We expect the SHL to be eliminated by other optimizations. 1315 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1316 Op.getOperand(0)); 1317 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1318 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1319 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1320 Sign, ShAmt)); 1321 } 1322 } 1323#endif 1324 break; 1325 default: 1326 // Just use ComputeMaskedBits to compute output bits. 1327 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1328 break; 1329 } 1330 1331 // If we know the value of all of the demanded bits, return this as a 1332 // constant. 1333 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1334 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1335 1336 return false; 1337} 1338 1339/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1340/// in Mask are known to be either zero or one and return them in the 1341/// KnownZero/KnownOne bitsets. 1342void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1343 const APInt &Mask, 1344 APInt &KnownZero, 1345 APInt &KnownOne, 1346 const SelectionDAG &DAG, 1347 unsigned Depth) const { 1348 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1349 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1350 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1351 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1352 "Should use MaskedValueIsZero if you don't know whether Op" 1353 " is a target node!"); 1354 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1355} 1356 1357/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1358/// targets that want to expose additional information about sign bits to the 1359/// DAG Combiner. 1360unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1361 unsigned Depth) const { 1362 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1363 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1364 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1365 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1366 "Should use ComputeNumSignBits if you don't know whether Op" 1367 " is a target node!"); 1368 return 1; 1369} 1370 1371/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1372/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1373/// determine which bit is set. 1374/// 1375static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1376 // A left-shift of a constant one will have exactly one bit set, because 1377 // shifting the bit off the end is undefined. 1378 if (Val.getOpcode() == ISD::SHL) 1379 if (ConstantSDNode *C = 1380 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1381 if (C->getAPIntValue() == 1) 1382 return true; 1383 1384 // Similarly, a right-shift of a constant sign-bit will have exactly 1385 // one bit set. 1386 if (Val.getOpcode() == ISD::SRL) 1387 if (ConstantSDNode *C = 1388 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1389 if (C->getAPIntValue().isSignBit()) 1390 return true; 1391 1392 // More could be done here, though the above checks are enough 1393 // to handle some common cases. 1394 1395 // Fall back to ComputeMaskedBits to catch other known cases. 1396 MVT OpVT = Val.getValueType(); 1397 unsigned BitWidth = OpVT.getSizeInBits(); 1398 APInt Mask = APInt::getAllOnesValue(BitWidth); 1399 APInt KnownZero, KnownOne; 1400 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1401 return (KnownZero.countPopulation() == BitWidth - 1) && 1402 (KnownOne.countPopulation() == 1); 1403} 1404 1405/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1406/// and cc. If it is unable to simplify it, return a null SDValue. 1407SDValue 1408TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1409 ISD::CondCode Cond, bool foldBooleans, 1410 DAGCombinerInfo &DCI, DebugLoc dl) const { 1411 SelectionDAG &DAG = DCI.DAG; 1412 1413 // These setcc operations always fold. 1414 switch (Cond) { 1415 default: break; 1416 case ISD::SETFALSE: 1417 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1418 case ISD::SETTRUE: 1419 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1420 } 1421 1422 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1423 const APInt &C1 = N1C->getAPIntValue(); 1424 if (isa<ConstantSDNode>(N0.getNode())) { 1425 return DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1426 } else { 1427 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1428 // equality comparison, then we're just comparing whether X itself is 1429 // zero. 1430 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1431 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1432 N0.getOperand(1).getOpcode() == ISD::Constant) { 1433 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1434 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1435 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1436 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1437 // (srl (ctlz x), 5) == 0 -> X != 0 1438 // (srl (ctlz x), 5) != 1 -> X != 0 1439 Cond = ISD::SETNE; 1440 } else { 1441 // (srl (ctlz x), 5) != 0 -> X == 0 1442 // (srl (ctlz x), 5) == 1 -> X == 0 1443 Cond = ISD::SETEQ; 1444 } 1445 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1446 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1447 Zero, Cond); 1448 } 1449 } 1450 1451 // If the LHS is '(and load, const)', the RHS is 0, 1452 // the test is for equality or unsigned, and all 1 bits of the const are 1453 // in the same partial word, see if we can shorten the load. 1454 if (DCI.isBeforeLegalize() && 1455 N0.getOpcode() == ISD::AND && C1 == 0 && 1456 isa<LoadSDNode>(N0.getOperand(0)) && 1457 N0.getOperand(0).getNode()->hasOneUse() && 1458 isa<ConstantSDNode>(N0.getOperand(1))) { 1459 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1460 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1461 uint64_t bestMask = 0; 1462 unsigned bestWidth = 0, bestOffset = 0; 1463 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1464 unsigned origWidth = N0.getValueType().getSizeInBits(); 1465 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1466 // 8 bits, but have to be careful... 1467 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1468 origWidth = Lod->getMemoryVT().getSizeInBits(); 1469 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1470 uint64_t newMask = (1ULL << width) - 1; 1471 for (unsigned offset=0; offset<origWidth/width; offset++) { 1472 if ((newMask & Mask)==Mask) { 1473 if (!TD->isLittleEndian()) 1474 bestOffset = (origWidth/width - offset - 1) * (width/8); 1475 else 1476 bestOffset = (uint64_t)offset * (width/8); 1477 bestMask = Mask >> (offset * (width/8) * 8); 1478 bestWidth = width; 1479 break; 1480 } 1481 newMask = newMask << width; 1482 } 1483 } 1484 } 1485 if (bestWidth) { 1486 MVT newVT = MVT::getIntegerVT(bestWidth); 1487 if (newVT.isRound()) { 1488 MVT PtrType = Lod->getOperand(1).getValueType(); 1489 SDValue Ptr = Lod->getBasePtr(); 1490 if (bestOffset != 0) 1491 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1492 DAG.getConstant(bestOffset, PtrType)); 1493 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1494 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1495 Lod->getSrcValue(), 1496 Lod->getSrcValueOffset() + bestOffset, 1497 false, NewAlign); 1498 return DAG.getSetCC(dl, VT, 1499 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1500 DAG.getConstant(bestMask, newVT)), 1501 DAG.getConstant(0LL, newVT), Cond); 1502 } 1503 } 1504 } 1505 1506 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1507 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1508 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1509 1510 // If the comparison constant has bits in the upper part, the 1511 // zero-extended value could never match. 1512 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1513 C1.getBitWidth() - InSize))) { 1514 switch (Cond) { 1515 case ISD::SETUGT: 1516 case ISD::SETUGE: 1517 case ISD::SETEQ: return DAG.getConstant(0, VT); 1518 case ISD::SETULT: 1519 case ISD::SETULE: 1520 case ISD::SETNE: return DAG.getConstant(1, VT); 1521 case ISD::SETGT: 1522 case ISD::SETGE: 1523 // True if the sign bit of C1 is set. 1524 return DAG.getConstant(C1.isNegative(), VT); 1525 case ISD::SETLT: 1526 case ISD::SETLE: 1527 // True if the sign bit of C1 isn't set. 1528 return DAG.getConstant(C1.isNonNegative(), VT); 1529 default: 1530 break; 1531 } 1532 } 1533 1534 // Otherwise, we can perform the comparison with the low bits. 1535 switch (Cond) { 1536 case ISD::SETEQ: 1537 case ISD::SETNE: 1538 case ISD::SETUGT: 1539 case ISD::SETUGE: 1540 case ISD::SETULT: 1541 case ISD::SETULE: 1542 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1543 DAG.getConstant(APInt(C1).trunc(InSize), 1544 N0.getOperand(0).getValueType()), 1545 Cond); 1546 default: 1547 break; // todo, be more careful with signed comparisons 1548 } 1549 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1550 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1551 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1552 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1553 MVT ExtDstTy = N0.getValueType(); 1554 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1555 1556 // If the extended part has any inconsistent bits, it cannot ever 1557 // compare equal. In other words, they have to be all ones or all 1558 // zeros. 1559 APInt ExtBits = 1560 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1561 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1562 return DAG.getConstant(Cond == ISD::SETNE, VT); 1563 1564 SDValue ZextOp; 1565 MVT Op0Ty = N0.getOperand(0).getValueType(); 1566 if (Op0Ty == ExtSrcTy) { 1567 ZextOp = N0.getOperand(0); 1568 } else { 1569 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1570 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1571 DAG.getConstant(Imm, Op0Ty)); 1572 } 1573 if (!DCI.isCalledByLegalizer()) 1574 DCI.AddToWorklist(ZextOp.getNode()); 1575 // Otherwise, make this a use of a zext. 1576 return DAG.getSetCC(dl, VT, ZextOp, 1577 DAG.getConstant(C1 & APInt::getLowBitsSet( 1578 ExtDstTyBits, 1579 ExtSrcTyBits), 1580 ExtDstTy), 1581 Cond); 1582 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1583 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1584 1585 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1586 if (N0.getOpcode() == ISD::SETCC) { 1587 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1588 if (TrueWhenTrue) 1589 return N0; 1590 1591 // Invert the condition. 1592 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1593 CC = ISD::getSetCCInverse(CC, 1594 N0.getOperand(0).getValueType().isInteger()); 1595 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1596 } 1597 1598 if ((N0.getOpcode() == ISD::XOR || 1599 (N0.getOpcode() == ISD::AND && 1600 N0.getOperand(0).getOpcode() == ISD::XOR && 1601 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1602 isa<ConstantSDNode>(N0.getOperand(1)) && 1603 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1604 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1605 // can only do this if the top bits are known zero. 1606 unsigned BitWidth = N0.getValueSizeInBits(); 1607 if (DAG.MaskedValueIsZero(N0, 1608 APInt::getHighBitsSet(BitWidth, 1609 BitWidth-1))) { 1610 // Okay, get the un-inverted input value. 1611 SDValue Val; 1612 if (N0.getOpcode() == ISD::XOR) 1613 Val = N0.getOperand(0); 1614 else { 1615 assert(N0.getOpcode() == ISD::AND && 1616 N0.getOperand(0).getOpcode() == ISD::XOR); 1617 // ((X^1)&1)^1 -> X & 1 1618 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1619 N0.getOperand(0).getOperand(0), 1620 N0.getOperand(1)); 1621 } 1622 return DAG.getSetCC(dl, VT, Val, N1, 1623 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1624 } 1625 } 1626 } 1627 1628 APInt MinVal, MaxVal; 1629 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1630 if (ISD::isSignedIntSetCC(Cond)) { 1631 MinVal = APInt::getSignedMinValue(OperandBitSize); 1632 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1633 } else { 1634 MinVal = APInt::getMinValue(OperandBitSize); 1635 MaxVal = APInt::getMaxValue(OperandBitSize); 1636 } 1637 1638 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1639 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1640 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1641 // X >= C0 --> X > (C0-1) 1642 return DAG.getSetCC(dl, VT, N0, 1643 DAG.getConstant(C1-1, N1.getValueType()), 1644 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1645 } 1646 1647 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1648 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1649 // X <= C0 --> X < (C0+1) 1650 return DAG.getSetCC(dl, VT, N0, 1651 DAG.getConstant(C1+1, N1.getValueType()), 1652 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1653 } 1654 1655 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1656 return DAG.getConstant(0, VT); // X < MIN --> false 1657 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1658 return DAG.getConstant(1, VT); // X >= MIN --> true 1659 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1660 return DAG.getConstant(0, VT); // X > MAX --> false 1661 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1662 return DAG.getConstant(1, VT); // X <= MAX --> true 1663 1664 // Canonicalize setgt X, Min --> setne X, Min 1665 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1666 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1667 // Canonicalize setlt X, Max --> setne X, Max 1668 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1669 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1670 1671 // If we have setult X, 1, turn it into seteq X, 0 1672 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1673 return DAG.getSetCC(dl, VT, N0, 1674 DAG.getConstant(MinVal, N0.getValueType()), 1675 ISD::SETEQ); 1676 // If we have setugt X, Max-1, turn it into seteq X, Max 1677 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1678 return DAG.getSetCC(dl, VT, N0, 1679 DAG.getConstant(MaxVal, N0.getValueType()), 1680 ISD::SETEQ); 1681 1682 // If we have "setcc X, C0", check to see if we can shrink the immediate 1683 // by changing cc. 1684 1685 // SETUGT X, SINTMAX -> SETLT X, 0 1686 if (Cond == ISD::SETUGT && 1687 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1688 return DAG.getSetCC(dl, VT, N0, 1689 DAG.getConstant(0, N1.getValueType()), 1690 ISD::SETLT); 1691 1692 // SETULT X, SINTMIN -> SETGT X, -1 1693 if (Cond == ISD::SETULT && 1694 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1695 SDValue ConstMinusOne = 1696 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1697 N1.getValueType()); 1698 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1699 } 1700 1701 // Fold bit comparisons when we can. 1702 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1703 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1704 if (ConstantSDNode *AndRHS = 1705 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1706 MVT ShiftTy = DCI.isBeforeLegalize() ? 1707 getPointerTy() : getShiftAmountTy(); 1708 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1709 // Perform the xform if the AND RHS is a single bit. 1710 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1711 return DAG.getNode(ISD::SRL, dl, VT, N0, 1712 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1713 ShiftTy)); 1714 } 1715 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1716 // (X & 8) == 8 --> (X & 8) >> 3 1717 // Perform the xform if C1 is a single bit. 1718 if (C1.isPowerOf2()) { 1719 return DAG.getNode(ISD::SRL, dl, VT, N0, 1720 DAG.getConstant(C1.logBase2(), ShiftTy)); 1721 } 1722 } 1723 } 1724 } 1725 } else if (isa<ConstantSDNode>(N0.getNode())) { 1726 // Ensure that the constant occurs on the RHS. 1727 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1728 } 1729 1730 if (isa<ConstantFPSDNode>(N0.getNode())) { 1731 // Constant fold or commute setcc. 1732 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1733 if (O.getNode()) return O; 1734 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1735 // If the RHS of an FP comparison is a constant, simplify it away in 1736 // some cases. 1737 if (CFP->getValueAPF().isNaN()) { 1738 // If an operand is known to be a nan, we can fold it. 1739 switch (ISD::getUnorderedFlavor(Cond)) { 1740 default: assert(0 && "Unknown flavor!"); 1741 case 0: // Known false. 1742 return DAG.getConstant(0, VT); 1743 case 1: // Known true. 1744 return DAG.getConstant(1, VT); 1745 case 2: // Undefined. 1746 return DAG.getUNDEF(VT); 1747 } 1748 } 1749 1750 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1751 // constant if knowing that the operand is non-nan is enough. We prefer to 1752 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1753 // materialize 0.0. 1754 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1755 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1756 } 1757 1758 if (N0 == N1) { 1759 // We can always fold X == X for integer setcc's. 1760 if (N0.getValueType().isInteger()) 1761 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1762 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1763 if (UOF == 2) // FP operators that are undefined on NaNs. 1764 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1765 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1766 return DAG.getConstant(UOF, VT); 1767 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1768 // if it is not already. 1769 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1770 if (NewCond != Cond) 1771 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1772 } 1773 1774 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1775 N0.getValueType().isInteger()) { 1776 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1777 N0.getOpcode() == ISD::XOR) { 1778 // Simplify (X+Y) == (X+Z) --> Y == Z 1779 if (N0.getOpcode() == N1.getOpcode()) { 1780 if (N0.getOperand(0) == N1.getOperand(0)) 1781 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1782 if (N0.getOperand(1) == N1.getOperand(1)) 1783 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1784 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1785 // If X op Y == Y op X, try other combinations. 1786 if (N0.getOperand(0) == N1.getOperand(1)) 1787 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1788 Cond); 1789 if (N0.getOperand(1) == N1.getOperand(0)) 1790 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1791 Cond); 1792 } 1793 } 1794 1795 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1796 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1797 // Turn (X+C1) == C2 --> X == C2-C1 1798 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1799 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1800 DAG.getConstant(RHSC->getAPIntValue()- 1801 LHSR->getAPIntValue(), 1802 N0.getValueType()), Cond); 1803 } 1804 1805 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1806 if (N0.getOpcode() == ISD::XOR) 1807 // If we know that all of the inverted bits are zero, don't bother 1808 // performing the inversion. 1809 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1810 return 1811 DAG.getSetCC(dl, VT, N0.getOperand(0), 1812 DAG.getConstant(LHSR->getAPIntValue() ^ 1813 RHSC->getAPIntValue(), 1814 N0.getValueType()), 1815 Cond); 1816 } 1817 1818 // Turn (C1-X) == C2 --> X == C1-C2 1819 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1820 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1821 return 1822 DAG.getSetCC(dl, VT, N0.getOperand(1), 1823 DAG.getConstant(SUBC->getAPIntValue() - 1824 RHSC->getAPIntValue(), 1825 N0.getValueType()), 1826 Cond); 1827 } 1828 } 1829 } 1830 1831 // Simplify (X+Z) == X --> Z == 0 1832 if (N0.getOperand(0) == N1) 1833 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1834 DAG.getConstant(0, N0.getValueType()), Cond); 1835 if (N0.getOperand(1) == N1) { 1836 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1837 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1838 DAG.getConstant(0, N0.getValueType()), Cond); 1839 else if (N0.getNode()->hasOneUse()) { 1840 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1841 // (Z-X) == X --> Z == X<<1 1842 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1843 N1, 1844 DAG.getConstant(1, getShiftAmountTy())); 1845 if (!DCI.isCalledByLegalizer()) 1846 DCI.AddToWorklist(SH.getNode()); 1847 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1848 } 1849 } 1850 } 1851 1852 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1853 N1.getOpcode() == ISD::XOR) { 1854 // Simplify X == (X+Z) --> Z == 0 1855 if (N1.getOperand(0) == N0) { 1856 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1857 DAG.getConstant(0, N1.getValueType()), Cond); 1858 } else if (N1.getOperand(1) == N0) { 1859 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1860 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1861 DAG.getConstant(0, N1.getValueType()), Cond); 1862 } else if (N1.getNode()->hasOneUse()) { 1863 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1864 // X == (Z-X) --> X<<1 == Z 1865 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1866 DAG.getConstant(1, getShiftAmountTy())); 1867 if (!DCI.isCalledByLegalizer()) 1868 DCI.AddToWorklist(SH.getNode()); 1869 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1870 } 1871 } 1872 } 1873 1874 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1875 // Note that where y is variable and is known to have at most 1876 // one bit set (for example, if it is z&1) we cannot do this; 1877 // the expressions are not equivalent when y==0. 1878 if (N0.getOpcode() == ISD::AND) 1879 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1880 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1881 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1882 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1883 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1884 } 1885 } 1886 if (N1.getOpcode() == ISD::AND) 1887 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1888 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1889 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1890 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1891 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1892 } 1893 } 1894 } 1895 1896 // Fold away ALL boolean setcc's. 1897 SDValue Temp; 1898 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1899 switch (Cond) { 1900 default: assert(0 && "Unknown integer setcc!"); 1901 case ISD::SETEQ: // X == Y -> ~(X^Y) 1902 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1903 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1904 if (!DCI.isCalledByLegalizer()) 1905 DCI.AddToWorklist(Temp.getNode()); 1906 break; 1907 case ISD::SETNE: // X != Y --> (X^Y) 1908 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1909 break; 1910 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1911 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1912 Temp = DAG.getNOT(dl, N0, MVT::i1); 1913 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1914 if (!DCI.isCalledByLegalizer()) 1915 DCI.AddToWorklist(Temp.getNode()); 1916 break; 1917 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1918 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1919 Temp = DAG.getNOT(dl, N1, MVT::i1); 1920 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 1921 if (!DCI.isCalledByLegalizer()) 1922 DCI.AddToWorklist(Temp.getNode()); 1923 break; 1924 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1925 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1926 Temp = DAG.getNOT(dl, N0, MVT::i1); 1927 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 1928 if (!DCI.isCalledByLegalizer()) 1929 DCI.AddToWorklist(Temp.getNode()); 1930 break; 1931 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1932 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1933 Temp = DAG.getNOT(dl, N1, MVT::i1); 1934 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 1935 break; 1936 } 1937 if (VT != MVT::i1) { 1938 if (!DCI.isCalledByLegalizer()) 1939 DCI.AddToWorklist(N0.getNode()); 1940 // FIXME: If running after legalize, we probably can't do this. 1941 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 1942 } 1943 return N0; 1944 } 1945 1946 // Could not fold it. 1947 return SDValue(); 1948} 1949 1950/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1951/// node is a GlobalAddress + offset. 1952bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1953 int64_t &Offset) const { 1954 if (isa<GlobalAddressSDNode>(N)) { 1955 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1956 GA = GASD->getGlobal(); 1957 Offset += GASD->getOffset(); 1958 return true; 1959 } 1960 1961 if (N->getOpcode() == ISD::ADD) { 1962 SDValue N1 = N->getOperand(0); 1963 SDValue N2 = N->getOperand(1); 1964 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1965 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1966 if (V) { 1967 Offset += V->getSExtValue(); 1968 return true; 1969 } 1970 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1971 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1972 if (V) { 1973 Offset += V->getSExtValue(); 1974 return true; 1975 } 1976 } 1977 } 1978 return false; 1979} 1980 1981 1982/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1983/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1984/// location that the 'Base' load is loading from. 1985bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1986 unsigned Bytes, int Dist, 1987 const MachineFrameInfo *MFI) const { 1988 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1989 return false; 1990 MVT VT = LD->getValueType(0); 1991 if (VT.getSizeInBits() / 8 != Bytes) 1992 return false; 1993 1994 SDValue Loc = LD->getOperand(1); 1995 SDValue BaseLoc = Base->getOperand(1); 1996 if (Loc.getOpcode() == ISD::FrameIndex) { 1997 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1998 return false; 1999 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 2000 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 2001 int FS = MFI->getObjectSize(FI); 2002 int BFS = MFI->getObjectSize(BFI); 2003 if (FS != BFS || FS != (int)Bytes) return false; 2004 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 2005 } 2006 2007 GlobalValue *GV1 = NULL; 2008 GlobalValue *GV2 = NULL; 2009 int64_t Offset1 = 0; 2010 int64_t Offset2 = 0; 2011 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 2012 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 2013 if (isGA1 && isGA2 && GV1 == GV2) 2014 return Offset1 == (Offset2 + Dist*Bytes); 2015 return false; 2016} 2017 2018 2019SDValue TargetLowering:: 2020PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2021 // Default implementation: no optimization. 2022 return SDValue(); 2023} 2024 2025//===----------------------------------------------------------------------===// 2026// Inline Assembler Implementation Methods 2027//===----------------------------------------------------------------------===// 2028 2029 2030TargetLowering::ConstraintType 2031TargetLowering::getConstraintType(const std::string &Constraint) const { 2032 // FIXME: lots more standard ones to handle. 2033 if (Constraint.size() == 1) { 2034 switch (Constraint[0]) { 2035 default: break; 2036 case 'r': return C_RegisterClass; 2037 case 'm': // memory 2038 case 'o': // offsetable 2039 case 'V': // not offsetable 2040 return C_Memory; 2041 case 'i': // Simple Integer or Relocatable Constant 2042 case 'n': // Simple Integer 2043 case 's': // Relocatable Constant 2044 case 'X': // Allow ANY value. 2045 case 'I': // Target registers. 2046 case 'J': 2047 case 'K': 2048 case 'L': 2049 case 'M': 2050 case 'N': 2051 case 'O': 2052 case 'P': 2053 return C_Other; 2054 } 2055 } 2056 2057 if (Constraint.size() > 1 && Constraint[0] == '{' && 2058 Constraint[Constraint.size()-1] == '}') 2059 return C_Register; 2060 return C_Unknown; 2061} 2062 2063/// LowerXConstraint - try to replace an X constraint, which matches anything, 2064/// with another that has more specific requirements based on the type of the 2065/// corresponding operand. 2066const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2067 if (ConstraintVT.isInteger()) 2068 return "r"; 2069 if (ConstraintVT.isFloatingPoint()) 2070 return "f"; // works for many targets 2071 return 0; 2072} 2073 2074/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2075/// vector. If it is invalid, don't add anything to Ops. 2076void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2077 char ConstraintLetter, 2078 bool hasMemory, 2079 std::vector<SDValue> &Ops, 2080 SelectionDAG &DAG) const { 2081 switch (ConstraintLetter) { 2082 default: break; 2083 case 'X': // Allows any operand; labels (basic block) use this. 2084 if (Op.getOpcode() == ISD::BasicBlock) { 2085 Ops.push_back(Op); 2086 return; 2087 } 2088 // fall through 2089 case 'i': // Simple Integer or Relocatable Constant 2090 case 'n': // Simple Integer 2091 case 's': { // Relocatable Constant 2092 // These operands are interested in values of the form (GV+C), where C may 2093 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2094 // is possible and fine if either GV or C are missing. 2095 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2096 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2097 2098 // If we have "(add GV, C)", pull out GV/C 2099 if (Op.getOpcode() == ISD::ADD) { 2100 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2101 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2102 if (C == 0 || GA == 0) { 2103 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2104 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2105 } 2106 if (C == 0 || GA == 0) 2107 C = 0, GA = 0; 2108 } 2109 2110 // If we find a valid operand, map to the TargetXXX version so that the 2111 // value itself doesn't get selected. 2112 if (GA) { // Either &GV or &GV+C 2113 if (ConstraintLetter != 'n') { 2114 int64_t Offs = GA->getOffset(); 2115 if (C) Offs += C->getZExtValue(); 2116 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2117 Op.getValueType(), Offs)); 2118 return; 2119 } 2120 } 2121 if (C) { // just C, no GV. 2122 // Simple constants are not allowed for 's'. 2123 if (ConstraintLetter != 's') { 2124 // gcc prints these as sign extended. Sign extend value to 64 bits 2125 // now; without this it would get ZExt'd later in 2126 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2127 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2128 MVT::i64)); 2129 return; 2130 } 2131 } 2132 break; 2133 } 2134 } 2135} 2136 2137std::vector<unsigned> TargetLowering:: 2138getRegClassForInlineAsmConstraint(const std::string &Constraint, 2139 MVT VT) const { 2140 return std::vector<unsigned>(); 2141} 2142 2143 2144std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2145getRegForInlineAsmConstraint(const std::string &Constraint, 2146 MVT VT) const { 2147 if (Constraint[0] != '{') 2148 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2149 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2150 2151 // Remove the braces from around the name. 2152 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2153 2154 // Figure out which register class contains this reg. 2155 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2156 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2157 E = RI->regclass_end(); RCI != E; ++RCI) { 2158 const TargetRegisterClass *RC = *RCI; 2159 2160 // If none of the the value types for this register class are valid, we 2161 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2162 bool isLegal = false; 2163 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2164 I != E; ++I) { 2165 if (isTypeLegal(*I)) { 2166 isLegal = true; 2167 break; 2168 } 2169 } 2170 2171 if (!isLegal) continue; 2172 2173 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2174 I != E; ++I) { 2175 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2176 return std::make_pair(*I, RC); 2177 } 2178 } 2179 2180 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2181} 2182 2183//===----------------------------------------------------------------------===// 2184// Constraint Selection. 2185 2186/// isMatchingInputConstraint - Return true of this is an input operand that is 2187/// a matching constraint like "4". 2188bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2189 assert(!ConstraintCode.empty() && "No known constraint!"); 2190 return isdigit(ConstraintCode[0]); 2191} 2192 2193/// getMatchedOperand - If this is an input matching constraint, this method 2194/// returns the output operand it matches. 2195unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2196 assert(!ConstraintCode.empty() && "No known constraint!"); 2197 return atoi(ConstraintCode.c_str()); 2198} 2199 2200 2201/// getConstraintGenerality - Return an integer indicating how general CT 2202/// is. 2203static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2204 switch (CT) { 2205 default: assert(0 && "Unknown constraint type!"); 2206 case TargetLowering::C_Other: 2207 case TargetLowering::C_Unknown: 2208 return 0; 2209 case TargetLowering::C_Register: 2210 return 1; 2211 case TargetLowering::C_RegisterClass: 2212 return 2; 2213 case TargetLowering::C_Memory: 2214 return 3; 2215 } 2216} 2217 2218/// ChooseConstraint - If there are multiple different constraints that we 2219/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2220/// This is somewhat tricky: constraints fall into four classes: 2221/// Other -> immediates and magic values 2222/// Register -> one specific register 2223/// RegisterClass -> a group of regs 2224/// Memory -> memory 2225/// Ideally, we would pick the most specific constraint possible: if we have 2226/// something that fits into a register, we would pick it. The problem here 2227/// is that if we have something that could either be in a register or in 2228/// memory that use of the register could cause selection of *other* 2229/// operands to fail: they might only succeed if we pick memory. Because of 2230/// this the heuristic we use is: 2231/// 2232/// 1) If there is an 'other' constraint, and if the operand is valid for 2233/// that constraint, use it. This makes us take advantage of 'i' 2234/// constraints when available. 2235/// 2) Otherwise, pick the most general constraint present. This prefers 2236/// 'm' over 'r', for example. 2237/// 2238static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2239 bool hasMemory, const TargetLowering &TLI, 2240 SDValue Op, SelectionDAG *DAG) { 2241 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2242 unsigned BestIdx = 0; 2243 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2244 int BestGenerality = -1; 2245 2246 // Loop over the options, keeping track of the most general one. 2247 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2248 TargetLowering::ConstraintType CType = 2249 TLI.getConstraintType(OpInfo.Codes[i]); 2250 2251 // If this is an 'other' constraint, see if the operand is valid for it. 2252 // For example, on X86 we might have an 'rI' constraint. If the operand 2253 // is an integer in the range [0..31] we want to use I (saving a load 2254 // of a register), otherwise we must use 'r'. 2255 if (CType == TargetLowering::C_Other && Op.getNode()) { 2256 assert(OpInfo.Codes[i].size() == 1 && 2257 "Unhandled multi-letter 'other' constraint"); 2258 std::vector<SDValue> ResultOps; 2259 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2260 ResultOps, *DAG); 2261 if (!ResultOps.empty()) { 2262 BestType = CType; 2263 BestIdx = i; 2264 break; 2265 } 2266 } 2267 2268 // This constraint letter is more general than the previous one, use it. 2269 int Generality = getConstraintGenerality(CType); 2270 if (Generality > BestGenerality) { 2271 BestType = CType; 2272 BestIdx = i; 2273 BestGenerality = Generality; 2274 } 2275 } 2276 2277 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2278 OpInfo.ConstraintType = BestType; 2279} 2280 2281/// ComputeConstraintToUse - Determines the constraint code and constraint 2282/// type to use for the specific AsmOperandInfo, setting 2283/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2284void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2285 SDValue Op, 2286 bool hasMemory, 2287 SelectionDAG *DAG) const { 2288 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2289 2290 // Single-letter constraints ('r') are very common. 2291 if (OpInfo.Codes.size() == 1) { 2292 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2293 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2294 } else { 2295 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2296 } 2297 2298 // 'X' matches anything. 2299 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2300 // Labels and constants are handled elsewhere ('X' is the only thing 2301 // that matches labels). 2302 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2303 isa<ConstantInt>(OpInfo.CallOperandVal)) 2304 return; 2305 2306 // Otherwise, try to resolve it to something we know about by looking at 2307 // the actual operand type. 2308 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2309 OpInfo.ConstraintCode = Repl; 2310 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2311 } 2312 } 2313} 2314 2315//===----------------------------------------------------------------------===// 2316// Loop Strength Reduction hooks 2317//===----------------------------------------------------------------------===// 2318 2319/// isLegalAddressingMode - Return true if the addressing mode represented 2320/// by AM is legal for this target, for a load/store of the specified type. 2321bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2322 const Type *Ty) const { 2323 // The default implementation of this implements a conservative RISCy, r+r and 2324 // r+i addr mode. 2325 2326 // Allows a sign-extended 16-bit immediate field. 2327 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2328 return false; 2329 2330 // No global is ever allowed as a base. 2331 if (AM.BaseGV) 2332 return false; 2333 2334 // Only support r+r, 2335 switch (AM.Scale) { 2336 case 0: // "r+i" or just "i", depending on HasBaseReg. 2337 break; 2338 case 1: 2339 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2340 return false; 2341 // Otherwise we have r+r or r+i. 2342 break; 2343 case 2: 2344 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2345 return false; 2346 // Allow 2*r as r+r. 2347 break; 2348 } 2349 2350 return true; 2351} 2352 2353struct mu { 2354 APInt m; // magic number 2355 bool a; // add indicator 2356 unsigned s; // shift amount 2357}; 2358 2359/// magicu - calculate the magic numbers required to codegen an integer udiv as 2360/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2361static mu magicu(const APInt& d) { 2362 unsigned p; 2363 APInt nc, delta, q1, r1, q2, r2; 2364 struct mu magu; 2365 magu.a = 0; // initialize "add" indicator 2366 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2367 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2368 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2369 2370 nc = allOnes - (-d).urem(d); 2371 p = d.getBitWidth() - 1; // initialize p 2372 q1 = signedMin.udiv(nc); // initialize q1 = 2p/nc 2373 r1 = signedMin - q1*nc; // initialize r1 = rem(2p,nc) 2374 q2 = signedMax.udiv(d); // initialize q2 = (2p-1)/d 2375 r2 = signedMax - q2*d; // initialize r2 = rem((2p-1),d) 2376 do { 2377 p = p + 1; 2378 if (r1.uge(nc - r1)) { 2379 q1 = q1 + q1 + 1; // update q1 2380 r1 = r1 + r1 - nc; // update r1 2381 } 2382 else { 2383 q1 = q1+q1; // update q1 2384 r1 = r1+r1; // update r1 2385 } 2386 if ((r2 + 1).uge(d - r2)) { 2387 if (q2.uge(signedMax)) magu.a = 1; 2388 q2 = q2+q2 + 1; // update q2 2389 r2 = r2+r2 + 1 - d; // update r2 2390 } 2391 else { 2392 if (q2.uge(signedMin)) magu.a = 1; 2393 q2 = q2+q2; // update q2 2394 r2 = r2+r2 + 1; // update r2 2395 } 2396 delta = d - 1 - r2; 2397 } while (p < d.getBitWidth()*2 && 2398 (q1.ult(delta) || (q1 == delta && r1 == 0))); 2399 magu.m = q2 + 1; // resulting magic number 2400 magu.s = p - d.getBitWidth(); // resulting shift 2401 return magu; 2402} 2403 2404// Magic for divide replacement 2405struct ms { 2406 APInt m; // magic number 2407 unsigned s; // shift amount 2408}; 2409 2410/// magic - calculate the magic numbers required to codegen an integer sdiv as 2411/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2412/// or -1. 2413static ms magic(const APInt& d) { 2414 unsigned p; 2415 APInt ad, anc, delta, q1, r1, q2, r2, t; 2416 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2417 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2418 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2419 struct ms mag; 2420 2421 ad = d.abs(); 2422 t = signedMin + (d.lshr(d.getBitWidth() - 1)); 2423 anc = t - 1 - t.urem(ad); // absolute value of nc 2424 p = d.getBitWidth() - 1; // initialize p 2425 q1 = signedMin.udiv(anc); // initialize q1 = 2p/abs(nc) 2426 r1 = signedMin - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2427 q2 = signedMin.udiv(ad); // initialize q2 = 2p/abs(d) 2428 r2 = signedMin - q2*ad; // initialize r2 = rem(2p,abs(d)) 2429 do { 2430 p = p + 1; 2431 q1 = q1<<1; // update q1 = 2p/abs(nc) 2432 r1 = r1<<1; // update r1 = rem(2p/abs(nc)) 2433 if (r1.uge(anc)) { // must be unsigned comparison 2434 q1 = q1 + 1; 2435 r1 = r1 - anc; 2436 } 2437 q2 = q2<<1; // update q2 = 2p/abs(d) 2438 r2 = r2<<1; // update r2 = rem(2p/abs(d)) 2439 if (r2.uge(ad)) { // must be unsigned comparison 2440 q2 = q2 + 1; 2441 r2 = r2 - ad; 2442 } 2443 delta = ad - r2; 2444 } while (q1.ule(delta) || (q1 == delta && r1 == 0)); 2445 2446 mag.m = q2 + 1; 2447 if (d.isNegative()) mag.m = -mag.m; // resulting magic number 2448 mag.s = p - d.getBitWidth(); // resulting shift 2449 return mag; 2450} 2451 2452/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2453/// return a DAG expression to select that will generate the same value by 2454/// multiplying by a magic number. See: 2455/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2456SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2457 std::vector<SDNode*>* Created) const { 2458 MVT VT = N->getValueType(0); 2459 DebugLoc dl= N->getDebugLoc(); 2460 2461 // Check to see if we can do this. 2462 // FIXME: We should be more aggressive here. 2463 if (!isTypeLegal(VT)) 2464 return SDValue(); 2465 2466 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2467 ms magics = magic(d); 2468 2469 // Multiply the numerator (operand 0) by the magic value 2470 // FIXME: We should support doing a MUL in a wider type 2471 SDValue Q; 2472 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2473 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2474 DAG.getConstant(magics.m, VT)); 2475 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2476 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2477 N->getOperand(0), 2478 DAG.getConstant(magics.m, VT)).getNode(), 1); 2479 else 2480 return SDValue(); // No mulhs or equvialent 2481 // If d > 0 and m < 0, add the numerator 2482 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2483 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2484 if (Created) 2485 Created->push_back(Q.getNode()); 2486 } 2487 // If d < 0 and m > 0, subtract the numerator. 2488 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2489 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2490 if (Created) 2491 Created->push_back(Q.getNode()); 2492 } 2493 // Shift right algebraic if shift value is nonzero 2494 if (magics.s > 0) { 2495 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2496 DAG.getConstant(magics.s, getShiftAmountTy())); 2497 if (Created) 2498 Created->push_back(Q.getNode()); 2499 } 2500 // Extract the sign bit and add it to the quotient 2501 SDValue T = 2502 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2503 getShiftAmountTy())); 2504 if (Created) 2505 Created->push_back(T.getNode()); 2506 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2507} 2508 2509/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2510/// return a DAG expression to select that will generate the same value by 2511/// multiplying by a magic number. See: 2512/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2513SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2514 std::vector<SDNode*>* Created) const { 2515 MVT VT = N->getValueType(0); 2516 DebugLoc dl = N->getDebugLoc(); 2517 2518 // Check to see if we can do this. 2519 // FIXME: We should be more aggressive here. 2520 if (!isTypeLegal(VT)) 2521 return SDValue(); 2522 2523 // FIXME: We should use a narrower constant when the upper 2524 // bits are known to be zero. 2525 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2526 mu magics = magicu(N1C->getAPIntValue()); 2527 2528 // Multiply the numerator (operand 0) by the magic value 2529 // FIXME: We should support doing a MUL in a wider type 2530 SDValue Q; 2531 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2532 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2533 DAG.getConstant(magics.m, VT)); 2534 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2535 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2536 N->getOperand(0), 2537 DAG.getConstant(magics.m, VT)).getNode(), 1); 2538 else 2539 return SDValue(); // No mulhu or equvialent 2540 if (Created) 2541 Created->push_back(Q.getNode()); 2542 2543 if (magics.a == 0) { 2544 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2545 "We shouldn't generate an undefined shift!"); 2546 return DAG.getNode(ISD::SRL, dl, VT, Q, 2547 DAG.getConstant(magics.s, getShiftAmountTy())); 2548 } else { 2549 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2550 if (Created) 2551 Created->push_back(NPQ.getNode()); 2552 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2553 DAG.getConstant(1, getShiftAmountTy())); 2554 if (Created) 2555 Created->push_back(NPQ.getNode()); 2556 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2557 if (Created) 2558 Created->push_back(NPQ.getNode()); 2559 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2560 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2561 } 2562} 2563