TargetLowering.cpp revision 8101682108a26049367567a8fbc0ecaf7307481b
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/ADT/STLExtras.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30using namespace llvm; 31 32namespace llvm { 33TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 34 bool isLocal = GV->hasLocalLinkage(); 35 bool isDeclaration = GV->isDeclaration(); 36 // FIXME: what should we do for protected and internal visibility? 37 // For variables, is internal different from hidden? 38 bool isHidden = GV->hasHiddenVisibility(); 39 40 if (reloc == Reloc::PIC_) { 41 if (isLocal || isHidden) 42 return TLSModel::LocalDynamic; 43 else 44 return TLSModel::GeneralDynamic; 45 } else { 46 if (!isDeclaration || isHidden) 47 return TLSModel::LocalExec; 48 else 49 return TLSModel::InitialExec; 50 } 51} 52} 53 54/// InitLibcallNames - Set default libcall names. 55/// 56static void InitLibcallNames(const char **Names) { 57 Names[RTLIB::SHL_I16] = "__ashlhi3"; 58 Names[RTLIB::SHL_I32] = "__ashlsi3"; 59 Names[RTLIB::SHL_I64] = "__ashldi3"; 60 Names[RTLIB::SHL_I128] = "__ashlti3"; 61 Names[RTLIB::SRL_I16] = "__lshrhi3"; 62 Names[RTLIB::SRL_I32] = "__lshrsi3"; 63 Names[RTLIB::SRL_I64] = "__lshrdi3"; 64 Names[RTLIB::SRL_I128] = "__lshrti3"; 65 Names[RTLIB::SRA_I16] = "__ashrhi3"; 66 Names[RTLIB::SRA_I32] = "__ashrsi3"; 67 Names[RTLIB::SRA_I64] = "__ashrdi3"; 68 Names[RTLIB::SRA_I128] = "__ashrti3"; 69 Names[RTLIB::MUL_I8] = "__mulqi3"; 70 Names[RTLIB::MUL_I16] = "__mulhi3"; 71 Names[RTLIB::MUL_I32] = "__mulsi3"; 72 Names[RTLIB::MUL_I64] = "__muldi3"; 73 Names[RTLIB::MUL_I128] = "__multi3"; 74 Names[RTLIB::SDIV_I8] = "__divqi3"; 75 Names[RTLIB::SDIV_I16] = "__divhi3"; 76 Names[RTLIB::SDIV_I32] = "__divsi3"; 77 Names[RTLIB::SDIV_I64] = "__divdi3"; 78 Names[RTLIB::SDIV_I128] = "__divti3"; 79 Names[RTLIB::UDIV_I8] = "__udivqi3"; 80 Names[RTLIB::UDIV_I16] = "__udivhi3"; 81 Names[RTLIB::UDIV_I32] = "__udivsi3"; 82 Names[RTLIB::UDIV_I64] = "__udivdi3"; 83 Names[RTLIB::UDIV_I128] = "__udivti3"; 84 Names[RTLIB::SREM_I8] = "__modqi3"; 85 Names[RTLIB::SREM_I16] = "__modhi3"; 86 Names[RTLIB::SREM_I32] = "__modsi3"; 87 Names[RTLIB::SREM_I64] = "__moddi3"; 88 Names[RTLIB::SREM_I128] = "__modti3"; 89 Names[RTLIB::UREM_I8] = "__umodqi3"; 90 Names[RTLIB::UREM_I16] = "__umodhi3"; 91 Names[RTLIB::UREM_I32] = "__umodsi3"; 92 Names[RTLIB::UREM_I64] = "__umoddi3"; 93 Names[RTLIB::UREM_I128] = "__umodti3"; 94 Names[RTLIB::NEG_I32] = "__negsi2"; 95 Names[RTLIB::NEG_I64] = "__negdi2"; 96 Names[RTLIB::ADD_F32] = "__addsf3"; 97 Names[RTLIB::ADD_F64] = "__adddf3"; 98 Names[RTLIB::ADD_F80] = "__addxf3"; 99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 100 Names[RTLIB::SUB_F32] = "__subsf3"; 101 Names[RTLIB::SUB_F64] = "__subdf3"; 102 Names[RTLIB::SUB_F80] = "__subxf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 108 Names[RTLIB::DIV_F32] = "__divsf3"; 109 Names[RTLIB::DIV_F64] = "__divdf3"; 110 Names[RTLIB::DIV_F80] = "__divxf3"; 111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 112 Names[RTLIB::REM_F32] = "fmodf"; 113 Names[RTLIB::REM_F64] = "fmod"; 114 Names[RTLIB::REM_F80] = "fmodl"; 115 Names[RTLIB::REM_PPCF128] = "fmodl"; 116 Names[RTLIB::POWI_F32] = "__powisf2"; 117 Names[RTLIB::POWI_F64] = "__powidf2"; 118 Names[RTLIB::POWI_F80] = "__powixf2"; 119 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 120 Names[RTLIB::SQRT_F32] = "sqrtf"; 121 Names[RTLIB::SQRT_F64] = "sqrt"; 122 Names[RTLIB::SQRT_F80] = "sqrtl"; 123 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 124 Names[RTLIB::LOG_F32] = "logf"; 125 Names[RTLIB::LOG_F64] = "log"; 126 Names[RTLIB::LOG_F80] = "logl"; 127 Names[RTLIB::LOG_PPCF128] = "logl"; 128 Names[RTLIB::LOG2_F32] = "log2f"; 129 Names[RTLIB::LOG2_F64] = "log2"; 130 Names[RTLIB::LOG2_F80] = "log2l"; 131 Names[RTLIB::LOG2_PPCF128] = "log2l"; 132 Names[RTLIB::LOG10_F32] = "log10f"; 133 Names[RTLIB::LOG10_F64] = "log10"; 134 Names[RTLIB::LOG10_F80] = "log10l"; 135 Names[RTLIB::LOG10_PPCF128] = "log10l"; 136 Names[RTLIB::EXP_F32] = "expf"; 137 Names[RTLIB::EXP_F64] = "exp"; 138 Names[RTLIB::EXP_F80] = "expl"; 139 Names[RTLIB::EXP_PPCF128] = "expl"; 140 Names[RTLIB::EXP2_F32] = "exp2f"; 141 Names[RTLIB::EXP2_F64] = "exp2"; 142 Names[RTLIB::EXP2_F80] = "exp2l"; 143 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 144 Names[RTLIB::SIN_F32] = "sinf"; 145 Names[RTLIB::SIN_F64] = "sin"; 146 Names[RTLIB::SIN_F80] = "sinl"; 147 Names[RTLIB::SIN_PPCF128] = "sinl"; 148 Names[RTLIB::COS_F32] = "cosf"; 149 Names[RTLIB::COS_F64] = "cos"; 150 Names[RTLIB::COS_F80] = "cosl"; 151 Names[RTLIB::COS_PPCF128] = "cosl"; 152 Names[RTLIB::POW_F32] = "powf"; 153 Names[RTLIB::POW_F64] = "pow"; 154 Names[RTLIB::POW_F80] = "powl"; 155 Names[RTLIB::POW_PPCF128] = "powl"; 156 Names[RTLIB::CEIL_F32] = "ceilf"; 157 Names[RTLIB::CEIL_F64] = "ceil"; 158 Names[RTLIB::CEIL_F80] = "ceill"; 159 Names[RTLIB::CEIL_PPCF128] = "ceill"; 160 Names[RTLIB::TRUNC_F32] = "truncf"; 161 Names[RTLIB::TRUNC_F64] = "trunc"; 162 Names[RTLIB::TRUNC_F80] = "truncl"; 163 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 164 Names[RTLIB::RINT_F32] = "rintf"; 165 Names[RTLIB::RINT_F64] = "rint"; 166 Names[RTLIB::RINT_F80] = "rintl"; 167 Names[RTLIB::RINT_PPCF128] = "rintl"; 168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 169 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 172 Names[RTLIB::FLOOR_F32] = "floorf"; 173 Names[RTLIB::FLOOR_F64] = "floor"; 174 Names[RTLIB::FLOOR_F80] = "floorl"; 175 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 176 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 177 Names[RTLIB::COPYSIGN_F64] = "copysign"; 178 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 244 Names[RTLIB::OEQ_F32] = "__eqsf2"; 245 Names[RTLIB::OEQ_F64] = "__eqdf2"; 246 Names[RTLIB::UNE_F32] = "__nesf2"; 247 Names[RTLIB::UNE_F64] = "__nedf2"; 248 Names[RTLIB::OGE_F32] = "__gesf2"; 249 Names[RTLIB::OGE_F64] = "__gedf2"; 250 Names[RTLIB::OLT_F32] = "__ltsf2"; 251 Names[RTLIB::OLT_F64] = "__ltdf2"; 252 Names[RTLIB::OLE_F32] = "__lesf2"; 253 Names[RTLIB::OLE_F64] = "__ledf2"; 254 Names[RTLIB::OGT_F32] = "__gtsf2"; 255 Names[RTLIB::OGT_F64] = "__gtdf2"; 256 Names[RTLIB::UO_F32] = "__unordsf2"; 257 Names[RTLIB::UO_F64] = "__unorddf2"; 258 Names[RTLIB::O_F32] = "__unordsf2"; 259 Names[RTLIB::O_F64] = "__unorddf2"; 260 Names[RTLIB::MEMCPY] = "memcpy"; 261 Names[RTLIB::MEMMOVE] = "memmove"; 262 Names[RTLIB::MEMSET] = "memset"; 263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 264} 265 266/// InitLibcallCallingConvs - Set default libcall CallingConvs. 267/// 268static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 269 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 270 CCs[i] = CallingConv::C; 271 } 272} 273 274/// getFPEXT - Return the FPEXT_*_* value for the given types, or 275/// UNKNOWN_LIBCALL if there is none. 276RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 277 if (OpVT == MVT::f32) { 278 if (RetVT == MVT::f64) 279 return FPEXT_F32_F64; 280 } 281 282 return UNKNOWN_LIBCALL; 283} 284 285/// getFPROUND - Return the FPROUND_*_* value for the given types, or 286/// UNKNOWN_LIBCALL if there is none. 287RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 288 if (RetVT == MVT::f32) { 289 if (OpVT == MVT::f64) 290 return FPROUND_F64_F32; 291 if (OpVT == MVT::f80) 292 return FPROUND_F80_F32; 293 if (OpVT == MVT::ppcf128) 294 return FPROUND_PPCF128_F32; 295 } else if (RetVT == MVT::f64) { 296 if (OpVT == MVT::f80) 297 return FPROUND_F80_F64; 298 if (OpVT == MVT::ppcf128) 299 return FPROUND_PPCF128_F64; 300 } 301 302 return UNKNOWN_LIBCALL; 303} 304 305/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 306/// UNKNOWN_LIBCALL if there is none. 307RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 308 if (OpVT == MVT::f32) { 309 if (RetVT == MVT::i8) 310 return FPTOSINT_F32_I8; 311 if (RetVT == MVT::i16) 312 return FPTOSINT_F32_I16; 313 if (RetVT == MVT::i32) 314 return FPTOSINT_F32_I32; 315 if (RetVT == MVT::i64) 316 return FPTOSINT_F32_I64; 317 if (RetVT == MVT::i128) 318 return FPTOSINT_F32_I128; 319 } else if (OpVT == MVT::f64) { 320 if (RetVT == MVT::i8) 321 return FPTOSINT_F64_I8; 322 if (RetVT == MVT::i16) 323 return FPTOSINT_F64_I16; 324 if (RetVT == MVT::i32) 325 return FPTOSINT_F64_I32; 326 if (RetVT == MVT::i64) 327 return FPTOSINT_F64_I64; 328 if (RetVT == MVT::i128) 329 return FPTOSINT_F64_I128; 330 } else if (OpVT == MVT::f80) { 331 if (RetVT == MVT::i32) 332 return FPTOSINT_F80_I32; 333 if (RetVT == MVT::i64) 334 return FPTOSINT_F80_I64; 335 if (RetVT == MVT::i128) 336 return FPTOSINT_F80_I128; 337 } else if (OpVT == MVT::ppcf128) { 338 if (RetVT == MVT::i32) 339 return FPTOSINT_PPCF128_I32; 340 if (RetVT == MVT::i64) 341 return FPTOSINT_PPCF128_I64; 342 if (RetVT == MVT::i128) 343 return FPTOSINT_PPCF128_I128; 344 } 345 return UNKNOWN_LIBCALL; 346} 347 348/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 349/// UNKNOWN_LIBCALL if there is none. 350RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 351 if (OpVT == MVT::f32) { 352 if (RetVT == MVT::i8) 353 return FPTOUINT_F32_I8; 354 if (RetVT == MVT::i16) 355 return FPTOUINT_F32_I16; 356 if (RetVT == MVT::i32) 357 return FPTOUINT_F32_I32; 358 if (RetVT == MVT::i64) 359 return FPTOUINT_F32_I64; 360 if (RetVT == MVT::i128) 361 return FPTOUINT_F32_I128; 362 } else if (OpVT == MVT::f64) { 363 if (RetVT == MVT::i8) 364 return FPTOUINT_F64_I8; 365 if (RetVT == MVT::i16) 366 return FPTOUINT_F64_I16; 367 if (RetVT == MVT::i32) 368 return FPTOUINT_F64_I32; 369 if (RetVT == MVT::i64) 370 return FPTOUINT_F64_I64; 371 if (RetVT == MVT::i128) 372 return FPTOUINT_F64_I128; 373 } else if (OpVT == MVT::f80) { 374 if (RetVT == MVT::i32) 375 return FPTOUINT_F80_I32; 376 if (RetVT == MVT::i64) 377 return FPTOUINT_F80_I64; 378 if (RetVT == MVT::i128) 379 return FPTOUINT_F80_I128; 380 } else if (OpVT == MVT::ppcf128) { 381 if (RetVT == MVT::i32) 382 return FPTOUINT_PPCF128_I32; 383 if (RetVT == MVT::i64) 384 return FPTOUINT_PPCF128_I64; 385 if (RetVT == MVT::i128) 386 return FPTOUINT_PPCF128_I128; 387 } 388 return UNKNOWN_LIBCALL; 389} 390 391/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 392/// UNKNOWN_LIBCALL if there is none. 393RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 394 if (OpVT == MVT::i32) { 395 if (RetVT == MVT::f32) 396 return SINTTOFP_I32_F32; 397 else if (RetVT == MVT::f64) 398 return SINTTOFP_I32_F64; 399 else if (RetVT == MVT::f80) 400 return SINTTOFP_I32_F80; 401 else if (RetVT == MVT::ppcf128) 402 return SINTTOFP_I32_PPCF128; 403 } else if (OpVT == MVT::i64) { 404 if (RetVT == MVT::f32) 405 return SINTTOFP_I64_F32; 406 else if (RetVT == MVT::f64) 407 return SINTTOFP_I64_F64; 408 else if (RetVT == MVT::f80) 409 return SINTTOFP_I64_F80; 410 else if (RetVT == MVT::ppcf128) 411 return SINTTOFP_I64_PPCF128; 412 } else if (OpVT == MVT::i128) { 413 if (RetVT == MVT::f32) 414 return SINTTOFP_I128_F32; 415 else if (RetVT == MVT::f64) 416 return SINTTOFP_I128_F64; 417 else if (RetVT == MVT::f80) 418 return SINTTOFP_I128_F80; 419 else if (RetVT == MVT::ppcf128) 420 return SINTTOFP_I128_PPCF128; 421 } 422 return UNKNOWN_LIBCALL; 423} 424 425/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 426/// UNKNOWN_LIBCALL if there is none. 427RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 428 if (OpVT == MVT::i32) { 429 if (RetVT == MVT::f32) 430 return UINTTOFP_I32_F32; 431 else if (RetVT == MVT::f64) 432 return UINTTOFP_I32_F64; 433 else if (RetVT == MVT::f80) 434 return UINTTOFP_I32_F80; 435 else if (RetVT == MVT::ppcf128) 436 return UINTTOFP_I32_PPCF128; 437 } else if (OpVT == MVT::i64) { 438 if (RetVT == MVT::f32) 439 return UINTTOFP_I64_F32; 440 else if (RetVT == MVT::f64) 441 return UINTTOFP_I64_F64; 442 else if (RetVT == MVT::f80) 443 return UINTTOFP_I64_F80; 444 else if (RetVT == MVT::ppcf128) 445 return UINTTOFP_I64_PPCF128; 446 } else if (OpVT == MVT::i128) { 447 if (RetVT == MVT::f32) 448 return UINTTOFP_I128_F32; 449 else if (RetVT == MVT::f64) 450 return UINTTOFP_I128_F64; 451 else if (RetVT == MVT::f80) 452 return UINTTOFP_I128_F80; 453 else if (RetVT == MVT::ppcf128) 454 return UINTTOFP_I128_PPCF128; 455 } 456 return UNKNOWN_LIBCALL; 457} 458 459/// InitCmpLibcallCCs - Set default comparison libcall CC. 460/// 461static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 462 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 463 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 464 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 465 CCs[RTLIB::UNE_F32] = ISD::SETNE; 466 CCs[RTLIB::UNE_F64] = ISD::SETNE; 467 CCs[RTLIB::OGE_F32] = ISD::SETGE; 468 CCs[RTLIB::OGE_F64] = ISD::SETGE; 469 CCs[RTLIB::OLT_F32] = ISD::SETLT; 470 CCs[RTLIB::OLT_F64] = ISD::SETLT; 471 CCs[RTLIB::OLE_F32] = ISD::SETLE; 472 CCs[RTLIB::OLE_F64] = ISD::SETLE; 473 CCs[RTLIB::OGT_F32] = ISD::SETGT; 474 CCs[RTLIB::OGT_F64] = ISD::SETGT; 475 CCs[RTLIB::UO_F32] = ISD::SETNE; 476 CCs[RTLIB::UO_F64] = ISD::SETNE; 477 CCs[RTLIB::O_F32] = ISD::SETEQ; 478 CCs[RTLIB::O_F64] = ISD::SETEQ; 479} 480 481/// NOTE: The constructor takes ownership of TLOF. 482TargetLowering::TargetLowering(const TargetMachine &tm, 483 const TargetLoweringObjectFile *tlof) 484 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 485 // All operations default to being supported. 486 memset(OpActions, 0, sizeof(OpActions)); 487 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 488 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 489 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 490 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 491 492 // Set default actions for various operations. 493 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 494 // Default all indexed load / store to expand. 495 for (unsigned IM = (unsigned)ISD::PRE_INC; 496 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 497 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 498 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 499 } 500 501 // These operations default to expand. 502 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 503 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 504 } 505 506 // Most targets ignore the @llvm.prefetch intrinsic. 507 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 508 509 // ConstantFP nodes default to expand. Targets can either change this to 510 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 511 // to optimize expansions for certain constants. 512 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 513 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 514 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 515 516 // These library functions default to expand. 517 setOperationAction(ISD::FLOG , MVT::f64, Expand); 518 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 519 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 520 setOperationAction(ISD::FEXP , MVT::f64, Expand); 521 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 522 setOperationAction(ISD::FLOG , MVT::f32, Expand); 523 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 524 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 525 setOperationAction(ISD::FEXP , MVT::f32, Expand); 526 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 527 528 // Default ISD::TRAP to expand (which turns it into abort). 529 setOperationAction(ISD::TRAP, MVT::Other, Expand); 530 531 IsLittleEndian = TD->isLittleEndian(); 532 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 533 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 534 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 535 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 536 benefitFromCodePlacementOpt = false; 537 UseUnderscoreSetJmp = false; 538 UseUnderscoreLongJmp = false; 539 SelectIsExpensive = false; 540 IntDivIsCheap = false; 541 Pow2DivIsCheap = false; 542 StackPointerRegisterToSaveRestore = 0; 543 ExceptionPointerRegister = 0; 544 ExceptionSelectorRegister = 0; 545 BooleanContents = UndefinedBooleanContent; 546 SchedPreferenceInfo = Sched::Latency; 547 JumpBufSize = 0; 548 JumpBufAlignment = 0; 549 IfCvtBlockSizeLimit = 2; 550 IfCvtDupBlockSizeLimit = 0; 551 PrefLoopAlignment = 0; 552 553 InitLibcallNames(LibcallRoutineNames); 554 InitCmpLibcallCCs(CmpLibcallCCs); 555 InitLibcallCallingConvs(LibcallCallingConvs); 556} 557 558TargetLowering::~TargetLowering() { 559 delete &TLOF; 560} 561 562/// canOpTrap - Returns true if the operation can trap for the value type. 563/// VT must be a legal type. 564bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 565 assert(isTypeLegal(VT)); 566 switch (Op) { 567 default: 568 return false; 569 case ISD::FDIV: 570 case ISD::FREM: 571 case ISD::SDIV: 572 case ISD::UDIV: 573 case ISD::SREM: 574 case ISD::UREM: 575 return true; 576 } 577} 578 579 580static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 581 unsigned &NumIntermediates, 582 EVT &RegisterVT, 583 TargetLowering* TLI) { 584 // Figure out the right, legal destination reg to copy into. 585 unsigned NumElts = VT.getVectorNumElements(); 586 MVT EltTy = VT.getVectorElementType(); 587 588 unsigned NumVectorRegs = 1; 589 590 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 591 // could break down into LHS/RHS like LegalizeDAG does. 592 if (!isPowerOf2_32(NumElts)) { 593 NumVectorRegs = NumElts; 594 NumElts = 1; 595 } 596 597 // Divide the input until we get to a supported size. This will always 598 // end with a scalar if the target doesn't support vectors. 599 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 600 NumElts >>= 1; 601 NumVectorRegs <<= 1; 602 } 603 604 NumIntermediates = NumVectorRegs; 605 606 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 607 if (!TLI->isTypeLegal(NewVT)) 608 NewVT = EltTy; 609 IntermediateVT = NewVT; 610 611 EVT DestVT = TLI->getRegisterType(NewVT); 612 RegisterVT = DestVT; 613 if (EVT(DestVT).bitsLT(NewVT)) { 614 // Value is expanded, e.g. i64 -> i16. 615 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 616 } else { 617 // Otherwise, promotion or legal types use the same number of registers as 618 // the vector decimated to the appropriate level. 619 return NumVectorRegs; 620 } 621 622 return 1; 623} 624 625/// computeRegisterProperties - Once all of the register classes are added, 626/// this allows us to compute derived properties we expose. 627void TargetLowering::computeRegisterProperties() { 628 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 629 "Too many value types for ValueTypeActions to hold!"); 630 631 // Everything defaults to needing one register. 632 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 633 NumRegistersForVT[i] = 1; 634 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 635 } 636 // ...except isVoid, which doesn't need any registers. 637 NumRegistersForVT[MVT::isVoid] = 0; 638 639 // Find the largest integer register class. 640 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 641 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 642 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 643 644 // Every integer value type larger than this largest register takes twice as 645 // many registers to represent as the previous ValueType. 646 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 647 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 648 if (!ExpandedVT.isInteger()) 649 break; 650 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 651 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 652 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 653 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 654 } 655 656 // Inspect all of the ValueType's smaller than the largest integer 657 // register to see which ones need promotion. 658 unsigned LegalIntReg = LargestIntReg; 659 for (unsigned IntReg = LargestIntReg - 1; 660 IntReg >= (unsigned)MVT::i1; --IntReg) { 661 EVT IVT = (MVT::SimpleValueType)IntReg; 662 if (isTypeLegal(IVT)) { 663 LegalIntReg = IntReg; 664 } else { 665 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 666 (MVT::SimpleValueType)LegalIntReg; 667 ValueTypeActions.setTypeAction(IVT, Promote); 668 } 669 } 670 671 // ppcf128 type is really two f64's. 672 if (!isTypeLegal(MVT::ppcf128)) { 673 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 674 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 675 TransformToType[MVT::ppcf128] = MVT::f64; 676 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 677 } 678 679 // Decide how to handle f64. If the target does not have native f64 support, 680 // expand it to i64 and we will be generating soft float library calls. 681 if (!isTypeLegal(MVT::f64)) { 682 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 683 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 684 TransformToType[MVT::f64] = MVT::i64; 685 ValueTypeActions.setTypeAction(MVT::f64, Expand); 686 } 687 688 // Decide how to handle f32. If the target does not have native support for 689 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 690 if (!isTypeLegal(MVT::f32)) { 691 if (isTypeLegal(MVT::f64)) { 692 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 693 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 694 TransformToType[MVT::f32] = MVT::f64; 695 ValueTypeActions.setTypeAction(MVT::f32, Promote); 696 } else { 697 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 698 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 699 TransformToType[MVT::f32] = MVT::i32; 700 ValueTypeActions.setTypeAction(MVT::f32, Expand); 701 } 702 } 703 704 // Loop over all of the vector value types to see which need transformations. 705 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 706 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 707 MVT VT = (MVT::SimpleValueType)i; 708 if (!isTypeLegal(VT)) { 709 MVT IntermediateVT; 710 EVT RegisterVT; 711 unsigned NumIntermediates; 712 NumRegistersForVT[i] = 713 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 714 RegisterVT, this); 715 RegisterTypeForVT[i] = RegisterVT; 716 717 // Determine if there is a legal wider type. 718 bool IsLegalWiderType = false; 719 EVT EltVT = VT.getVectorElementType(); 720 unsigned NElts = VT.getVectorNumElements(); 721 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 722 EVT SVT = (MVT::SimpleValueType)nVT; 723 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 724 SVT.getVectorNumElements() > NElts && NElts != 1) { 725 TransformToType[i] = SVT; 726 ValueTypeActions.setTypeAction(VT, Promote); 727 IsLegalWiderType = true; 728 break; 729 } 730 } 731 if (!IsLegalWiderType) { 732 EVT NVT = VT.getPow2VectorType(); 733 if (NVT == VT) { 734 // Type is already a power of 2. The default action is to split. 735 TransformToType[i] = MVT::Other; 736 ValueTypeActions.setTypeAction(VT, Expand); 737 } else { 738 TransformToType[i] = NVT; 739 ValueTypeActions.setTypeAction(VT, Promote); 740 } 741 } 742 } 743 } 744} 745 746const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 747 return NULL; 748} 749 750 751MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 752 return PointerTy.SimpleTy; 753} 754 755MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 756 return MVT::i32; // return the default value 757} 758 759/// getVectorTypeBreakdown - Vector types are broken down into some number of 760/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 761/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 762/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 763/// 764/// This method returns the number of registers needed, and the VT for each 765/// register. It also returns the VT and quantity of the intermediate values 766/// before they are promoted/expanded. 767/// 768unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 769 EVT &IntermediateVT, 770 unsigned &NumIntermediates, 771 EVT &RegisterVT) const { 772 // Figure out the right, legal destination reg to copy into. 773 unsigned NumElts = VT.getVectorNumElements(); 774 EVT EltTy = VT.getVectorElementType(); 775 776 unsigned NumVectorRegs = 1; 777 778 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 779 // could break down into LHS/RHS like LegalizeDAG does. 780 if (!isPowerOf2_32(NumElts)) { 781 NumVectorRegs = NumElts; 782 NumElts = 1; 783 } 784 785 // Divide the input until we get to a supported size. This will always 786 // end with a scalar if the target doesn't support vectors. 787 while (NumElts > 1 && !isTypeLegal( 788 EVT::getVectorVT(Context, EltTy, NumElts))) { 789 NumElts >>= 1; 790 NumVectorRegs <<= 1; 791 } 792 793 NumIntermediates = NumVectorRegs; 794 795 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 796 if (!isTypeLegal(NewVT)) 797 NewVT = EltTy; 798 IntermediateVT = NewVT; 799 800 EVT DestVT = getRegisterType(Context, NewVT); 801 RegisterVT = DestVT; 802 if (DestVT.bitsLT(NewVT)) { 803 // Value is expanded, e.g. i64 -> i16. 804 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 805 } else { 806 // Otherwise, promotion or legal types use the same number of registers as 807 // the vector decimated to the appropriate level. 808 return NumVectorRegs; 809 } 810 811 return 1; 812} 813 814/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 815/// function arguments in the caller parameter area. This is the actual 816/// alignment, not its logarithm. 817unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 818 return TD->getCallFrameTypeAlignment(Ty); 819} 820 821/// getJumpTableEncoding - Return the entry encoding for a jump table in the 822/// current function. The returned value is a member of the 823/// MachineJumpTableInfo::JTEntryKind enum. 824unsigned TargetLowering::getJumpTableEncoding() const { 825 // In non-pic modes, just use the address of a block. 826 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 827 return MachineJumpTableInfo::EK_BlockAddress; 828 829 // In PIC mode, if the target supports a GPRel32 directive, use it. 830 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 831 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 832 833 // Otherwise, use a label difference. 834 return MachineJumpTableInfo::EK_LabelDifference32; 835} 836 837SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 838 SelectionDAG &DAG) const { 839 // If our PIC model is GP relative, use the global offset table as the base. 840 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 841 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 842 return Table; 843} 844 845/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 846/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 847/// MCExpr. 848const MCExpr * 849TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 850 unsigned JTI,MCContext &Ctx) const{ 851 // The normal PIC reloc base is the label at the start of the jump table. 852 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 853} 854 855bool 856TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 857 // Assume that everything is safe in static mode. 858 if (getTargetMachine().getRelocationModel() == Reloc::Static) 859 return true; 860 861 // In dynamic-no-pic mode, assume that known defined values are safe. 862 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 863 GA && 864 !GA->getGlobal()->isDeclaration() && 865 !GA->getGlobal()->isWeakForLinker()) 866 return true; 867 868 // Otherwise assume nothing is safe. 869 return false; 870} 871 872//===----------------------------------------------------------------------===// 873// Optimization Methods 874//===----------------------------------------------------------------------===// 875 876/// ShrinkDemandedConstant - Check to see if the specified operand of the 877/// specified instruction is a constant integer. If so, check to see if there 878/// are any bits set in the constant that are not demanded. If so, shrink the 879/// constant and return true. 880bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 881 const APInt &Demanded) { 882 DebugLoc dl = Op.getDebugLoc(); 883 884 // FIXME: ISD::SELECT, ISD::SELECT_CC 885 switch (Op.getOpcode()) { 886 default: break; 887 case ISD::XOR: 888 case ISD::AND: 889 case ISD::OR: { 890 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 891 if (!C) return false; 892 893 if (Op.getOpcode() == ISD::XOR && 894 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 895 return false; 896 897 // if we can expand it to have all bits set, do it 898 if (C->getAPIntValue().intersects(~Demanded)) { 899 EVT VT = Op.getValueType(); 900 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 901 DAG.getConstant(Demanded & 902 C->getAPIntValue(), 903 VT)); 904 return CombineTo(Op, New); 905 } 906 907 break; 908 } 909 } 910 911 return false; 912} 913 914/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 915/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 916/// cast, but it could be generalized for targets with other types of 917/// implicit widening casts. 918bool 919TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 920 unsigned BitWidth, 921 const APInt &Demanded, 922 DebugLoc dl) { 923 assert(Op.getNumOperands() == 2 && 924 "ShrinkDemandedOp only supports binary operators!"); 925 assert(Op.getNode()->getNumValues() == 1 && 926 "ShrinkDemandedOp only supports nodes with one result!"); 927 928 // Don't do this if the node has another user, which may require the 929 // full value. 930 if (!Op.getNode()->hasOneUse()) 931 return false; 932 933 // Search for the smallest integer type with free casts to and from 934 // Op's type. For expedience, just check power-of-2 integer types. 935 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 936 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 937 if (!isPowerOf2_32(SmallVTBits)) 938 SmallVTBits = NextPowerOf2(SmallVTBits); 939 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 940 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 941 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 942 TLI.isZExtFree(SmallVT, Op.getValueType())) { 943 // We found a type with free casts. 944 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 945 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 946 Op.getNode()->getOperand(0)), 947 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 948 Op.getNode()->getOperand(1))); 949 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 950 return CombineTo(Op, Z); 951 } 952 } 953 return false; 954} 955 956/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 957/// DemandedMask bits of the result of Op are ever used downstream. If we can 958/// use this information to simplify Op, create a new simplified DAG node and 959/// return true, returning the original and new nodes in Old and New. Otherwise, 960/// analyze the expression and return a mask of KnownOne and KnownZero bits for 961/// the expression (used to simplify the caller). The KnownZero/One bits may 962/// only be accurate for those bits in the DemandedMask. 963bool TargetLowering::SimplifyDemandedBits(SDValue Op, 964 const APInt &DemandedMask, 965 APInt &KnownZero, 966 APInt &KnownOne, 967 TargetLoweringOpt &TLO, 968 unsigned Depth) const { 969 unsigned BitWidth = DemandedMask.getBitWidth(); 970 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 971 "Mask size mismatches value type size!"); 972 APInt NewMask = DemandedMask; 973 DebugLoc dl = Op.getDebugLoc(); 974 975 // Don't know anything. 976 KnownZero = KnownOne = APInt(BitWidth, 0); 977 978 // Other users may use these bits. 979 if (!Op.getNode()->hasOneUse()) { 980 if (Depth != 0) { 981 // If not at the root, Just compute the KnownZero/KnownOne bits to 982 // simplify things downstream. 983 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 984 return false; 985 } 986 // If this is the root being simplified, allow it to have multiple uses, 987 // just set the NewMask to all bits. 988 NewMask = APInt::getAllOnesValue(BitWidth); 989 } else if (DemandedMask == 0) { 990 // Not demanding any bits from Op. 991 if (Op.getOpcode() != ISD::UNDEF) 992 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 993 return false; 994 } else if (Depth == 6) { // Limit search depth. 995 return false; 996 } 997 998 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 999 switch (Op.getOpcode()) { 1000 case ISD::Constant: 1001 // We know all of the bits for a constant! 1002 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1003 KnownZero = ~KnownOne & NewMask; 1004 return false; // Don't fall through, will infinitely loop. 1005 case ISD::AND: 1006 // If the RHS is a constant, check to see if the LHS would be zero without 1007 // using the bits from the RHS. Below, we use knowledge about the RHS to 1008 // simplify the LHS, here we're using information from the LHS to simplify 1009 // the RHS. 1010 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1011 APInt LHSZero, LHSOne; 1012 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1013 LHSZero, LHSOne, Depth+1); 1014 // If the LHS already has zeros where RHSC does, this and is dead. 1015 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1016 return TLO.CombineTo(Op, Op.getOperand(0)); 1017 // If any of the set bits in the RHS are known zero on the LHS, shrink 1018 // the constant. 1019 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1020 return true; 1021 } 1022 1023 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1024 KnownOne, TLO, Depth+1)) 1025 return true; 1026 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1027 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1028 KnownZero2, KnownOne2, TLO, Depth+1)) 1029 return true; 1030 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1031 1032 // If all of the demanded bits are known one on one side, return the other. 1033 // These bits cannot contribute to the result of the 'and'. 1034 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1035 return TLO.CombineTo(Op, Op.getOperand(0)); 1036 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1037 return TLO.CombineTo(Op, Op.getOperand(1)); 1038 // If all of the demanded bits in the inputs are known zeros, return zero. 1039 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1040 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1041 // If the RHS is a constant, see if we can simplify it. 1042 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1043 return true; 1044 // If the operation can be done in a smaller type, do so. 1045 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1046 return true; 1047 1048 // Output known-1 bits are only known if set in both the LHS & RHS. 1049 KnownOne &= KnownOne2; 1050 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1051 KnownZero |= KnownZero2; 1052 break; 1053 case ISD::OR: 1054 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1055 KnownOne, TLO, Depth+1)) 1056 return true; 1057 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1058 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1059 KnownZero2, KnownOne2, TLO, Depth+1)) 1060 return true; 1061 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1062 1063 // If all of the demanded bits are known zero on one side, return the other. 1064 // These bits cannot contribute to the result of the 'or'. 1065 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1066 return TLO.CombineTo(Op, Op.getOperand(0)); 1067 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1068 return TLO.CombineTo(Op, Op.getOperand(1)); 1069 // If all of the potentially set bits on one side are known to be set on 1070 // the other side, just use the 'other' side. 1071 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1072 return TLO.CombineTo(Op, Op.getOperand(0)); 1073 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1074 return TLO.CombineTo(Op, Op.getOperand(1)); 1075 // If the RHS is a constant, see if we can simplify it. 1076 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1077 return true; 1078 // If the operation can be done in a smaller type, do so. 1079 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1080 return true; 1081 1082 // Output known-0 bits are only known if clear in both the LHS & RHS. 1083 KnownZero &= KnownZero2; 1084 // Output known-1 are known to be set if set in either the LHS | RHS. 1085 KnownOne |= KnownOne2; 1086 break; 1087 case ISD::XOR: 1088 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1089 KnownOne, TLO, Depth+1)) 1090 return true; 1091 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1092 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1093 KnownOne2, TLO, Depth+1)) 1094 return true; 1095 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1096 1097 // If all of the demanded bits are known zero on one side, return the other. 1098 // These bits cannot contribute to the result of the 'xor'. 1099 if ((KnownZero & NewMask) == NewMask) 1100 return TLO.CombineTo(Op, Op.getOperand(0)); 1101 if ((KnownZero2 & NewMask) == NewMask) 1102 return TLO.CombineTo(Op, Op.getOperand(1)); 1103 // If the operation can be done in a smaller type, do so. 1104 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1105 return true; 1106 1107 // If all of the unknown bits are known to be zero on one side or the other 1108 // (but not both) turn this into an *inclusive* or. 1109 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1110 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1111 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1112 Op.getOperand(0), 1113 Op.getOperand(1))); 1114 1115 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1116 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1117 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1118 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1119 1120 // If all of the demanded bits on one side are known, and all of the set 1121 // bits on that side are also known to be set on the other side, turn this 1122 // into an AND, as we know the bits will be cleared. 1123 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1124 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1125 if ((KnownOne & KnownOne2) == KnownOne) { 1126 EVT VT = Op.getValueType(); 1127 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1128 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1129 Op.getOperand(0), ANDC)); 1130 } 1131 } 1132 1133 // If the RHS is a constant, see if we can simplify it. 1134 // for XOR, we prefer to force bits to 1 if they will make a -1. 1135 // if we can't force bits, try to shrink constant 1136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1137 APInt Expanded = C->getAPIntValue() | (~NewMask); 1138 // if we can expand it to have all bits set, do it 1139 if (Expanded.isAllOnesValue()) { 1140 if (Expanded != C->getAPIntValue()) { 1141 EVT VT = Op.getValueType(); 1142 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1143 TLO.DAG.getConstant(Expanded, VT)); 1144 return TLO.CombineTo(Op, New); 1145 } 1146 // if it already has all the bits set, nothing to change 1147 // but don't shrink either! 1148 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1149 return true; 1150 } 1151 } 1152 1153 KnownZero = KnownZeroOut; 1154 KnownOne = KnownOneOut; 1155 break; 1156 case ISD::SELECT: 1157 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1158 KnownOne, TLO, Depth+1)) 1159 return true; 1160 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1161 KnownOne2, TLO, Depth+1)) 1162 return true; 1163 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1164 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1165 1166 // If the operands are constants, see if we can simplify them. 1167 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1168 return true; 1169 1170 // Only known if known in both the LHS and RHS. 1171 KnownOne &= KnownOne2; 1172 KnownZero &= KnownZero2; 1173 break; 1174 case ISD::SELECT_CC: 1175 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1176 KnownOne, TLO, Depth+1)) 1177 return true; 1178 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1179 KnownOne2, TLO, Depth+1)) 1180 return true; 1181 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1182 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1183 1184 // If the operands are constants, see if we can simplify them. 1185 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1186 return true; 1187 1188 // Only known if known in both the LHS and RHS. 1189 KnownOne &= KnownOne2; 1190 KnownZero &= KnownZero2; 1191 break; 1192 case ISD::SHL: 1193 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1194 unsigned ShAmt = SA->getZExtValue(); 1195 SDValue InOp = Op.getOperand(0); 1196 1197 // If the shift count is an invalid immediate, don't do anything. 1198 if (ShAmt >= BitWidth) 1199 break; 1200 1201 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1202 // single shift. We can do this if the bottom bits (which are shifted 1203 // out) are never demanded. 1204 if (InOp.getOpcode() == ISD::SRL && 1205 isa<ConstantSDNode>(InOp.getOperand(1))) { 1206 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1207 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1208 unsigned Opc = ISD::SHL; 1209 int Diff = ShAmt-C1; 1210 if (Diff < 0) { 1211 Diff = -Diff; 1212 Opc = ISD::SRL; 1213 } 1214 1215 SDValue NewSA = 1216 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1217 EVT VT = Op.getValueType(); 1218 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1219 InOp.getOperand(0), NewSA)); 1220 } 1221 } 1222 1223 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1224 KnownZero, KnownOne, TLO, Depth+1)) 1225 return true; 1226 KnownZero <<= SA->getZExtValue(); 1227 KnownOne <<= SA->getZExtValue(); 1228 // low bits known zero. 1229 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1230 } 1231 break; 1232 case ISD::SRL: 1233 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1234 EVT VT = Op.getValueType(); 1235 unsigned ShAmt = SA->getZExtValue(); 1236 unsigned VTSize = VT.getSizeInBits(); 1237 SDValue InOp = Op.getOperand(0); 1238 1239 // If the shift count is an invalid immediate, don't do anything. 1240 if (ShAmt >= BitWidth) 1241 break; 1242 1243 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1244 // single shift. We can do this if the top bits (which are shifted out) 1245 // are never demanded. 1246 if (InOp.getOpcode() == ISD::SHL && 1247 isa<ConstantSDNode>(InOp.getOperand(1))) { 1248 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1249 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1250 unsigned Opc = ISD::SRL; 1251 int Diff = ShAmt-C1; 1252 if (Diff < 0) { 1253 Diff = -Diff; 1254 Opc = ISD::SHL; 1255 } 1256 1257 SDValue NewSA = 1258 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1259 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1260 InOp.getOperand(0), NewSA)); 1261 } 1262 } 1263 1264 // Compute the new bits that are at the top now. 1265 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1266 KnownZero, KnownOne, TLO, Depth+1)) 1267 return true; 1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1269 KnownZero = KnownZero.lshr(ShAmt); 1270 KnownOne = KnownOne.lshr(ShAmt); 1271 1272 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1273 KnownZero |= HighBits; // High bits known zero. 1274 } 1275 break; 1276 case ISD::SRA: 1277 // If this is an arithmetic shift right and only the low-bit is set, we can 1278 // always convert this into a logical shr, even if the shift amount is 1279 // variable. The low bit of the shift cannot be an input sign bit unless 1280 // the shift amount is >= the size of the datatype, which is undefined. 1281 if (DemandedMask == 1) 1282 return TLO.CombineTo(Op, 1283 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1284 Op.getOperand(0), Op.getOperand(1))); 1285 1286 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1287 EVT VT = Op.getValueType(); 1288 unsigned ShAmt = SA->getZExtValue(); 1289 1290 // If the shift count is an invalid immediate, don't do anything. 1291 if (ShAmt >= BitWidth) 1292 break; 1293 1294 APInt InDemandedMask = (NewMask << ShAmt); 1295 1296 // If any of the demanded bits are produced by the sign extension, we also 1297 // demand the input sign bit. 1298 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1299 if (HighBits.intersects(NewMask)) 1300 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1301 1302 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1303 KnownZero, KnownOne, TLO, Depth+1)) 1304 return true; 1305 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1306 KnownZero = KnownZero.lshr(ShAmt); 1307 KnownOne = KnownOne.lshr(ShAmt); 1308 1309 // Handle the sign bit, adjusted to where it is now in the mask. 1310 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1311 1312 // If the input sign bit is known to be zero, or if none of the top bits 1313 // are demanded, turn this into an unsigned shift right. 1314 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1315 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1316 Op.getOperand(0), 1317 Op.getOperand(1))); 1318 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1319 KnownOne |= HighBits; 1320 } 1321 } 1322 break; 1323 case ISD::SIGN_EXTEND_INREG: { 1324 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1325 1326 // Sign extension. Compute the demanded bits in the result that are not 1327 // present in the input. 1328 APInt NewBits = 1329 APInt::getHighBitsSet(BitWidth, 1330 BitWidth - EVT.getScalarType().getSizeInBits()) & 1331 NewMask; 1332 1333 // If none of the extended bits are demanded, eliminate the sextinreg. 1334 if (NewBits == 0) 1335 return TLO.CombineTo(Op, Op.getOperand(0)); 1336 1337 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1338 InSignBit.zext(BitWidth); 1339 APInt InputDemandedBits = 1340 APInt::getLowBitsSet(BitWidth, 1341 EVT.getScalarType().getSizeInBits()) & 1342 NewMask; 1343 1344 // Since the sign extended bits are demanded, we know that the sign 1345 // bit is demanded. 1346 InputDemandedBits |= InSignBit; 1347 1348 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1349 KnownZero, KnownOne, TLO, Depth+1)) 1350 return true; 1351 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1352 1353 // If the sign bit of the input is known set or clear, then we know the 1354 // top bits of the result. 1355 1356 // If the input sign bit is known zero, convert this into a zero extension. 1357 if (KnownZero.intersects(InSignBit)) 1358 return TLO.CombineTo(Op, 1359 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1360 1361 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1362 KnownOne |= NewBits; 1363 KnownZero &= ~NewBits; 1364 } else { // Input sign bit unknown 1365 KnownZero &= ~NewBits; 1366 KnownOne &= ~NewBits; 1367 } 1368 break; 1369 } 1370 case ISD::ZERO_EXTEND: { 1371 unsigned OperandBitWidth = 1372 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1373 APInt InMask = NewMask; 1374 InMask.trunc(OperandBitWidth); 1375 1376 // If none of the top bits are demanded, convert this into an any_extend. 1377 APInt NewBits = 1378 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1379 if (!NewBits.intersects(NewMask)) 1380 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1381 Op.getValueType(), 1382 Op.getOperand(0))); 1383 1384 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1385 KnownZero, KnownOne, TLO, Depth+1)) 1386 return true; 1387 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1388 KnownZero.zext(BitWidth); 1389 KnownOne.zext(BitWidth); 1390 KnownZero |= NewBits; 1391 break; 1392 } 1393 case ISD::SIGN_EXTEND: { 1394 EVT InVT = Op.getOperand(0).getValueType(); 1395 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1396 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1397 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1398 APInt NewBits = ~InMask & NewMask; 1399 1400 // If none of the top bits are demanded, convert this into an any_extend. 1401 if (NewBits == 0) 1402 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1403 Op.getValueType(), 1404 Op.getOperand(0))); 1405 1406 // Since some of the sign extended bits are demanded, we know that the sign 1407 // bit is demanded. 1408 APInt InDemandedBits = InMask & NewMask; 1409 InDemandedBits |= InSignBit; 1410 InDemandedBits.trunc(InBits); 1411 1412 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1413 KnownOne, TLO, Depth+1)) 1414 return true; 1415 KnownZero.zext(BitWidth); 1416 KnownOne.zext(BitWidth); 1417 1418 // If the sign bit is known zero, convert this to a zero extend. 1419 if (KnownZero.intersects(InSignBit)) 1420 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1421 Op.getValueType(), 1422 Op.getOperand(0))); 1423 1424 // If the sign bit is known one, the top bits match. 1425 if (KnownOne.intersects(InSignBit)) { 1426 KnownOne |= NewBits; 1427 KnownZero &= ~NewBits; 1428 } else { // Otherwise, top bits aren't known. 1429 KnownOne &= ~NewBits; 1430 KnownZero &= ~NewBits; 1431 } 1432 break; 1433 } 1434 case ISD::ANY_EXTEND: { 1435 unsigned OperandBitWidth = 1436 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1437 APInt InMask = NewMask; 1438 InMask.trunc(OperandBitWidth); 1439 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1440 KnownZero, KnownOne, TLO, Depth+1)) 1441 return true; 1442 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1443 KnownZero.zext(BitWidth); 1444 KnownOne.zext(BitWidth); 1445 break; 1446 } 1447 case ISD::TRUNCATE: { 1448 // Simplify the input, using demanded bit information, and compute the known 1449 // zero/one bits live out. 1450 unsigned OperandBitWidth = 1451 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1452 APInt TruncMask = NewMask; 1453 TruncMask.zext(OperandBitWidth); 1454 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1455 KnownZero, KnownOne, TLO, Depth+1)) 1456 return true; 1457 KnownZero.trunc(BitWidth); 1458 KnownOne.trunc(BitWidth); 1459 1460 // If the input is only used by this truncate, see if we can shrink it based 1461 // on the known demanded bits. 1462 if (Op.getOperand(0).getNode()->hasOneUse()) { 1463 SDValue In = Op.getOperand(0); 1464 switch (In.getOpcode()) { 1465 default: break; 1466 case ISD::SRL: 1467 // Shrink SRL by a constant if none of the high bits shifted in are 1468 // demanded. 1469 if (TLO.LegalTypes() && 1470 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1471 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1472 // undesirable. 1473 break; 1474 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1475 if (!ShAmt) 1476 break; 1477 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1478 OperandBitWidth - BitWidth); 1479 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1480 HighBits.trunc(BitWidth); 1481 1482 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1483 // None of the shifted in bits are needed. Add a truncate of the 1484 // shift input, then shift it. 1485 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1486 Op.getValueType(), 1487 In.getOperand(0)); 1488 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1489 Op.getValueType(), 1490 NewTrunc, 1491 In.getOperand(1))); 1492 } 1493 break; 1494 } 1495 } 1496 1497 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1498 break; 1499 } 1500 case ISD::AssertZext: { 1501 // Demand all the bits of the input that are demanded in the output. 1502 // The low bits are obvious; the high bits are demanded because we're 1503 // asserting that they're zero here. 1504 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1505 KnownZero, KnownOne, TLO, Depth+1)) 1506 return true; 1507 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1508 1509 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1510 APInt InMask = APInt::getLowBitsSet(BitWidth, 1511 VT.getSizeInBits()); 1512 KnownZero |= ~InMask & NewMask; 1513 break; 1514 } 1515 case ISD::BIT_CONVERT: 1516#if 0 1517 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1518 // is demanded, turn this into a FGETSIGN. 1519 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1520 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1521 !MVT::isVector(Op.getOperand(0).getValueType())) { 1522 // Only do this xform if FGETSIGN is valid or if before legalize. 1523 if (!TLO.AfterLegalize || 1524 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1525 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1526 // place. We expect the SHL to be eliminated by other optimizations. 1527 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1528 Op.getOperand(0)); 1529 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1530 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1531 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1532 Sign, ShAmt)); 1533 } 1534 } 1535#endif 1536 break; 1537 case ISD::ADD: 1538 case ISD::MUL: 1539 case ISD::SUB: { 1540 // Add, Sub, and Mul don't demand any bits in positions beyond that 1541 // of the highest bit demanded of them. 1542 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1543 BitWidth - NewMask.countLeadingZeros()); 1544 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1545 KnownOne2, TLO, Depth+1)) 1546 return true; 1547 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1548 KnownOne2, TLO, Depth+1)) 1549 return true; 1550 // See if the operation should be performed at a smaller bit width. 1551 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1552 return true; 1553 } 1554 // FALL THROUGH 1555 default: 1556 // Just use ComputeMaskedBits to compute output bits. 1557 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1558 break; 1559 } 1560 1561 // If we know the value of all of the demanded bits, return this as a 1562 // constant. 1563 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1564 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1565 1566 return false; 1567} 1568 1569/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1570/// in Mask are known to be either zero or one and return them in the 1571/// KnownZero/KnownOne bitsets. 1572void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1573 const APInt &Mask, 1574 APInt &KnownZero, 1575 APInt &KnownOne, 1576 const SelectionDAG &DAG, 1577 unsigned Depth) const { 1578 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1579 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1580 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1581 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1582 "Should use MaskedValueIsZero if you don't know whether Op" 1583 " is a target node!"); 1584 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1585} 1586 1587/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1588/// targets that want to expose additional information about sign bits to the 1589/// DAG Combiner. 1590unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1591 unsigned Depth) const { 1592 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1593 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1594 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1595 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1596 "Should use ComputeNumSignBits if you don't know whether Op" 1597 " is a target node!"); 1598 return 1; 1599} 1600 1601/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1602/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1603/// determine which bit is set. 1604/// 1605static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1606 // A left-shift of a constant one will have exactly one bit set, because 1607 // shifting the bit off the end is undefined. 1608 if (Val.getOpcode() == ISD::SHL) 1609 if (ConstantSDNode *C = 1610 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1611 if (C->getAPIntValue() == 1) 1612 return true; 1613 1614 // Similarly, a right-shift of a constant sign-bit will have exactly 1615 // one bit set. 1616 if (Val.getOpcode() == ISD::SRL) 1617 if (ConstantSDNode *C = 1618 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1619 if (C->getAPIntValue().isSignBit()) 1620 return true; 1621 1622 // More could be done here, though the above checks are enough 1623 // to handle some common cases. 1624 1625 // Fall back to ComputeMaskedBits to catch other known cases. 1626 EVT OpVT = Val.getValueType(); 1627 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1628 APInt Mask = APInt::getAllOnesValue(BitWidth); 1629 APInt KnownZero, KnownOne; 1630 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1631 return (KnownZero.countPopulation() == BitWidth - 1) && 1632 (KnownOne.countPopulation() == 1); 1633} 1634 1635/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1636/// and cc. If it is unable to simplify it, return a null SDValue. 1637SDValue 1638TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1639 ISD::CondCode Cond, bool foldBooleans, 1640 DAGCombinerInfo &DCI, DebugLoc dl) const { 1641 SelectionDAG &DAG = DCI.DAG; 1642 LLVMContext &Context = *DAG.getContext(); 1643 1644 // These setcc operations always fold. 1645 switch (Cond) { 1646 default: break; 1647 case ISD::SETFALSE: 1648 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1649 case ISD::SETTRUE: 1650 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1651 } 1652 1653 if (isa<ConstantSDNode>(N0.getNode())) { 1654 // Ensure that the constant occurs on the RHS, and fold constant 1655 // comparisons. 1656 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1657 } 1658 1659 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1660 const APInt &C1 = N1C->getAPIntValue(); 1661 1662 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1663 // equality comparison, then we're just comparing whether X itself is 1664 // zero. 1665 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1666 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1667 N0.getOperand(1).getOpcode() == ISD::Constant) { 1668 const APInt &ShAmt 1669 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1670 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1671 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1672 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1673 // (srl (ctlz x), 5) == 0 -> X != 0 1674 // (srl (ctlz x), 5) != 1 -> X != 0 1675 Cond = ISD::SETNE; 1676 } else { 1677 // (srl (ctlz x), 5) != 0 -> X == 0 1678 // (srl (ctlz x), 5) == 1 -> X == 0 1679 Cond = ISD::SETEQ; 1680 } 1681 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1682 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1683 Zero, Cond); 1684 } 1685 } 1686 1687 // If the LHS is '(and load, const)', the RHS is 0, 1688 // the test is for equality or unsigned, and all 1 bits of the const are 1689 // in the same partial word, see if we can shorten the load. 1690 if (DCI.isBeforeLegalize() && 1691 N0.getOpcode() == ISD::AND && C1 == 0 && 1692 N0.getNode()->hasOneUse() && 1693 isa<LoadSDNode>(N0.getOperand(0)) && 1694 N0.getOperand(0).getNode()->hasOneUse() && 1695 isa<ConstantSDNode>(N0.getOperand(1))) { 1696 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1697 APInt bestMask; 1698 unsigned bestWidth = 0, bestOffset = 0; 1699 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1700 unsigned origWidth = N0.getValueType().getSizeInBits(); 1701 unsigned maskWidth = origWidth; 1702 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1703 // 8 bits, but have to be careful... 1704 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1705 origWidth = Lod->getMemoryVT().getSizeInBits(); 1706 const APInt &Mask = 1707 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1708 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1709 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1710 for (unsigned offset=0; offset<origWidth/width; offset++) { 1711 if ((newMask & Mask) == Mask) { 1712 if (!TD->isLittleEndian()) 1713 bestOffset = (origWidth/width - offset - 1) * (width/8); 1714 else 1715 bestOffset = (uint64_t)offset * (width/8); 1716 bestMask = Mask.lshr(offset * (width/8) * 8); 1717 bestWidth = width; 1718 break; 1719 } 1720 newMask = newMask << width; 1721 } 1722 } 1723 } 1724 if (bestWidth) { 1725 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1726 if (newVT.isRound()) { 1727 EVT PtrType = Lod->getOperand(1).getValueType(); 1728 SDValue Ptr = Lod->getBasePtr(); 1729 if (bestOffset != 0) 1730 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1731 DAG.getConstant(bestOffset, PtrType)); 1732 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1733 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1734 Lod->getSrcValue(), 1735 Lod->getSrcValueOffset() + bestOffset, 1736 false, false, NewAlign); 1737 return DAG.getSetCC(dl, VT, 1738 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1739 DAG.getConstant(bestMask.trunc(bestWidth), 1740 newVT)), 1741 DAG.getConstant(0LL, newVT), Cond); 1742 } 1743 } 1744 } 1745 1746 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1747 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1748 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1749 1750 // If the comparison constant has bits in the upper part, the 1751 // zero-extended value could never match. 1752 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1753 C1.getBitWidth() - InSize))) { 1754 switch (Cond) { 1755 case ISD::SETUGT: 1756 case ISD::SETUGE: 1757 case ISD::SETEQ: return DAG.getConstant(0, VT); 1758 case ISD::SETULT: 1759 case ISD::SETULE: 1760 case ISD::SETNE: return DAG.getConstant(1, VT); 1761 case ISD::SETGT: 1762 case ISD::SETGE: 1763 // True if the sign bit of C1 is set. 1764 return DAG.getConstant(C1.isNegative(), VT); 1765 case ISD::SETLT: 1766 case ISD::SETLE: 1767 // True if the sign bit of C1 isn't set. 1768 return DAG.getConstant(C1.isNonNegative(), VT); 1769 default: 1770 break; 1771 } 1772 } 1773 1774 // Otherwise, we can perform the comparison with the low bits. 1775 switch (Cond) { 1776 case ISD::SETEQ: 1777 case ISD::SETNE: 1778 case ISD::SETUGT: 1779 case ISD::SETUGE: 1780 case ISD::SETULT: 1781 case ISD::SETULE: { 1782 EVT newVT = N0.getOperand(0).getValueType(); 1783 if (DCI.isBeforeLegalizeOps() || 1784 (isOperationLegal(ISD::SETCC, newVT) && 1785 getCondCodeAction(Cond, newVT)==Legal)) 1786 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1787 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1788 Cond); 1789 break; 1790 } 1791 default: 1792 break; // todo, be more careful with signed comparisons 1793 } 1794 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1795 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1796 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1797 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1798 EVT ExtDstTy = N0.getValueType(); 1799 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1800 1801 // If the extended part has any inconsistent bits, it cannot ever 1802 // compare equal. In other words, they have to be all ones or all 1803 // zeros. 1804 APInt ExtBits = 1805 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1806 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1807 return DAG.getConstant(Cond == ISD::SETNE, VT); 1808 1809 SDValue ZextOp; 1810 EVT Op0Ty = N0.getOperand(0).getValueType(); 1811 if (Op0Ty == ExtSrcTy) { 1812 ZextOp = N0.getOperand(0); 1813 } else { 1814 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1815 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1816 DAG.getConstant(Imm, Op0Ty)); 1817 } 1818 if (!DCI.isCalledByLegalizer()) 1819 DCI.AddToWorklist(ZextOp.getNode()); 1820 // Otherwise, make this a use of a zext. 1821 return DAG.getSetCC(dl, VT, ZextOp, 1822 DAG.getConstant(C1 & APInt::getLowBitsSet( 1823 ExtDstTyBits, 1824 ExtSrcTyBits), 1825 ExtDstTy), 1826 Cond); 1827 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1828 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1829 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1830 if (N0.getOpcode() == ISD::SETCC && 1831 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1832 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1833 if (TrueWhenTrue) 1834 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1835 // Invert the condition. 1836 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1837 CC = ISD::getSetCCInverse(CC, 1838 N0.getOperand(0).getValueType().isInteger()); 1839 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1840 } 1841 1842 if ((N0.getOpcode() == ISD::XOR || 1843 (N0.getOpcode() == ISD::AND && 1844 N0.getOperand(0).getOpcode() == ISD::XOR && 1845 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1846 isa<ConstantSDNode>(N0.getOperand(1)) && 1847 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1848 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1849 // can only do this if the top bits are known zero. 1850 unsigned BitWidth = N0.getValueSizeInBits(); 1851 if (DAG.MaskedValueIsZero(N0, 1852 APInt::getHighBitsSet(BitWidth, 1853 BitWidth-1))) { 1854 // Okay, get the un-inverted input value. 1855 SDValue Val; 1856 if (N0.getOpcode() == ISD::XOR) 1857 Val = N0.getOperand(0); 1858 else { 1859 assert(N0.getOpcode() == ISD::AND && 1860 N0.getOperand(0).getOpcode() == ISD::XOR); 1861 // ((X^1)&1)^1 -> X & 1 1862 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1863 N0.getOperand(0).getOperand(0), 1864 N0.getOperand(1)); 1865 } 1866 1867 return DAG.getSetCC(dl, VT, Val, N1, 1868 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1869 } 1870 } else if (N1C->getAPIntValue() == 1 && 1871 (VT == MVT::i1 || 1872 getBooleanContents() == ZeroOrOneBooleanContent)) { 1873 SDValue Op0 = N0; 1874 if (Op0.getOpcode() == ISD::TRUNCATE) 1875 Op0 = Op0.getOperand(0); 1876 1877 if ((Op0.getOpcode() == ISD::XOR) && 1878 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1879 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1880 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1881 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1882 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1883 Cond); 1884 } else if (Op0.getOpcode() == ISD::AND && 1885 isa<ConstantSDNode>(Op0.getOperand(1)) && 1886 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1887 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1888 if (Op0.getValueType().bitsGT(VT)) 1889 Op0 = DAG.getNode(ISD::AND, dl, VT, 1890 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1891 DAG.getConstant(1, VT)); 1892 else if (Op0.getValueType().bitsLT(VT)) 1893 Op0 = DAG.getNode(ISD::AND, dl, VT, 1894 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1895 DAG.getConstant(1, VT)); 1896 1897 return DAG.getSetCC(dl, VT, Op0, 1898 DAG.getConstant(0, Op0.getValueType()), 1899 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1900 } 1901 } 1902 } 1903 1904 APInt MinVal, MaxVal; 1905 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1906 if (ISD::isSignedIntSetCC(Cond)) { 1907 MinVal = APInt::getSignedMinValue(OperandBitSize); 1908 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1909 } else { 1910 MinVal = APInt::getMinValue(OperandBitSize); 1911 MaxVal = APInt::getMaxValue(OperandBitSize); 1912 } 1913 1914 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1915 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1916 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1917 // X >= C0 --> X > (C0-1) 1918 return DAG.getSetCC(dl, VT, N0, 1919 DAG.getConstant(C1-1, N1.getValueType()), 1920 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1921 } 1922 1923 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1924 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1925 // X <= C0 --> X < (C0+1) 1926 return DAG.getSetCC(dl, VT, N0, 1927 DAG.getConstant(C1+1, N1.getValueType()), 1928 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1929 } 1930 1931 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1932 return DAG.getConstant(0, VT); // X < MIN --> false 1933 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1934 return DAG.getConstant(1, VT); // X >= MIN --> true 1935 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1936 return DAG.getConstant(0, VT); // X > MAX --> false 1937 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1938 return DAG.getConstant(1, VT); // X <= MAX --> true 1939 1940 // Canonicalize setgt X, Min --> setne X, Min 1941 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1942 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1943 // Canonicalize setlt X, Max --> setne X, Max 1944 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1945 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1946 1947 // If we have setult X, 1, turn it into seteq X, 0 1948 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1949 return DAG.getSetCC(dl, VT, N0, 1950 DAG.getConstant(MinVal, N0.getValueType()), 1951 ISD::SETEQ); 1952 // If we have setugt X, Max-1, turn it into seteq X, Max 1953 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1954 return DAG.getSetCC(dl, VT, N0, 1955 DAG.getConstant(MaxVal, N0.getValueType()), 1956 ISD::SETEQ); 1957 1958 // If we have "setcc X, C0", check to see if we can shrink the immediate 1959 // by changing cc. 1960 1961 // SETUGT X, SINTMAX -> SETLT X, 0 1962 if (Cond == ISD::SETUGT && 1963 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1964 return DAG.getSetCC(dl, VT, N0, 1965 DAG.getConstant(0, N1.getValueType()), 1966 ISD::SETLT); 1967 1968 // SETULT X, SINTMIN -> SETGT X, -1 1969 if (Cond == ISD::SETULT && 1970 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1971 SDValue ConstMinusOne = 1972 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1973 N1.getValueType()); 1974 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1975 } 1976 1977 // Fold bit comparisons when we can. 1978 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1979 (VT == N0.getValueType() || 1980 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1981 N0.getOpcode() == ISD::AND) 1982 if (ConstantSDNode *AndRHS = 1983 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1984 EVT ShiftTy = DCI.isBeforeLegalize() ? 1985 getPointerTy() : getShiftAmountTy(); 1986 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1987 // Perform the xform if the AND RHS is a single bit. 1988 if (AndRHS->getAPIntValue().isPowerOf2()) { 1989 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1990 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1991 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1992 } 1993 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1994 // (X & 8) == 8 --> (X & 8) >> 3 1995 // Perform the xform if C1 is a single bit. 1996 if (C1.isPowerOf2()) { 1997 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1998 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1999 DAG.getConstant(C1.logBase2(), ShiftTy))); 2000 } 2001 } 2002 } 2003 } 2004 2005 if (isa<ConstantFPSDNode>(N0.getNode())) { 2006 // Constant fold or commute setcc. 2007 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2008 if (O.getNode()) return O; 2009 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2010 // If the RHS of an FP comparison is a constant, simplify it away in 2011 // some cases. 2012 if (CFP->getValueAPF().isNaN()) { 2013 // If an operand is known to be a nan, we can fold it. 2014 switch (ISD::getUnorderedFlavor(Cond)) { 2015 default: llvm_unreachable("Unknown flavor!"); 2016 case 0: // Known false. 2017 return DAG.getConstant(0, VT); 2018 case 1: // Known true. 2019 return DAG.getConstant(1, VT); 2020 case 2: // Undefined. 2021 return DAG.getUNDEF(VT); 2022 } 2023 } 2024 2025 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2026 // constant if knowing that the operand is non-nan is enough. We prefer to 2027 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2028 // materialize 0.0. 2029 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2030 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2031 2032 // If the condition is not legal, see if we can find an equivalent one 2033 // which is legal. 2034 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2035 // If the comparison was an awkward floating-point == or != and one of 2036 // the comparison operands is infinity or negative infinity, convert the 2037 // condition to a less-awkward <= or >=. 2038 if (CFP->getValueAPF().isInfinity()) { 2039 if (CFP->getValueAPF().isNegative()) { 2040 if (Cond == ISD::SETOEQ && 2041 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2042 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2043 if (Cond == ISD::SETUEQ && 2044 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2045 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2046 if (Cond == ISD::SETUNE && 2047 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2048 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2049 if (Cond == ISD::SETONE && 2050 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2051 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2052 } else { 2053 if (Cond == ISD::SETOEQ && 2054 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2055 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2056 if (Cond == ISD::SETUEQ && 2057 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2058 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2059 if (Cond == ISD::SETUNE && 2060 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2061 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2062 if (Cond == ISD::SETONE && 2063 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2064 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2065 } 2066 } 2067 } 2068 } 2069 2070 if (N0 == N1) { 2071 // We can always fold X == X for integer setcc's. 2072 if (N0.getValueType().isInteger()) 2073 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2074 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2075 if (UOF == 2) // FP operators that are undefined on NaNs. 2076 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2077 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2078 return DAG.getConstant(UOF, VT); 2079 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2080 // if it is not already. 2081 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2082 if (NewCond != Cond) 2083 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2084 } 2085 2086 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2087 N0.getValueType().isInteger()) { 2088 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2089 N0.getOpcode() == ISD::XOR) { 2090 // Simplify (X+Y) == (X+Z) --> Y == Z 2091 if (N0.getOpcode() == N1.getOpcode()) { 2092 if (N0.getOperand(0) == N1.getOperand(0)) 2093 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2094 if (N0.getOperand(1) == N1.getOperand(1)) 2095 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2096 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2097 // If X op Y == Y op X, try other combinations. 2098 if (N0.getOperand(0) == N1.getOperand(1)) 2099 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2100 Cond); 2101 if (N0.getOperand(1) == N1.getOperand(0)) 2102 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2103 Cond); 2104 } 2105 } 2106 2107 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2108 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2109 // Turn (X+C1) == C2 --> X == C2-C1 2110 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2111 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2112 DAG.getConstant(RHSC->getAPIntValue()- 2113 LHSR->getAPIntValue(), 2114 N0.getValueType()), Cond); 2115 } 2116 2117 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2118 if (N0.getOpcode() == ISD::XOR) 2119 // If we know that all of the inverted bits are zero, don't bother 2120 // performing the inversion. 2121 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2122 return 2123 DAG.getSetCC(dl, VT, N0.getOperand(0), 2124 DAG.getConstant(LHSR->getAPIntValue() ^ 2125 RHSC->getAPIntValue(), 2126 N0.getValueType()), 2127 Cond); 2128 } 2129 2130 // Turn (C1-X) == C2 --> X == C1-C2 2131 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2132 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2133 return 2134 DAG.getSetCC(dl, VT, N0.getOperand(1), 2135 DAG.getConstant(SUBC->getAPIntValue() - 2136 RHSC->getAPIntValue(), 2137 N0.getValueType()), 2138 Cond); 2139 } 2140 } 2141 } 2142 2143 // Simplify (X+Z) == X --> Z == 0 2144 if (N0.getOperand(0) == N1) 2145 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2146 DAG.getConstant(0, N0.getValueType()), Cond); 2147 if (N0.getOperand(1) == N1) { 2148 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2149 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2150 DAG.getConstant(0, N0.getValueType()), Cond); 2151 else if (N0.getNode()->hasOneUse()) { 2152 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2153 // (Z-X) == X --> Z == X<<1 2154 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2155 N1, 2156 DAG.getConstant(1, getShiftAmountTy())); 2157 if (!DCI.isCalledByLegalizer()) 2158 DCI.AddToWorklist(SH.getNode()); 2159 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2160 } 2161 } 2162 } 2163 2164 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2165 N1.getOpcode() == ISD::XOR) { 2166 // Simplify X == (X+Z) --> Z == 0 2167 if (N1.getOperand(0) == N0) { 2168 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2169 DAG.getConstant(0, N1.getValueType()), Cond); 2170 } else if (N1.getOperand(1) == N0) { 2171 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2172 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2173 DAG.getConstant(0, N1.getValueType()), Cond); 2174 } else if (N1.getNode()->hasOneUse()) { 2175 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2176 // X == (Z-X) --> X<<1 == Z 2177 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2178 DAG.getConstant(1, getShiftAmountTy())); 2179 if (!DCI.isCalledByLegalizer()) 2180 DCI.AddToWorklist(SH.getNode()); 2181 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2182 } 2183 } 2184 } 2185 2186 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2187 // Note that where y is variable and is known to have at most 2188 // one bit set (for example, if it is z&1) we cannot do this; 2189 // the expressions are not equivalent when y==0. 2190 if (N0.getOpcode() == ISD::AND) 2191 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2192 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2193 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2194 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2195 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2196 } 2197 } 2198 if (N1.getOpcode() == ISD::AND) 2199 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2200 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2201 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2202 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2203 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2204 } 2205 } 2206 } 2207 2208 // Fold away ALL boolean setcc's. 2209 SDValue Temp; 2210 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2211 switch (Cond) { 2212 default: llvm_unreachable("Unknown integer setcc!"); 2213 case ISD::SETEQ: // X == Y -> ~(X^Y) 2214 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2215 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2216 if (!DCI.isCalledByLegalizer()) 2217 DCI.AddToWorklist(Temp.getNode()); 2218 break; 2219 case ISD::SETNE: // X != Y --> (X^Y) 2220 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2221 break; 2222 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2223 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2224 Temp = DAG.getNOT(dl, N0, MVT::i1); 2225 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2226 if (!DCI.isCalledByLegalizer()) 2227 DCI.AddToWorklist(Temp.getNode()); 2228 break; 2229 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2230 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2231 Temp = DAG.getNOT(dl, N1, MVT::i1); 2232 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2233 if (!DCI.isCalledByLegalizer()) 2234 DCI.AddToWorklist(Temp.getNode()); 2235 break; 2236 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2237 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2238 Temp = DAG.getNOT(dl, N0, MVT::i1); 2239 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2240 if (!DCI.isCalledByLegalizer()) 2241 DCI.AddToWorklist(Temp.getNode()); 2242 break; 2243 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2244 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2245 Temp = DAG.getNOT(dl, N1, MVT::i1); 2246 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2247 break; 2248 } 2249 if (VT != MVT::i1) { 2250 if (!DCI.isCalledByLegalizer()) 2251 DCI.AddToWorklist(N0.getNode()); 2252 // FIXME: If running after legalize, we probably can't do this. 2253 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2254 } 2255 return N0; 2256 } 2257 2258 // Could not fold it. 2259 return SDValue(); 2260} 2261 2262/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2263/// node is a GlobalAddress + offset. 2264bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2265 int64_t &Offset) const { 2266 if (isa<GlobalAddressSDNode>(N)) { 2267 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2268 GA = GASD->getGlobal(); 2269 Offset += GASD->getOffset(); 2270 return true; 2271 } 2272 2273 if (N->getOpcode() == ISD::ADD) { 2274 SDValue N1 = N->getOperand(0); 2275 SDValue N2 = N->getOperand(1); 2276 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2277 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2278 if (V) { 2279 Offset += V->getSExtValue(); 2280 return true; 2281 } 2282 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2283 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2284 if (V) { 2285 Offset += V->getSExtValue(); 2286 return true; 2287 } 2288 } 2289 } 2290 return false; 2291} 2292 2293 2294SDValue TargetLowering:: 2295PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2296 // Default implementation: no optimization. 2297 return SDValue(); 2298} 2299 2300//===----------------------------------------------------------------------===// 2301// Inline Assembler Implementation Methods 2302//===----------------------------------------------------------------------===// 2303 2304 2305TargetLowering::ConstraintType 2306TargetLowering::getConstraintType(const std::string &Constraint) const { 2307 // FIXME: lots more standard ones to handle. 2308 if (Constraint.size() == 1) { 2309 switch (Constraint[0]) { 2310 default: break; 2311 case 'r': return C_RegisterClass; 2312 case 'm': // memory 2313 case 'o': // offsetable 2314 case 'V': // not offsetable 2315 return C_Memory; 2316 case 'i': // Simple Integer or Relocatable Constant 2317 case 'n': // Simple Integer 2318 case 's': // Relocatable Constant 2319 case 'X': // Allow ANY value. 2320 case 'I': // Target registers. 2321 case 'J': 2322 case 'K': 2323 case 'L': 2324 case 'M': 2325 case 'N': 2326 case 'O': 2327 case 'P': 2328 return C_Other; 2329 } 2330 } 2331 2332 if (Constraint.size() > 1 && Constraint[0] == '{' && 2333 Constraint[Constraint.size()-1] == '}') 2334 return C_Register; 2335 return C_Unknown; 2336} 2337 2338/// LowerXConstraint - try to replace an X constraint, which matches anything, 2339/// with another that has more specific requirements based on the type of the 2340/// corresponding operand. 2341const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2342 if (ConstraintVT.isInteger()) 2343 return "r"; 2344 if (ConstraintVT.isFloatingPoint()) 2345 return "f"; // works for many targets 2346 return 0; 2347} 2348 2349/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2350/// vector. If it is invalid, don't add anything to Ops. 2351void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2352 char ConstraintLetter, 2353 bool hasMemory, 2354 std::vector<SDValue> &Ops, 2355 SelectionDAG &DAG) const { 2356 switch (ConstraintLetter) { 2357 default: break; 2358 case 'X': // Allows any operand; labels (basic block) use this. 2359 if (Op.getOpcode() == ISD::BasicBlock) { 2360 Ops.push_back(Op); 2361 return; 2362 } 2363 // fall through 2364 case 'i': // Simple Integer or Relocatable Constant 2365 case 'n': // Simple Integer 2366 case 's': { // Relocatable Constant 2367 // These operands are interested in values of the form (GV+C), where C may 2368 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2369 // is possible and fine if either GV or C are missing. 2370 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2371 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2372 2373 // If we have "(add GV, C)", pull out GV/C 2374 if (Op.getOpcode() == ISD::ADD) { 2375 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2376 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2377 if (C == 0 || GA == 0) { 2378 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2379 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2380 } 2381 if (C == 0 || GA == 0) 2382 C = 0, GA = 0; 2383 } 2384 2385 // If we find a valid operand, map to the TargetXXX version so that the 2386 // value itself doesn't get selected. 2387 if (GA) { // Either &GV or &GV+C 2388 if (ConstraintLetter != 'n') { 2389 int64_t Offs = GA->getOffset(); 2390 if (C) Offs += C->getZExtValue(); 2391 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2392 Op.getValueType(), Offs)); 2393 return; 2394 } 2395 } 2396 if (C) { // just C, no GV. 2397 // Simple constants are not allowed for 's'. 2398 if (ConstraintLetter != 's') { 2399 // gcc prints these as sign extended. Sign extend value to 64 bits 2400 // now; without this it would get ZExt'd later in 2401 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2402 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2403 MVT::i64)); 2404 return; 2405 } 2406 } 2407 break; 2408 } 2409 } 2410} 2411 2412std::vector<unsigned> TargetLowering:: 2413getRegClassForInlineAsmConstraint(const std::string &Constraint, 2414 EVT VT) const { 2415 return std::vector<unsigned>(); 2416} 2417 2418 2419std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2420getRegForInlineAsmConstraint(const std::string &Constraint, 2421 EVT VT) const { 2422 if (Constraint[0] != '{') 2423 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2424 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2425 2426 // Remove the braces from around the name. 2427 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2428 2429 // Figure out which register class contains this reg. 2430 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2431 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2432 E = RI->regclass_end(); RCI != E; ++RCI) { 2433 const TargetRegisterClass *RC = *RCI; 2434 2435 // If none of the value types for this register class are valid, we 2436 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2437 bool isLegal = false; 2438 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2439 I != E; ++I) { 2440 if (isTypeLegal(*I)) { 2441 isLegal = true; 2442 break; 2443 } 2444 } 2445 2446 if (!isLegal) continue; 2447 2448 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2449 I != E; ++I) { 2450 if (RegName.equals_lower(RI->getName(*I))) 2451 return std::make_pair(*I, RC); 2452 } 2453 } 2454 2455 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2456} 2457 2458//===----------------------------------------------------------------------===// 2459// Constraint Selection. 2460 2461/// isMatchingInputConstraint - Return true of this is an input operand that is 2462/// a matching constraint like "4". 2463bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2464 assert(!ConstraintCode.empty() && "No known constraint!"); 2465 return isdigit(ConstraintCode[0]); 2466} 2467 2468/// getMatchedOperand - If this is an input matching constraint, this method 2469/// returns the output operand it matches. 2470unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2471 assert(!ConstraintCode.empty() && "No known constraint!"); 2472 return atoi(ConstraintCode.c_str()); 2473} 2474 2475 2476/// getConstraintGenerality - Return an integer indicating how general CT 2477/// is. 2478static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2479 switch (CT) { 2480 default: llvm_unreachable("Unknown constraint type!"); 2481 case TargetLowering::C_Other: 2482 case TargetLowering::C_Unknown: 2483 return 0; 2484 case TargetLowering::C_Register: 2485 return 1; 2486 case TargetLowering::C_RegisterClass: 2487 return 2; 2488 case TargetLowering::C_Memory: 2489 return 3; 2490 } 2491} 2492 2493/// ChooseConstraint - If there are multiple different constraints that we 2494/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2495/// This is somewhat tricky: constraints fall into four classes: 2496/// Other -> immediates and magic values 2497/// Register -> one specific register 2498/// RegisterClass -> a group of regs 2499/// Memory -> memory 2500/// Ideally, we would pick the most specific constraint possible: if we have 2501/// something that fits into a register, we would pick it. The problem here 2502/// is that if we have something that could either be in a register or in 2503/// memory that use of the register could cause selection of *other* 2504/// operands to fail: they might only succeed if we pick memory. Because of 2505/// this the heuristic we use is: 2506/// 2507/// 1) If there is an 'other' constraint, and if the operand is valid for 2508/// that constraint, use it. This makes us take advantage of 'i' 2509/// constraints when available. 2510/// 2) Otherwise, pick the most general constraint present. This prefers 2511/// 'm' over 'r', for example. 2512/// 2513static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2514 bool hasMemory, const TargetLowering &TLI, 2515 SDValue Op, SelectionDAG *DAG) { 2516 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2517 unsigned BestIdx = 0; 2518 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2519 int BestGenerality = -1; 2520 2521 // Loop over the options, keeping track of the most general one. 2522 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2523 TargetLowering::ConstraintType CType = 2524 TLI.getConstraintType(OpInfo.Codes[i]); 2525 2526 // If this is an 'other' constraint, see if the operand is valid for it. 2527 // For example, on X86 we might have an 'rI' constraint. If the operand 2528 // is an integer in the range [0..31] we want to use I (saving a load 2529 // of a register), otherwise we must use 'r'. 2530 if (CType == TargetLowering::C_Other && Op.getNode()) { 2531 assert(OpInfo.Codes[i].size() == 1 && 2532 "Unhandled multi-letter 'other' constraint"); 2533 std::vector<SDValue> ResultOps; 2534 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2535 ResultOps, *DAG); 2536 if (!ResultOps.empty()) { 2537 BestType = CType; 2538 BestIdx = i; 2539 break; 2540 } 2541 } 2542 2543 // This constraint letter is more general than the previous one, use it. 2544 int Generality = getConstraintGenerality(CType); 2545 if (Generality > BestGenerality) { 2546 BestType = CType; 2547 BestIdx = i; 2548 BestGenerality = Generality; 2549 } 2550 } 2551 2552 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2553 OpInfo.ConstraintType = BestType; 2554} 2555 2556/// ComputeConstraintToUse - Determines the constraint code and constraint 2557/// type to use for the specific AsmOperandInfo, setting 2558/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2559void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2560 SDValue Op, 2561 bool hasMemory, 2562 SelectionDAG *DAG) const { 2563 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2564 2565 // Single-letter constraints ('r') are very common. 2566 if (OpInfo.Codes.size() == 1) { 2567 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2568 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2569 } else { 2570 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2571 } 2572 2573 // 'X' matches anything. 2574 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2575 // Labels and constants are handled elsewhere ('X' is the only thing 2576 // that matches labels). For Functions, the type here is the type of 2577 // the result, which is not what we want to look at; leave them alone. 2578 Value *v = OpInfo.CallOperandVal; 2579 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2580 OpInfo.CallOperandVal = v; 2581 return; 2582 } 2583 2584 // Otherwise, try to resolve it to something we know about by looking at 2585 // the actual operand type. 2586 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2587 OpInfo.ConstraintCode = Repl; 2588 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2589 } 2590 } 2591} 2592 2593//===----------------------------------------------------------------------===// 2594// Loop Strength Reduction hooks 2595//===----------------------------------------------------------------------===// 2596 2597/// isLegalAddressingMode - Return true if the addressing mode represented 2598/// by AM is legal for this target, for a load/store of the specified type. 2599bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2600 const Type *Ty) const { 2601 // The default implementation of this implements a conservative RISCy, r+r and 2602 // r+i addr mode. 2603 2604 // Allows a sign-extended 16-bit immediate field. 2605 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2606 return false; 2607 2608 // No global is ever allowed as a base. 2609 if (AM.BaseGV) 2610 return false; 2611 2612 // Only support r+r, 2613 switch (AM.Scale) { 2614 case 0: // "r+i" or just "i", depending on HasBaseReg. 2615 break; 2616 case 1: 2617 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2618 return false; 2619 // Otherwise we have r+r or r+i. 2620 break; 2621 case 2: 2622 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2623 return false; 2624 // Allow 2*r as r+r. 2625 break; 2626 } 2627 2628 return true; 2629} 2630 2631/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2632/// return a DAG expression to select that will generate the same value by 2633/// multiplying by a magic number. See: 2634/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2635SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2636 std::vector<SDNode*>* Created) const { 2637 EVT VT = N->getValueType(0); 2638 DebugLoc dl= N->getDebugLoc(); 2639 2640 // Check to see if we can do this. 2641 // FIXME: We should be more aggressive here. 2642 if (!isTypeLegal(VT)) 2643 return SDValue(); 2644 2645 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2646 APInt::ms magics = d.magic(); 2647 2648 // Multiply the numerator (operand 0) by the magic value 2649 // FIXME: We should support doing a MUL in a wider type 2650 SDValue Q; 2651 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2652 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2653 DAG.getConstant(magics.m, VT)); 2654 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2655 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2656 N->getOperand(0), 2657 DAG.getConstant(magics.m, VT)).getNode(), 1); 2658 else 2659 return SDValue(); // No mulhs or equvialent 2660 // If d > 0 and m < 0, add the numerator 2661 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2662 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2663 if (Created) 2664 Created->push_back(Q.getNode()); 2665 } 2666 // If d < 0 and m > 0, subtract the numerator. 2667 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2668 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2669 if (Created) 2670 Created->push_back(Q.getNode()); 2671 } 2672 // Shift right algebraic if shift value is nonzero 2673 if (magics.s > 0) { 2674 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2675 DAG.getConstant(magics.s, getShiftAmountTy())); 2676 if (Created) 2677 Created->push_back(Q.getNode()); 2678 } 2679 // Extract the sign bit and add it to the quotient 2680 SDValue T = 2681 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2682 getShiftAmountTy())); 2683 if (Created) 2684 Created->push_back(T.getNode()); 2685 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2686} 2687 2688/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2689/// return a DAG expression to select that will generate the same value by 2690/// multiplying by a magic number. See: 2691/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2692SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2693 std::vector<SDNode*>* Created) const { 2694 EVT VT = N->getValueType(0); 2695 DebugLoc dl = N->getDebugLoc(); 2696 2697 // Check to see if we can do this. 2698 // FIXME: We should be more aggressive here. 2699 if (!isTypeLegal(VT)) 2700 return SDValue(); 2701 2702 // FIXME: We should use a narrower constant when the upper 2703 // bits are known to be zero. 2704 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2705 APInt::mu magics = N1C->getAPIntValue().magicu(); 2706 2707 // Multiply the numerator (operand 0) by the magic value 2708 // FIXME: We should support doing a MUL in a wider type 2709 SDValue Q; 2710 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2711 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2712 DAG.getConstant(magics.m, VT)); 2713 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2714 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2715 N->getOperand(0), 2716 DAG.getConstant(magics.m, VT)).getNode(), 1); 2717 else 2718 return SDValue(); // No mulhu or equvialent 2719 if (Created) 2720 Created->push_back(Q.getNode()); 2721 2722 if (magics.a == 0) { 2723 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2724 "We shouldn't generate an undefined shift!"); 2725 return DAG.getNode(ISD::SRL, dl, VT, Q, 2726 DAG.getConstant(magics.s, getShiftAmountTy())); 2727 } else { 2728 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2729 if (Created) 2730 Created->push_back(NPQ.getNode()); 2731 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2732 DAG.getConstant(1, getShiftAmountTy())); 2733 if (Created) 2734 Created->push_back(NPQ.getNode()); 2735 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2736 if (Created) 2737 Created->push_back(NPQ.getNode()); 2738 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2739 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2740 } 2741} 2742