TargetLowering.cpp revision 833a29c296da0a6af622448569dcbe01b5cae6c7
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/CodeGen/Analysis.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineJumpTableInfo.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/IR/DataLayout.h" 23#include "llvm/IR/DerivedTypes.h" 24#include "llvm/IR/GlobalVariable.h" 25#include "llvm/MC/MCAsmInfo.h" 26#include "llvm/MC/MCExpr.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetLoweringObjectFile.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Target/TargetRegisterInfo.h" 33#include <cctype> 34using namespace llvm; 35 36/// NOTE: The constructor takes ownership of TLOF. 37TargetLowering::TargetLowering(const TargetMachine &tm, 38 const TargetLoweringObjectFile *tlof) 39 : TargetLoweringBase(tm, tlof) {} 40 41const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 42 return NULL; 43} 44 45/// Check whether a given call node is in tail position within its function. If 46/// so, it sets Chain to the input chain of the tail call. 47bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 48 SDValue &Chain) const { 49 const Function *F = DAG.getMachineFunction().getFunction(); 50 51 // Conservatively require the attributes of the call to match those of 52 // the return. Ignore noalias because it doesn't affect the call sequence. 53 AttributeSet CallerAttrs = F->getAttributes(); 54 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex) 55 .removeAttribute(Attribute::NoAlias).hasAttributes()) 56 return false; 57 58 // It's not safe to eliminate the sign / zero extension of the return value. 59 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) || 60 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 61 return false; 62 63 // Check if the only use is a function return node. 64 return isUsedByReturnOnly(Node, Chain); 65} 66 67 68/// Generate a libcall taking the given operands as arguments and returning a 69/// result of type RetVT. 70std::pair<SDValue, SDValue> 71TargetLowering::makeLibCall(SelectionDAG &DAG, 72 RTLIB::Libcall LC, EVT RetVT, 73 const SDValue *Ops, unsigned NumOps, 74 bool isSigned, SDLoc dl, 75 bool doesNotReturn, 76 bool isReturnValueUsed) const { 77 TargetLowering::ArgListTy Args; 78 Args.reserve(NumOps); 79 80 TargetLowering::ArgListEntry Entry; 81 for (unsigned i = 0; i != NumOps; ++i) { 82 Entry.Node = Ops[i]; 83 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 84 Entry.isSExt = isSigned; 85 Entry.isZExt = !isSigned; 86 Args.push_back(Entry); 87 } 88 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); 89 90 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 91 TargetLowering:: 92 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 93 false, 0, getLibcallCallingConv(LC), 94 /*isTailCall=*/false, 95 doesNotReturn, isReturnValueUsed, Callee, Args, 96 DAG, dl); 97 return LowerCallTo(CLI); 98} 99 100 101/// SoftenSetCCOperands - Soften the operands of a comparison. This code is 102/// shared among BR_CC, SELECT_CC, and SETCC handlers. 103void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, 104 SDValue &NewLHS, SDValue &NewRHS, 105 ISD::CondCode &CCCode, 106 SDLoc dl) const { 107 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) 108 && "Unsupported setcc type!"); 109 110 // Expand into one or more soft-fp libcall(s). 111 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 112 switch (CCCode) { 113 case ISD::SETEQ: 114 case ISD::SETOEQ: 115 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 116 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 117 break; 118 case ISD::SETNE: 119 case ISD::SETUNE: 120 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : 121 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; 122 break; 123 case ISD::SETGE: 124 case ISD::SETOGE: 125 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 126 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 127 break; 128 case ISD::SETLT: 129 case ISD::SETOLT: 130 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 131 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 132 break; 133 case ISD::SETLE: 134 case ISD::SETOLE: 135 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 136 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 137 break; 138 case ISD::SETGT: 139 case ISD::SETOGT: 140 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 141 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 142 break; 143 case ISD::SETUO: 144 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 145 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 146 break; 147 case ISD::SETO: 148 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : 149 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128; 150 break; 151 default: 152 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 153 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 154 switch (CCCode) { 155 case ISD::SETONE: 156 // SETONE = SETOLT | SETOGT 157 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 158 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 159 // Fallthrough 160 case ISD::SETUGT: 161 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 162 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 163 break; 164 case ISD::SETUGE: 165 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 166 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 167 break; 168 case ISD::SETULT: 169 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 170 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 171 break; 172 case ISD::SETULE: 173 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 174 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 175 break; 176 case ISD::SETUEQ: 177 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 178 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 179 break; 180 default: llvm_unreachable("Do not know how to soften this setcc!"); 181 } 182 } 183 184 // Use the target specific return value for comparions lib calls. 185 EVT RetVT = getCmpLibcallReturnType(); 186 SDValue Ops[2] = { NewLHS, NewRHS }; 187 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, 188 dl).first; 189 NewRHS = DAG.getConstant(0, RetVT); 190 CCCode = getCmpLibcallCC(LC1); 191 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 192 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, 193 getSetCCResultType(*DAG.getContext(), RetVT), 194 NewLHS, NewRHS, DAG.getCondCode(CCCode)); 195 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, 196 dl).first; 197 NewLHS = DAG.getNode(ISD::SETCC, dl, 198 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS, 199 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); 200 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); 201 NewRHS = SDValue(); 202 } 203} 204 205/// getJumpTableEncoding - Return the entry encoding for a jump table in the 206/// current function. The returned value is a member of the 207/// MachineJumpTableInfo::JTEntryKind enum. 208unsigned TargetLowering::getJumpTableEncoding() const { 209 // In non-pic modes, just use the address of a block. 210 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 211 return MachineJumpTableInfo::EK_BlockAddress; 212 213 // In PIC mode, if the target supports a GPRel32 directive, use it. 214 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 215 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 216 217 // Otherwise, use a label difference. 218 return MachineJumpTableInfo::EK_LabelDifference32; 219} 220 221SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 222 SelectionDAG &DAG) const { 223 // If our PIC model is GP relative, use the global offset table as the base. 224 unsigned JTEncoding = getJumpTableEncoding(); 225 226 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 227 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 228 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 229 230 return Table; 231} 232 233/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 234/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 235/// MCExpr. 236const MCExpr * 237TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 238 unsigned JTI,MCContext &Ctx) const{ 239 // The normal PIC reloc base is the label at the start of the jump table. 240 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 241} 242 243bool 244TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 245 // Assume that everything is safe in static mode. 246 if (getTargetMachine().getRelocationModel() == Reloc::Static) 247 return true; 248 249 // In dynamic-no-pic mode, assume that known defined values are safe. 250 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 251 GA && 252 !GA->getGlobal()->isDeclaration() && 253 !GA->getGlobal()->isWeakForLinker()) 254 return true; 255 256 // Otherwise assume nothing is safe. 257 return false; 258} 259 260//===----------------------------------------------------------------------===// 261// Optimization Methods 262//===----------------------------------------------------------------------===// 263 264/// ShrinkDemandedConstant - Check to see if the specified operand of the 265/// specified instruction is a constant integer. If so, check to see if there 266/// are any bits set in the constant that are not demanded. If so, shrink the 267/// constant and return true. 268bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 269 const APInt &Demanded) { 270 SDLoc dl(Op); 271 272 // FIXME: ISD::SELECT, ISD::SELECT_CC 273 switch (Op.getOpcode()) { 274 default: break; 275 case ISD::XOR: 276 case ISD::AND: 277 case ISD::OR: { 278 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 279 if (!C) return false; 280 281 if (Op.getOpcode() == ISD::XOR && 282 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 283 return false; 284 285 // if we can expand it to have all bits set, do it 286 if (C->getAPIntValue().intersects(~Demanded)) { 287 EVT VT = Op.getValueType(); 288 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 289 DAG.getConstant(Demanded & 290 C->getAPIntValue(), 291 VT)); 292 return CombineTo(Op, New); 293 } 294 295 break; 296 } 297 } 298 299 return false; 300} 301 302/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 303/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 304/// cast, but it could be generalized for targets with other types of 305/// implicit widening casts. 306bool 307TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 308 unsigned BitWidth, 309 const APInt &Demanded, 310 SDLoc dl) { 311 assert(Op.getNumOperands() == 2 && 312 "ShrinkDemandedOp only supports binary operators!"); 313 assert(Op.getNode()->getNumValues() == 1 && 314 "ShrinkDemandedOp only supports nodes with one result!"); 315 316 // Don't do this if the node has another user, which may require the 317 // full value. 318 if (!Op.getNode()->hasOneUse()) 319 return false; 320 321 // Search for the smallest integer type with free casts to and from 322 // Op's type. For expedience, just check power-of-2 integer types. 323 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 324 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 325 unsigned SmallVTBits = DemandedSize; 326 if (!isPowerOf2_32(SmallVTBits)) 327 SmallVTBits = NextPowerOf2(SmallVTBits); 328 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 329 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 330 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 331 TLI.isZExtFree(SmallVT, Op.getValueType())) { 332 // We found a type with free casts. 333 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 334 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 335 Op.getNode()->getOperand(0)), 336 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 337 Op.getNode()->getOperand(1))); 338 bool NeedZext = DemandedSize > SmallVTBits; 339 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 340 dl, Op.getValueType(), X); 341 return CombineTo(Op, Z); 342 } 343 } 344 return false; 345} 346 347/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 348/// DemandedMask bits of the result of Op are ever used downstream. If we can 349/// use this information to simplify Op, create a new simplified DAG node and 350/// return true, returning the original and new nodes in Old and New. Otherwise, 351/// analyze the expression and return a mask of KnownOne and KnownZero bits for 352/// the expression (used to simplify the caller). The KnownZero/One bits may 353/// only be accurate for those bits in the DemandedMask. 354bool TargetLowering::SimplifyDemandedBits(SDValue Op, 355 const APInt &DemandedMask, 356 APInt &KnownZero, 357 APInt &KnownOne, 358 TargetLoweringOpt &TLO, 359 unsigned Depth) const { 360 unsigned BitWidth = DemandedMask.getBitWidth(); 361 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 362 "Mask size mismatches value type size!"); 363 APInt NewMask = DemandedMask; 364 SDLoc dl(Op); 365 366 // Don't know anything. 367 KnownZero = KnownOne = APInt(BitWidth, 0); 368 369 // Other users may use these bits. 370 if (!Op.getNode()->hasOneUse()) { 371 if (Depth != 0) { 372 // If not at the root, Just compute the KnownZero/KnownOne bits to 373 // simplify things downstream. 374 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 375 return false; 376 } 377 // If this is the root being simplified, allow it to have multiple uses, 378 // just set the NewMask to all bits. 379 NewMask = APInt::getAllOnesValue(BitWidth); 380 } else if (DemandedMask == 0) { 381 // Not demanding any bits from Op. 382 if (Op.getOpcode() != ISD::UNDEF) 383 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 384 return false; 385 } else if (Depth == 6) { // Limit search depth. 386 return false; 387 } 388 389 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 390 switch (Op.getOpcode()) { 391 case ISD::Constant: 392 // We know all of the bits for a constant! 393 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 394 KnownZero = ~KnownOne; 395 return false; // Don't fall through, will infinitely loop. 396 case ISD::AND: 397 // If the RHS is a constant, check to see if the LHS would be zero without 398 // using the bits from the RHS. Below, we use knowledge about the RHS to 399 // simplify the LHS, here we're using information from the LHS to simplify 400 // the RHS. 401 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 402 APInt LHSZero, LHSOne; 403 // Do not increment Depth here; that can cause an infinite loop. 404 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 405 // If the LHS already has zeros where RHSC does, this and is dead. 406 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 407 return TLO.CombineTo(Op, Op.getOperand(0)); 408 // If any of the set bits in the RHS are known zero on the LHS, shrink 409 // the constant. 410 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 411 return true; 412 } 413 414 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 415 KnownOne, TLO, Depth+1)) 416 return true; 417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 418 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 419 KnownZero2, KnownOne2, TLO, Depth+1)) 420 return true; 421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 422 423 // If all of the demanded bits are known one on one side, return the other. 424 // These bits cannot contribute to the result of the 'and'. 425 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 426 return TLO.CombineTo(Op, Op.getOperand(0)); 427 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 428 return TLO.CombineTo(Op, Op.getOperand(1)); 429 // If all of the demanded bits in the inputs are known zeros, return zero. 430 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 431 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 432 // If the RHS is a constant, see if we can simplify it. 433 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 434 return true; 435 // If the operation can be done in a smaller type, do so. 436 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 437 return true; 438 439 // Output known-1 bits are only known if set in both the LHS & RHS. 440 KnownOne &= KnownOne2; 441 // Output known-0 are known to be clear if zero in either the LHS | RHS. 442 KnownZero |= KnownZero2; 443 break; 444 case ISD::OR: 445 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 446 KnownOne, TLO, Depth+1)) 447 return true; 448 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 449 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 450 KnownZero2, KnownOne2, TLO, Depth+1)) 451 return true; 452 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 453 454 // If all of the demanded bits are known zero on one side, return the other. 455 // These bits cannot contribute to the result of the 'or'. 456 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 457 return TLO.CombineTo(Op, Op.getOperand(0)); 458 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 459 return TLO.CombineTo(Op, Op.getOperand(1)); 460 // If all of the potentially set bits on one side are known to be set on 461 // the other side, just use the 'other' side. 462 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 463 return TLO.CombineTo(Op, Op.getOperand(0)); 464 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 465 return TLO.CombineTo(Op, Op.getOperand(1)); 466 // If the RHS is a constant, see if we can simplify it. 467 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 468 return true; 469 // If the operation can be done in a smaller type, do so. 470 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 471 return true; 472 473 // Output known-0 bits are only known if clear in both the LHS & RHS. 474 KnownZero &= KnownZero2; 475 // Output known-1 are known to be set if set in either the LHS | RHS. 476 KnownOne |= KnownOne2; 477 break; 478 case ISD::XOR: 479 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 480 KnownOne, TLO, Depth+1)) 481 return true; 482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 483 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 484 KnownOne2, TLO, Depth+1)) 485 return true; 486 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 487 488 // If all of the demanded bits are known zero on one side, return the other. 489 // These bits cannot contribute to the result of the 'xor'. 490 if ((KnownZero & NewMask) == NewMask) 491 return TLO.CombineTo(Op, Op.getOperand(0)); 492 if ((KnownZero2 & NewMask) == NewMask) 493 return TLO.CombineTo(Op, Op.getOperand(1)); 494 // If the operation can be done in a smaller type, do so. 495 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 496 return true; 497 498 // If all of the unknown bits are known to be zero on one side or the other 499 // (but not both) turn this into an *inclusive* or. 500 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 501 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 502 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 503 Op.getOperand(0), 504 Op.getOperand(1))); 505 506 // Output known-0 bits are known if clear or set in both the LHS & RHS. 507 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 508 // Output known-1 are known to be set if set in only one of the LHS, RHS. 509 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 510 511 // If all of the demanded bits on one side are known, and all of the set 512 // bits on that side are also known to be set on the other side, turn this 513 // into an AND, as we know the bits will be cleared. 514 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 515 // NB: it is okay if more bits are known than are requested 516 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 517 if (KnownOne == KnownOne2) { // set bits are the same on both sides 518 EVT VT = Op.getValueType(); 519 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 521 Op.getOperand(0), ANDC)); 522 } 523 } 524 525 // If the RHS is a constant, see if we can simplify it. 526 // for XOR, we prefer to force bits to 1 if they will make a -1. 527 // if we can't force bits, try to shrink constant 528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 529 APInt Expanded = C->getAPIntValue() | (~NewMask); 530 // if we can expand it to have all bits set, do it 531 if (Expanded.isAllOnesValue()) { 532 if (Expanded != C->getAPIntValue()) { 533 EVT VT = Op.getValueType(); 534 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 535 TLO.DAG.getConstant(Expanded, VT)); 536 return TLO.CombineTo(Op, New); 537 } 538 // if it already has all the bits set, nothing to change 539 // but don't shrink either! 540 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 541 return true; 542 } 543 } 544 545 KnownZero = KnownZeroOut; 546 KnownOne = KnownOneOut; 547 break; 548 case ISD::SELECT: 549 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 550 KnownOne, TLO, Depth+1)) 551 return true; 552 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 553 KnownOne2, TLO, Depth+1)) 554 return true; 555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 557 558 // If the operands are constants, see if we can simplify them. 559 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 560 return true; 561 562 // Only known if known in both the LHS and RHS. 563 KnownOne &= KnownOne2; 564 KnownZero &= KnownZero2; 565 break; 566 case ISD::SELECT_CC: 567 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 568 KnownOne, TLO, Depth+1)) 569 return true; 570 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 571 KnownOne2, TLO, Depth+1)) 572 return true; 573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 574 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 575 576 // If the operands are constants, see if we can simplify them. 577 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 578 return true; 579 580 // Only known if known in both the LHS and RHS. 581 KnownOne &= KnownOne2; 582 KnownZero &= KnownZero2; 583 break; 584 case ISD::SHL: 585 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 586 unsigned ShAmt = SA->getZExtValue(); 587 SDValue InOp = Op.getOperand(0); 588 589 // If the shift count is an invalid immediate, don't do anything. 590 if (ShAmt >= BitWidth) 591 break; 592 593 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 594 // single shift. We can do this if the bottom bits (which are shifted 595 // out) are never demanded. 596 if (InOp.getOpcode() == ISD::SRL && 597 isa<ConstantSDNode>(InOp.getOperand(1))) { 598 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 599 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 600 unsigned Opc = ISD::SHL; 601 int Diff = ShAmt-C1; 602 if (Diff < 0) { 603 Diff = -Diff; 604 Opc = ISD::SRL; 605 } 606 607 SDValue NewSA = 608 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 609 EVT VT = Op.getValueType(); 610 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 611 InOp.getOperand(0), NewSA)); 612 } 613 } 614 615 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 616 KnownZero, KnownOne, TLO, Depth+1)) 617 return true; 618 619 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 620 // are not demanded. This will likely allow the anyext to be folded away. 621 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 622 SDValue InnerOp = InOp.getNode()->getOperand(0); 623 EVT InnerVT = InnerOp.getValueType(); 624 unsigned InnerBits = InnerVT.getSizeInBits(); 625 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 626 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 627 EVT ShTy = getShiftAmountTy(InnerVT); 628 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 629 ShTy = InnerVT; 630 SDValue NarrowShl = 631 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 632 TLO.DAG.getConstant(ShAmt, ShTy)); 633 return 634 TLO.CombineTo(Op, 635 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 636 NarrowShl)); 637 } 638 } 639 640 KnownZero <<= SA->getZExtValue(); 641 KnownOne <<= SA->getZExtValue(); 642 // low bits known zero. 643 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 644 } 645 break; 646 case ISD::SRL: 647 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 648 EVT VT = Op.getValueType(); 649 unsigned ShAmt = SA->getZExtValue(); 650 unsigned VTSize = VT.getSizeInBits(); 651 SDValue InOp = Op.getOperand(0); 652 653 // If the shift count is an invalid immediate, don't do anything. 654 if (ShAmt >= BitWidth) 655 break; 656 657 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 658 // single shift. We can do this if the top bits (which are shifted out) 659 // are never demanded. 660 if (InOp.getOpcode() == ISD::SHL && 661 isa<ConstantSDNode>(InOp.getOperand(1))) { 662 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 663 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 664 unsigned Opc = ISD::SRL; 665 int Diff = ShAmt-C1; 666 if (Diff < 0) { 667 Diff = -Diff; 668 Opc = ISD::SHL; 669 } 670 671 SDValue NewSA = 672 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 673 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 674 InOp.getOperand(0), NewSA)); 675 } 676 } 677 678 // Compute the new bits that are at the top now. 679 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 680 KnownZero, KnownOne, TLO, Depth+1)) 681 return true; 682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 683 KnownZero = KnownZero.lshr(ShAmt); 684 KnownOne = KnownOne.lshr(ShAmt); 685 686 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 687 KnownZero |= HighBits; // High bits known zero. 688 } 689 break; 690 case ISD::SRA: 691 // If this is an arithmetic shift right and only the low-bit is set, we can 692 // always convert this into a logical shr, even if the shift amount is 693 // variable. The low bit of the shift cannot be an input sign bit unless 694 // the shift amount is >= the size of the datatype, which is undefined. 695 if (NewMask == 1) 696 return TLO.CombineTo(Op, 697 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 698 Op.getOperand(0), Op.getOperand(1))); 699 700 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 701 EVT VT = Op.getValueType(); 702 unsigned ShAmt = SA->getZExtValue(); 703 704 // If the shift count is an invalid immediate, don't do anything. 705 if (ShAmt >= BitWidth) 706 break; 707 708 APInt InDemandedMask = (NewMask << ShAmt); 709 710 // If any of the demanded bits are produced by the sign extension, we also 711 // demand the input sign bit. 712 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 713 if (HighBits.intersects(NewMask)) 714 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 715 716 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 717 KnownZero, KnownOne, TLO, Depth+1)) 718 return true; 719 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 720 KnownZero = KnownZero.lshr(ShAmt); 721 KnownOne = KnownOne.lshr(ShAmt); 722 723 // Handle the sign bit, adjusted to where it is now in the mask. 724 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 725 726 // If the input sign bit is known to be zero, or if none of the top bits 727 // are demanded, turn this into an unsigned shift right. 728 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 729 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 730 Op.getOperand(0), 731 Op.getOperand(1))); 732 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 733 KnownOne |= HighBits; 734 } 735 } 736 break; 737 case ISD::SIGN_EXTEND_INREG: { 738 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 739 740 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 741 // If we only care about the highest bit, don't bother shifting right. 742 if (MsbMask == DemandedMask) { 743 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 744 SDValue InOp = Op.getOperand(0); 745 746 // Compute the correct shift amount type, which must be getShiftAmountTy 747 // for scalar types after legalization. 748 EVT ShiftAmtTy = Op.getValueType(); 749 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 750 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 751 752 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 753 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 754 Op.getValueType(), InOp, ShiftAmt)); 755 } 756 757 // Sign extension. Compute the demanded bits in the result that are not 758 // present in the input. 759 APInt NewBits = 760 APInt::getHighBitsSet(BitWidth, 761 BitWidth - ExVT.getScalarType().getSizeInBits()); 762 763 // If none of the extended bits are demanded, eliminate the sextinreg. 764 if ((NewBits & NewMask) == 0) 765 return TLO.CombineTo(Op, Op.getOperand(0)); 766 767 APInt InSignBit = 768 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 769 APInt InputDemandedBits = 770 APInt::getLowBitsSet(BitWidth, 771 ExVT.getScalarType().getSizeInBits()) & 772 NewMask; 773 774 // Since the sign extended bits are demanded, we know that the sign 775 // bit is demanded. 776 InputDemandedBits |= InSignBit; 777 778 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 779 KnownZero, KnownOne, TLO, Depth+1)) 780 return true; 781 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 782 783 // If the sign bit of the input is known set or clear, then we know the 784 // top bits of the result. 785 786 // If the input sign bit is known zero, convert this into a zero extension. 787 if (KnownZero.intersects(InSignBit)) 788 return TLO.CombineTo(Op, 789 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 790 791 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 792 KnownOne |= NewBits; 793 KnownZero &= ~NewBits; 794 } else { // Input sign bit unknown 795 KnownZero &= ~NewBits; 796 KnownOne &= ~NewBits; 797 } 798 break; 799 } 800 case ISD::ZERO_EXTEND: { 801 unsigned OperandBitWidth = 802 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 803 APInt InMask = NewMask.trunc(OperandBitWidth); 804 805 // If none of the top bits are demanded, convert this into an any_extend. 806 APInt NewBits = 807 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 808 if (!NewBits.intersects(NewMask)) 809 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 810 Op.getValueType(), 811 Op.getOperand(0))); 812 813 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 814 KnownZero, KnownOne, TLO, Depth+1)) 815 return true; 816 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 817 KnownZero = KnownZero.zext(BitWidth); 818 KnownOne = KnownOne.zext(BitWidth); 819 KnownZero |= NewBits; 820 break; 821 } 822 case ISD::SIGN_EXTEND: { 823 EVT InVT = Op.getOperand(0).getValueType(); 824 unsigned InBits = InVT.getScalarType().getSizeInBits(); 825 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 826 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 827 APInt NewBits = ~InMask & NewMask; 828 829 // If none of the top bits are demanded, convert this into an any_extend. 830 if (NewBits == 0) 831 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 832 Op.getValueType(), 833 Op.getOperand(0))); 834 835 // Since some of the sign extended bits are demanded, we know that the sign 836 // bit is demanded. 837 APInt InDemandedBits = InMask & NewMask; 838 InDemandedBits |= InSignBit; 839 InDemandedBits = InDemandedBits.trunc(InBits); 840 841 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 842 KnownOne, TLO, Depth+1)) 843 return true; 844 KnownZero = KnownZero.zext(BitWidth); 845 KnownOne = KnownOne.zext(BitWidth); 846 847 // If the sign bit is known zero, convert this to a zero extend. 848 if (KnownZero.intersects(InSignBit)) 849 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 850 Op.getValueType(), 851 Op.getOperand(0))); 852 853 // If the sign bit is known one, the top bits match. 854 if (KnownOne.intersects(InSignBit)) { 855 KnownOne |= NewBits; 856 assert((KnownZero & NewBits) == 0); 857 } else { // Otherwise, top bits aren't known. 858 assert((KnownOne & NewBits) == 0); 859 assert((KnownZero & NewBits) == 0); 860 } 861 break; 862 } 863 case ISD::ANY_EXTEND: { 864 unsigned OperandBitWidth = 865 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 866 APInt InMask = NewMask.trunc(OperandBitWidth); 867 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 868 KnownZero, KnownOne, TLO, Depth+1)) 869 return true; 870 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 871 KnownZero = KnownZero.zext(BitWidth); 872 KnownOne = KnownOne.zext(BitWidth); 873 break; 874 } 875 case ISD::TRUNCATE: { 876 // Simplify the input, using demanded bit information, and compute the known 877 // zero/one bits live out. 878 unsigned OperandBitWidth = 879 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 880 APInt TruncMask = NewMask.zext(OperandBitWidth); 881 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 882 KnownZero, KnownOne, TLO, Depth+1)) 883 return true; 884 KnownZero = KnownZero.trunc(BitWidth); 885 KnownOne = KnownOne.trunc(BitWidth); 886 887 // If the input is only used by this truncate, see if we can shrink it based 888 // on the known demanded bits. 889 if (Op.getOperand(0).getNode()->hasOneUse()) { 890 SDValue In = Op.getOperand(0); 891 switch (In.getOpcode()) { 892 default: break; 893 case ISD::SRL: 894 // Shrink SRL by a constant if none of the high bits shifted in are 895 // demanded. 896 if (TLO.LegalTypes() && 897 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 898 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 899 // undesirable. 900 break; 901 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 902 if (!ShAmt) 903 break; 904 SDValue Shift = In.getOperand(1); 905 if (TLO.LegalTypes()) { 906 uint64_t ShVal = ShAmt->getZExtValue(); 907 Shift = 908 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 909 } 910 911 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 912 OperandBitWidth - BitWidth); 913 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 914 915 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 916 // None of the shifted in bits are needed. Add a truncate of the 917 // shift input, then shift it. 918 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 919 Op.getValueType(), 920 In.getOperand(0)); 921 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 922 Op.getValueType(), 923 NewTrunc, 924 Shift)); 925 } 926 break; 927 } 928 } 929 930 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 931 break; 932 } 933 case ISD::AssertZext: { 934 // AssertZext demands all of the high bits, plus any of the low bits 935 // demanded by its users. 936 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 937 APInt InMask = APInt::getLowBitsSet(BitWidth, 938 VT.getSizeInBits()); 939 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 940 KnownZero, KnownOne, TLO, Depth+1)) 941 return true; 942 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 943 944 KnownZero |= ~InMask & NewMask; 945 break; 946 } 947 case ISD::BITCAST: 948 // If this is an FP->Int bitcast and if the sign bit is the only 949 // thing demanded, turn this into a FGETSIGN. 950 if (!TLO.LegalOperations() && 951 !Op.getValueType().isVector() && 952 !Op.getOperand(0).getValueType().isVector() && 953 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 954 Op.getOperand(0).getValueType().isFloatingPoint()) { 955 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 956 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 957 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 958 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 959 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 960 // place. We expect the SHL to be eliminated by other optimizations. 961 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 962 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 963 if (!OpVTLegal && OpVTSizeInBits > 32) 964 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 965 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 966 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 967 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 968 Op.getValueType(), 969 Sign, ShAmt)); 970 } 971 } 972 break; 973 case ISD::ADD: 974 case ISD::MUL: 975 case ISD::SUB: { 976 // Add, Sub, and Mul don't demand any bits in positions beyond that 977 // of the highest bit demanded of them. 978 APInt LoMask = APInt::getLowBitsSet(BitWidth, 979 BitWidth - NewMask.countLeadingZeros()); 980 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 981 KnownOne2, TLO, Depth+1)) 982 return true; 983 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 984 KnownOne2, TLO, Depth+1)) 985 return true; 986 // See if the operation should be performed at a smaller bit width. 987 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 988 return true; 989 } 990 // FALL THROUGH 991 default: 992 // Just use ComputeMaskedBits to compute output bits. 993 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 994 break; 995 } 996 997 // If we know the value of all of the demanded bits, return this as a 998 // constant. 999 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1000 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1001 1002 return false; 1003} 1004 1005/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1006/// in Mask are known to be either zero or one and return them in the 1007/// KnownZero/KnownOne bitsets. 1008void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1009 APInt &KnownZero, 1010 APInt &KnownOne, 1011 const SelectionDAG &DAG, 1012 unsigned Depth) const { 1013 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1014 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1015 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1016 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1017 "Should use MaskedValueIsZero if you don't know whether Op" 1018 " is a target node!"); 1019 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1020} 1021 1022/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1023/// targets that want to expose additional information about sign bits to the 1024/// DAG Combiner. 1025unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1026 unsigned Depth) const { 1027 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1028 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1029 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1030 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1031 "Should use ComputeNumSignBits if you don't know whether Op" 1032 " is a target node!"); 1033 return 1; 1034} 1035 1036/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1037/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1038/// determine which bit is set. 1039/// 1040static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1041 // A left-shift of a constant one will have exactly one bit set, because 1042 // shifting the bit off the end is undefined. 1043 if (Val.getOpcode() == ISD::SHL) 1044 if (ConstantSDNode *C = 1045 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1046 if (C->getAPIntValue() == 1) 1047 return true; 1048 1049 // Similarly, a right-shift of a constant sign-bit will have exactly 1050 // one bit set. 1051 if (Val.getOpcode() == ISD::SRL) 1052 if (ConstantSDNode *C = 1053 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1054 if (C->getAPIntValue().isSignBit()) 1055 return true; 1056 1057 // More could be done here, though the above checks are enough 1058 // to handle some common cases. 1059 1060 // Fall back to ComputeMaskedBits to catch other known cases. 1061 EVT OpVT = Val.getValueType(); 1062 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1063 APInt KnownZero, KnownOne; 1064 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1065 return (KnownZero.countPopulation() == BitWidth - 1) && 1066 (KnownOne.countPopulation() == 1); 1067} 1068 1069/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1070/// and cc. If it is unable to simplify it, return a null SDValue. 1071SDValue 1072TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1073 ISD::CondCode Cond, bool foldBooleans, 1074 DAGCombinerInfo &DCI, SDLoc dl) const { 1075 SelectionDAG &DAG = DCI.DAG; 1076 1077 // These setcc operations always fold. 1078 switch (Cond) { 1079 default: break; 1080 case ISD::SETFALSE: 1081 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1082 case ISD::SETTRUE: 1083 case ISD::SETTRUE2: { 1084 TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector()); 1085 return DAG.getConstant( 1086 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT); 1087 } 1088 } 1089 1090 // Ensure that the constant occurs on the RHS, and fold constant 1091 // comparisons. 1092 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1093 if (isa<ConstantSDNode>(N0.getNode()) && 1094 (DCI.isBeforeLegalizeOps() || 1095 isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) 1096 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); 1097 1098 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1099 const APInt &C1 = N1C->getAPIntValue(); 1100 1101 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1102 // equality comparison, then we're just comparing whether X itself is 1103 // zero. 1104 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1105 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1106 N0.getOperand(1).getOpcode() == ISD::Constant) { 1107 const APInt &ShAmt 1108 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1109 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1110 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1111 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1112 // (srl (ctlz x), 5) == 0 -> X != 0 1113 // (srl (ctlz x), 5) != 1 -> X != 0 1114 Cond = ISD::SETNE; 1115 } else { 1116 // (srl (ctlz x), 5) != 0 -> X == 0 1117 // (srl (ctlz x), 5) == 1 -> X == 0 1118 Cond = ISD::SETEQ; 1119 } 1120 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1121 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1122 Zero, Cond); 1123 } 1124 } 1125 1126 SDValue CTPOP = N0; 1127 // Look through truncs that don't change the value of a ctpop. 1128 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1129 CTPOP = N0.getOperand(0); 1130 1131 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1132 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1133 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1134 EVT CTVT = CTPOP.getValueType(); 1135 SDValue CTOp = CTPOP.getOperand(0); 1136 1137 // (ctpop x) u< 2 -> (x & x-1) == 0 1138 // (ctpop x) u> 1 -> (x & x-1) != 0 1139 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1140 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1141 DAG.getConstant(1, CTVT)); 1142 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1143 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1144 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1145 } 1146 1147 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1148 } 1149 1150 // (zext x) == C --> x == (trunc C) 1151 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1152 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1153 unsigned MinBits = N0.getValueSizeInBits(); 1154 SDValue PreZExt; 1155 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1156 // ZExt 1157 MinBits = N0->getOperand(0).getValueSizeInBits(); 1158 PreZExt = N0->getOperand(0); 1159 } else if (N0->getOpcode() == ISD::AND) { 1160 // DAGCombine turns costly ZExts into ANDs 1161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1162 if ((C->getAPIntValue()+1).isPowerOf2()) { 1163 MinBits = C->getAPIntValue().countTrailingOnes(); 1164 PreZExt = N0->getOperand(0); 1165 } 1166 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1167 // ZEXTLOAD 1168 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1169 MinBits = LN0->getMemoryVT().getSizeInBits(); 1170 PreZExt = N0; 1171 } 1172 } 1173 1174 // Make sure we're not losing bits from the constant. 1175 if (MinBits > 0 && 1176 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) { 1177 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1178 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1179 // Will get folded away. 1180 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1181 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1182 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1183 } 1184 } 1185 } 1186 1187 // If the LHS is '(and load, const)', the RHS is 0, 1188 // the test is for equality or unsigned, and all 1 bits of the const are 1189 // in the same partial word, see if we can shorten the load. 1190 if (DCI.isBeforeLegalize() && 1191 !ISD::isSignedIntSetCC(Cond) && 1192 N0.getOpcode() == ISD::AND && C1 == 0 && 1193 N0.getNode()->hasOneUse() && 1194 isa<LoadSDNode>(N0.getOperand(0)) && 1195 N0.getOperand(0).getNode()->hasOneUse() && 1196 isa<ConstantSDNode>(N0.getOperand(1))) { 1197 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1198 APInt bestMask; 1199 unsigned bestWidth = 0, bestOffset = 0; 1200 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1201 unsigned origWidth = N0.getValueType().getSizeInBits(); 1202 unsigned maskWidth = origWidth; 1203 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1204 // 8 bits, but have to be careful... 1205 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1206 origWidth = Lod->getMemoryVT().getSizeInBits(); 1207 const APInt &Mask = 1208 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1209 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1210 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1211 for (unsigned offset=0; offset<origWidth/width; offset++) { 1212 if ((newMask & Mask) == Mask) { 1213 if (!getDataLayout()->isLittleEndian()) 1214 bestOffset = (origWidth/width - offset - 1) * (width/8); 1215 else 1216 bestOffset = (uint64_t)offset * (width/8); 1217 bestMask = Mask.lshr(offset * (width/8) * 8); 1218 bestWidth = width; 1219 break; 1220 } 1221 newMask = newMask << width; 1222 } 1223 } 1224 } 1225 if (bestWidth) { 1226 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 1227 if (newVT.isRound()) { 1228 EVT PtrType = Lod->getOperand(1).getValueType(); 1229 SDValue Ptr = Lod->getBasePtr(); 1230 if (bestOffset != 0) 1231 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1232 DAG.getConstant(bestOffset, PtrType)); 1233 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1234 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1235 Lod->getPointerInfo().getWithOffset(bestOffset), 1236 false, false, false, NewAlign); 1237 return DAG.getSetCC(dl, VT, 1238 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1239 DAG.getConstant(bestMask.trunc(bestWidth), 1240 newVT)), 1241 DAG.getConstant(0LL, newVT), Cond); 1242 } 1243 } 1244 } 1245 1246 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1247 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1248 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1249 1250 // If the comparison constant has bits in the upper part, the 1251 // zero-extended value could never match. 1252 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1253 C1.getBitWidth() - InSize))) { 1254 switch (Cond) { 1255 case ISD::SETUGT: 1256 case ISD::SETUGE: 1257 case ISD::SETEQ: return DAG.getConstant(0, VT); 1258 case ISD::SETULT: 1259 case ISD::SETULE: 1260 case ISD::SETNE: return DAG.getConstant(1, VT); 1261 case ISD::SETGT: 1262 case ISD::SETGE: 1263 // True if the sign bit of C1 is set. 1264 return DAG.getConstant(C1.isNegative(), VT); 1265 case ISD::SETLT: 1266 case ISD::SETLE: 1267 // True if the sign bit of C1 isn't set. 1268 return DAG.getConstant(C1.isNonNegative(), VT); 1269 default: 1270 break; 1271 } 1272 } 1273 1274 // Otherwise, we can perform the comparison with the low bits. 1275 switch (Cond) { 1276 case ISD::SETEQ: 1277 case ISD::SETNE: 1278 case ISD::SETUGT: 1279 case ISD::SETUGE: 1280 case ISD::SETULT: 1281 case ISD::SETULE: { 1282 EVT newVT = N0.getOperand(0).getValueType(); 1283 if (DCI.isBeforeLegalizeOps() || 1284 (isOperationLegal(ISD::SETCC, newVT) && 1285 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal)) 1286 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1287 DAG.getConstant(C1.trunc(InSize), newVT), 1288 Cond); 1289 break; 1290 } 1291 default: 1292 break; // todo, be more careful with signed comparisons 1293 } 1294 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1295 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1296 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1297 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1298 EVT ExtDstTy = N0.getValueType(); 1299 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1300 1301 // If the constant doesn't fit into the number of bits for the source of 1302 // the sign extension, it is impossible for both sides to be equal. 1303 if (C1.getMinSignedBits() > ExtSrcTyBits) 1304 return DAG.getConstant(Cond == ISD::SETNE, VT); 1305 1306 SDValue ZextOp; 1307 EVT Op0Ty = N0.getOperand(0).getValueType(); 1308 if (Op0Ty == ExtSrcTy) { 1309 ZextOp = N0.getOperand(0); 1310 } else { 1311 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1312 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1313 DAG.getConstant(Imm, Op0Ty)); 1314 } 1315 if (!DCI.isCalledByLegalizer()) 1316 DCI.AddToWorklist(ZextOp.getNode()); 1317 // Otherwise, make this a use of a zext. 1318 return DAG.getSetCC(dl, VT, ZextOp, 1319 DAG.getConstant(C1 & APInt::getLowBitsSet( 1320 ExtDstTyBits, 1321 ExtSrcTyBits), 1322 ExtDstTy), 1323 Cond); 1324 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1325 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1326 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1327 if (N0.getOpcode() == ISD::SETCC && 1328 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1329 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1330 if (TrueWhenTrue) 1331 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1332 // Invert the condition. 1333 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1334 CC = ISD::getSetCCInverse(CC, 1335 N0.getOperand(0).getValueType().isInteger()); 1336 if (DCI.isBeforeLegalizeOps() || 1337 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) 1338 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1339 } 1340 1341 if ((N0.getOpcode() == ISD::XOR || 1342 (N0.getOpcode() == ISD::AND && 1343 N0.getOperand(0).getOpcode() == ISD::XOR && 1344 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1345 isa<ConstantSDNode>(N0.getOperand(1)) && 1346 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1347 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1348 // can only do this if the top bits are known zero. 1349 unsigned BitWidth = N0.getValueSizeInBits(); 1350 if (DAG.MaskedValueIsZero(N0, 1351 APInt::getHighBitsSet(BitWidth, 1352 BitWidth-1))) { 1353 // Okay, get the un-inverted input value. 1354 SDValue Val; 1355 if (N0.getOpcode() == ISD::XOR) 1356 Val = N0.getOperand(0); 1357 else { 1358 assert(N0.getOpcode() == ISD::AND && 1359 N0.getOperand(0).getOpcode() == ISD::XOR); 1360 // ((X^1)&1)^1 -> X & 1 1361 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1362 N0.getOperand(0).getOperand(0), 1363 N0.getOperand(1)); 1364 } 1365 1366 return DAG.getSetCC(dl, VT, Val, N1, 1367 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1368 } 1369 } else if (N1C->getAPIntValue() == 1 && 1370 (VT == MVT::i1 || 1371 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 1372 SDValue Op0 = N0; 1373 if (Op0.getOpcode() == ISD::TRUNCATE) 1374 Op0 = Op0.getOperand(0); 1375 1376 if ((Op0.getOpcode() == ISD::XOR) && 1377 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1378 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1379 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1380 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1381 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1382 Cond); 1383 } 1384 if (Op0.getOpcode() == ISD::AND && 1385 isa<ConstantSDNode>(Op0.getOperand(1)) && 1386 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1387 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1388 if (Op0.getValueType().bitsGT(VT)) 1389 Op0 = DAG.getNode(ISD::AND, dl, VT, 1390 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1391 DAG.getConstant(1, VT)); 1392 else if (Op0.getValueType().bitsLT(VT)) 1393 Op0 = DAG.getNode(ISD::AND, dl, VT, 1394 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1395 DAG.getConstant(1, VT)); 1396 1397 return DAG.getSetCC(dl, VT, Op0, 1398 DAG.getConstant(0, Op0.getValueType()), 1399 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1400 } 1401 if (Op0.getOpcode() == ISD::AssertZext && 1402 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 1403 return DAG.getSetCC(dl, VT, Op0, 1404 DAG.getConstant(0, Op0.getValueType()), 1405 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1406 } 1407 } 1408 1409 APInt MinVal, MaxVal; 1410 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1411 if (ISD::isSignedIntSetCC(Cond)) { 1412 MinVal = APInt::getSignedMinValue(OperandBitSize); 1413 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1414 } else { 1415 MinVal = APInt::getMinValue(OperandBitSize); 1416 MaxVal = APInt::getMaxValue(OperandBitSize); 1417 } 1418 1419 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1420 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1421 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1422 // X >= C0 --> X > (C0-1) 1423 return DAG.getSetCC(dl, VT, N0, 1424 DAG.getConstant(C1-1, N1.getValueType()), 1425 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1426 } 1427 1428 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1429 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1430 // X <= C0 --> X < (C0+1) 1431 return DAG.getSetCC(dl, VT, N0, 1432 DAG.getConstant(C1+1, N1.getValueType()), 1433 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1434 } 1435 1436 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1437 return DAG.getConstant(0, VT); // X < MIN --> false 1438 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1439 return DAG.getConstant(1, VT); // X >= MIN --> true 1440 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1441 return DAG.getConstant(0, VT); // X > MAX --> false 1442 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1443 return DAG.getConstant(1, VT); // X <= MAX --> true 1444 1445 // Canonicalize setgt X, Min --> setne X, Min 1446 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1447 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1448 // Canonicalize setlt X, Max --> setne X, Max 1449 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1450 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1451 1452 // If we have setult X, 1, turn it into seteq X, 0 1453 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1454 return DAG.getSetCC(dl, VT, N0, 1455 DAG.getConstant(MinVal, N0.getValueType()), 1456 ISD::SETEQ); 1457 // If we have setugt X, Max-1, turn it into seteq X, Max 1458 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1459 return DAG.getSetCC(dl, VT, N0, 1460 DAG.getConstant(MaxVal, N0.getValueType()), 1461 ISD::SETEQ); 1462 1463 // If we have "setcc X, C0", check to see if we can shrink the immediate 1464 // by changing cc. 1465 1466 // SETUGT X, SINTMAX -> SETLT X, 0 1467 if (Cond == ISD::SETUGT && 1468 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1469 return DAG.getSetCC(dl, VT, N0, 1470 DAG.getConstant(0, N1.getValueType()), 1471 ISD::SETLT); 1472 1473 // SETULT X, SINTMIN -> SETGT X, -1 1474 if (Cond == ISD::SETULT && 1475 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1476 SDValue ConstMinusOne = 1477 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1478 N1.getValueType()); 1479 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1480 } 1481 1482 // Fold bit comparisons when we can. 1483 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1484 (VT == N0.getValueType() || 1485 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1486 N0.getOpcode() == ISD::AND) 1487 if (ConstantSDNode *AndRHS = 1488 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1489 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1490 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1491 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1492 // Perform the xform if the AND RHS is a single bit. 1493 if (AndRHS->getAPIntValue().isPowerOf2()) { 1494 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1495 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1496 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1497 } 1498 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1499 // (X & 8) == 8 --> (X & 8) >> 3 1500 // Perform the xform if C1 is a single bit. 1501 if (C1.isPowerOf2()) { 1502 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1503 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1504 DAG.getConstant(C1.logBase2(), ShiftTy))); 1505 } 1506 } 1507 } 1508 1509 if (C1.getMinSignedBits() <= 64 && 1510 !isLegalICmpImmediate(C1.getSExtValue())) { 1511 // (X & -256) == 256 -> (X >> 8) == 1 1512 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1513 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 1514 if (ConstantSDNode *AndRHS = 1515 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1516 const APInt &AndRHSC = AndRHS->getAPIntValue(); 1517 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 1518 unsigned ShiftBits = AndRHSC.countTrailingZeros(); 1519 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1520 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1521 EVT CmpTy = N0.getValueType(); 1522 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 1523 DAG.getConstant(ShiftBits, ShiftTy)); 1524 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 1525 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1526 } 1527 } 1528 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 1529 Cond == ISD::SETULE || Cond == ISD::SETUGT) { 1530 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 1531 // X < 0x100000000 -> (X >> 32) < 1 1532 // X >= 0x100000000 -> (X >> 32) >= 1 1533 // X <= 0x0ffffffff -> (X >> 32) < 1 1534 // X > 0x0ffffffff -> (X >> 32) >= 1 1535 unsigned ShiftBits; 1536 APInt NewC = C1; 1537 ISD::CondCode NewCond = Cond; 1538 if (AdjOne) { 1539 ShiftBits = C1.countTrailingOnes(); 1540 NewC = NewC + 1; 1541 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1542 } else { 1543 ShiftBits = C1.countTrailingZeros(); 1544 } 1545 NewC = NewC.lshr(ShiftBits); 1546 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 1547 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1548 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1549 EVT CmpTy = N0.getValueType(); 1550 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 1551 DAG.getConstant(ShiftBits, ShiftTy)); 1552 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 1553 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 1554 } 1555 } 1556 } 1557 } 1558 1559 if (isa<ConstantFPSDNode>(N0.getNode())) { 1560 // Constant fold or commute setcc. 1561 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1562 if (O.getNode()) return O; 1563 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1564 // If the RHS of an FP comparison is a constant, simplify it away in 1565 // some cases. 1566 if (CFP->getValueAPF().isNaN()) { 1567 // If an operand is known to be a nan, we can fold it. 1568 switch (ISD::getUnorderedFlavor(Cond)) { 1569 default: llvm_unreachable("Unknown flavor!"); 1570 case 0: // Known false. 1571 return DAG.getConstant(0, VT); 1572 case 1: // Known true. 1573 return DAG.getConstant(1, VT); 1574 case 2: // Undefined. 1575 return DAG.getUNDEF(VT); 1576 } 1577 } 1578 1579 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1580 // constant if knowing that the operand is non-nan is enough. We prefer to 1581 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1582 // materialize 0.0. 1583 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1584 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1585 1586 // If the condition is not legal, see if we can find an equivalent one 1587 // which is legal. 1588 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1589 // If the comparison was an awkward floating-point == or != and one of 1590 // the comparison operands is infinity or negative infinity, convert the 1591 // condition to a less-awkward <= or >=. 1592 if (CFP->getValueAPF().isInfinity()) { 1593 if (CFP->getValueAPF().isNegative()) { 1594 if (Cond == ISD::SETOEQ && 1595 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 1597 if (Cond == ISD::SETUEQ && 1598 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1599 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 1600 if (Cond == ISD::SETUNE && 1601 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 1603 if (Cond == ISD::SETONE && 1604 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1605 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 1606 } else { 1607 if (Cond == ISD::SETOEQ && 1608 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1609 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 1610 if (Cond == ISD::SETUEQ && 1611 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1612 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 1613 if (Cond == ISD::SETUNE && 1614 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1615 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 1616 if (Cond == ISD::SETONE && 1617 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1618 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 1619 } 1620 } 1621 } 1622 } 1623 1624 if (N0 == N1) { 1625 // The sext(setcc()) => setcc() optimization relies on the appropriate 1626 // constant being emitted. 1627 uint64_t EqVal = 0; 1628 switch (getBooleanContents(N0.getValueType().isVector())) { 1629 case UndefinedBooleanContent: 1630 case ZeroOrOneBooleanContent: 1631 EqVal = ISD::isTrueWhenEqual(Cond); 1632 break; 1633 case ZeroOrNegativeOneBooleanContent: 1634 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 1635 break; 1636 } 1637 1638 // We can always fold X == X for integer setcc's. 1639 if (N0.getValueType().isInteger()) { 1640 return DAG.getConstant(EqVal, VT); 1641 } 1642 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1643 if (UOF == 2) // FP operators that are undefined on NaNs. 1644 return DAG.getConstant(EqVal, VT); 1645 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1646 return DAG.getConstant(EqVal, VT); 1647 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1648 // if it is not already. 1649 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1650 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 1651 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 1652 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1653 } 1654 1655 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1656 N0.getValueType().isInteger()) { 1657 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1658 N0.getOpcode() == ISD::XOR) { 1659 // Simplify (X+Y) == (X+Z) --> Y == Z 1660 if (N0.getOpcode() == N1.getOpcode()) { 1661 if (N0.getOperand(0) == N1.getOperand(0)) 1662 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1663 if (N0.getOperand(1) == N1.getOperand(1)) 1664 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1665 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1666 // If X op Y == Y op X, try other combinations. 1667 if (N0.getOperand(0) == N1.getOperand(1)) 1668 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1669 Cond); 1670 if (N0.getOperand(1) == N1.getOperand(0)) 1671 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1672 Cond); 1673 } 1674 } 1675 1676 // If RHS is a legal immediate value for a compare instruction, we need 1677 // to be careful about increasing register pressure needlessly. 1678 bool LegalRHSImm = false; 1679 1680 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1681 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1682 // Turn (X+C1) == C2 --> X == C2-C1 1683 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1684 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1685 DAG.getConstant(RHSC->getAPIntValue()- 1686 LHSR->getAPIntValue(), 1687 N0.getValueType()), Cond); 1688 } 1689 1690 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1691 if (N0.getOpcode() == ISD::XOR) 1692 // If we know that all of the inverted bits are zero, don't bother 1693 // performing the inversion. 1694 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1695 return 1696 DAG.getSetCC(dl, VT, N0.getOperand(0), 1697 DAG.getConstant(LHSR->getAPIntValue() ^ 1698 RHSC->getAPIntValue(), 1699 N0.getValueType()), 1700 Cond); 1701 } 1702 1703 // Turn (C1-X) == C2 --> X == C1-C2 1704 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1705 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1706 return 1707 DAG.getSetCC(dl, VT, N0.getOperand(1), 1708 DAG.getConstant(SUBC->getAPIntValue() - 1709 RHSC->getAPIntValue(), 1710 N0.getValueType()), 1711 Cond); 1712 } 1713 } 1714 1715 // Could RHSC fold directly into a compare? 1716 if (RHSC->getValueType(0).getSizeInBits() <= 64) 1717 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 1718 } 1719 1720 // Simplify (X+Z) == X --> Z == 0 1721 // Don't do this if X is an immediate that can fold into a cmp 1722 // instruction and X+Z has other uses. It could be an induction variable 1723 // chain, and the transform would increase register pressure. 1724 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 1725 if (N0.getOperand(0) == N1) 1726 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1727 DAG.getConstant(0, N0.getValueType()), Cond); 1728 if (N0.getOperand(1) == N1) { 1729 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1730 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1731 DAG.getConstant(0, N0.getValueType()), Cond); 1732 if (N0.getNode()->hasOneUse()) { 1733 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1734 // (Z-X) == X --> Z == X<<1 1735 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 1736 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 1737 if (!DCI.isCalledByLegalizer()) 1738 DCI.AddToWorklist(SH.getNode()); 1739 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1740 } 1741 } 1742 } 1743 } 1744 1745 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1746 N1.getOpcode() == ISD::XOR) { 1747 // Simplify X == (X+Z) --> Z == 0 1748 if (N1.getOperand(0) == N0) 1749 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1750 DAG.getConstant(0, N1.getValueType()), Cond); 1751 if (N1.getOperand(1) == N0) { 1752 if (DAG.isCommutativeBinOp(N1.getOpcode())) 1753 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1754 DAG.getConstant(0, N1.getValueType()), Cond); 1755 if (N1.getNode()->hasOneUse()) { 1756 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1757 // X == (Z-X) --> X<<1 == Z 1758 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1759 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 1760 if (!DCI.isCalledByLegalizer()) 1761 DCI.AddToWorklist(SH.getNode()); 1762 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1763 } 1764 } 1765 } 1766 1767 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1768 // Note that where y is variable and is known to have at most 1769 // one bit set (for example, if it is z&1) we cannot do this; 1770 // the expressions are not equivalent when y==0. 1771 if (N0.getOpcode() == ISD::AND) 1772 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1773 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1774 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1775 if (DCI.isBeforeLegalizeOps() || 1776 isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1777 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1778 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1779 } 1780 } 1781 } 1782 if (N1.getOpcode() == ISD::AND) 1783 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1784 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1785 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1786 if (DCI.isBeforeLegalizeOps() || 1787 isCondCodeLegal(Cond, N1.getSimpleValueType())) { 1788 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1789 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1790 } 1791 } 1792 } 1793 } 1794 1795 // Fold away ALL boolean setcc's. 1796 SDValue Temp; 1797 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1798 switch (Cond) { 1799 default: llvm_unreachable("Unknown integer setcc!"); 1800 case ISD::SETEQ: // X == Y -> ~(X^Y) 1801 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1802 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1803 if (!DCI.isCalledByLegalizer()) 1804 DCI.AddToWorklist(Temp.getNode()); 1805 break; 1806 case ISD::SETNE: // X != Y --> (X^Y) 1807 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1808 break; 1809 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1810 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1811 Temp = DAG.getNOT(dl, N0, MVT::i1); 1812 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1813 if (!DCI.isCalledByLegalizer()) 1814 DCI.AddToWorklist(Temp.getNode()); 1815 break; 1816 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1817 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1818 Temp = DAG.getNOT(dl, N1, MVT::i1); 1819 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 1820 if (!DCI.isCalledByLegalizer()) 1821 DCI.AddToWorklist(Temp.getNode()); 1822 break; 1823 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1824 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1825 Temp = DAG.getNOT(dl, N0, MVT::i1); 1826 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 1827 if (!DCI.isCalledByLegalizer()) 1828 DCI.AddToWorklist(Temp.getNode()); 1829 break; 1830 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1831 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1832 Temp = DAG.getNOT(dl, N1, MVT::i1); 1833 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 1834 break; 1835 } 1836 if (VT != MVT::i1) { 1837 if (!DCI.isCalledByLegalizer()) 1838 DCI.AddToWorklist(N0.getNode()); 1839 // FIXME: If running after legalize, we probably can't do this. 1840 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 1841 } 1842 return N0; 1843 } 1844 1845 // Could not fold it. 1846 return SDValue(); 1847} 1848 1849/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1850/// node is a GlobalAddress + offset. 1851bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 1852 int64_t &Offset) const { 1853 if (isa<GlobalAddressSDNode>(N)) { 1854 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1855 GA = GASD->getGlobal(); 1856 Offset += GASD->getOffset(); 1857 return true; 1858 } 1859 1860 if (N->getOpcode() == ISD::ADD) { 1861 SDValue N1 = N->getOperand(0); 1862 SDValue N2 = N->getOperand(1); 1863 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1864 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1865 if (V) { 1866 Offset += V->getSExtValue(); 1867 return true; 1868 } 1869 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1870 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1871 if (V) { 1872 Offset += V->getSExtValue(); 1873 return true; 1874 } 1875 } 1876 } 1877 1878 return false; 1879} 1880 1881 1882SDValue TargetLowering:: 1883PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1884 // Default implementation: no optimization. 1885 return SDValue(); 1886} 1887 1888//===----------------------------------------------------------------------===// 1889// Inline Assembler Implementation Methods 1890//===----------------------------------------------------------------------===// 1891 1892 1893TargetLowering::ConstraintType 1894TargetLowering::getConstraintType(const std::string &Constraint) const { 1895 unsigned S = Constraint.size(); 1896 1897 if (S == 1) { 1898 switch (Constraint[0]) { 1899 default: break; 1900 case 'r': return C_RegisterClass; 1901 case 'm': // memory 1902 case 'o': // offsetable 1903 case 'V': // not offsetable 1904 return C_Memory; 1905 case 'i': // Simple Integer or Relocatable Constant 1906 case 'n': // Simple Integer 1907 case 'E': // Floating Point Constant 1908 case 'F': // Floating Point Constant 1909 case 's': // Relocatable Constant 1910 case 'p': // Address. 1911 case 'X': // Allow ANY value. 1912 case 'I': // Target registers. 1913 case 'J': 1914 case 'K': 1915 case 'L': 1916 case 'M': 1917 case 'N': 1918 case 'O': 1919 case 'P': 1920 case '<': 1921 case '>': 1922 return C_Other; 1923 } 1924 } 1925 1926 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { 1927 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" 1928 return C_Memory; 1929 return C_Register; 1930 } 1931 return C_Unknown; 1932} 1933 1934/// LowerXConstraint - try to replace an X constraint, which matches anything, 1935/// with another that has more specific requirements based on the type of the 1936/// corresponding operand. 1937const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 1938 if (ConstraintVT.isInteger()) 1939 return "r"; 1940 if (ConstraintVT.isFloatingPoint()) 1941 return "f"; // works for many targets 1942 return 0; 1943} 1944 1945/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1946/// vector. If it is invalid, don't add anything to Ops. 1947void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1948 std::string &Constraint, 1949 std::vector<SDValue> &Ops, 1950 SelectionDAG &DAG) const { 1951 1952 if (Constraint.length() > 1) return; 1953 1954 char ConstraintLetter = Constraint[0]; 1955 switch (ConstraintLetter) { 1956 default: break; 1957 case 'X': // Allows any operand; labels (basic block) use this. 1958 if (Op.getOpcode() == ISD::BasicBlock) { 1959 Ops.push_back(Op); 1960 return; 1961 } 1962 // fall through 1963 case 'i': // Simple Integer or Relocatable Constant 1964 case 'n': // Simple Integer 1965 case 's': { // Relocatable Constant 1966 // These operands are interested in values of the form (GV+C), where C may 1967 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1968 // is possible and fine if either GV or C are missing. 1969 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1970 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1971 1972 // If we have "(add GV, C)", pull out GV/C 1973 if (Op.getOpcode() == ISD::ADD) { 1974 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1975 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1976 if (C == 0 || GA == 0) { 1977 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1978 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1979 } 1980 if (C == 0 || GA == 0) 1981 C = 0, GA = 0; 1982 } 1983 1984 // If we find a valid operand, map to the TargetXXX version so that the 1985 // value itself doesn't get selected. 1986 if (GA) { // Either &GV or &GV+C 1987 if (ConstraintLetter != 'n') { 1988 int64_t Offs = GA->getOffset(); 1989 if (C) Offs += C->getZExtValue(); 1990 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1991 C ? SDLoc(C) : SDLoc(), 1992 Op.getValueType(), Offs)); 1993 return; 1994 } 1995 } 1996 if (C) { // just C, no GV. 1997 // Simple constants are not allowed for 's'. 1998 if (ConstraintLetter != 's') { 1999 // gcc prints these as sign extended. Sign extend value to 64 bits 2000 // now; without this it would get ZExt'd later in 2001 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2002 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2003 MVT::i64)); 2004 return; 2005 } 2006 } 2007 break; 2008 } 2009 } 2010} 2011 2012std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2013getRegForInlineAsmConstraint(const std::string &Constraint, 2014 MVT VT) const { 2015 if (Constraint.empty() || Constraint[0] != '{') 2016 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2017 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2018 2019 // Remove the braces from around the name. 2020 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2021 2022 std::pair<unsigned, const TargetRegisterClass*> R = 2023 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2024 2025 // Figure out which register class contains this reg. 2026 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo(); 2027 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2028 E = RI->regclass_end(); RCI != E; ++RCI) { 2029 const TargetRegisterClass *RC = *RCI; 2030 2031 // If none of the value types for this register class are valid, we 2032 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2033 if (!isLegalRC(RC)) 2034 continue; 2035 2036 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2037 I != E; ++I) { 2038 if (RegName.equals_lower(RI->getName(*I))) { 2039 std::pair<unsigned, const TargetRegisterClass*> S = 2040 std::make_pair(*I, RC); 2041 2042 // If this register class has the requested value type, return it, 2043 // otherwise keep searching and return the first class found 2044 // if no other is found which explicitly has the requested type. 2045 if (RC->hasType(VT)) 2046 return S; 2047 else if (!R.second) 2048 R = S; 2049 } 2050 } 2051 } 2052 2053 return R; 2054} 2055 2056//===----------------------------------------------------------------------===// 2057// Constraint Selection. 2058 2059/// isMatchingInputConstraint - Return true of this is an input operand that is 2060/// a matching constraint like "4". 2061bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2062 assert(!ConstraintCode.empty() && "No known constraint!"); 2063 return isdigit(static_cast<unsigned char>(ConstraintCode[0])); 2064} 2065 2066/// getMatchedOperand - If this is an input matching constraint, this method 2067/// returns the output operand it matches. 2068unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2069 assert(!ConstraintCode.empty() && "No known constraint!"); 2070 return atoi(ConstraintCode.c_str()); 2071} 2072 2073 2074/// ParseConstraints - Split up the constraint string from the inline 2075/// assembly value into the specific constraints and their prefixes, 2076/// and also tie in the associated operand values. 2077/// If this returns an empty vector, and if the constraint string itself 2078/// isn't empty, there was an error parsing. 2079TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2080 ImmutableCallSite CS) const { 2081 /// ConstraintOperands - Information about all of the constraints. 2082 AsmOperandInfoVector ConstraintOperands; 2083 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2084 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2085 2086 // Do a prepass over the constraints, canonicalizing them, and building up the 2087 // ConstraintOperands list. 2088 InlineAsm::ConstraintInfoVector 2089 ConstraintInfos = IA->ParseConstraints(); 2090 2091 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2092 unsigned ResNo = 0; // ResNo - The result number of the next output. 2093 2094 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2095 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2096 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2097 2098 // Update multiple alternative constraint count. 2099 if (OpInfo.multipleAlternatives.size() > maCount) 2100 maCount = OpInfo.multipleAlternatives.size(); 2101 2102 OpInfo.ConstraintVT = MVT::Other; 2103 2104 // Compute the value type for each operand. 2105 switch (OpInfo.Type) { 2106 case InlineAsm::isOutput: 2107 // Indirect outputs just consume an argument. 2108 if (OpInfo.isIndirect) { 2109 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2110 break; 2111 } 2112 2113 // The return value of the call is this value. As such, there is no 2114 // corresponding argument. 2115 assert(!CS.getType()->isVoidTy() && 2116 "Bad inline asm!"); 2117 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2118 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); 2119 } else { 2120 assert(ResNo == 0 && "Asm only has one result!"); 2121 OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); 2122 } 2123 ++ResNo; 2124 break; 2125 case InlineAsm::isInput: 2126 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2127 break; 2128 case InlineAsm::isClobber: 2129 // Nothing to do. 2130 break; 2131 } 2132 2133 if (OpInfo.CallOperandVal) { 2134 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2135 if (OpInfo.isIndirect) { 2136 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2137 if (!PtrTy) 2138 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2139 OpTy = PtrTy->getElementType(); 2140 } 2141 2142 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2143 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2144 if (STy->getNumElements() == 1) 2145 OpTy = STy->getElementType(0); 2146 2147 // If OpTy is not a single value, it may be a struct/union that we 2148 // can tile with integers. 2149 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2150 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy); 2151 switch (BitSize) { 2152 default: break; 2153 case 1: 2154 case 8: 2155 case 16: 2156 case 32: 2157 case 64: 2158 case 128: 2159 OpInfo.ConstraintVT = 2160 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2161 break; 2162 } 2163 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 2164 unsigned PtrSize 2165 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace()); 2166 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); 2167 } else { 2168 OpInfo.ConstraintVT = MVT::getVT(OpTy, true); 2169 } 2170 } 2171 } 2172 2173 // If we have multiple alternative constraints, select the best alternative. 2174 if (ConstraintInfos.size()) { 2175 if (maCount) { 2176 unsigned bestMAIndex = 0; 2177 int bestWeight = -1; 2178 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2179 int weight = -1; 2180 unsigned maIndex; 2181 // Compute the sums of the weights for each alternative, keeping track 2182 // of the best (highest weight) one so far. 2183 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2184 int weightSum = 0; 2185 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2186 cIndex != eIndex; ++cIndex) { 2187 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2188 if (OpInfo.Type == InlineAsm::isClobber) 2189 continue; 2190 2191 // If this is an output operand with a matching input operand, 2192 // look up the matching input. If their types mismatch, e.g. one 2193 // is an integer, the other is floating point, or their sizes are 2194 // different, flag it as an maCantMatch. 2195 if (OpInfo.hasMatchingInput()) { 2196 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2197 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2198 if ((OpInfo.ConstraintVT.isInteger() != 2199 Input.ConstraintVT.isInteger()) || 2200 (OpInfo.ConstraintVT.getSizeInBits() != 2201 Input.ConstraintVT.getSizeInBits())) { 2202 weightSum = -1; // Can't match. 2203 break; 2204 } 2205 } 2206 } 2207 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2208 if (weight == -1) { 2209 weightSum = -1; 2210 break; 2211 } 2212 weightSum += weight; 2213 } 2214 // Update best. 2215 if (weightSum > bestWeight) { 2216 bestWeight = weightSum; 2217 bestMAIndex = maIndex; 2218 } 2219 } 2220 2221 // Now select chosen alternative in each constraint. 2222 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2223 cIndex != eIndex; ++cIndex) { 2224 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2225 if (cInfo.Type == InlineAsm::isClobber) 2226 continue; 2227 cInfo.selectAlternative(bestMAIndex); 2228 } 2229 } 2230 } 2231 2232 // Check and hook up tied operands, choose constraint code to use. 2233 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2234 cIndex != eIndex; ++cIndex) { 2235 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2236 2237 // If this is an output operand with a matching input operand, look up the 2238 // matching input. If their types mismatch, e.g. one is an integer, the 2239 // other is floating point, or their sizes are different, flag it as an 2240 // error. 2241 if (OpInfo.hasMatchingInput()) { 2242 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2243 2244 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2245 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 2246 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 2247 OpInfo.ConstraintVT); 2248 std::pair<unsigned, const TargetRegisterClass*> InputRC = 2249 getRegForInlineAsmConstraint(Input.ConstraintCode, 2250 Input.ConstraintVT); 2251 if ((OpInfo.ConstraintVT.isInteger() != 2252 Input.ConstraintVT.isInteger()) || 2253 (MatchRC.second != InputRC.second)) { 2254 report_fatal_error("Unsupported asm: input constraint" 2255 " with a matching output constraint of" 2256 " incompatible type!"); 2257 } 2258 } 2259 2260 } 2261 } 2262 2263 return ConstraintOperands; 2264} 2265 2266 2267/// getConstraintGenerality - Return an integer indicating how general CT 2268/// is. 2269static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2270 switch (CT) { 2271 case TargetLowering::C_Other: 2272 case TargetLowering::C_Unknown: 2273 return 0; 2274 case TargetLowering::C_Register: 2275 return 1; 2276 case TargetLowering::C_RegisterClass: 2277 return 2; 2278 case TargetLowering::C_Memory: 2279 return 3; 2280 } 2281 llvm_unreachable("Invalid constraint type"); 2282} 2283 2284/// Examine constraint type and operand type and determine a weight value. 2285/// This object must already have been set up with the operand type 2286/// and the current alternative constraint selected. 2287TargetLowering::ConstraintWeight 2288 TargetLowering::getMultipleConstraintMatchWeight( 2289 AsmOperandInfo &info, int maIndex) const { 2290 InlineAsm::ConstraintCodeVector *rCodes; 2291 if (maIndex >= (int)info.multipleAlternatives.size()) 2292 rCodes = &info.Codes; 2293 else 2294 rCodes = &info.multipleAlternatives[maIndex].Codes; 2295 ConstraintWeight BestWeight = CW_Invalid; 2296 2297 // Loop over the options, keeping track of the most general one. 2298 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2299 ConstraintWeight weight = 2300 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2301 if (weight > BestWeight) 2302 BestWeight = weight; 2303 } 2304 2305 return BestWeight; 2306} 2307 2308/// Examine constraint type and operand type and determine a weight value. 2309/// This object must already have been set up with the operand type 2310/// and the current alternative constraint selected. 2311TargetLowering::ConstraintWeight 2312 TargetLowering::getSingleConstraintMatchWeight( 2313 AsmOperandInfo &info, const char *constraint) const { 2314 ConstraintWeight weight = CW_Invalid; 2315 Value *CallOperandVal = info.CallOperandVal; 2316 // If we don't have a value, we can't do a match, 2317 // but allow it at the lowest weight. 2318 if (CallOperandVal == NULL) 2319 return CW_Default; 2320 // Look at the constraint type. 2321 switch (*constraint) { 2322 case 'i': // immediate integer. 2323 case 'n': // immediate integer with a known value. 2324 if (isa<ConstantInt>(CallOperandVal)) 2325 weight = CW_Constant; 2326 break; 2327 case 's': // non-explicit intregal immediate. 2328 if (isa<GlobalValue>(CallOperandVal)) 2329 weight = CW_Constant; 2330 break; 2331 case 'E': // immediate float if host format. 2332 case 'F': // immediate float. 2333 if (isa<ConstantFP>(CallOperandVal)) 2334 weight = CW_Constant; 2335 break; 2336 case '<': // memory operand with autodecrement. 2337 case '>': // memory operand with autoincrement. 2338 case 'm': // memory operand. 2339 case 'o': // offsettable memory operand 2340 case 'V': // non-offsettable memory operand 2341 weight = CW_Memory; 2342 break; 2343 case 'r': // general register. 2344 case 'g': // general register, memory operand or immediate integer. 2345 // note: Clang converts "g" to "imr". 2346 if (CallOperandVal->getType()->isIntegerTy()) 2347 weight = CW_Register; 2348 break; 2349 case 'X': // any operand. 2350 default: 2351 weight = CW_Default; 2352 break; 2353 } 2354 return weight; 2355} 2356 2357/// ChooseConstraint - If there are multiple different constraints that we 2358/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2359/// This is somewhat tricky: constraints fall into four classes: 2360/// Other -> immediates and magic values 2361/// Register -> one specific register 2362/// RegisterClass -> a group of regs 2363/// Memory -> memory 2364/// Ideally, we would pick the most specific constraint possible: if we have 2365/// something that fits into a register, we would pick it. The problem here 2366/// is that if we have something that could either be in a register or in 2367/// memory that use of the register could cause selection of *other* 2368/// operands to fail: they might only succeed if we pick memory. Because of 2369/// this the heuristic we use is: 2370/// 2371/// 1) If there is an 'other' constraint, and if the operand is valid for 2372/// that constraint, use it. This makes us take advantage of 'i' 2373/// constraints when available. 2374/// 2) Otherwise, pick the most general constraint present. This prefers 2375/// 'm' over 'r', for example. 2376/// 2377static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2378 const TargetLowering &TLI, 2379 SDValue Op, SelectionDAG *DAG) { 2380 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2381 unsigned BestIdx = 0; 2382 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2383 int BestGenerality = -1; 2384 2385 // Loop over the options, keeping track of the most general one. 2386 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2387 TargetLowering::ConstraintType CType = 2388 TLI.getConstraintType(OpInfo.Codes[i]); 2389 2390 // If this is an 'other' constraint, see if the operand is valid for it. 2391 // For example, on X86 we might have an 'rI' constraint. If the operand 2392 // is an integer in the range [0..31] we want to use I (saving a load 2393 // of a register), otherwise we must use 'r'. 2394 if (CType == TargetLowering::C_Other && Op.getNode()) { 2395 assert(OpInfo.Codes[i].size() == 1 && 2396 "Unhandled multi-letter 'other' constraint"); 2397 std::vector<SDValue> ResultOps; 2398 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 2399 ResultOps, *DAG); 2400 if (!ResultOps.empty()) { 2401 BestType = CType; 2402 BestIdx = i; 2403 break; 2404 } 2405 } 2406 2407 // Things with matching constraints can only be registers, per gcc 2408 // documentation. This mainly affects "g" constraints. 2409 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2410 continue; 2411 2412 // This constraint letter is more general than the previous one, use it. 2413 int Generality = getConstraintGenerality(CType); 2414 if (Generality > BestGenerality) { 2415 BestType = CType; 2416 BestIdx = i; 2417 BestGenerality = Generality; 2418 } 2419 } 2420 2421 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2422 OpInfo.ConstraintType = BestType; 2423} 2424 2425/// ComputeConstraintToUse - Determines the constraint code and constraint 2426/// type to use for the specific AsmOperandInfo, setting 2427/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2428void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2429 SDValue Op, 2430 SelectionDAG *DAG) const { 2431 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2432 2433 // Single-letter constraints ('r') are very common. 2434 if (OpInfo.Codes.size() == 1) { 2435 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2436 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2437 } else { 2438 ChooseConstraint(OpInfo, *this, Op, DAG); 2439 } 2440 2441 // 'X' matches anything. 2442 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2443 // Labels and constants are handled elsewhere ('X' is the only thing 2444 // that matches labels). For Functions, the type here is the type of 2445 // the result, which is not what we want to look at; leave them alone. 2446 Value *v = OpInfo.CallOperandVal; 2447 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2448 OpInfo.CallOperandVal = v; 2449 return; 2450 } 2451 2452 // Otherwise, try to resolve it to something we know about by looking at 2453 // the actual operand type. 2454 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2455 OpInfo.ConstraintCode = Repl; 2456 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2457 } 2458 } 2459} 2460 2461/// \brief Given an exact SDIV by a constant, create a multiplication 2462/// with the multiplicative inverse of the constant. 2463SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2464 SelectionDAG &DAG) const { 2465 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2466 APInt d = C->getAPIntValue(); 2467 assert(d != 0 && "Division by zero!"); 2468 2469 // Shift the value upfront if it is even, so the LSB is one. 2470 unsigned ShAmt = d.countTrailingZeros(); 2471 if (ShAmt) { 2472 // TODO: For UDIV use SRL instead of SRA. 2473 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 2474 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 2475 d = d.ashr(ShAmt); 2476 } 2477 2478 // Calculate the multiplicative inverse, using Newton's method. 2479 APInt t, xn = d; 2480 while ((t = d*xn) != 1) 2481 xn *= APInt(d.getBitWidth(), 2) - t; 2482 2483 Op2 = DAG.getConstant(xn, Op1.getValueType()); 2484 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 2485} 2486 2487/// \brief Given an ISD::SDIV node expressing a divide by constant, 2488/// return a DAG expression to select that will generate the same value by 2489/// multiplying by a magic number. See: 2490/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2491SDValue TargetLowering:: 2492BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2493 std::vector<SDNode*> *Created) const { 2494 EVT VT = N->getValueType(0); 2495 SDLoc dl(N); 2496 2497 // Check to see if we can do this. 2498 // FIXME: We should be more aggressive here. 2499 if (!isTypeLegal(VT)) 2500 return SDValue(); 2501 2502 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2503 APInt::ms magics = d.magic(); 2504 2505 // Multiply the numerator (operand 0) by the magic value 2506 // FIXME: We should support doing a MUL in a wider type 2507 SDValue Q; 2508 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 2509 isOperationLegalOrCustom(ISD::MULHS, VT)) 2510 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2511 DAG.getConstant(magics.m, VT)); 2512 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 2513 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2514 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2515 N->getOperand(0), 2516 DAG.getConstant(magics.m, VT)).getNode(), 1); 2517 else 2518 return SDValue(); // No mulhs or equvialent 2519 // If d > 0 and m < 0, add the numerator 2520 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2521 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2522 if (Created) 2523 Created->push_back(Q.getNode()); 2524 } 2525 // If d < 0 and m > 0, subtract the numerator. 2526 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2527 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2528 if (Created) 2529 Created->push_back(Q.getNode()); 2530 } 2531 // Shift right algebraic if shift value is nonzero 2532 if (magics.s > 0) { 2533 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2534 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2535 if (Created) 2536 Created->push_back(Q.getNode()); 2537 } 2538 // Extract the sign bit and add it to the quotient 2539 SDValue T = 2540 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2541 getShiftAmountTy(Q.getValueType()))); 2542 if (Created) 2543 Created->push_back(T.getNode()); 2544 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2545} 2546 2547/// \brief Given an ISD::UDIV node expressing a divide by constant, 2548/// return a DAG expression to select that will generate the same value by 2549/// multiplying by a magic number. See: 2550/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2551SDValue TargetLowering:: 2552BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2553 std::vector<SDNode*> *Created) const { 2554 EVT VT = N->getValueType(0); 2555 SDLoc dl(N); 2556 2557 // Check to see if we can do this. 2558 // FIXME: We should be more aggressive here. 2559 if (!isTypeLegal(VT)) 2560 return SDValue(); 2561 2562 // FIXME: We should use a narrower constant when the upper 2563 // bits are known to be zero. 2564 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2565 APInt::mu magics = N1C.magicu(); 2566 2567 SDValue Q = N->getOperand(0); 2568 2569 // If the divisor is even, we can avoid using the expensive fixup by shifting 2570 // the divided value upfront. 2571 if (magics.a != 0 && !N1C[0]) { 2572 unsigned Shift = N1C.countTrailingZeros(); 2573 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 2574 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 2575 if (Created) 2576 Created->push_back(Q.getNode()); 2577 2578 // Get magic number for the shifted divisor. 2579 magics = N1C.lshr(Shift).magicu(Shift); 2580 assert(magics.a == 0 && "Should use cheap fixup now"); 2581 } 2582 2583 // Multiply the numerator (operand 0) by the magic value 2584 // FIXME: We should support doing a MUL in a wider type 2585 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 2586 isOperationLegalOrCustom(ISD::MULHU, VT)) 2587 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 2588 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 2589 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2590 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 2591 DAG.getConstant(magics.m, VT)).getNode(), 1); 2592 else 2593 return SDValue(); // No mulhu or equvialent 2594 if (Created) 2595 Created->push_back(Q.getNode()); 2596 2597 if (magics.a == 0) { 2598 assert(magics.s < N1C.getBitWidth() && 2599 "We shouldn't generate an undefined shift!"); 2600 return DAG.getNode(ISD::SRL, dl, VT, Q, 2601 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2602 } else { 2603 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2604 if (Created) 2605 Created->push_back(NPQ.getNode()); 2606 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2607 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 2608 if (Created) 2609 Created->push_back(NPQ.getNode()); 2610 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2611 if (Created) 2612 Created->push_back(NPQ.getNode()); 2613 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2614 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 2615 } 2616} 2617