TargetLowering.cpp revision 89217a6f1852e764e58c489872b2d155dc2b7b8b
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I32] = "__ashlsi3"; 33 Names[RTLIB::SHL_I64] = "__ashldi3"; 34 Names[RTLIB::SHL_I128] = "__ashlti3"; 35 Names[RTLIB::SRL_I32] = "__lshrsi3"; 36 Names[RTLIB::SRL_I64] = "__lshrdi3"; 37 Names[RTLIB::SRL_I128] = "__lshrti3"; 38 Names[RTLIB::SRA_I32] = "__ashrsi3"; 39 Names[RTLIB::SRA_I64] = "__ashrdi3"; 40 Names[RTLIB::SRA_I128] = "__ashrti3"; 41 Names[RTLIB::MUL_I32] = "__mulsi3"; 42 Names[RTLIB::MUL_I64] = "__muldi3"; 43 Names[RTLIB::MUL_I128] = "__multi3"; 44 Names[RTLIB::SDIV_I32] = "__divsi3"; 45 Names[RTLIB::SDIV_I64] = "__divdi3"; 46 Names[RTLIB::SDIV_I128] = "__divti3"; 47 Names[RTLIB::UDIV_I32] = "__udivsi3"; 48 Names[RTLIB::UDIV_I64] = "__udivdi3"; 49 Names[RTLIB::UDIV_I128] = "__udivti3"; 50 Names[RTLIB::SREM_I32] = "__modsi3"; 51 Names[RTLIB::SREM_I64] = "__moddi3"; 52 Names[RTLIB::SREM_I128] = "__modti3"; 53 Names[RTLIB::UREM_I32] = "__umodsi3"; 54 Names[RTLIB::UREM_I64] = "__umoddi3"; 55 Names[RTLIB::UREM_I128] = "__umodti3"; 56 Names[RTLIB::NEG_I32] = "__negsi2"; 57 Names[RTLIB::NEG_I64] = "__negdi2"; 58 Names[RTLIB::ADD_F32] = "__addsf3"; 59 Names[RTLIB::ADD_F64] = "__adddf3"; 60 Names[RTLIB::ADD_F80] = "__addxf3"; 61 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 62 Names[RTLIB::SUB_F32] = "__subsf3"; 63 Names[RTLIB::SUB_F64] = "__subdf3"; 64 Names[RTLIB::SUB_F80] = "__subxf3"; 65 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 66 Names[RTLIB::MUL_F32] = "__mulsf3"; 67 Names[RTLIB::MUL_F64] = "__muldf3"; 68 Names[RTLIB::MUL_F80] = "__mulxf3"; 69 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 70 Names[RTLIB::DIV_F32] = "__divsf3"; 71 Names[RTLIB::DIV_F64] = "__divdf3"; 72 Names[RTLIB::DIV_F80] = "__divxf3"; 73 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 74 Names[RTLIB::REM_F32] = "fmodf"; 75 Names[RTLIB::REM_F64] = "fmod"; 76 Names[RTLIB::REM_F80] = "fmodl"; 77 Names[RTLIB::REM_PPCF128] = "fmodl"; 78 Names[RTLIB::POWI_F32] = "__powisf2"; 79 Names[RTLIB::POWI_F64] = "__powidf2"; 80 Names[RTLIB::POWI_F80] = "__powixf2"; 81 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 82 Names[RTLIB::SQRT_F32] = "sqrtf"; 83 Names[RTLIB::SQRT_F64] = "sqrt"; 84 Names[RTLIB::SQRT_F80] = "sqrtl"; 85 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 86 Names[RTLIB::LOG_F32] = "logf"; 87 Names[RTLIB::LOG_F64] = "log"; 88 Names[RTLIB::LOG_F80] = "logl"; 89 Names[RTLIB::LOG_PPCF128] = "logl"; 90 Names[RTLIB::LOG2_F32] = "log2f"; 91 Names[RTLIB::LOG2_F64] = "log2"; 92 Names[RTLIB::LOG2_F80] = "log2l"; 93 Names[RTLIB::LOG2_PPCF128] = "log2l"; 94 Names[RTLIB::LOG10_F32] = "log10f"; 95 Names[RTLIB::LOG10_F64] = "log10"; 96 Names[RTLIB::LOG10_F80] = "log10l"; 97 Names[RTLIB::LOG10_PPCF128] = "log10l"; 98 Names[RTLIB::EXP_F32] = "expf"; 99 Names[RTLIB::EXP_F64] = "exp"; 100 Names[RTLIB::EXP_F80] = "expl"; 101 Names[RTLIB::EXP_PPCF128] = "expl"; 102 Names[RTLIB::EXP2_F32] = "exp2f"; 103 Names[RTLIB::EXP2_F64] = "exp2"; 104 Names[RTLIB::EXP2_F80] = "exp2l"; 105 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 106 Names[RTLIB::SIN_F32] = "sinf"; 107 Names[RTLIB::SIN_F64] = "sin"; 108 Names[RTLIB::SIN_F80] = "sinl"; 109 Names[RTLIB::SIN_PPCF128] = "sinl"; 110 Names[RTLIB::COS_F32] = "cosf"; 111 Names[RTLIB::COS_F64] = "cos"; 112 Names[RTLIB::COS_F80] = "cosl"; 113 Names[RTLIB::COS_PPCF128] = "cosl"; 114 Names[RTLIB::POW_F32] = "powf"; 115 Names[RTLIB::POW_F64] = "pow"; 116 Names[RTLIB::POW_F80] = "powl"; 117 Names[RTLIB::POW_PPCF128] = "powl"; 118 Names[RTLIB::CEIL_F32] = "ceilf"; 119 Names[RTLIB::CEIL_F64] = "ceil"; 120 Names[RTLIB::CEIL_F80] = "ceill"; 121 Names[RTLIB::CEIL_PPCF128] = "ceill"; 122 Names[RTLIB::TRUNC_F32] = "truncf"; 123 Names[RTLIB::TRUNC_F64] = "trunc"; 124 Names[RTLIB::TRUNC_F80] = "truncl"; 125 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 126 Names[RTLIB::RINT_F32] = "rintf"; 127 Names[RTLIB::RINT_F64] = "rint"; 128 Names[RTLIB::RINT_F80] = "rintl"; 129 Names[RTLIB::RINT_PPCF128] = "rintl"; 130 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 131 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 132 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 133 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 134 Names[RTLIB::FLOOR_F32] = "floorf"; 135 Names[RTLIB::FLOOR_F64] = "floor"; 136 Names[RTLIB::FLOOR_F80] = "floorl"; 137 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 138 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 139 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 140 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 141 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 142 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 143 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 144 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 145 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 146 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 147 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 148 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 149 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 150 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 151 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 152 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 153 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 154 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 155 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 156 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 157 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 158 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 159 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 160 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 161 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 162 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 163 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 164 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 165 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 166 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 167 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 168 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 169 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 170 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 171 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 172 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 173 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 174 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 175 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 176 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 177 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 178 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 179 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 180 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 181 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 182 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 183 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 184 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 185 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 186 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 187 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 188 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 189 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 190 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 191 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 192 Names[RTLIB::OEQ_F32] = "__eqsf2"; 193 Names[RTLIB::OEQ_F64] = "__eqdf2"; 194 Names[RTLIB::UNE_F32] = "__nesf2"; 195 Names[RTLIB::UNE_F64] = "__nedf2"; 196 Names[RTLIB::OGE_F32] = "__gesf2"; 197 Names[RTLIB::OGE_F64] = "__gedf2"; 198 Names[RTLIB::OLT_F32] = "__ltsf2"; 199 Names[RTLIB::OLT_F64] = "__ltdf2"; 200 Names[RTLIB::OLE_F32] = "__lesf2"; 201 Names[RTLIB::OLE_F64] = "__ledf2"; 202 Names[RTLIB::OGT_F32] = "__gtsf2"; 203 Names[RTLIB::OGT_F64] = "__gtdf2"; 204 Names[RTLIB::UO_F32] = "__unordsf2"; 205 Names[RTLIB::UO_F64] = "__unorddf2"; 206 Names[RTLIB::O_F32] = "__unordsf2"; 207 Names[RTLIB::O_F64] = "__unorddf2"; 208} 209 210/// getFPEXT - Return the FPEXT_*_* value for the given types, or 211/// UNKNOWN_LIBCALL if there is none. 212RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 213 if (OpVT == MVT::f32) { 214 if (RetVT == MVT::f64) 215 return FPEXT_F32_F64; 216 } 217 return UNKNOWN_LIBCALL; 218} 219 220/// getFPROUND - Return the FPROUND_*_* value for the given types, or 221/// UNKNOWN_LIBCALL if there is none. 222RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 223 if (RetVT == MVT::f32) { 224 if (OpVT == MVT::f64) 225 return FPROUND_F64_F32; 226 if (OpVT == MVT::f80) 227 return FPROUND_F80_F32; 228 if (OpVT == MVT::ppcf128) 229 return FPROUND_PPCF128_F32; 230 } else if (RetVT == MVT::f64) { 231 if (OpVT == MVT::f80) 232 return FPROUND_F80_F64; 233 if (OpVT == MVT::ppcf128) 234 return FPROUND_PPCF128_F64; 235 } 236 return UNKNOWN_LIBCALL; 237} 238 239/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 240/// UNKNOWN_LIBCALL if there is none. 241RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 242 if (OpVT == MVT::f32) { 243 if (RetVT == MVT::i32) 244 return FPTOSINT_F32_I32; 245 if (RetVT == MVT::i64) 246 return FPTOSINT_F32_I64; 247 if (RetVT == MVT::i128) 248 return FPTOSINT_F32_I128; 249 } else if (OpVT == MVT::f64) { 250 if (RetVT == MVT::i32) 251 return FPTOSINT_F64_I32; 252 if (RetVT == MVT::i64) 253 return FPTOSINT_F64_I64; 254 if (RetVT == MVT::i128) 255 return FPTOSINT_F64_I128; 256 } else if (OpVT == MVT::f80) { 257 if (RetVT == MVT::i32) 258 return FPTOSINT_F80_I32; 259 if (RetVT == MVT::i64) 260 return FPTOSINT_F80_I64; 261 if (RetVT == MVT::i128) 262 return FPTOSINT_F80_I128; 263 } else if (OpVT == MVT::ppcf128) { 264 if (RetVT == MVT::i32) 265 return FPTOSINT_PPCF128_I32; 266 if (RetVT == MVT::i64) 267 return FPTOSINT_PPCF128_I64; 268 if (RetVT == MVT::i128) 269 return FPTOSINT_PPCF128_I128; 270 } 271 return UNKNOWN_LIBCALL; 272} 273 274/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 275/// UNKNOWN_LIBCALL if there is none. 276RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 277 if (OpVT == MVT::f32) { 278 if (RetVT == MVT::i32) 279 return FPTOUINT_F32_I32; 280 if (RetVT == MVT::i64) 281 return FPTOUINT_F32_I64; 282 if (RetVT == MVT::i128) 283 return FPTOUINT_F32_I128; 284 } else if (OpVT == MVT::f64) { 285 if (RetVT == MVT::i32) 286 return FPTOUINT_F64_I32; 287 if (RetVT == MVT::i64) 288 return FPTOUINT_F64_I64; 289 if (RetVT == MVT::i128) 290 return FPTOUINT_F64_I128; 291 } else if (OpVT == MVT::f80) { 292 if (RetVT == MVT::i32) 293 return FPTOUINT_F80_I32; 294 if (RetVT == MVT::i64) 295 return FPTOUINT_F80_I64; 296 if (RetVT == MVT::i128) 297 return FPTOUINT_F80_I128; 298 } else if (OpVT == MVT::ppcf128) { 299 if (RetVT == MVT::i32) 300 return FPTOUINT_PPCF128_I32; 301 if (RetVT == MVT::i64) 302 return FPTOUINT_PPCF128_I64; 303 if (RetVT == MVT::i128) 304 return FPTOUINT_PPCF128_I128; 305 } 306 return UNKNOWN_LIBCALL; 307} 308 309/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 310/// UNKNOWN_LIBCALL if there is none. 311RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 312 if (OpVT == MVT::i32) { 313 if (RetVT == MVT::f32) 314 return SINTTOFP_I32_F32; 315 else if (RetVT == MVT::f64) 316 return SINTTOFP_I32_F64; 317 else if (RetVT == MVT::f80) 318 return SINTTOFP_I32_F80; 319 else if (RetVT == MVT::ppcf128) 320 return SINTTOFP_I32_PPCF128; 321 } else if (OpVT == MVT::i64) { 322 if (RetVT == MVT::f32) 323 return SINTTOFP_I64_F32; 324 else if (RetVT == MVT::f64) 325 return SINTTOFP_I64_F64; 326 else if (RetVT == MVT::f80) 327 return SINTTOFP_I64_F80; 328 else if (RetVT == MVT::ppcf128) 329 return SINTTOFP_I64_PPCF128; 330 } else if (OpVT == MVT::i128) { 331 if (RetVT == MVT::f32) 332 return SINTTOFP_I128_F32; 333 else if (RetVT == MVT::f64) 334 return SINTTOFP_I128_F64; 335 else if (RetVT == MVT::f80) 336 return SINTTOFP_I128_F80; 337 else if (RetVT == MVT::ppcf128) 338 return SINTTOFP_I128_PPCF128; 339 } 340 return UNKNOWN_LIBCALL; 341} 342 343/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 344/// UNKNOWN_LIBCALL if there is none. 345RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 346 if (OpVT == MVT::i32) { 347 if (RetVT == MVT::f32) 348 return UINTTOFP_I32_F32; 349 else if (RetVT == MVT::f64) 350 return UINTTOFP_I32_F64; 351 else if (RetVT == MVT::f80) 352 return UINTTOFP_I32_F80; 353 else if (RetVT == MVT::ppcf128) 354 return UINTTOFP_I32_PPCF128; 355 } else if (OpVT == MVT::i64) { 356 if (RetVT == MVT::f32) 357 return UINTTOFP_I64_F32; 358 else if (RetVT == MVT::f64) 359 return UINTTOFP_I64_F64; 360 else if (RetVT == MVT::f80) 361 return UINTTOFP_I64_F80; 362 else if (RetVT == MVT::ppcf128) 363 return UINTTOFP_I64_PPCF128; 364 } else if (OpVT == MVT::i128) { 365 if (RetVT == MVT::f32) 366 return UINTTOFP_I128_F32; 367 else if (RetVT == MVT::f64) 368 return UINTTOFP_I128_F64; 369 else if (RetVT == MVT::f80) 370 return UINTTOFP_I128_F80; 371 else if (RetVT == MVT::ppcf128) 372 return UINTTOFP_I128_PPCF128; 373 } 374 return UNKNOWN_LIBCALL; 375} 376 377/// InitCmpLibcallCCs - Set default comparison libcall CC. 378/// 379static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 380 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 381 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 382 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 383 CCs[RTLIB::UNE_F32] = ISD::SETNE; 384 CCs[RTLIB::UNE_F64] = ISD::SETNE; 385 CCs[RTLIB::OGE_F32] = ISD::SETGE; 386 CCs[RTLIB::OGE_F64] = ISD::SETGE; 387 CCs[RTLIB::OLT_F32] = ISD::SETLT; 388 CCs[RTLIB::OLT_F64] = ISD::SETLT; 389 CCs[RTLIB::OLE_F32] = ISD::SETLE; 390 CCs[RTLIB::OLE_F64] = ISD::SETLE; 391 CCs[RTLIB::OGT_F32] = ISD::SETGT; 392 CCs[RTLIB::OGT_F64] = ISD::SETGT; 393 CCs[RTLIB::UO_F32] = ISD::SETNE; 394 CCs[RTLIB::UO_F64] = ISD::SETNE; 395 CCs[RTLIB::O_F32] = ISD::SETEQ; 396 CCs[RTLIB::O_F64] = ISD::SETEQ; 397} 398 399TargetLowering::TargetLowering(TargetMachine &tm) 400 : TM(tm), TD(TM.getTargetData()) { 401 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 402 "Fixed size array in TargetLowering is not large enough!"); 403 // All operations default to being supported. 404 memset(OpActions, 0, sizeof(OpActions)); 405 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 406 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 407 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 408 memset(ConvertActions, 0, sizeof(ConvertActions)); 409 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 410 411 // Set default actions for various operations. 412 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 413 // Default all indexed load / store to expand. 414 for (unsigned IM = (unsigned)ISD::PRE_INC; 415 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 416 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 417 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 418 } 419 420 // These operations default to expand. 421 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 422 } 423 424 // Most targets ignore the @llvm.prefetch intrinsic. 425 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 426 427 // ConstantFP nodes default to expand. Targets can either change this to 428 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 429 // to optimize expansions for certain constants. 430 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 431 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 432 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 433 434 // These library functions default to expand. 435 setOperationAction(ISD::FLOG , MVT::f64, Expand); 436 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 437 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 438 setOperationAction(ISD::FEXP , MVT::f64, Expand); 439 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 440 setOperationAction(ISD::FLOG , MVT::f32, Expand); 441 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 443 setOperationAction(ISD::FEXP , MVT::f32, Expand); 444 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 445 446 // Default ISD::TRAP to expand (which turns it into abort). 447 setOperationAction(ISD::TRAP, MVT::Other, Expand); 448 449 IsLittleEndian = TD->isLittleEndian(); 450 UsesGlobalOffsetTable = false; 451 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 452 ShiftAmtHandling = Undefined; 453 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 454 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 455 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 456 allowUnalignedMemoryAccesses = false; 457 UseUnderscoreSetJmp = false; 458 UseUnderscoreLongJmp = false; 459 SelectIsExpensive = false; 460 IntDivIsCheap = false; 461 Pow2DivIsCheap = false; 462 StackPointerRegisterToSaveRestore = 0; 463 ExceptionPointerRegister = 0; 464 ExceptionSelectorRegister = 0; 465 SetCCResultContents = UndefinedSetCCResult; 466 SchedPreferenceInfo = SchedulingForLatency; 467 JumpBufSize = 0; 468 JumpBufAlignment = 0; 469 IfCvtBlockSizeLimit = 2; 470 IfCvtDupBlockSizeLimit = 0; 471 PrefLoopAlignment = 0; 472 473 InitLibcallNames(LibcallRoutineNames); 474 InitCmpLibcallCCs(CmpLibcallCCs); 475 476 // Tell Legalize whether the assembler supports DEBUG_LOC. 477 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 478 if (!TASM || !TASM->hasDotLocAndDotFile()) 479 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 480} 481 482TargetLowering::~TargetLowering() {} 483 484/// computeRegisterProperties - Once all of the register classes are added, 485/// this allows us to compute derived properties we expose. 486void TargetLowering::computeRegisterProperties() { 487 assert(MVT::LAST_VALUETYPE <= 32 && 488 "Too many value types for ValueTypeActions to hold!"); 489 490 // Everything defaults to needing one register. 491 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 492 NumRegistersForVT[i] = 1; 493 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 494 } 495 // ...except isVoid, which doesn't need any registers. 496 NumRegistersForVT[MVT::isVoid] = 0; 497 498 // Find the largest integer register class. 499 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 500 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 501 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 502 503 // Every integer value type larger than this largest register takes twice as 504 // many registers to represent as the previous ValueType. 505 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 506 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 507 if (!EVT.isInteger()) 508 break; 509 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 510 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 511 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 512 ValueTypeActions.setTypeAction(EVT, Expand); 513 } 514 515 // Inspect all of the ValueType's smaller than the largest integer 516 // register to see which ones need promotion. 517 unsigned LegalIntReg = LargestIntReg; 518 for (unsigned IntReg = LargestIntReg - 1; 519 IntReg >= (unsigned)MVT::i1; --IntReg) { 520 MVT IVT = (MVT::SimpleValueType)IntReg; 521 if (isTypeLegal(IVT)) { 522 LegalIntReg = IntReg; 523 } else { 524 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 525 (MVT::SimpleValueType)LegalIntReg; 526 ValueTypeActions.setTypeAction(IVT, Promote); 527 } 528 } 529 530 // ppcf128 type is really two f64's. 531 if (!isTypeLegal(MVT::ppcf128)) { 532 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 533 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 534 TransformToType[MVT::ppcf128] = MVT::f64; 535 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 536 } 537 538 // Decide how to handle f64. If the target does not have native f64 support, 539 // expand it to i64 and we will be generating soft float library calls. 540 if (!isTypeLegal(MVT::f64)) { 541 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 542 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 543 TransformToType[MVT::f64] = MVT::i64; 544 ValueTypeActions.setTypeAction(MVT::f64, Expand); 545 } 546 547 // Decide how to handle f32. If the target does not have native support for 548 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 549 if (!isTypeLegal(MVT::f32)) { 550 if (isTypeLegal(MVT::f64)) { 551 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 552 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 553 TransformToType[MVT::f32] = MVT::f64; 554 ValueTypeActions.setTypeAction(MVT::f32, Promote); 555 } else { 556 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 557 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 558 TransformToType[MVT::f32] = MVT::i32; 559 ValueTypeActions.setTypeAction(MVT::f32, Expand); 560 } 561 } 562 563 // Loop over all of the vector value types to see which need transformations. 564 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 565 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 566 MVT VT = (MVT::SimpleValueType)i; 567 if (!isTypeLegal(VT)) { 568 MVT IntermediateVT, RegisterVT; 569 unsigned NumIntermediates; 570 NumRegistersForVT[i] = 571 getVectorTypeBreakdown(VT, 572 IntermediateVT, NumIntermediates, 573 RegisterVT); 574 RegisterTypeForVT[i] = RegisterVT; 575 TransformToType[i] = MVT::Other; // this isn't actually used 576 ValueTypeActions.setTypeAction(VT, Promote); 577 } 578 } 579} 580 581const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 582 return NULL; 583} 584 585 586MVT TargetLowering::getSetCCResultType(const SDValue &) const { 587 return getValueType(TD->getIntPtrType()); 588} 589 590 591/// getVectorTypeBreakdown - Vector types are broken down into some number of 592/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 593/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 594/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 595/// 596/// This method returns the number of registers needed, and the VT for each 597/// register. It also returns the VT and quantity of the intermediate values 598/// before they are promoted/expanded. 599/// 600unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 601 MVT &IntermediateVT, 602 unsigned &NumIntermediates, 603 MVT &RegisterVT) const { 604 // Figure out the right, legal destination reg to copy into. 605 unsigned NumElts = VT.getVectorNumElements(); 606 MVT EltTy = VT.getVectorElementType(); 607 608 unsigned NumVectorRegs = 1; 609 610 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 611 // could break down into LHS/RHS like LegalizeDAG does. 612 if (!isPowerOf2_32(NumElts)) { 613 NumVectorRegs = NumElts; 614 NumElts = 1; 615 } 616 617 // Divide the input until we get to a supported size. This will always 618 // end with a scalar if the target doesn't support vectors. 619 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 620 NumElts >>= 1; 621 NumVectorRegs <<= 1; 622 } 623 624 NumIntermediates = NumVectorRegs; 625 626 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 627 if (!isTypeLegal(NewVT)) 628 NewVT = EltTy; 629 IntermediateVT = NewVT; 630 631 MVT DestVT = getTypeToTransformTo(NewVT); 632 RegisterVT = DestVT; 633 if (DestVT.bitsLT(NewVT)) { 634 // Value is expanded, e.g. i64 -> i16. 635 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 636 } else { 637 // Otherwise, promotion or legal types use the same number of registers as 638 // the vector decimated to the appropriate level. 639 return NumVectorRegs; 640 } 641 642 return 1; 643} 644 645/// getWidenVectorType: given a vector type, returns the type to widen to 646/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 647/// If there is no vector type that we want to widen to, returns MVT::Other 648/// When and where to widen is target dependent based on the cost of 649/// scalarizing vs using the wider vector type. 650MVT TargetLowering::getWidenVectorType(MVT VT) { 651 assert(VT.isVector()); 652 if (isTypeLegal(VT)) 653 return VT; 654 655 // Default is not to widen until moved to LegalizeTypes 656 return MVT::Other; 657} 658 659/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 660/// function arguments in the caller parameter area. This is the actual 661/// alignment, not its logarithm. 662unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 663 return TD->getCallFrameTypeAlignment(Ty); 664} 665 666SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 667 SelectionDAG &DAG) const { 668 if (usesGlobalOffsetTable()) 669 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 670 return Table; 671} 672 673bool 674TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 675 // Assume that everything is safe in static mode. 676 if (getTargetMachine().getRelocationModel() == Reloc::Static) 677 return true; 678 679 // In dynamic-no-pic mode, assume that known defined values are safe. 680 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 681 GA && 682 !GA->getGlobal()->isDeclaration() && 683 !GA->getGlobal()->mayBeOverridden()) 684 return true; 685 686 // Otherwise assume nothing is safe. 687 return false; 688} 689 690//===----------------------------------------------------------------------===// 691// Optimization Methods 692//===----------------------------------------------------------------------===// 693 694/// ShrinkDemandedConstant - Check to see if the specified operand of the 695/// specified instruction is a constant integer. If so, check to see if there 696/// are any bits set in the constant that are not demanded. If so, shrink the 697/// constant and return true. 698bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 699 const APInt &Demanded) { 700 // FIXME: ISD::SELECT, ISD::SELECT_CC 701 switch(Op.getOpcode()) { 702 default: break; 703 case ISD::AND: 704 case ISD::OR: 705 case ISD::XOR: 706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 707 if (C->getAPIntValue().intersects(~Demanded)) { 708 MVT VT = Op.getValueType(); 709 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 710 DAG.getConstant(Demanded & 711 C->getAPIntValue(), 712 VT)); 713 return CombineTo(Op, New); 714 } 715 break; 716 } 717 return false; 718} 719 720/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 721/// DemandedMask bits of the result of Op are ever used downstream. If we can 722/// use this information to simplify Op, create a new simplified DAG node and 723/// return true, returning the original and new nodes in Old and New. Otherwise, 724/// analyze the expression and return a mask of KnownOne and KnownZero bits for 725/// the expression (used to simplify the caller). The KnownZero/One bits may 726/// only be accurate for those bits in the DemandedMask. 727bool TargetLowering::SimplifyDemandedBits(SDValue Op, 728 const APInt &DemandedMask, 729 APInt &KnownZero, 730 APInt &KnownOne, 731 TargetLoweringOpt &TLO, 732 unsigned Depth) const { 733 unsigned BitWidth = DemandedMask.getBitWidth(); 734 assert(Op.getValueSizeInBits() == BitWidth && 735 "Mask size mismatches value type size!"); 736 APInt NewMask = DemandedMask; 737 738 // Don't know anything. 739 KnownZero = KnownOne = APInt(BitWidth, 0); 740 741 // Other users may use these bits. 742 if (!Op.getNode()->hasOneUse()) { 743 if (Depth != 0) { 744 // If not at the root, Just compute the KnownZero/KnownOne bits to 745 // simplify things downstream. 746 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 747 return false; 748 } 749 // If this is the root being simplified, allow it to have multiple uses, 750 // just set the NewMask to all bits. 751 NewMask = APInt::getAllOnesValue(BitWidth); 752 } else if (DemandedMask == 0) { 753 // Not demanding any bits from Op. 754 if (Op.getOpcode() != ISD::UNDEF) 755 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 756 return false; 757 } else if (Depth == 6) { // Limit search depth. 758 return false; 759 } 760 761 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 762 switch (Op.getOpcode()) { 763 case ISD::Constant: 764 // We know all of the bits for a constant! 765 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 766 KnownZero = ~KnownOne & NewMask; 767 return false; // Don't fall through, will infinitely loop. 768 case ISD::AND: 769 // If the RHS is a constant, check to see if the LHS would be zero without 770 // using the bits from the RHS. Below, we use knowledge about the RHS to 771 // simplify the LHS, here we're using information from the LHS to simplify 772 // the RHS. 773 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 774 APInt LHSZero, LHSOne; 775 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 776 LHSZero, LHSOne, Depth+1); 777 // If the LHS already has zeros where RHSC does, this and is dead. 778 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 779 return TLO.CombineTo(Op, Op.getOperand(0)); 780 // If any of the set bits in the RHS are known zero on the LHS, shrink 781 // the constant. 782 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 783 return true; 784 } 785 786 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 787 KnownOne, TLO, Depth+1)) 788 return true; 789 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 790 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 791 KnownZero2, KnownOne2, TLO, Depth+1)) 792 return true; 793 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 794 795 // If all of the demanded bits are known one on one side, return the other. 796 // These bits cannot contribute to the result of the 'and'. 797 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 798 return TLO.CombineTo(Op, Op.getOperand(0)); 799 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 800 return TLO.CombineTo(Op, Op.getOperand(1)); 801 // If all of the demanded bits in the inputs are known zeros, return zero. 802 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 803 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 804 // If the RHS is a constant, see if we can simplify it. 805 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 806 return true; 807 808 // Output known-1 bits are only known if set in both the LHS & RHS. 809 KnownOne &= KnownOne2; 810 // Output known-0 are known to be clear if zero in either the LHS | RHS. 811 KnownZero |= KnownZero2; 812 break; 813 case ISD::OR: 814 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 815 KnownOne, TLO, Depth+1)) 816 return true; 817 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 818 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 819 KnownZero2, KnownOne2, TLO, Depth+1)) 820 return true; 821 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 822 823 // If all of the demanded bits are known zero on one side, return the other. 824 // These bits cannot contribute to the result of the 'or'. 825 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 826 return TLO.CombineTo(Op, Op.getOperand(0)); 827 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 828 return TLO.CombineTo(Op, Op.getOperand(1)); 829 // If all of the potentially set bits on one side are known to be set on 830 // the other side, just use the 'other' side. 831 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 832 return TLO.CombineTo(Op, Op.getOperand(0)); 833 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 834 return TLO.CombineTo(Op, Op.getOperand(1)); 835 // If the RHS is a constant, see if we can simplify it. 836 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 837 return true; 838 839 // Output known-0 bits are only known if clear in both the LHS & RHS. 840 KnownZero &= KnownZero2; 841 // Output known-1 are known to be set if set in either the LHS | RHS. 842 KnownOne |= KnownOne2; 843 break; 844 case ISD::XOR: 845 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 846 KnownOne, TLO, Depth+1)) 847 return true; 848 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 849 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 850 KnownOne2, TLO, Depth+1)) 851 return true; 852 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 853 854 // If all of the demanded bits are known zero on one side, return the other. 855 // These bits cannot contribute to the result of the 'xor'. 856 if ((KnownZero & NewMask) == NewMask) 857 return TLO.CombineTo(Op, Op.getOperand(0)); 858 if ((KnownZero2 & NewMask) == NewMask) 859 return TLO.CombineTo(Op, Op.getOperand(1)); 860 861 // If all of the unknown bits are known to be zero on one side or the other 862 // (but not both) turn this into an *inclusive* or. 863 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 864 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 865 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 866 Op.getOperand(0), 867 Op.getOperand(1))); 868 869 // Output known-0 bits are known if clear or set in both the LHS & RHS. 870 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 871 // Output known-1 are known to be set if set in only one of the LHS, RHS. 872 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 873 874 // If all of the demanded bits on one side are known, and all of the set 875 // bits on that side are also known to be set on the other side, turn this 876 // into an AND, as we know the bits will be cleared. 877 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 878 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 879 if ((KnownOne & KnownOne2) == KnownOne) { 880 MVT VT = Op.getValueType(); 881 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 882 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 883 ANDC)); 884 } 885 } 886 887 // If the RHS is a constant, see if we can simplify it. 888 // for XOR, we prefer to force bits to 1 if they will make a -1. 889 // if we can't force bits, try to shrink constant 890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 891 APInt Expanded = C->getAPIntValue() | (~NewMask); 892 // if we can expand it to have all bits set, do it 893 if (Expanded.isAllOnesValue()) { 894 if (Expanded != C->getAPIntValue()) { 895 MVT VT = Op.getValueType(); 896 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 897 TLO.DAG.getConstant(Expanded, VT)); 898 return TLO.CombineTo(Op, New); 899 } 900 // if it already has all the bits set, nothing to change 901 // but don't shrink either! 902 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 903 return true; 904 } 905 } 906 907 KnownZero = KnownZeroOut; 908 KnownOne = KnownOneOut; 909 break; 910 case ISD::SELECT: 911 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 912 KnownOne, TLO, Depth+1)) 913 return true; 914 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 915 KnownOne2, TLO, Depth+1)) 916 return true; 917 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 918 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 919 920 // If the operands are constants, see if we can simplify them. 921 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 922 return true; 923 924 // Only known if known in both the LHS and RHS. 925 KnownOne &= KnownOne2; 926 KnownZero &= KnownZero2; 927 break; 928 case ISD::SELECT_CC: 929 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 930 KnownOne, TLO, Depth+1)) 931 return true; 932 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 933 KnownOne2, TLO, Depth+1)) 934 return true; 935 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 936 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 937 938 // If the operands are constants, see if we can simplify them. 939 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 940 return true; 941 942 // Only known if known in both the LHS and RHS. 943 KnownOne &= KnownOne2; 944 KnownZero &= KnownZero2; 945 break; 946 case ISD::SHL: 947 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 948 unsigned ShAmt = SA->getZExtValue(); 949 SDValue InOp = Op.getOperand(0); 950 951 // If the shift count is an invalid immediate, don't do anything. 952 if (ShAmt >= BitWidth) 953 break; 954 955 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 956 // single shift. We can do this if the bottom bits (which are shifted 957 // out) are never demanded. 958 if (InOp.getOpcode() == ISD::SRL && 959 isa<ConstantSDNode>(InOp.getOperand(1))) { 960 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 961 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 962 unsigned Opc = ISD::SHL; 963 int Diff = ShAmt-C1; 964 if (Diff < 0) { 965 Diff = -Diff; 966 Opc = ISD::SRL; 967 } 968 969 SDValue NewSA = 970 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 971 MVT VT = Op.getValueType(); 972 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 973 InOp.getOperand(0), NewSA)); 974 } 975 } 976 977 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 978 KnownZero, KnownOne, TLO, Depth+1)) 979 return true; 980 KnownZero <<= SA->getZExtValue(); 981 KnownOne <<= SA->getZExtValue(); 982 // low bits known zero. 983 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 984 } 985 break; 986 case ISD::SRL: 987 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 988 MVT VT = Op.getValueType(); 989 unsigned ShAmt = SA->getZExtValue(); 990 unsigned VTSize = VT.getSizeInBits(); 991 SDValue InOp = Op.getOperand(0); 992 993 // If the shift count is an invalid immediate, don't do anything. 994 if (ShAmt >= BitWidth) 995 break; 996 997 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 998 // single shift. We can do this if the top bits (which are shifted out) 999 // are never demanded. 1000 if (InOp.getOpcode() == ISD::SHL && 1001 isa<ConstantSDNode>(InOp.getOperand(1))) { 1002 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1003 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1004 unsigned Opc = ISD::SRL; 1005 int Diff = ShAmt-C1; 1006 if (Diff < 0) { 1007 Diff = -Diff; 1008 Opc = ISD::SHL; 1009 } 1010 1011 SDValue NewSA = 1012 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1013 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 1014 InOp.getOperand(0), NewSA)); 1015 } 1016 } 1017 1018 // Compute the new bits that are at the top now. 1019 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1020 KnownZero, KnownOne, TLO, Depth+1)) 1021 return true; 1022 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1023 KnownZero = KnownZero.lshr(ShAmt); 1024 KnownOne = KnownOne.lshr(ShAmt); 1025 1026 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1027 KnownZero |= HighBits; // High bits known zero. 1028 } 1029 break; 1030 case ISD::SRA: 1031 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1032 MVT VT = Op.getValueType(); 1033 unsigned ShAmt = SA->getZExtValue(); 1034 1035 // If the shift count is an invalid immediate, don't do anything. 1036 if (ShAmt >= BitWidth) 1037 break; 1038 1039 APInt InDemandedMask = (NewMask << ShAmt); 1040 1041 // If any of the demanded bits are produced by the sign extension, we also 1042 // demand the input sign bit. 1043 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1044 if (HighBits.intersects(NewMask)) 1045 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1046 1047 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1048 KnownZero, KnownOne, TLO, Depth+1)) 1049 return true; 1050 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1051 KnownZero = KnownZero.lshr(ShAmt); 1052 KnownOne = KnownOne.lshr(ShAmt); 1053 1054 // Handle the sign bit, adjusted to where it is now in the mask. 1055 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1056 1057 // If the input sign bit is known to be zero, or if none of the top bits 1058 // are demanded, turn this into an unsigned shift right. 1059 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1060 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 1061 Op.getOperand(1))); 1062 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1063 KnownOne |= HighBits; 1064 } 1065 } 1066 break; 1067 case ISD::SIGN_EXTEND_INREG: { 1068 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1069 1070 // Sign extension. Compute the demanded bits in the result that are not 1071 // present in the input. 1072 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1073 BitWidth - EVT.getSizeInBits()) & 1074 NewMask; 1075 1076 // If none of the extended bits are demanded, eliminate the sextinreg. 1077 if (NewBits == 0) 1078 return TLO.CombineTo(Op, Op.getOperand(0)); 1079 1080 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1081 InSignBit.zext(BitWidth); 1082 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1083 EVT.getSizeInBits()) & 1084 NewMask; 1085 1086 // Since the sign extended bits are demanded, we know that the sign 1087 // bit is demanded. 1088 InputDemandedBits |= InSignBit; 1089 1090 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1091 KnownZero, KnownOne, TLO, Depth+1)) 1092 return true; 1093 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1094 1095 // If the sign bit of the input is known set or clear, then we know the 1096 // top bits of the result. 1097 1098 // If the input sign bit is known zero, convert this into a zero extension. 1099 if (KnownZero.intersects(InSignBit)) 1100 return TLO.CombineTo(Op, 1101 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1102 1103 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1104 KnownOne |= NewBits; 1105 KnownZero &= ~NewBits; 1106 } else { // Input sign bit unknown 1107 KnownZero &= ~NewBits; 1108 KnownOne &= ~NewBits; 1109 } 1110 break; 1111 } 1112 case ISD::ZERO_EXTEND: { 1113 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1114 APInt InMask = NewMask; 1115 InMask.trunc(OperandBitWidth); 1116 1117 // If none of the top bits are demanded, convert this into an any_extend. 1118 APInt NewBits = 1119 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1120 if (!NewBits.intersects(NewMask)) 1121 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1122 Op.getValueType(), 1123 Op.getOperand(0))); 1124 1125 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1126 KnownZero, KnownOne, TLO, Depth+1)) 1127 return true; 1128 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1129 KnownZero.zext(BitWidth); 1130 KnownOne.zext(BitWidth); 1131 KnownZero |= NewBits; 1132 break; 1133 } 1134 case ISD::SIGN_EXTEND: { 1135 MVT InVT = Op.getOperand(0).getValueType(); 1136 unsigned InBits = InVT.getSizeInBits(); 1137 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1138 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1139 APInt NewBits = ~InMask & NewMask; 1140 1141 // If none of the top bits are demanded, convert this into an any_extend. 1142 if (NewBits == 0) 1143 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1144 Op.getOperand(0))); 1145 1146 // Since some of the sign extended bits are demanded, we know that the sign 1147 // bit is demanded. 1148 APInt InDemandedBits = InMask & NewMask; 1149 InDemandedBits |= InSignBit; 1150 InDemandedBits.trunc(InBits); 1151 1152 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1153 KnownOne, TLO, Depth+1)) 1154 return true; 1155 KnownZero.zext(BitWidth); 1156 KnownOne.zext(BitWidth); 1157 1158 // If the sign bit is known zero, convert this to a zero extend. 1159 if (KnownZero.intersects(InSignBit)) 1160 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1161 Op.getValueType(), 1162 Op.getOperand(0))); 1163 1164 // If the sign bit is known one, the top bits match. 1165 if (KnownOne.intersects(InSignBit)) { 1166 KnownOne |= NewBits; 1167 KnownZero &= ~NewBits; 1168 } else { // Otherwise, top bits aren't known. 1169 KnownOne &= ~NewBits; 1170 KnownZero &= ~NewBits; 1171 } 1172 break; 1173 } 1174 case ISD::ANY_EXTEND: { 1175 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1176 APInt InMask = NewMask; 1177 InMask.trunc(OperandBitWidth); 1178 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1179 KnownZero, KnownOne, TLO, Depth+1)) 1180 return true; 1181 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1182 KnownZero.zext(BitWidth); 1183 KnownOne.zext(BitWidth); 1184 break; 1185 } 1186 case ISD::TRUNCATE: { 1187 // Simplify the input, using demanded bit information, and compute the known 1188 // zero/one bits live out. 1189 APInt TruncMask = NewMask; 1190 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1191 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1192 KnownZero, KnownOne, TLO, Depth+1)) 1193 return true; 1194 KnownZero.trunc(BitWidth); 1195 KnownOne.trunc(BitWidth); 1196 1197 // If the input is only used by this truncate, see if we can shrink it based 1198 // on the known demanded bits. 1199 if (Op.getOperand(0).getNode()->hasOneUse()) { 1200 SDValue In = Op.getOperand(0); 1201 unsigned InBitWidth = In.getValueSizeInBits(); 1202 switch (In.getOpcode()) { 1203 default: break; 1204 case ISD::SRL: 1205 // Shrink SRL by a constant if none of the high bits shifted in are 1206 // demanded. 1207 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1208 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1209 InBitWidth - BitWidth); 1210 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1211 HighBits.trunc(BitWidth); 1212 1213 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1214 // None of the shifted in bits are needed. Add a truncate of the 1215 // shift input, then shift it. 1216 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1217 Op.getValueType(), 1218 In.getOperand(0)); 1219 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1220 NewTrunc, In.getOperand(1))); 1221 } 1222 } 1223 break; 1224 } 1225 } 1226 1227 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1228 break; 1229 } 1230 case ISD::AssertZext: { 1231 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1232 APInt InMask = APInt::getLowBitsSet(BitWidth, 1233 VT.getSizeInBits()); 1234 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1235 KnownZero, KnownOne, TLO, Depth+1)) 1236 return true; 1237 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1238 KnownZero |= ~InMask & NewMask; 1239 break; 1240 } 1241 case ISD::BIT_CONVERT: 1242#if 0 1243 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1244 // is demanded, turn this into a FGETSIGN. 1245 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1246 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1247 !MVT::isVector(Op.getOperand(0).getValueType())) { 1248 // Only do this xform if FGETSIGN is valid or if before legalize. 1249 if (!TLO.AfterLegalize || 1250 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1251 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1252 // place. We expect the SHL to be eliminated by other optimizations. 1253 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1254 Op.getOperand(0)); 1255 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1256 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1257 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1258 Sign, ShAmt)); 1259 } 1260 } 1261#endif 1262 break; 1263 default: 1264 // Just use ComputeMaskedBits to compute output bits. 1265 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1266 break; 1267 } 1268 1269 // If we know the value of all of the demanded bits, return this as a 1270 // constant. 1271 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1272 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1273 1274 return false; 1275} 1276 1277/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1278/// in Mask are known to be either zero or one and return them in the 1279/// KnownZero/KnownOne bitsets. 1280void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1281 const APInt &Mask, 1282 APInt &KnownZero, 1283 APInt &KnownOne, 1284 const SelectionDAG &DAG, 1285 unsigned Depth) const { 1286 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1287 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1288 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1289 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1290 "Should use MaskedValueIsZero if you don't know whether Op" 1291 " is a target node!"); 1292 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1293} 1294 1295/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1296/// targets that want to expose additional information about sign bits to the 1297/// DAG Combiner. 1298unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1299 unsigned Depth) const { 1300 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1301 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1302 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1303 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1304 "Should use ComputeNumSignBits if you don't know whether Op" 1305 " is a target node!"); 1306 return 1; 1307} 1308 1309 1310/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1311/// and cc. If it is unable to simplify it, return a null SDValue. 1312SDValue 1313TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1314 ISD::CondCode Cond, bool foldBooleans, 1315 DAGCombinerInfo &DCI) const { 1316 SelectionDAG &DAG = DCI.DAG; 1317 1318 // These setcc operations always fold. 1319 switch (Cond) { 1320 default: break; 1321 case ISD::SETFALSE: 1322 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1323 case ISD::SETTRUE: 1324 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1325 } 1326 1327 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1328 const APInt &C1 = N1C->getAPIntValue(); 1329 if (isa<ConstantSDNode>(N0.getNode())) { 1330 return DAG.FoldSetCC(VT, N0, N1, Cond); 1331 } else { 1332 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1333 // equality comparison, then we're just comparing whether X itself is 1334 // zero. 1335 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1336 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1337 N0.getOperand(1).getOpcode() == ISD::Constant) { 1338 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1339 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1340 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1341 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1342 // (srl (ctlz x), 5) == 0 -> X != 0 1343 // (srl (ctlz x), 5) != 1 -> X != 0 1344 Cond = ISD::SETNE; 1345 } else { 1346 // (srl (ctlz x), 5) != 0 -> X == 0 1347 // (srl (ctlz x), 5) == 1 -> X == 0 1348 Cond = ISD::SETEQ; 1349 } 1350 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1351 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1352 Zero, Cond); 1353 } 1354 } 1355 1356 // If the LHS is '(and load, const)', the RHS is 0, 1357 // the test is for equality or unsigned, and all 1 bits of the const are 1358 // in the same partial word, see if we can shorten the load. 1359 if (DCI.isBeforeLegalize() && 1360 N0.getOpcode() == ISD::AND && C1 == 0 && 1361 isa<LoadSDNode>(N0.getOperand(0)) && 1362 N0.getOperand(0).getNode()->hasOneUse() && 1363 isa<ConstantSDNode>(N0.getOperand(1))) { 1364 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1365 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1366 unsigned bestWidth = 0, bestOffset = 0; 1367 if (!Lod->isVolatile()) { 1368 unsigned origWidth = N0.getValueType().getSizeInBits(); 1369 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1370 uint64_t newMask = (1ULL << width) - 1; 1371 for (unsigned offset=0; offset<origWidth/width; offset++) { 1372 if ((newMask & Mask)==Mask) { 1373 bestOffset = (uint64_t)offset * (width/8); 1374 bestWidth = width; 1375 break; 1376 } 1377 newMask = newMask << width; 1378 } 1379 } 1380 } 1381 if (bestWidth) { 1382 MVT newVT = MVT::getIntegerVT(bestWidth); 1383 if (newVT.isRound()) { 1384 uint64_t bestMask = Mask >> (bestOffset * 8); 1385 MVT PtrType = Lod->getOperand(1).getValueType(); 1386 SDValue Ptr = Lod->getBasePtr(); 1387 if (bestOffset != 0) 1388 Ptr = DAG.getNode(ISD::ADD, PtrType, Lod->getBasePtr(), 1389 DAG.getConstant(bestOffset, PtrType)); 1390 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1391 SDValue NewLoad = DAG.getLoad(newVT, Lod->getChain(), Ptr, 1392 Lod->getSrcValue(), 1393 Lod->getSrcValueOffset() + bestOffset, 1394 false, NewAlign); 1395 return DAG.getSetCC(VT, DAG.getNode(ISD::AND, newVT, NewLoad, 1396 DAG.getConstant(bestMask, newVT)), 1397 DAG.getConstant(0LL, newVT), Cond); 1398 } 1399 } 1400 } 1401 1402 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1403 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1404 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1405 1406 // If the comparison constant has bits in the upper part, the 1407 // zero-extended value could never match. 1408 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1409 C1.getBitWidth() - InSize))) { 1410 switch (Cond) { 1411 case ISD::SETUGT: 1412 case ISD::SETUGE: 1413 case ISD::SETEQ: return DAG.getConstant(0, VT); 1414 case ISD::SETULT: 1415 case ISD::SETULE: 1416 case ISD::SETNE: return DAG.getConstant(1, VT); 1417 case ISD::SETGT: 1418 case ISD::SETGE: 1419 // True if the sign bit of C1 is set. 1420 return DAG.getConstant(C1.isNegative(), VT); 1421 case ISD::SETLT: 1422 case ISD::SETLE: 1423 // True if the sign bit of C1 isn't set. 1424 return DAG.getConstant(C1.isNonNegative(), VT); 1425 default: 1426 break; 1427 } 1428 } 1429 1430 // Otherwise, we can perform the comparison with the low bits. 1431 switch (Cond) { 1432 case ISD::SETEQ: 1433 case ISD::SETNE: 1434 case ISD::SETUGT: 1435 case ISD::SETUGE: 1436 case ISD::SETULT: 1437 case ISD::SETULE: 1438 return DAG.getSetCC(VT, N0.getOperand(0), 1439 DAG.getConstant(APInt(C1).trunc(InSize), 1440 N0.getOperand(0).getValueType()), 1441 Cond); 1442 default: 1443 break; // todo, be more careful with signed comparisons 1444 } 1445 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1446 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1447 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1448 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1449 MVT ExtDstTy = N0.getValueType(); 1450 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1451 1452 // If the extended part has any inconsistent bits, it cannot ever 1453 // compare equal. In other words, they have to be all ones or all 1454 // zeros. 1455 APInt ExtBits = 1456 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1457 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1458 return DAG.getConstant(Cond == ISD::SETNE, VT); 1459 1460 SDValue ZextOp; 1461 MVT Op0Ty = N0.getOperand(0).getValueType(); 1462 if (Op0Ty == ExtSrcTy) { 1463 ZextOp = N0.getOperand(0); 1464 } else { 1465 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1466 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1467 DAG.getConstant(Imm, Op0Ty)); 1468 } 1469 if (!DCI.isCalledByLegalizer()) 1470 DCI.AddToWorklist(ZextOp.getNode()); 1471 // Otherwise, make this a use of a zext. 1472 return DAG.getSetCC(VT, ZextOp, 1473 DAG.getConstant(C1 & APInt::getLowBitsSet( 1474 ExtDstTyBits, 1475 ExtSrcTyBits), 1476 ExtDstTy), 1477 Cond); 1478 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1479 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1480 1481 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1482 if (N0.getOpcode() == ISD::SETCC) { 1483 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1484 if (TrueWhenTrue) 1485 return N0; 1486 1487 // Invert the condition. 1488 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1489 CC = ISD::getSetCCInverse(CC, 1490 N0.getOperand(0).getValueType().isInteger()); 1491 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1492 } 1493 1494 if ((N0.getOpcode() == ISD::XOR || 1495 (N0.getOpcode() == ISD::AND && 1496 N0.getOperand(0).getOpcode() == ISD::XOR && 1497 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1498 isa<ConstantSDNode>(N0.getOperand(1)) && 1499 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1500 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1501 // can only do this if the top bits are known zero. 1502 unsigned BitWidth = N0.getValueSizeInBits(); 1503 if (DAG.MaskedValueIsZero(N0, 1504 APInt::getHighBitsSet(BitWidth, 1505 BitWidth-1))) { 1506 // Okay, get the un-inverted input value. 1507 SDValue Val; 1508 if (N0.getOpcode() == ISD::XOR) 1509 Val = N0.getOperand(0); 1510 else { 1511 assert(N0.getOpcode() == ISD::AND && 1512 N0.getOperand(0).getOpcode() == ISD::XOR); 1513 // ((X^1)&1)^1 -> X & 1 1514 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1515 N0.getOperand(0).getOperand(0), 1516 N0.getOperand(1)); 1517 } 1518 return DAG.getSetCC(VT, Val, N1, 1519 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1520 } 1521 } 1522 } 1523 1524 APInt MinVal, MaxVal; 1525 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1526 if (ISD::isSignedIntSetCC(Cond)) { 1527 MinVal = APInt::getSignedMinValue(OperandBitSize); 1528 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1529 } else { 1530 MinVal = APInt::getMinValue(OperandBitSize); 1531 MaxVal = APInt::getMaxValue(OperandBitSize); 1532 } 1533 1534 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1535 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1536 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1537 // X >= C0 --> X > (C0-1) 1538 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1539 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1540 } 1541 1542 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1543 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1544 // X <= C0 --> X < (C0+1) 1545 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1546 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1547 } 1548 1549 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1550 return DAG.getConstant(0, VT); // X < MIN --> false 1551 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1552 return DAG.getConstant(1, VT); // X >= MIN --> true 1553 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1554 return DAG.getConstant(0, VT); // X > MAX --> false 1555 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1556 return DAG.getConstant(1, VT); // X <= MAX --> true 1557 1558 // Canonicalize setgt X, Min --> setne X, Min 1559 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1560 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1561 // Canonicalize setlt X, Max --> setne X, Max 1562 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1563 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1564 1565 // If we have setult X, 1, turn it into seteq X, 0 1566 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1567 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1568 ISD::SETEQ); 1569 // If we have setugt X, Max-1, turn it into seteq X, Max 1570 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1571 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1572 ISD::SETEQ); 1573 1574 // If we have "setcc X, C0", check to see if we can shrink the immediate 1575 // by changing cc. 1576 1577 // SETUGT X, SINTMAX -> SETLT X, 0 1578 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1579 C1 == (~0ULL >> (65-OperandBitSize))) 1580 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1581 ISD::SETLT); 1582 1583 // FIXME: Implement the rest of these. 1584 1585 // Fold bit comparisons when we can. 1586 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1587 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1588 if (ConstantSDNode *AndRHS = 1589 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1590 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1591 // Perform the xform if the AND RHS is a single bit. 1592 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1593 return DAG.getNode(ISD::SRL, VT, N0, 1594 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1595 getShiftAmountTy())); 1596 } 1597 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1598 // (X & 8) == 8 --> (X & 8) >> 3 1599 // Perform the xform if C1 is a single bit. 1600 if (C1.isPowerOf2()) { 1601 return DAG.getNode(ISD::SRL, VT, N0, 1602 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1603 } 1604 } 1605 } 1606 } 1607 } else if (isa<ConstantSDNode>(N0.getNode())) { 1608 // Ensure that the constant occurs on the RHS. 1609 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1610 } 1611 1612 if (isa<ConstantFPSDNode>(N0.getNode())) { 1613 // Constant fold or commute setcc. 1614 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1615 if (O.getNode()) return O; 1616 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1617 // If the RHS of an FP comparison is a constant, simplify it away in 1618 // some cases. 1619 if (CFP->getValueAPF().isNaN()) { 1620 // If an operand is known to be a nan, we can fold it. 1621 switch (ISD::getUnorderedFlavor(Cond)) { 1622 default: assert(0 && "Unknown flavor!"); 1623 case 0: // Known false. 1624 return DAG.getConstant(0, VT); 1625 case 1: // Known true. 1626 return DAG.getConstant(1, VT); 1627 case 2: // Undefined. 1628 return DAG.getNode(ISD::UNDEF, VT); 1629 } 1630 } 1631 1632 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1633 // constant if knowing that the operand is non-nan is enough. We prefer to 1634 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1635 // materialize 0.0. 1636 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1637 return DAG.getSetCC(VT, N0, N0, Cond); 1638 } 1639 1640 if (N0 == N1) { 1641 // We can always fold X == X for integer setcc's. 1642 if (N0.getValueType().isInteger()) 1643 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1644 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1645 if (UOF == 2) // FP operators that are undefined on NaNs. 1646 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1647 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1648 return DAG.getConstant(UOF, VT); 1649 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1650 // if it is not already. 1651 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1652 if (NewCond != Cond) 1653 return DAG.getSetCC(VT, N0, N1, NewCond); 1654 } 1655 1656 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1657 N0.getValueType().isInteger()) { 1658 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1659 N0.getOpcode() == ISD::XOR) { 1660 // Simplify (X+Y) == (X+Z) --> Y == Z 1661 if (N0.getOpcode() == N1.getOpcode()) { 1662 if (N0.getOperand(0) == N1.getOperand(0)) 1663 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1664 if (N0.getOperand(1) == N1.getOperand(1)) 1665 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1666 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1667 // If X op Y == Y op X, try other combinations. 1668 if (N0.getOperand(0) == N1.getOperand(1)) 1669 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1670 if (N0.getOperand(1) == N1.getOperand(0)) 1671 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1672 } 1673 } 1674 1675 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1676 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1677 // Turn (X+C1) == C2 --> X == C2-C1 1678 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1679 return DAG.getSetCC(VT, N0.getOperand(0), 1680 DAG.getConstant(RHSC->getAPIntValue()- 1681 LHSR->getAPIntValue(), 1682 N0.getValueType()), Cond); 1683 } 1684 1685 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1686 if (N0.getOpcode() == ISD::XOR) 1687 // If we know that all of the inverted bits are zero, don't bother 1688 // performing the inversion. 1689 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1690 return 1691 DAG.getSetCC(VT, N0.getOperand(0), 1692 DAG.getConstant(LHSR->getAPIntValue() ^ 1693 RHSC->getAPIntValue(), 1694 N0.getValueType()), 1695 Cond); 1696 } 1697 1698 // Turn (C1-X) == C2 --> X == C1-C2 1699 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1700 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1701 return 1702 DAG.getSetCC(VT, N0.getOperand(1), 1703 DAG.getConstant(SUBC->getAPIntValue() - 1704 RHSC->getAPIntValue(), 1705 N0.getValueType()), 1706 Cond); 1707 } 1708 } 1709 } 1710 1711 // Simplify (X+Z) == X --> Z == 0 1712 if (N0.getOperand(0) == N1) 1713 return DAG.getSetCC(VT, N0.getOperand(1), 1714 DAG.getConstant(0, N0.getValueType()), Cond); 1715 if (N0.getOperand(1) == N1) { 1716 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1717 return DAG.getSetCC(VT, N0.getOperand(0), 1718 DAG.getConstant(0, N0.getValueType()), Cond); 1719 else if (N0.getNode()->hasOneUse()) { 1720 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1721 // (Z-X) == X --> Z == X<<1 1722 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1723 N1, 1724 DAG.getConstant(1, getShiftAmountTy())); 1725 if (!DCI.isCalledByLegalizer()) 1726 DCI.AddToWorklist(SH.getNode()); 1727 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1728 } 1729 } 1730 } 1731 1732 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1733 N1.getOpcode() == ISD::XOR) { 1734 // Simplify X == (X+Z) --> Z == 0 1735 if (N1.getOperand(0) == N0) { 1736 return DAG.getSetCC(VT, N1.getOperand(1), 1737 DAG.getConstant(0, N1.getValueType()), Cond); 1738 } else if (N1.getOperand(1) == N0) { 1739 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1740 return DAG.getSetCC(VT, N1.getOperand(0), 1741 DAG.getConstant(0, N1.getValueType()), Cond); 1742 } else if (N1.getNode()->hasOneUse()) { 1743 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1744 // X == (Z-X) --> X<<1 == Z 1745 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1746 DAG.getConstant(1, getShiftAmountTy())); 1747 if (!DCI.isCalledByLegalizer()) 1748 DCI.AddToWorklist(SH.getNode()); 1749 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1750 } 1751 } 1752 } 1753 } 1754 1755 // Fold away ALL boolean setcc's. 1756 SDValue Temp; 1757 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1758 switch (Cond) { 1759 default: assert(0 && "Unknown integer setcc!"); 1760 case ISD::SETEQ: // X == Y -> (X^Y)^1 1761 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1762 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1763 if (!DCI.isCalledByLegalizer()) 1764 DCI.AddToWorklist(Temp.getNode()); 1765 break; 1766 case ISD::SETNE: // X != Y --> (X^Y) 1767 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1768 break; 1769 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1770 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1771 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1772 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1773 if (!DCI.isCalledByLegalizer()) 1774 DCI.AddToWorklist(Temp.getNode()); 1775 break; 1776 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1777 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1778 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1779 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1780 if (!DCI.isCalledByLegalizer()) 1781 DCI.AddToWorklist(Temp.getNode()); 1782 break; 1783 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1784 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1785 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1786 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1787 if (!DCI.isCalledByLegalizer()) 1788 DCI.AddToWorklist(Temp.getNode()); 1789 break; 1790 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1791 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1792 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1793 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1794 break; 1795 } 1796 if (VT != MVT::i1) { 1797 if (!DCI.isCalledByLegalizer()) 1798 DCI.AddToWorklist(N0.getNode()); 1799 // FIXME: If running after legalize, we probably can't do this. 1800 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1801 } 1802 return N0; 1803 } 1804 1805 // Could not fold it. 1806 return SDValue(); 1807} 1808 1809/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1810/// node is a GlobalAddress + offset. 1811bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1812 int64_t &Offset) const { 1813 if (isa<GlobalAddressSDNode>(N)) { 1814 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1815 GA = GASD->getGlobal(); 1816 Offset += GASD->getOffset(); 1817 return true; 1818 } 1819 1820 if (N->getOpcode() == ISD::ADD) { 1821 SDValue N1 = N->getOperand(0); 1822 SDValue N2 = N->getOperand(1); 1823 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1824 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1825 if (V) { 1826 Offset += V->getSExtValue(); 1827 return true; 1828 } 1829 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1830 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1831 if (V) { 1832 Offset += V->getSExtValue(); 1833 return true; 1834 } 1835 } 1836 } 1837 return false; 1838} 1839 1840 1841/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1842/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1843/// location that the 'Base' load is loading from. 1844bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1845 unsigned Bytes, int Dist, 1846 const MachineFrameInfo *MFI) const { 1847 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1848 return false; 1849 MVT VT = LD->getValueType(0); 1850 if (VT.getSizeInBits() / 8 != Bytes) 1851 return false; 1852 1853 SDValue Loc = LD->getOperand(1); 1854 SDValue BaseLoc = Base->getOperand(1); 1855 if (Loc.getOpcode() == ISD::FrameIndex) { 1856 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1857 return false; 1858 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1859 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1860 int FS = MFI->getObjectSize(FI); 1861 int BFS = MFI->getObjectSize(BFI); 1862 if (FS != BFS || FS != (int)Bytes) return false; 1863 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1864 } 1865 1866 GlobalValue *GV1 = NULL; 1867 GlobalValue *GV2 = NULL; 1868 int64_t Offset1 = 0; 1869 int64_t Offset2 = 0; 1870 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1871 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1872 if (isGA1 && isGA2 && GV1 == GV2) 1873 return Offset1 == (Offset2 + Dist*Bytes); 1874 return false; 1875} 1876 1877 1878SDValue TargetLowering:: 1879PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1880 // Default implementation: no optimization. 1881 return SDValue(); 1882} 1883 1884//===----------------------------------------------------------------------===// 1885// Inline Assembler Implementation Methods 1886//===----------------------------------------------------------------------===// 1887 1888 1889TargetLowering::ConstraintType 1890TargetLowering::getConstraintType(const std::string &Constraint) const { 1891 // FIXME: lots more standard ones to handle. 1892 if (Constraint.size() == 1) { 1893 switch (Constraint[0]) { 1894 default: break; 1895 case 'r': return C_RegisterClass; 1896 case 'm': // memory 1897 case 'o': // offsetable 1898 case 'V': // not offsetable 1899 return C_Memory; 1900 case 'i': // Simple Integer or Relocatable Constant 1901 case 'n': // Simple Integer 1902 case 's': // Relocatable Constant 1903 case 'X': // Allow ANY value. 1904 case 'I': // Target registers. 1905 case 'J': 1906 case 'K': 1907 case 'L': 1908 case 'M': 1909 case 'N': 1910 case 'O': 1911 case 'P': 1912 return C_Other; 1913 } 1914 } 1915 1916 if (Constraint.size() > 1 && Constraint[0] == '{' && 1917 Constraint[Constraint.size()-1] == '}') 1918 return C_Register; 1919 return C_Unknown; 1920} 1921 1922/// LowerXConstraint - try to replace an X constraint, which matches anything, 1923/// with another that has more specific requirements based on the type of the 1924/// corresponding operand. 1925const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 1926 if (ConstraintVT.isInteger()) 1927 return "r"; 1928 if (ConstraintVT.isFloatingPoint()) 1929 return "f"; // works for many targets 1930 return 0; 1931} 1932 1933/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1934/// vector. If it is invalid, don't add anything to Ops. 1935void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1936 char ConstraintLetter, 1937 bool hasMemory, 1938 std::vector<SDValue> &Ops, 1939 SelectionDAG &DAG) const { 1940 switch (ConstraintLetter) { 1941 default: break; 1942 case 'X': // Allows any operand; labels (basic block) use this. 1943 if (Op.getOpcode() == ISD::BasicBlock) { 1944 Ops.push_back(Op); 1945 return; 1946 } 1947 // fall through 1948 case 'i': // Simple Integer or Relocatable Constant 1949 case 'n': // Simple Integer 1950 case 's': { // Relocatable Constant 1951 // These operands are interested in values of the form (GV+C), where C may 1952 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1953 // is possible and fine if either GV or C are missing. 1954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1955 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1956 1957 // If we have "(add GV, C)", pull out GV/C 1958 if (Op.getOpcode() == ISD::ADD) { 1959 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1960 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1961 if (C == 0 || GA == 0) { 1962 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1963 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1964 } 1965 if (C == 0 || GA == 0) 1966 C = 0, GA = 0; 1967 } 1968 1969 // If we find a valid operand, map to the TargetXXX version so that the 1970 // value itself doesn't get selected. 1971 if (GA) { // Either &GV or &GV+C 1972 if (ConstraintLetter != 'n') { 1973 int64_t Offs = GA->getOffset(); 1974 if (C) Offs += C->getZExtValue(); 1975 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1976 Op.getValueType(), Offs)); 1977 return; 1978 } 1979 } 1980 if (C) { // just C, no GV. 1981 // Simple constants are not allowed for 's'. 1982 if (ConstraintLetter != 's') { 1983 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), 1984 Op.getValueType())); 1985 return; 1986 } 1987 } 1988 break; 1989 } 1990 } 1991} 1992 1993std::vector<unsigned> TargetLowering:: 1994getRegClassForInlineAsmConstraint(const std::string &Constraint, 1995 MVT VT) const { 1996 return std::vector<unsigned>(); 1997} 1998 1999 2000std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2001getRegForInlineAsmConstraint(const std::string &Constraint, 2002 MVT VT) const { 2003 if (Constraint[0] != '{') 2004 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2005 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2006 2007 // Remove the braces from around the name. 2008 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2009 2010 // Figure out which register class contains this reg. 2011 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2012 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2013 E = RI->regclass_end(); RCI != E; ++RCI) { 2014 const TargetRegisterClass *RC = *RCI; 2015 2016 // If none of the the value types for this register class are valid, we 2017 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2018 bool isLegal = false; 2019 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2020 I != E; ++I) { 2021 if (isTypeLegal(*I)) { 2022 isLegal = true; 2023 break; 2024 } 2025 } 2026 2027 if (!isLegal) continue; 2028 2029 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2030 I != E; ++I) { 2031 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2032 return std::make_pair(*I, RC); 2033 } 2034 } 2035 2036 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2037} 2038 2039//===----------------------------------------------------------------------===// 2040// Constraint Selection. 2041 2042/// isMatchingInputConstraint - Return true of this is an input operand that is 2043/// a matching constraint like "4". 2044bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2045 assert(!ConstraintCode.empty() && "No known constraint!"); 2046 return isdigit(ConstraintCode[0]); 2047} 2048 2049/// getMatchedOperand - If this is an input matching constraint, this method 2050/// returns the output operand it matches. 2051unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2052 assert(!ConstraintCode.empty() && "No known constraint!"); 2053 return atoi(ConstraintCode.c_str()); 2054} 2055 2056 2057/// getConstraintGenerality - Return an integer indicating how general CT 2058/// is. 2059static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2060 switch (CT) { 2061 default: assert(0 && "Unknown constraint type!"); 2062 case TargetLowering::C_Other: 2063 case TargetLowering::C_Unknown: 2064 return 0; 2065 case TargetLowering::C_Register: 2066 return 1; 2067 case TargetLowering::C_RegisterClass: 2068 return 2; 2069 case TargetLowering::C_Memory: 2070 return 3; 2071 } 2072} 2073 2074/// ChooseConstraint - If there are multiple different constraints that we 2075/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2076/// This is somewhat tricky: constraints fall into four classes: 2077/// Other -> immediates and magic values 2078/// Register -> one specific register 2079/// RegisterClass -> a group of regs 2080/// Memory -> memory 2081/// Ideally, we would pick the most specific constraint possible: if we have 2082/// something that fits into a register, we would pick it. The problem here 2083/// is that if we have something that could either be in a register or in 2084/// memory that use of the register could cause selection of *other* 2085/// operands to fail: they might only succeed if we pick memory. Because of 2086/// this the heuristic we use is: 2087/// 2088/// 1) If there is an 'other' constraint, and if the operand is valid for 2089/// that constraint, use it. This makes us take advantage of 'i' 2090/// constraints when available. 2091/// 2) Otherwise, pick the most general constraint present. This prefers 2092/// 'm' over 'r', for example. 2093/// 2094static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2095 bool hasMemory, const TargetLowering &TLI, 2096 SDValue Op, SelectionDAG *DAG) { 2097 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2098 unsigned BestIdx = 0; 2099 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2100 int BestGenerality = -1; 2101 2102 // Loop over the options, keeping track of the most general one. 2103 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2104 TargetLowering::ConstraintType CType = 2105 TLI.getConstraintType(OpInfo.Codes[i]); 2106 2107 // If this is an 'other' constraint, see if the operand is valid for it. 2108 // For example, on X86 we might have an 'rI' constraint. If the operand 2109 // is an integer in the range [0..31] we want to use I (saving a load 2110 // of a register), otherwise we must use 'r'. 2111 if (CType == TargetLowering::C_Other && Op.getNode()) { 2112 assert(OpInfo.Codes[i].size() == 1 && 2113 "Unhandled multi-letter 'other' constraint"); 2114 std::vector<SDValue> ResultOps; 2115 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2116 ResultOps, *DAG); 2117 if (!ResultOps.empty()) { 2118 BestType = CType; 2119 BestIdx = i; 2120 break; 2121 } 2122 } 2123 2124 // This constraint letter is more general than the previous one, use it. 2125 int Generality = getConstraintGenerality(CType); 2126 if (Generality > BestGenerality) { 2127 BestType = CType; 2128 BestIdx = i; 2129 BestGenerality = Generality; 2130 } 2131 } 2132 2133 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2134 OpInfo.ConstraintType = BestType; 2135} 2136 2137/// ComputeConstraintToUse - Determines the constraint code and constraint 2138/// type to use for the specific AsmOperandInfo, setting 2139/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2140void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2141 SDValue Op, 2142 bool hasMemory, 2143 SelectionDAG *DAG) const { 2144 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2145 2146 // Single-letter constraints ('r') are very common. 2147 if (OpInfo.Codes.size() == 1) { 2148 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2149 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2150 } else { 2151 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2152 } 2153 2154 // 'X' matches anything. 2155 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2156 // Labels and constants are handled elsewhere ('X' is the only thing 2157 // that matches labels). 2158 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2159 isa<ConstantInt>(OpInfo.CallOperandVal)) 2160 return; 2161 2162 // Otherwise, try to resolve it to something we know about by looking at 2163 // the actual operand type. 2164 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2165 OpInfo.ConstraintCode = Repl; 2166 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2167 } 2168 } 2169} 2170 2171//===----------------------------------------------------------------------===// 2172// Loop Strength Reduction hooks 2173//===----------------------------------------------------------------------===// 2174 2175/// isLegalAddressingMode - Return true if the addressing mode represented 2176/// by AM is legal for this target, for a load/store of the specified type. 2177bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2178 const Type *Ty) const { 2179 // The default implementation of this implements a conservative RISCy, r+r and 2180 // r+i addr mode. 2181 2182 // Allows a sign-extended 16-bit immediate field. 2183 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2184 return false; 2185 2186 // No global is ever allowed as a base. 2187 if (AM.BaseGV) 2188 return false; 2189 2190 // Only support r+r, 2191 switch (AM.Scale) { 2192 case 0: // "r+i" or just "i", depending on HasBaseReg. 2193 break; 2194 case 1: 2195 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2196 return false; 2197 // Otherwise we have r+r or r+i. 2198 break; 2199 case 2: 2200 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2201 return false; 2202 // Allow 2*r as r+r. 2203 break; 2204 } 2205 2206 return true; 2207} 2208 2209// Magic for divide replacement 2210 2211struct ms { 2212 int64_t m; // magic number 2213 int64_t s; // shift amount 2214}; 2215 2216struct mu { 2217 uint64_t m; // magic number 2218 int64_t a; // add indicator 2219 int64_t s; // shift amount 2220}; 2221 2222/// magic - calculate the magic numbers required to codegen an integer sdiv as 2223/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2224/// or -1. 2225static ms magic32(int32_t d) { 2226 int32_t p; 2227 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2228 const uint32_t two31 = 0x80000000U; 2229 struct ms mag; 2230 2231 ad = abs(d); 2232 t = two31 + ((uint32_t)d >> 31); 2233 anc = t - 1 - t%ad; // absolute value of nc 2234 p = 31; // initialize p 2235 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2236 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2237 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2238 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2239 do { 2240 p = p + 1; 2241 q1 = 2*q1; // update q1 = 2p/abs(nc) 2242 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2243 if (r1 >= anc) { // must be unsigned comparison 2244 q1 = q1 + 1; 2245 r1 = r1 - anc; 2246 } 2247 q2 = 2*q2; // update q2 = 2p/abs(d) 2248 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2249 if (r2 >= ad) { // must be unsigned comparison 2250 q2 = q2 + 1; 2251 r2 = r2 - ad; 2252 } 2253 delta = ad - r2; 2254 } while (q1 < delta || (q1 == delta && r1 == 0)); 2255 2256 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2257 if (d < 0) mag.m = -mag.m; // resulting magic number 2258 mag.s = p - 32; // resulting shift 2259 return mag; 2260} 2261 2262/// magicu - calculate the magic numbers required to codegen an integer udiv as 2263/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2264static mu magicu32(uint32_t d) { 2265 int32_t p; 2266 uint32_t nc, delta, q1, r1, q2, r2; 2267 struct mu magu; 2268 magu.a = 0; // initialize "add" indicator 2269 nc = - 1 - (-d)%d; 2270 p = 31; // initialize p 2271 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2272 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2273 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2274 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2275 do { 2276 p = p + 1; 2277 if (r1 >= nc - r1 ) { 2278 q1 = 2*q1 + 1; // update q1 2279 r1 = 2*r1 - nc; // update r1 2280 } 2281 else { 2282 q1 = 2*q1; // update q1 2283 r1 = 2*r1; // update r1 2284 } 2285 if (r2 + 1 >= d - r2) { 2286 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2287 q2 = 2*q2 + 1; // update q2 2288 r2 = 2*r2 + 1 - d; // update r2 2289 } 2290 else { 2291 if (q2 >= 0x80000000) magu.a = 1; 2292 q2 = 2*q2; // update q2 2293 r2 = 2*r2 + 1; // update r2 2294 } 2295 delta = d - 1 - r2; 2296 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2297 magu.m = q2 + 1; // resulting magic number 2298 magu.s = p - 32; // resulting shift 2299 return magu; 2300} 2301 2302/// magic - calculate the magic numbers required to codegen an integer sdiv as 2303/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2304/// or -1. 2305static ms magic64(int64_t d) { 2306 int64_t p; 2307 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2308 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2309 struct ms mag; 2310 2311 ad = d >= 0 ? d : -d; 2312 t = two63 + ((uint64_t)d >> 63); 2313 anc = t - 1 - t%ad; // absolute value of nc 2314 p = 63; // initialize p 2315 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2316 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2317 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2318 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2319 do { 2320 p = p + 1; 2321 q1 = 2*q1; // update q1 = 2p/abs(nc) 2322 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2323 if (r1 >= anc) { // must be unsigned comparison 2324 q1 = q1 + 1; 2325 r1 = r1 - anc; 2326 } 2327 q2 = 2*q2; // update q2 = 2p/abs(d) 2328 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2329 if (r2 >= ad) { // must be unsigned comparison 2330 q2 = q2 + 1; 2331 r2 = r2 - ad; 2332 } 2333 delta = ad - r2; 2334 } while (q1 < delta || (q1 == delta && r1 == 0)); 2335 2336 mag.m = q2 + 1; 2337 if (d < 0) mag.m = -mag.m; // resulting magic number 2338 mag.s = p - 64; // resulting shift 2339 return mag; 2340} 2341 2342/// magicu - calculate the magic numbers required to codegen an integer udiv as 2343/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2344static mu magicu64(uint64_t d) 2345{ 2346 int64_t p; 2347 uint64_t nc, delta, q1, r1, q2, r2; 2348 struct mu magu; 2349 magu.a = 0; // initialize "add" indicator 2350 nc = - 1 - (-d)%d; 2351 p = 63; // initialize p 2352 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2353 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2354 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2355 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2356 do { 2357 p = p + 1; 2358 if (r1 >= nc - r1 ) { 2359 q1 = 2*q1 + 1; // update q1 2360 r1 = 2*r1 - nc; // update r1 2361 } 2362 else { 2363 q1 = 2*q1; // update q1 2364 r1 = 2*r1; // update r1 2365 } 2366 if (r2 + 1 >= d - r2) { 2367 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2368 q2 = 2*q2 + 1; // update q2 2369 r2 = 2*r2 + 1 - d; // update r2 2370 } 2371 else { 2372 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2373 q2 = 2*q2; // update q2 2374 r2 = 2*r2 + 1; // update r2 2375 } 2376 delta = d - 1 - r2; 2377 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2378 magu.m = q2 + 1; // resulting magic number 2379 magu.s = p - 64; // resulting shift 2380 return magu; 2381} 2382 2383/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2384/// return a DAG expression to select that will generate the same value by 2385/// multiplying by a magic number. See: 2386/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2387SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2388 std::vector<SDNode*>* Created) const { 2389 MVT VT = N->getValueType(0); 2390 2391 // Check to see if we can do this. 2392 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2393 return SDValue(); // BuildSDIV only operates on i32 or i64 2394 2395 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue(); 2396 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2397 2398 // Multiply the numerator (operand 0) by the magic value 2399 SDValue Q; 2400 if (isOperationLegal(ISD::MULHS, VT)) 2401 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2402 DAG.getConstant(magics.m, VT)); 2403 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 2404 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2405 N->getOperand(0), 2406 DAG.getConstant(magics.m, VT)).getNode(), 1); 2407 else 2408 return SDValue(); // No mulhs or equvialent 2409 // If d > 0 and m < 0, add the numerator 2410 if (d > 0 && magics.m < 0) { 2411 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2412 if (Created) 2413 Created->push_back(Q.getNode()); 2414 } 2415 // If d < 0 and m > 0, subtract the numerator. 2416 if (d < 0 && magics.m > 0) { 2417 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2418 if (Created) 2419 Created->push_back(Q.getNode()); 2420 } 2421 // Shift right algebraic if shift value is nonzero 2422 if (magics.s > 0) { 2423 Q = DAG.getNode(ISD::SRA, VT, Q, 2424 DAG.getConstant(magics.s, getShiftAmountTy())); 2425 if (Created) 2426 Created->push_back(Q.getNode()); 2427 } 2428 // Extract the sign bit and add it to the quotient 2429 SDValue T = 2430 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2431 getShiftAmountTy())); 2432 if (Created) 2433 Created->push_back(T.getNode()); 2434 return DAG.getNode(ISD::ADD, VT, Q, T); 2435} 2436 2437/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2438/// return a DAG expression to select that will generate the same value by 2439/// multiplying by a magic number. See: 2440/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2441SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2442 std::vector<SDNode*>* Created) const { 2443 MVT VT = N->getValueType(0); 2444 2445 // Check to see if we can do this. 2446 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2447 return SDValue(); // BuildUDIV only operates on i32 or i64 2448 2449 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 2450 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2451 2452 // Multiply the numerator (operand 0) by the magic value 2453 SDValue Q; 2454 if (isOperationLegal(ISD::MULHU, VT)) 2455 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2456 DAG.getConstant(magics.m, VT)); 2457 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2458 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2459 N->getOperand(0), 2460 DAG.getConstant(magics.m, VT)).getNode(), 1); 2461 else 2462 return SDValue(); // No mulhu or equvialent 2463 if (Created) 2464 Created->push_back(Q.getNode()); 2465 2466 if (magics.a == 0) { 2467 return DAG.getNode(ISD::SRL, VT, Q, 2468 DAG.getConstant(magics.s, getShiftAmountTy())); 2469 } else { 2470 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2471 if (Created) 2472 Created->push_back(NPQ.getNode()); 2473 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2474 DAG.getConstant(1, getShiftAmountTy())); 2475 if (Created) 2476 Created->push_back(NPQ.getNode()); 2477 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2478 if (Created) 2479 Created->push_back(NPQ.getNode()); 2480 return DAG.getNode(ISD::SRL, VT, NPQ, 2481 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2482 } 2483} 2484