TargetLowering.cpp revision 8c1ec5a0a21dcb3364aace8174f29f209ff3224e
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/MathExtras.h" 32#include <cctype> 33using namespace llvm; 34 35/// We are in the process of implementing a new TypeLegalization action 36/// - the promotion of vector elements. This feature is disabled by default 37/// and only enabled using this flag. 38static cl::opt<bool> 39AllowPromoteIntElem("promote-elements", cl::Hidden, 40 cl::desc("Allow promotion of integer vector element types")); 41 42namespace llvm { 43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 44 bool isLocal = GV->hasLocalLinkage(); 45 bool isDeclaration = GV->isDeclaration(); 46 // FIXME: what should we do for protected and internal visibility? 47 // For variables, is internal different from hidden? 48 bool isHidden = GV->hasHiddenVisibility(); 49 50 if (reloc == Reloc::PIC_) { 51 if (isLocal || isHidden) 52 return TLSModel::LocalDynamic; 53 else 54 return TLSModel::GeneralDynamic; 55 } else { 56 if (!isDeclaration || isHidden) 57 return TLSModel::LocalExec; 58 else 59 return TLSModel::InitialExec; 60 } 61} 62} 63 64/// InitLibcallNames - Set default libcall names. 65/// 66static void InitLibcallNames(const char **Names) { 67 Names[RTLIB::SHL_I16] = "__ashlhi3"; 68 Names[RTLIB::SHL_I32] = "__ashlsi3"; 69 Names[RTLIB::SHL_I64] = "__ashldi3"; 70 Names[RTLIB::SHL_I128] = "__ashlti3"; 71 Names[RTLIB::SRL_I16] = "__lshrhi3"; 72 Names[RTLIB::SRL_I32] = "__lshrsi3"; 73 Names[RTLIB::SRL_I64] = "__lshrdi3"; 74 Names[RTLIB::SRL_I128] = "__lshrti3"; 75 Names[RTLIB::SRA_I16] = "__ashrhi3"; 76 Names[RTLIB::SRA_I32] = "__ashrsi3"; 77 Names[RTLIB::SRA_I64] = "__ashrdi3"; 78 Names[RTLIB::SRA_I128] = "__ashrti3"; 79 Names[RTLIB::MUL_I8] = "__mulqi3"; 80 Names[RTLIB::MUL_I16] = "__mulhi3"; 81 Names[RTLIB::MUL_I32] = "__mulsi3"; 82 Names[RTLIB::MUL_I64] = "__muldi3"; 83 Names[RTLIB::MUL_I128] = "__multi3"; 84 Names[RTLIB::SDIV_I8] = "__divqi3"; 85 Names[RTLIB::SDIV_I16] = "__divhi3"; 86 Names[RTLIB::SDIV_I32] = "__divsi3"; 87 Names[RTLIB::SDIV_I64] = "__divdi3"; 88 Names[RTLIB::SDIV_I128] = "__divti3"; 89 Names[RTLIB::UDIV_I8] = "__udivqi3"; 90 Names[RTLIB::UDIV_I16] = "__udivhi3"; 91 Names[RTLIB::UDIV_I32] = "__udivsi3"; 92 Names[RTLIB::UDIV_I64] = "__udivdi3"; 93 Names[RTLIB::UDIV_I128] = "__udivti3"; 94 Names[RTLIB::SREM_I8] = "__modqi3"; 95 Names[RTLIB::SREM_I16] = "__modhi3"; 96 Names[RTLIB::SREM_I32] = "__modsi3"; 97 Names[RTLIB::SREM_I64] = "__moddi3"; 98 Names[RTLIB::SREM_I128] = "__modti3"; 99 Names[RTLIB::UREM_I8] = "__umodqi3"; 100 Names[RTLIB::UREM_I16] = "__umodhi3"; 101 Names[RTLIB::UREM_I32] = "__umodsi3"; 102 Names[RTLIB::UREM_I64] = "__umoddi3"; 103 Names[RTLIB::UREM_I128] = "__umodti3"; 104 105 // These are generally not available. 106 Names[RTLIB::SDIVREM_I8] = 0; 107 Names[RTLIB::SDIVREM_I16] = 0; 108 Names[RTLIB::SDIVREM_I32] = 0; 109 Names[RTLIB::SDIVREM_I64] = 0; 110 Names[RTLIB::SDIVREM_I128] = 0; 111 Names[RTLIB::UDIVREM_I8] = 0; 112 Names[RTLIB::UDIVREM_I16] = 0; 113 Names[RTLIB::UDIVREM_I32] = 0; 114 Names[RTLIB::UDIVREM_I64] = 0; 115 Names[RTLIB::UDIVREM_I128] = 0; 116 117 Names[RTLIB::NEG_I32] = "__negsi2"; 118 Names[RTLIB::NEG_I64] = "__negdi2"; 119 Names[RTLIB::ADD_F32] = "__addsf3"; 120 Names[RTLIB::ADD_F64] = "__adddf3"; 121 Names[RTLIB::ADD_F80] = "__addxf3"; 122 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 123 Names[RTLIB::SUB_F32] = "__subsf3"; 124 Names[RTLIB::SUB_F64] = "__subdf3"; 125 Names[RTLIB::SUB_F80] = "__subxf3"; 126 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 127 Names[RTLIB::MUL_F32] = "__mulsf3"; 128 Names[RTLIB::MUL_F64] = "__muldf3"; 129 Names[RTLIB::MUL_F80] = "__mulxf3"; 130 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 131 Names[RTLIB::DIV_F32] = "__divsf3"; 132 Names[RTLIB::DIV_F64] = "__divdf3"; 133 Names[RTLIB::DIV_F80] = "__divxf3"; 134 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 135 Names[RTLIB::REM_F32] = "fmodf"; 136 Names[RTLIB::REM_F64] = "fmod"; 137 Names[RTLIB::REM_F80] = "fmodl"; 138 Names[RTLIB::REM_PPCF128] = "fmodl"; 139 Names[RTLIB::POWI_F32] = "__powisf2"; 140 Names[RTLIB::POWI_F64] = "__powidf2"; 141 Names[RTLIB::POWI_F80] = "__powixf2"; 142 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 143 Names[RTLIB::SQRT_F32] = "sqrtf"; 144 Names[RTLIB::SQRT_F64] = "sqrt"; 145 Names[RTLIB::SQRT_F80] = "sqrtl"; 146 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 147 Names[RTLIB::LOG_F32] = "logf"; 148 Names[RTLIB::LOG_F64] = "log"; 149 Names[RTLIB::LOG_F80] = "logl"; 150 Names[RTLIB::LOG_PPCF128] = "logl"; 151 Names[RTLIB::LOG2_F32] = "log2f"; 152 Names[RTLIB::LOG2_F64] = "log2"; 153 Names[RTLIB::LOG2_F80] = "log2l"; 154 Names[RTLIB::LOG2_PPCF128] = "log2l"; 155 Names[RTLIB::LOG10_F32] = "log10f"; 156 Names[RTLIB::LOG10_F64] = "log10"; 157 Names[RTLIB::LOG10_F80] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_PPCF128] = "expl"; 163 Names[RTLIB::EXP2_F32] = "exp2f"; 164 Names[RTLIB::EXP2_F64] = "exp2"; 165 Names[RTLIB::EXP2_F80] = "exp2l"; 166 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 167 Names[RTLIB::SIN_F32] = "sinf"; 168 Names[RTLIB::SIN_F64] = "sin"; 169 Names[RTLIB::SIN_F80] = "sinl"; 170 Names[RTLIB::SIN_PPCF128] = "sinl"; 171 Names[RTLIB::COS_F32] = "cosf"; 172 Names[RTLIB::COS_F64] = "cos"; 173 Names[RTLIB::COS_F80] = "cosl"; 174 Names[RTLIB::COS_PPCF128] = "cosl"; 175 Names[RTLIB::POW_F32] = "powf"; 176 Names[RTLIB::POW_F64] = "pow"; 177 Names[RTLIB::POW_F80] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_PPCF128] = "ceill"; 183 Names[RTLIB::TRUNC_F32] = "truncf"; 184 Names[RTLIB::TRUNC_F64] = "trunc"; 185 Names[RTLIB::TRUNC_F80] = "truncl"; 186 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 187 Names[RTLIB::RINT_F32] = "rintf"; 188 Names[RTLIB::RINT_F64] = "rint"; 189 Names[RTLIB::RINT_F80] = "rintl"; 190 Names[RTLIB::RINT_PPCF128] = "rintl"; 191 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 192 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 193 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 194 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 195 Names[RTLIB::FLOOR_F32] = "floorf"; 196 Names[RTLIB::FLOOR_F64] = "floor"; 197 Names[RTLIB::FLOOR_F80] = "floorl"; 198 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 199 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 200 Names[RTLIB::COPYSIGN_F64] = "copysign"; 201 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 202 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 203 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 204 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 205 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 206 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 207 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 208 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 209 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 210 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 211 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 212 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 213 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 214 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 215 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 216 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 217 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 218 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 219 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 220 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 221 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 222 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 223 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 224 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 225 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 226 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 227 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 228 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 229 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 230 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 231 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 232 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 233 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 234 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 235 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 236 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 237 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 238 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 239 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 240 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 241 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 242 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 243 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 244 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 245 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 246 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 247 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 248 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 249 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 250 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 251 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 252 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 253 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 254 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 255 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 256 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 257 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 258 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 259 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 260 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 261 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 262 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 263 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 264 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 265 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 266 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 267 Names[RTLIB::OEQ_F32] = "__eqsf2"; 268 Names[RTLIB::OEQ_F64] = "__eqdf2"; 269 Names[RTLIB::UNE_F32] = "__nesf2"; 270 Names[RTLIB::UNE_F64] = "__nedf2"; 271 Names[RTLIB::OGE_F32] = "__gesf2"; 272 Names[RTLIB::OGE_F64] = "__gedf2"; 273 Names[RTLIB::OLT_F32] = "__ltsf2"; 274 Names[RTLIB::OLT_F64] = "__ltdf2"; 275 Names[RTLIB::OLE_F32] = "__lesf2"; 276 Names[RTLIB::OLE_F64] = "__ledf2"; 277 Names[RTLIB::OGT_F32] = "__gtsf2"; 278 Names[RTLIB::OGT_F64] = "__gtdf2"; 279 Names[RTLIB::UO_F32] = "__unordsf2"; 280 Names[RTLIB::UO_F64] = "__unorddf2"; 281 Names[RTLIB::O_F32] = "__unordsf2"; 282 Names[RTLIB::O_F64] = "__unorddf2"; 283 Names[RTLIB::MEMCPY] = "memcpy"; 284 Names[RTLIB::MEMMOVE] = "memmove"; 285 Names[RTLIB::MEMSET] = "memset"; 286 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 287 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 288 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 289 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 290 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 291 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 292 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 293 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 294 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 295 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 296 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 297 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 298 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 299 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 300 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 301 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 302 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 303 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 304 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 305 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 306 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 307 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 308 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 309 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 310 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 311 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 312 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 313 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 314 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 315 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 316 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 317 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 318 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 319} 320 321/// InitLibcallCallingConvs - Set default libcall CallingConvs. 322/// 323static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 324 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 325 CCs[i] = CallingConv::C; 326 } 327} 328 329/// getFPEXT - Return the FPEXT_*_* value for the given types, or 330/// UNKNOWN_LIBCALL if there is none. 331RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 332 if (OpVT == MVT::f32) { 333 if (RetVT == MVT::f64) 334 return FPEXT_F32_F64; 335 } 336 337 return UNKNOWN_LIBCALL; 338} 339 340/// getFPROUND - Return the FPROUND_*_* value for the given types, or 341/// UNKNOWN_LIBCALL if there is none. 342RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 343 if (RetVT == MVT::f32) { 344 if (OpVT == MVT::f64) 345 return FPROUND_F64_F32; 346 if (OpVT == MVT::f80) 347 return FPROUND_F80_F32; 348 if (OpVT == MVT::ppcf128) 349 return FPROUND_PPCF128_F32; 350 } else if (RetVT == MVT::f64) { 351 if (OpVT == MVT::f80) 352 return FPROUND_F80_F64; 353 if (OpVT == MVT::ppcf128) 354 return FPROUND_PPCF128_F64; 355 } 356 357 return UNKNOWN_LIBCALL; 358} 359 360/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 361/// UNKNOWN_LIBCALL if there is none. 362RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 363 if (OpVT == MVT::f32) { 364 if (RetVT == MVT::i8) 365 return FPTOSINT_F32_I8; 366 if (RetVT == MVT::i16) 367 return FPTOSINT_F32_I16; 368 if (RetVT == MVT::i32) 369 return FPTOSINT_F32_I32; 370 if (RetVT == MVT::i64) 371 return FPTOSINT_F32_I64; 372 if (RetVT == MVT::i128) 373 return FPTOSINT_F32_I128; 374 } else if (OpVT == MVT::f64) { 375 if (RetVT == MVT::i8) 376 return FPTOSINT_F64_I8; 377 if (RetVT == MVT::i16) 378 return FPTOSINT_F64_I16; 379 if (RetVT == MVT::i32) 380 return FPTOSINT_F64_I32; 381 if (RetVT == MVT::i64) 382 return FPTOSINT_F64_I64; 383 if (RetVT == MVT::i128) 384 return FPTOSINT_F64_I128; 385 } else if (OpVT == MVT::f80) { 386 if (RetVT == MVT::i32) 387 return FPTOSINT_F80_I32; 388 if (RetVT == MVT::i64) 389 return FPTOSINT_F80_I64; 390 if (RetVT == MVT::i128) 391 return FPTOSINT_F80_I128; 392 } else if (OpVT == MVT::ppcf128) { 393 if (RetVT == MVT::i32) 394 return FPTOSINT_PPCF128_I32; 395 if (RetVT == MVT::i64) 396 return FPTOSINT_PPCF128_I64; 397 if (RetVT == MVT::i128) 398 return FPTOSINT_PPCF128_I128; 399 } 400 return UNKNOWN_LIBCALL; 401} 402 403/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 404/// UNKNOWN_LIBCALL if there is none. 405RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 406 if (OpVT == MVT::f32) { 407 if (RetVT == MVT::i8) 408 return FPTOUINT_F32_I8; 409 if (RetVT == MVT::i16) 410 return FPTOUINT_F32_I16; 411 if (RetVT == MVT::i32) 412 return FPTOUINT_F32_I32; 413 if (RetVT == MVT::i64) 414 return FPTOUINT_F32_I64; 415 if (RetVT == MVT::i128) 416 return FPTOUINT_F32_I128; 417 } else if (OpVT == MVT::f64) { 418 if (RetVT == MVT::i8) 419 return FPTOUINT_F64_I8; 420 if (RetVT == MVT::i16) 421 return FPTOUINT_F64_I16; 422 if (RetVT == MVT::i32) 423 return FPTOUINT_F64_I32; 424 if (RetVT == MVT::i64) 425 return FPTOUINT_F64_I64; 426 if (RetVT == MVT::i128) 427 return FPTOUINT_F64_I128; 428 } else if (OpVT == MVT::f80) { 429 if (RetVT == MVT::i32) 430 return FPTOUINT_F80_I32; 431 if (RetVT == MVT::i64) 432 return FPTOUINT_F80_I64; 433 if (RetVT == MVT::i128) 434 return FPTOUINT_F80_I128; 435 } else if (OpVT == MVT::ppcf128) { 436 if (RetVT == MVT::i32) 437 return FPTOUINT_PPCF128_I32; 438 if (RetVT == MVT::i64) 439 return FPTOUINT_PPCF128_I64; 440 if (RetVT == MVT::i128) 441 return FPTOUINT_PPCF128_I128; 442 } 443 return UNKNOWN_LIBCALL; 444} 445 446/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 447/// UNKNOWN_LIBCALL if there is none. 448RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 449 if (OpVT == MVT::i32) { 450 if (RetVT == MVT::f32) 451 return SINTTOFP_I32_F32; 452 else if (RetVT == MVT::f64) 453 return SINTTOFP_I32_F64; 454 else if (RetVT == MVT::f80) 455 return SINTTOFP_I32_F80; 456 else if (RetVT == MVT::ppcf128) 457 return SINTTOFP_I32_PPCF128; 458 } else if (OpVT == MVT::i64) { 459 if (RetVT == MVT::f32) 460 return SINTTOFP_I64_F32; 461 else if (RetVT == MVT::f64) 462 return SINTTOFP_I64_F64; 463 else if (RetVT == MVT::f80) 464 return SINTTOFP_I64_F80; 465 else if (RetVT == MVT::ppcf128) 466 return SINTTOFP_I64_PPCF128; 467 } else if (OpVT == MVT::i128) { 468 if (RetVT == MVT::f32) 469 return SINTTOFP_I128_F32; 470 else if (RetVT == MVT::f64) 471 return SINTTOFP_I128_F64; 472 else if (RetVT == MVT::f80) 473 return SINTTOFP_I128_F80; 474 else if (RetVT == MVT::ppcf128) 475 return SINTTOFP_I128_PPCF128; 476 } 477 return UNKNOWN_LIBCALL; 478} 479 480/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 481/// UNKNOWN_LIBCALL if there is none. 482RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 483 if (OpVT == MVT::i32) { 484 if (RetVT == MVT::f32) 485 return UINTTOFP_I32_F32; 486 else if (RetVT == MVT::f64) 487 return UINTTOFP_I32_F64; 488 else if (RetVT == MVT::f80) 489 return UINTTOFP_I32_F80; 490 else if (RetVT == MVT::ppcf128) 491 return UINTTOFP_I32_PPCF128; 492 } else if (OpVT == MVT::i64) { 493 if (RetVT == MVT::f32) 494 return UINTTOFP_I64_F32; 495 else if (RetVT == MVT::f64) 496 return UINTTOFP_I64_F64; 497 else if (RetVT == MVT::f80) 498 return UINTTOFP_I64_F80; 499 else if (RetVT == MVT::ppcf128) 500 return UINTTOFP_I64_PPCF128; 501 } else if (OpVT == MVT::i128) { 502 if (RetVT == MVT::f32) 503 return UINTTOFP_I128_F32; 504 else if (RetVT == MVT::f64) 505 return UINTTOFP_I128_F64; 506 else if (RetVT == MVT::f80) 507 return UINTTOFP_I128_F80; 508 else if (RetVT == MVT::ppcf128) 509 return UINTTOFP_I128_PPCF128; 510 } 511 return UNKNOWN_LIBCALL; 512} 513 514/// InitCmpLibcallCCs - Set default comparison libcall CC. 515/// 516static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 517 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 518 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 519 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 520 CCs[RTLIB::UNE_F32] = ISD::SETNE; 521 CCs[RTLIB::UNE_F64] = ISD::SETNE; 522 CCs[RTLIB::OGE_F32] = ISD::SETGE; 523 CCs[RTLIB::OGE_F64] = ISD::SETGE; 524 CCs[RTLIB::OLT_F32] = ISD::SETLT; 525 CCs[RTLIB::OLT_F64] = ISD::SETLT; 526 CCs[RTLIB::OLE_F32] = ISD::SETLE; 527 CCs[RTLIB::OLE_F64] = ISD::SETLE; 528 CCs[RTLIB::OGT_F32] = ISD::SETGT; 529 CCs[RTLIB::OGT_F64] = ISD::SETGT; 530 CCs[RTLIB::UO_F32] = ISD::SETNE; 531 CCs[RTLIB::UO_F64] = ISD::SETNE; 532 CCs[RTLIB::O_F32] = ISD::SETEQ; 533 CCs[RTLIB::O_F64] = ISD::SETEQ; 534} 535 536/// NOTE: The constructor takes ownership of TLOF. 537TargetLowering::TargetLowering(const TargetMachine &tm, 538 const TargetLoweringObjectFile *tlof) 539 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 540 mayPromoteElements(AllowPromoteIntElem) { 541 // All operations default to being supported. 542 memset(OpActions, 0, sizeof(OpActions)); 543 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 544 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 545 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 546 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 547 548 // Set default actions for various operations. 549 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 550 // Default all indexed load / store to expand. 551 for (unsigned IM = (unsigned)ISD::PRE_INC; 552 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 553 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 554 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 555 } 556 557 // These operations default to expand. 558 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 560 } 561 562 // Most targets ignore the @llvm.prefetch intrinsic. 563 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 564 565 // ConstantFP nodes default to expand. Targets can either change this to 566 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 567 // to optimize expansions for certain constants. 568 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 569 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 570 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 571 572 // These library functions default to expand. 573 setOperationAction(ISD::FLOG , MVT::f64, Expand); 574 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 575 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 576 setOperationAction(ISD::FEXP , MVT::f64, Expand); 577 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 578 setOperationAction(ISD::FLOG , MVT::f32, Expand); 579 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 580 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 581 setOperationAction(ISD::FEXP , MVT::f32, Expand); 582 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 583 584 // Default ISD::TRAP to expand (which turns it into abort). 585 setOperationAction(ISD::TRAP, MVT::Other, Expand); 586 587 IsLittleEndian = TD->isLittleEndian(); 588 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 589 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 590 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 591 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 592 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 593 = maxStoresPerMemmoveOptSize = 4; 594 benefitFromCodePlacementOpt = false; 595 UseUnderscoreSetJmp = false; 596 UseUnderscoreLongJmp = false; 597 SelectIsExpensive = false; 598 IntDivIsCheap = false; 599 Pow2DivIsCheap = false; 600 JumpIsExpensive = false; 601 StackPointerRegisterToSaveRestore = 0; 602 ExceptionPointerRegister = 0; 603 ExceptionSelectorRegister = 0; 604 BooleanContents = UndefinedBooleanContent; 605 SchedPreferenceInfo = Sched::Latency; 606 JumpBufSize = 0; 607 JumpBufAlignment = 0; 608 MinFunctionAlignment = 0; 609 PrefFunctionAlignment = 0; 610 PrefLoopAlignment = 0; 611 MinStackArgumentAlignment = 1; 612 ShouldFoldAtomicFences = false; 613 614 InitLibcallNames(LibcallRoutineNames); 615 InitCmpLibcallCCs(CmpLibcallCCs); 616 InitLibcallCallingConvs(LibcallCallingConvs); 617} 618 619TargetLowering::~TargetLowering() { 620 delete &TLOF; 621} 622 623MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 624 return MVT::getIntegerVT(8*TD->getPointerSize()); 625} 626 627/// canOpTrap - Returns true if the operation can trap for the value type. 628/// VT must be a legal type. 629bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 630 assert(isTypeLegal(VT)); 631 switch (Op) { 632 default: 633 return false; 634 case ISD::FDIV: 635 case ISD::FREM: 636 case ISD::SDIV: 637 case ISD::UDIV: 638 case ISD::SREM: 639 case ISD::UREM: 640 return true; 641 } 642} 643 644 645static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 646 unsigned &NumIntermediates, 647 EVT &RegisterVT, 648 TargetLowering *TLI) { 649 // Figure out the right, legal destination reg to copy into. 650 unsigned NumElts = VT.getVectorNumElements(); 651 MVT EltTy = VT.getVectorElementType(); 652 653 unsigned NumVectorRegs = 1; 654 655 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 656 // could break down into LHS/RHS like LegalizeDAG does. 657 if (!isPowerOf2_32(NumElts)) { 658 NumVectorRegs = NumElts; 659 NumElts = 1; 660 } 661 662 // Divide the input until we get to a supported size. This will always 663 // end with a scalar if the target doesn't support vectors. 664 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 665 NumElts >>= 1; 666 NumVectorRegs <<= 1; 667 } 668 669 NumIntermediates = NumVectorRegs; 670 671 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 672 if (!TLI->isTypeLegal(NewVT)) 673 NewVT = EltTy; 674 IntermediateVT = NewVT; 675 676 EVT DestVT = TLI->getRegisterType(NewVT); 677 RegisterVT = DestVT; 678 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 679 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 680 681 // Otherwise, promotion or legal types use the same number of registers as 682 // the vector decimated to the appropriate level. 683 return NumVectorRegs; 684} 685 686/// isLegalRC - Return true if the value types that can be represented by the 687/// specified register class are all legal. 688bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 689 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 690 I != E; ++I) { 691 if (isTypeLegal(*I)) 692 return true; 693 } 694 return false; 695} 696 697/// hasLegalSuperRegRegClasses - Return true if the specified register class 698/// has one or more super-reg register classes that are legal. 699bool 700TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 701 if (*RC->superregclasses_begin() == 0) 702 return false; 703 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 704 E = RC->superregclasses_end(); I != E; ++I) { 705 const TargetRegisterClass *RRC = *I; 706 if (isLegalRC(RRC)) 707 return true; 708 } 709 return false; 710} 711 712/// findRepresentativeClass - Return the largest legal super-reg register class 713/// of the register class for the specified type and its associated "cost". 714std::pair<const TargetRegisterClass*, uint8_t> 715TargetLowering::findRepresentativeClass(EVT VT) const { 716 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 717 if (!RC) 718 return std::make_pair(RC, 0); 719 const TargetRegisterClass *BestRC = RC; 720 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 721 E = RC->superregclasses_end(); I != E; ++I) { 722 const TargetRegisterClass *RRC = *I; 723 if (RRC->isASubClass() || !isLegalRC(RRC)) 724 continue; 725 if (!hasLegalSuperRegRegClasses(RRC)) 726 return std::make_pair(RRC, 1); 727 BestRC = RRC; 728 } 729 return std::make_pair(BestRC, 1); 730} 731 732 733/// computeRegisterProperties - Once all of the register classes are added, 734/// this allows us to compute derived properties we expose. 735void TargetLowering::computeRegisterProperties() { 736 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 737 "Too many value types for ValueTypeActions to hold!"); 738 739 // Everything defaults to needing one register. 740 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 741 NumRegistersForVT[i] = 1; 742 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 743 } 744 // ...except isVoid, which doesn't need any registers. 745 NumRegistersForVT[MVT::isVoid] = 0; 746 747 // Find the largest integer register class. 748 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 749 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 750 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 751 752 // Every integer value type larger than this largest register takes twice as 753 // many registers to represent as the previous ValueType. 754 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 755 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 756 if (!ExpandedVT.isInteger()) 757 break; 758 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 759 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 760 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 761 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 762 } 763 764 // Inspect all of the ValueType's smaller than the largest integer 765 // register to see which ones need promotion. 766 unsigned LegalIntReg = LargestIntReg; 767 for (unsigned IntReg = LargestIntReg - 1; 768 IntReg >= (unsigned)MVT::i1; --IntReg) { 769 EVT IVT = (MVT::SimpleValueType)IntReg; 770 if (isTypeLegal(IVT)) { 771 LegalIntReg = IntReg; 772 } else { 773 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 774 (MVT::SimpleValueType)LegalIntReg; 775 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 776 } 777 } 778 779 // ppcf128 type is really two f64's. 780 if (!isTypeLegal(MVT::ppcf128)) { 781 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 782 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 783 TransformToType[MVT::ppcf128] = MVT::f64; 784 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 785 } 786 787 // Decide how to handle f64. If the target does not have native f64 support, 788 // expand it to i64 and we will be generating soft float library calls. 789 if (!isTypeLegal(MVT::f64)) { 790 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 791 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 792 TransformToType[MVT::f64] = MVT::i64; 793 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 794 } 795 796 // Decide how to handle f32. If the target does not have native support for 797 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 798 if (!isTypeLegal(MVT::f32)) { 799 if (isTypeLegal(MVT::f64)) { 800 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 801 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 802 TransformToType[MVT::f32] = MVT::f64; 803 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 804 } else { 805 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 806 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 807 TransformToType[MVT::f32] = MVT::i32; 808 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 809 } 810 } 811 812 // Loop over all of the vector value types to see which need transformations. 813 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 814 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 815 MVT VT = (MVT::SimpleValueType)i; 816 if (isTypeLegal(VT)) continue; 817 818 // Determine if there is a legal wider type. If so, we should promote to 819 // that wider vector type. 820 EVT EltVT = VT.getVectorElementType(); 821 unsigned NElts = VT.getVectorNumElements(); 822 if (NElts != 1) { 823 bool IsLegalWiderType = false; 824 // If we allow the promotion of vector elements using a flag, 825 // then return TypePromoteInteger on vector elements. 826 // First try to promote the elements of integer vectors. If no legal 827 // promotion was found, fallback to the widen-vector method. 828 if (mayPromoteElements) 829 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 830 EVT SVT = (MVT::SimpleValueType)nVT; 831 // Promote vectors of integers to vectors with the same number 832 // of elements, with a wider element type. 833 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 834 && SVT.getVectorNumElements() == NElts && 835 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 836 TransformToType[i] = SVT; 837 RegisterTypeForVT[i] = SVT; 838 NumRegistersForVT[i] = 1; 839 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 840 IsLegalWiderType = true; 841 break; 842 } 843 } 844 845 if (IsLegalWiderType) continue; 846 847 // Try to widen the vector. 848 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 849 EVT SVT = (MVT::SimpleValueType)nVT; 850 if (SVT.getVectorElementType() == EltVT && 851 SVT.getVectorNumElements() > NElts && 852 isTypeLegal(SVT)) { 853 TransformToType[i] = SVT; 854 RegisterTypeForVT[i] = SVT; 855 NumRegistersForVT[i] = 1; 856 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 857 IsLegalWiderType = true; 858 break; 859 } 860 } 861 if (IsLegalWiderType) continue; 862 } 863 864 MVT IntermediateVT; 865 EVT RegisterVT; 866 unsigned NumIntermediates; 867 NumRegistersForVT[i] = 868 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 869 RegisterVT, this); 870 RegisterTypeForVT[i] = RegisterVT; 871 872 EVT NVT = VT.getPow2VectorType(); 873 if (NVT == VT) { 874 // Type is already a power of 2. The default action is to split. 875 TransformToType[i] = MVT::Other; 876 unsigned NumElts = VT.getVectorNumElements(); 877 ValueTypeActions.setTypeAction(VT, 878 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 879 } else { 880 TransformToType[i] = NVT; 881 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 882 } 883 } 884 885 // Determine the 'representative' register class for each value type. 886 // An representative register class is the largest (meaning one which is 887 // not a sub-register class / subreg register class) legal register class for 888 // a group of value types. For example, on i386, i8, i16, and i32 889 // representative would be GR32; while on x86_64 it's GR64. 890 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 891 const TargetRegisterClass* RRC; 892 uint8_t Cost; 893 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 894 RepRegClassForVT[i] = RRC; 895 RepRegClassCostForVT[i] = Cost; 896 } 897} 898 899const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 900 return NULL; 901} 902 903 904MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 905 return PointerTy.SimpleTy; 906} 907 908MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 909 return MVT::i32; // return the default value 910} 911 912/// getVectorTypeBreakdown - Vector types are broken down into some number of 913/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 914/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 915/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 916/// 917/// This method returns the number of registers needed, and the VT for each 918/// register. It also returns the VT and quantity of the intermediate values 919/// before they are promoted/expanded. 920/// 921unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 922 EVT &IntermediateVT, 923 unsigned &NumIntermediates, 924 EVT &RegisterVT) const { 925 unsigned NumElts = VT.getVectorNumElements(); 926 927 // If there is a wider vector type with the same element type as this one, 928 // we should widen to that legal vector type. This handles things like 929 // <2 x float> -> <4 x float>. 930 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 931 RegisterVT = getTypeToTransformTo(Context, VT); 932 if (isTypeLegal(RegisterVT)) { 933 IntermediateVT = RegisterVT; 934 NumIntermediates = 1; 935 return 1; 936 } 937 } 938 939 // Figure out the right, legal destination reg to copy into. 940 EVT EltTy = VT.getVectorElementType(); 941 942 unsigned NumVectorRegs = 1; 943 944 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 945 // could break down into LHS/RHS like LegalizeDAG does. 946 if (!isPowerOf2_32(NumElts)) { 947 NumVectorRegs = NumElts; 948 NumElts = 1; 949 } 950 951 // Divide the input until we get to a supported size. This will always 952 // end with a scalar if the target doesn't support vectors. 953 while (NumElts > 1 && !isTypeLegal( 954 EVT::getVectorVT(Context, EltTy, NumElts))) { 955 NumElts >>= 1; 956 NumVectorRegs <<= 1; 957 } 958 959 NumIntermediates = NumVectorRegs; 960 961 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 962 if (!isTypeLegal(NewVT)) 963 NewVT = EltTy; 964 IntermediateVT = NewVT; 965 966 EVT DestVT = getRegisterType(Context, NewVT); 967 RegisterVT = DestVT; 968 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 969 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 970 971 // Otherwise, promotion or legal types use the same number of registers as 972 // the vector decimated to the appropriate level. 973 return NumVectorRegs; 974} 975 976/// Get the EVTs and ArgFlags collections that represent the legalized return 977/// type of the given function. This does not require a DAG or a return value, 978/// and is suitable for use before any DAGs for the function are constructed. 979/// TODO: Move this out of TargetLowering.cpp. 980void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 981 SmallVectorImpl<ISD::OutputArg> &Outs, 982 const TargetLowering &TLI, 983 SmallVectorImpl<uint64_t> *Offsets) { 984 SmallVector<EVT, 4> ValueVTs; 985 ComputeValueVTs(TLI, ReturnType, ValueVTs); 986 unsigned NumValues = ValueVTs.size(); 987 if (NumValues == 0) return; 988 unsigned Offset = 0; 989 990 for (unsigned j = 0, f = NumValues; j != f; ++j) { 991 EVT VT = ValueVTs[j]; 992 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 993 994 if (attr & Attribute::SExt) 995 ExtendKind = ISD::SIGN_EXTEND; 996 else if (attr & Attribute::ZExt) 997 ExtendKind = ISD::ZERO_EXTEND; 998 999 // FIXME: C calling convention requires the return type to be promoted to 1000 // at least 32-bit. But this is not necessary for non-C calling 1001 // conventions. The frontend should mark functions whose return values 1002 // require promoting with signext or zeroext attributes. 1003 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1004 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1005 if (VT.bitsLT(MinVT)) 1006 VT = MinVT; 1007 } 1008 1009 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1010 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1011 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 1012 PartVT.getTypeForEVT(ReturnType->getContext())); 1013 1014 // 'inreg' on function refers to return value 1015 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1016 if (attr & Attribute::InReg) 1017 Flags.setInReg(); 1018 1019 // Propagate extension type if any 1020 if (attr & Attribute::SExt) 1021 Flags.setSExt(); 1022 else if (attr & Attribute::ZExt) 1023 Flags.setZExt(); 1024 1025 for (unsigned i = 0; i < NumParts; ++i) { 1026 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1027 if (Offsets) { 1028 Offsets->push_back(Offset); 1029 Offset += PartSize; 1030 } 1031 } 1032 } 1033} 1034 1035/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1036/// function arguments in the caller parameter area. This is the actual 1037/// alignment, not its logarithm. 1038unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1039 return TD->getCallFrameTypeAlignment(Ty); 1040} 1041 1042/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1043/// current function. The returned value is a member of the 1044/// MachineJumpTableInfo::JTEntryKind enum. 1045unsigned TargetLowering::getJumpTableEncoding() const { 1046 // In non-pic modes, just use the address of a block. 1047 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1048 return MachineJumpTableInfo::EK_BlockAddress; 1049 1050 // In PIC mode, if the target supports a GPRel32 directive, use it. 1051 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1052 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1053 1054 // Otherwise, use a label difference. 1055 return MachineJumpTableInfo::EK_LabelDifference32; 1056} 1057 1058SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1059 SelectionDAG &DAG) const { 1060 // If our PIC model is GP relative, use the global offset table as the base. 1061 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1062 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1063 return Table; 1064} 1065 1066/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1067/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1068/// MCExpr. 1069const MCExpr * 1070TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1071 unsigned JTI,MCContext &Ctx) const{ 1072 // The normal PIC reloc base is the label at the start of the jump table. 1073 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1074} 1075 1076bool 1077TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1078 // Assume that everything is safe in static mode. 1079 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1080 return true; 1081 1082 // In dynamic-no-pic mode, assume that known defined values are safe. 1083 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1084 GA && 1085 !GA->getGlobal()->isDeclaration() && 1086 !GA->getGlobal()->isWeakForLinker()) 1087 return true; 1088 1089 // Otherwise assume nothing is safe. 1090 return false; 1091} 1092 1093//===----------------------------------------------------------------------===// 1094// Optimization Methods 1095//===----------------------------------------------------------------------===// 1096 1097/// ShrinkDemandedConstant - Check to see if the specified operand of the 1098/// specified instruction is a constant integer. If so, check to see if there 1099/// are any bits set in the constant that are not demanded. If so, shrink the 1100/// constant and return true. 1101bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1102 const APInt &Demanded) { 1103 DebugLoc dl = Op.getDebugLoc(); 1104 1105 // FIXME: ISD::SELECT, ISD::SELECT_CC 1106 switch (Op.getOpcode()) { 1107 default: break; 1108 case ISD::XOR: 1109 case ISD::AND: 1110 case ISD::OR: { 1111 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1112 if (!C) return false; 1113 1114 if (Op.getOpcode() == ISD::XOR && 1115 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1116 return false; 1117 1118 // if we can expand it to have all bits set, do it 1119 if (C->getAPIntValue().intersects(~Demanded)) { 1120 EVT VT = Op.getValueType(); 1121 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1122 DAG.getConstant(Demanded & 1123 C->getAPIntValue(), 1124 VT)); 1125 return CombineTo(Op, New); 1126 } 1127 1128 break; 1129 } 1130 } 1131 1132 return false; 1133} 1134 1135/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1136/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1137/// cast, but it could be generalized for targets with other types of 1138/// implicit widening casts. 1139bool 1140TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1141 unsigned BitWidth, 1142 const APInt &Demanded, 1143 DebugLoc dl) { 1144 assert(Op.getNumOperands() == 2 && 1145 "ShrinkDemandedOp only supports binary operators!"); 1146 assert(Op.getNode()->getNumValues() == 1 && 1147 "ShrinkDemandedOp only supports nodes with one result!"); 1148 1149 // Don't do this if the node has another user, which may require the 1150 // full value. 1151 if (!Op.getNode()->hasOneUse()) 1152 return false; 1153 1154 // Search for the smallest integer type with free casts to and from 1155 // Op's type. For expedience, just check power-of-2 integer types. 1156 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1157 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1158 if (!isPowerOf2_32(SmallVTBits)) 1159 SmallVTBits = NextPowerOf2(SmallVTBits); 1160 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1161 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1162 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1163 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1164 // We found a type with free casts. 1165 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1166 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1167 Op.getNode()->getOperand(0)), 1168 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1169 Op.getNode()->getOperand(1))); 1170 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1171 return CombineTo(Op, Z); 1172 } 1173 } 1174 return false; 1175} 1176 1177/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1178/// DemandedMask bits of the result of Op are ever used downstream. If we can 1179/// use this information to simplify Op, create a new simplified DAG node and 1180/// return true, returning the original and new nodes in Old and New. Otherwise, 1181/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1182/// the expression (used to simplify the caller). The KnownZero/One bits may 1183/// only be accurate for those bits in the DemandedMask. 1184bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1185 const APInt &DemandedMask, 1186 APInt &KnownZero, 1187 APInt &KnownOne, 1188 TargetLoweringOpt &TLO, 1189 unsigned Depth) const { 1190 unsigned BitWidth = DemandedMask.getBitWidth(); 1191 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1192 "Mask size mismatches value type size!"); 1193 APInt NewMask = DemandedMask; 1194 DebugLoc dl = Op.getDebugLoc(); 1195 1196 // Don't know anything. 1197 KnownZero = KnownOne = APInt(BitWidth, 0); 1198 1199 // Other users may use these bits. 1200 if (!Op.getNode()->hasOneUse()) { 1201 if (Depth != 0) { 1202 // If not at the root, Just compute the KnownZero/KnownOne bits to 1203 // simplify things downstream. 1204 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1205 return false; 1206 } 1207 // If this is the root being simplified, allow it to have multiple uses, 1208 // just set the NewMask to all bits. 1209 NewMask = APInt::getAllOnesValue(BitWidth); 1210 } else if (DemandedMask == 0) { 1211 // Not demanding any bits from Op. 1212 if (Op.getOpcode() != ISD::UNDEF) 1213 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1214 return false; 1215 } else if (Depth == 6) { // Limit search depth. 1216 return false; 1217 } 1218 1219 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1220 switch (Op.getOpcode()) { 1221 case ISD::Constant: 1222 // We know all of the bits for a constant! 1223 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1224 KnownZero = ~KnownOne & NewMask; 1225 return false; // Don't fall through, will infinitely loop. 1226 case ISD::AND: 1227 // If the RHS is a constant, check to see if the LHS would be zero without 1228 // using the bits from the RHS. Below, we use knowledge about the RHS to 1229 // simplify the LHS, here we're using information from the LHS to simplify 1230 // the RHS. 1231 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1232 APInt LHSZero, LHSOne; 1233 // Do not increment Depth here; that can cause an infinite loop. 1234 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1235 LHSZero, LHSOne, Depth); 1236 // If the LHS already has zeros where RHSC does, this and is dead. 1237 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1238 return TLO.CombineTo(Op, Op.getOperand(0)); 1239 // If any of the set bits in the RHS are known zero on the LHS, shrink 1240 // the constant. 1241 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1242 return true; 1243 } 1244 1245 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1246 KnownOne, TLO, Depth+1)) 1247 return true; 1248 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1249 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1250 KnownZero2, KnownOne2, TLO, Depth+1)) 1251 return true; 1252 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1253 1254 // If all of the demanded bits are known one on one side, return the other. 1255 // These bits cannot contribute to the result of the 'and'. 1256 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1257 return TLO.CombineTo(Op, Op.getOperand(0)); 1258 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1259 return TLO.CombineTo(Op, Op.getOperand(1)); 1260 // If all of the demanded bits in the inputs are known zeros, return zero. 1261 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1262 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1263 // If the RHS is a constant, see if we can simplify it. 1264 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1265 return true; 1266 // If the operation can be done in a smaller type, do so. 1267 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1268 return true; 1269 1270 // Output known-1 bits are only known if set in both the LHS & RHS. 1271 KnownOne &= KnownOne2; 1272 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1273 KnownZero |= KnownZero2; 1274 break; 1275 case ISD::OR: 1276 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1277 KnownOne, TLO, Depth+1)) 1278 return true; 1279 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1280 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1281 KnownZero2, KnownOne2, TLO, Depth+1)) 1282 return true; 1283 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1284 1285 // If all of the demanded bits are known zero on one side, return the other. 1286 // These bits cannot contribute to the result of the 'or'. 1287 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1288 return TLO.CombineTo(Op, Op.getOperand(0)); 1289 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1290 return TLO.CombineTo(Op, Op.getOperand(1)); 1291 // If all of the potentially set bits on one side are known to be set on 1292 // the other side, just use the 'other' side. 1293 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1294 return TLO.CombineTo(Op, Op.getOperand(0)); 1295 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1296 return TLO.CombineTo(Op, Op.getOperand(1)); 1297 // If the RHS is a constant, see if we can simplify it. 1298 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1299 return true; 1300 // If the operation can be done in a smaller type, do so. 1301 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1302 return true; 1303 1304 // Output known-0 bits are only known if clear in both the LHS & RHS. 1305 KnownZero &= KnownZero2; 1306 // Output known-1 are known to be set if set in either the LHS | RHS. 1307 KnownOne |= KnownOne2; 1308 break; 1309 case ISD::XOR: 1310 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1311 KnownOne, TLO, Depth+1)) 1312 return true; 1313 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1314 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1315 KnownOne2, TLO, Depth+1)) 1316 return true; 1317 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1318 1319 // If all of the demanded bits are known zero on one side, return the other. 1320 // These bits cannot contribute to the result of the 'xor'. 1321 if ((KnownZero & NewMask) == NewMask) 1322 return TLO.CombineTo(Op, Op.getOperand(0)); 1323 if ((KnownZero2 & NewMask) == NewMask) 1324 return TLO.CombineTo(Op, Op.getOperand(1)); 1325 // If the operation can be done in a smaller type, do so. 1326 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1327 return true; 1328 1329 // If all of the unknown bits are known to be zero on one side or the other 1330 // (but not both) turn this into an *inclusive* or. 1331 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1332 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1333 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1334 Op.getOperand(0), 1335 Op.getOperand(1))); 1336 1337 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1338 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1339 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1340 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1341 1342 // If all of the demanded bits on one side are known, and all of the set 1343 // bits on that side are also known to be set on the other side, turn this 1344 // into an AND, as we know the bits will be cleared. 1345 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1346 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1347 if ((KnownOne & KnownOne2) == KnownOne) { 1348 EVT VT = Op.getValueType(); 1349 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1350 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1351 Op.getOperand(0), ANDC)); 1352 } 1353 } 1354 1355 // If the RHS is a constant, see if we can simplify it. 1356 // for XOR, we prefer to force bits to 1 if they will make a -1. 1357 // if we can't force bits, try to shrink constant 1358 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1359 APInt Expanded = C->getAPIntValue() | (~NewMask); 1360 // if we can expand it to have all bits set, do it 1361 if (Expanded.isAllOnesValue()) { 1362 if (Expanded != C->getAPIntValue()) { 1363 EVT VT = Op.getValueType(); 1364 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1365 TLO.DAG.getConstant(Expanded, VT)); 1366 return TLO.CombineTo(Op, New); 1367 } 1368 // if it already has all the bits set, nothing to change 1369 // but don't shrink either! 1370 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1371 return true; 1372 } 1373 } 1374 1375 KnownZero = KnownZeroOut; 1376 KnownOne = KnownOneOut; 1377 break; 1378 case ISD::SELECT: 1379 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1380 KnownOne, TLO, Depth+1)) 1381 return true; 1382 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1383 KnownOne2, TLO, Depth+1)) 1384 return true; 1385 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1386 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1387 1388 // If the operands are constants, see if we can simplify them. 1389 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1390 return true; 1391 1392 // Only known if known in both the LHS and RHS. 1393 KnownOne &= KnownOne2; 1394 KnownZero &= KnownZero2; 1395 break; 1396 case ISD::SELECT_CC: 1397 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1398 KnownOne, TLO, Depth+1)) 1399 return true; 1400 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1401 KnownOne2, TLO, Depth+1)) 1402 return true; 1403 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1404 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1405 1406 // If the operands are constants, see if we can simplify them. 1407 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1408 return true; 1409 1410 // Only known if known in both the LHS and RHS. 1411 KnownOne &= KnownOne2; 1412 KnownZero &= KnownZero2; 1413 break; 1414 case ISD::SHL: 1415 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1416 unsigned ShAmt = SA->getZExtValue(); 1417 SDValue InOp = Op.getOperand(0); 1418 1419 // If the shift count is an invalid immediate, don't do anything. 1420 if (ShAmt >= BitWidth) 1421 break; 1422 1423 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1424 // single shift. We can do this if the bottom bits (which are shifted 1425 // out) are never demanded. 1426 if (InOp.getOpcode() == ISD::SRL && 1427 isa<ConstantSDNode>(InOp.getOperand(1))) { 1428 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1429 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1430 unsigned Opc = ISD::SHL; 1431 int Diff = ShAmt-C1; 1432 if (Diff < 0) { 1433 Diff = -Diff; 1434 Opc = ISD::SRL; 1435 } 1436 1437 SDValue NewSA = 1438 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1439 EVT VT = Op.getValueType(); 1440 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1441 InOp.getOperand(0), NewSA)); 1442 } 1443 } 1444 1445 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1446 KnownZero, KnownOne, TLO, Depth+1)) 1447 return true; 1448 1449 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1450 // are not demanded. This will likely allow the anyext to be folded away. 1451 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1452 SDValue InnerOp = InOp.getNode()->getOperand(0); 1453 EVT InnerVT = InnerOp.getValueType(); 1454 if ((APInt::getHighBitsSet(BitWidth, 1455 BitWidth - InnerVT.getSizeInBits()) & 1456 DemandedMask) == 0 && 1457 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1458 EVT ShTy = getShiftAmountTy(InnerVT); 1459 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1460 ShTy = InnerVT; 1461 SDValue NarrowShl = 1462 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1463 TLO.DAG.getConstant(ShAmt, ShTy)); 1464 return 1465 TLO.CombineTo(Op, 1466 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1467 NarrowShl)); 1468 } 1469 } 1470 1471 KnownZero <<= SA->getZExtValue(); 1472 KnownOne <<= SA->getZExtValue(); 1473 // low bits known zero. 1474 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1475 } 1476 break; 1477 case ISD::SRL: 1478 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1479 EVT VT = Op.getValueType(); 1480 unsigned ShAmt = SA->getZExtValue(); 1481 unsigned VTSize = VT.getSizeInBits(); 1482 SDValue InOp = Op.getOperand(0); 1483 1484 // If the shift count is an invalid immediate, don't do anything. 1485 if (ShAmt >= BitWidth) 1486 break; 1487 1488 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1489 // single shift. We can do this if the top bits (which are shifted out) 1490 // are never demanded. 1491 if (InOp.getOpcode() == ISD::SHL && 1492 isa<ConstantSDNode>(InOp.getOperand(1))) { 1493 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1494 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1495 unsigned Opc = ISD::SRL; 1496 int Diff = ShAmt-C1; 1497 if (Diff < 0) { 1498 Diff = -Diff; 1499 Opc = ISD::SHL; 1500 } 1501 1502 SDValue NewSA = 1503 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1504 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1505 InOp.getOperand(0), NewSA)); 1506 } 1507 } 1508 1509 // Compute the new bits that are at the top now. 1510 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1511 KnownZero, KnownOne, TLO, Depth+1)) 1512 return true; 1513 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1514 KnownZero = KnownZero.lshr(ShAmt); 1515 KnownOne = KnownOne.lshr(ShAmt); 1516 1517 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1518 KnownZero |= HighBits; // High bits known zero. 1519 } 1520 break; 1521 case ISD::SRA: 1522 // If this is an arithmetic shift right and only the low-bit is set, we can 1523 // always convert this into a logical shr, even if the shift amount is 1524 // variable. The low bit of the shift cannot be an input sign bit unless 1525 // the shift amount is >= the size of the datatype, which is undefined. 1526 if (DemandedMask == 1) 1527 return TLO.CombineTo(Op, 1528 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1529 Op.getOperand(0), Op.getOperand(1))); 1530 1531 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1532 EVT VT = Op.getValueType(); 1533 unsigned ShAmt = SA->getZExtValue(); 1534 1535 // If the shift count is an invalid immediate, don't do anything. 1536 if (ShAmt >= BitWidth) 1537 break; 1538 1539 APInt InDemandedMask = (NewMask << ShAmt); 1540 1541 // If any of the demanded bits are produced by the sign extension, we also 1542 // demand the input sign bit. 1543 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1544 if (HighBits.intersects(NewMask)) 1545 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1546 1547 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1548 KnownZero, KnownOne, TLO, Depth+1)) 1549 return true; 1550 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1551 KnownZero = KnownZero.lshr(ShAmt); 1552 KnownOne = KnownOne.lshr(ShAmt); 1553 1554 // Handle the sign bit, adjusted to where it is now in the mask. 1555 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1556 1557 // If the input sign bit is known to be zero, or if none of the top bits 1558 // are demanded, turn this into an unsigned shift right. 1559 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1560 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1561 Op.getOperand(0), 1562 Op.getOperand(1))); 1563 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1564 KnownOne |= HighBits; 1565 } 1566 } 1567 break; 1568 case ISD::SIGN_EXTEND_INREG: { 1569 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1570 1571 // Sign extension. Compute the demanded bits in the result that are not 1572 // present in the input. 1573 APInt NewBits = 1574 APInt::getHighBitsSet(BitWidth, 1575 BitWidth - EVT.getScalarType().getSizeInBits()); 1576 1577 // If none of the extended bits are demanded, eliminate the sextinreg. 1578 if ((NewBits & NewMask) == 0) 1579 return TLO.CombineTo(Op, Op.getOperand(0)); 1580 1581 APInt InSignBit = 1582 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1583 APInt InputDemandedBits = 1584 APInt::getLowBitsSet(BitWidth, 1585 EVT.getScalarType().getSizeInBits()) & 1586 NewMask; 1587 1588 // Since the sign extended bits are demanded, we know that the sign 1589 // bit is demanded. 1590 InputDemandedBits |= InSignBit; 1591 1592 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1593 KnownZero, KnownOne, TLO, Depth+1)) 1594 return true; 1595 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1596 1597 // If the sign bit of the input is known set or clear, then we know the 1598 // top bits of the result. 1599 1600 // If the input sign bit is known zero, convert this into a zero extension. 1601 if (KnownZero.intersects(InSignBit)) 1602 return TLO.CombineTo(Op, 1603 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1604 1605 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1606 KnownOne |= NewBits; 1607 KnownZero &= ~NewBits; 1608 } else { // Input sign bit unknown 1609 KnownZero &= ~NewBits; 1610 KnownOne &= ~NewBits; 1611 } 1612 break; 1613 } 1614 case ISD::ZERO_EXTEND: { 1615 unsigned OperandBitWidth = 1616 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1617 APInt InMask = NewMask.trunc(OperandBitWidth); 1618 1619 // If none of the top bits are demanded, convert this into an any_extend. 1620 APInt NewBits = 1621 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1622 if (!NewBits.intersects(NewMask)) 1623 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1624 Op.getValueType(), 1625 Op.getOperand(0))); 1626 1627 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1628 KnownZero, KnownOne, TLO, Depth+1)) 1629 return true; 1630 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1631 KnownZero = KnownZero.zext(BitWidth); 1632 KnownOne = KnownOne.zext(BitWidth); 1633 KnownZero |= NewBits; 1634 break; 1635 } 1636 case ISD::SIGN_EXTEND: { 1637 EVT InVT = Op.getOperand(0).getValueType(); 1638 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1639 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1640 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1641 APInt NewBits = ~InMask & NewMask; 1642 1643 // If none of the top bits are demanded, convert this into an any_extend. 1644 if (NewBits == 0) 1645 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1646 Op.getValueType(), 1647 Op.getOperand(0))); 1648 1649 // Since some of the sign extended bits are demanded, we know that the sign 1650 // bit is demanded. 1651 APInt InDemandedBits = InMask & NewMask; 1652 InDemandedBits |= InSignBit; 1653 InDemandedBits = InDemandedBits.trunc(InBits); 1654 1655 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1656 KnownOne, TLO, Depth+1)) 1657 return true; 1658 KnownZero = KnownZero.zext(BitWidth); 1659 KnownOne = KnownOne.zext(BitWidth); 1660 1661 // If the sign bit is known zero, convert this to a zero extend. 1662 if (KnownZero.intersects(InSignBit)) 1663 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1664 Op.getValueType(), 1665 Op.getOperand(0))); 1666 1667 // If the sign bit is known one, the top bits match. 1668 if (KnownOne.intersects(InSignBit)) { 1669 KnownOne |= NewBits; 1670 KnownZero &= ~NewBits; 1671 } else { // Otherwise, top bits aren't known. 1672 KnownOne &= ~NewBits; 1673 KnownZero &= ~NewBits; 1674 } 1675 break; 1676 } 1677 case ISD::ANY_EXTEND: { 1678 unsigned OperandBitWidth = 1679 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1680 APInt InMask = NewMask.trunc(OperandBitWidth); 1681 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1682 KnownZero, KnownOne, TLO, Depth+1)) 1683 return true; 1684 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1685 KnownZero = KnownZero.zext(BitWidth); 1686 KnownOne = KnownOne.zext(BitWidth); 1687 break; 1688 } 1689 case ISD::TRUNCATE: { 1690 // Simplify the input, using demanded bit information, and compute the known 1691 // zero/one bits live out. 1692 unsigned OperandBitWidth = 1693 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1694 APInt TruncMask = NewMask.zext(OperandBitWidth); 1695 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1696 KnownZero, KnownOne, TLO, Depth+1)) 1697 return true; 1698 KnownZero = KnownZero.trunc(BitWidth); 1699 KnownOne = KnownOne.trunc(BitWidth); 1700 1701 // If the input is only used by this truncate, see if we can shrink it based 1702 // on the known demanded bits. 1703 if (Op.getOperand(0).getNode()->hasOneUse()) { 1704 SDValue In = Op.getOperand(0); 1705 switch (In.getOpcode()) { 1706 default: break; 1707 case ISD::SRL: 1708 // Shrink SRL by a constant if none of the high bits shifted in are 1709 // demanded. 1710 if (TLO.LegalTypes() && 1711 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1712 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1713 // undesirable. 1714 break; 1715 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1716 if (!ShAmt) 1717 break; 1718 SDValue Shift = In.getOperand(1); 1719 if (TLO.LegalTypes()) { 1720 uint64_t ShVal = ShAmt->getZExtValue(); 1721 Shift = 1722 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1723 } 1724 1725 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1726 OperandBitWidth - BitWidth); 1727 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1728 1729 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1730 // None of the shifted in bits are needed. Add a truncate of the 1731 // shift input, then shift it. 1732 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1733 Op.getValueType(), 1734 In.getOperand(0)); 1735 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1736 Op.getValueType(), 1737 NewTrunc, 1738 Shift)); 1739 } 1740 break; 1741 } 1742 } 1743 1744 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1745 break; 1746 } 1747 case ISD::AssertZext: { 1748 // Demand all the bits of the input that are demanded in the output. 1749 // The low bits are obvious; the high bits are demanded because we're 1750 // asserting that they're zero here. 1751 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1752 KnownZero, KnownOne, TLO, Depth+1)) 1753 return true; 1754 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1755 1756 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1757 APInt InMask = APInt::getLowBitsSet(BitWidth, 1758 VT.getSizeInBits()); 1759 KnownZero |= ~InMask & NewMask; 1760 break; 1761 } 1762 case ISD::BITCAST: 1763 // If this is an FP->Int bitcast and if the sign bit is the only 1764 // thing demanded, turn this into a FGETSIGN. 1765 if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1766 Op.getOperand(0).getValueType().isFloatingPoint() && 1767 !Op.getOperand(0).getValueType().isVector()) { 1768 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1769 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1770 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 1771 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1772 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1773 // place. We expect the SHL to be eliminated by other optimizations. 1774 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1775 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 1776 if (!OpVTLegal && OpVTSizeInBits > 32) 1777 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1778 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1779 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1780 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1781 Op.getValueType(), 1782 Sign, ShAmt)); 1783 } 1784 } 1785 break; 1786 case ISD::ADD: 1787 case ISD::MUL: 1788 case ISD::SUB: { 1789 // Add, Sub, and Mul don't demand any bits in positions beyond that 1790 // of the highest bit demanded of them. 1791 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1792 BitWidth - NewMask.countLeadingZeros()); 1793 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1794 KnownOne2, TLO, Depth+1)) 1795 return true; 1796 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1797 KnownOne2, TLO, Depth+1)) 1798 return true; 1799 // See if the operation should be performed at a smaller bit width. 1800 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1801 return true; 1802 } 1803 // FALL THROUGH 1804 default: 1805 // Just use ComputeMaskedBits to compute output bits. 1806 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1807 break; 1808 } 1809 1810 // If we know the value of all of the demanded bits, return this as a 1811 // constant. 1812 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1813 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1814 1815 return false; 1816} 1817 1818/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1819/// in Mask are known to be either zero or one and return them in the 1820/// KnownZero/KnownOne bitsets. 1821void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1822 const APInt &Mask, 1823 APInt &KnownZero, 1824 APInt &KnownOne, 1825 const SelectionDAG &DAG, 1826 unsigned Depth) const { 1827 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1828 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1829 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1830 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1831 "Should use MaskedValueIsZero if you don't know whether Op" 1832 " is a target node!"); 1833 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1834} 1835 1836/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1837/// targets that want to expose additional information about sign bits to the 1838/// DAG Combiner. 1839unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1840 unsigned Depth) const { 1841 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1842 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1843 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1844 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1845 "Should use ComputeNumSignBits if you don't know whether Op" 1846 " is a target node!"); 1847 return 1; 1848} 1849 1850/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1851/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1852/// determine which bit is set. 1853/// 1854static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1855 // A left-shift of a constant one will have exactly one bit set, because 1856 // shifting the bit off the end is undefined. 1857 if (Val.getOpcode() == ISD::SHL) 1858 if (ConstantSDNode *C = 1859 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1860 if (C->getAPIntValue() == 1) 1861 return true; 1862 1863 // Similarly, a right-shift of a constant sign-bit will have exactly 1864 // one bit set. 1865 if (Val.getOpcode() == ISD::SRL) 1866 if (ConstantSDNode *C = 1867 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1868 if (C->getAPIntValue().isSignBit()) 1869 return true; 1870 1871 // More could be done here, though the above checks are enough 1872 // to handle some common cases. 1873 1874 // Fall back to ComputeMaskedBits to catch other known cases. 1875 EVT OpVT = Val.getValueType(); 1876 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1877 APInt Mask = APInt::getAllOnesValue(BitWidth); 1878 APInt KnownZero, KnownOne; 1879 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1880 return (KnownZero.countPopulation() == BitWidth - 1) && 1881 (KnownOne.countPopulation() == 1); 1882} 1883 1884/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1885/// and cc. If it is unable to simplify it, return a null SDValue. 1886SDValue 1887TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1888 ISD::CondCode Cond, bool foldBooleans, 1889 DAGCombinerInfo &DCI, DebugLoc dl) const { 1890 SelectionDAG &DAG = DCI.DAG; 1891 1892 // These setcc operations always fold. 1893 switch (Cond) { 1894 default: break; 1895 case ISD::SETFALSE: 1896 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1897 case ISD::SETTRUE: 1898 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1899 } 1900 1901 // Ensure that the constant occurs on the RHS, and fold constant 1902 // comparisons. 1903 if (isa<ConstantSDNode>(N0.getNode())) 1904 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1905 1906 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1907 const APInt &C1 = N1C->getAPIntValue(); 1908 1909 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1910 // equality comparison, then we're just comparing whether X itself is 1911 // zero. 1912 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1913 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1914 N0.getOperand(1).getOpcode() == ISD::Constant) { 1915 const APInt &ShAmt 1916 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1917 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1918 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1919 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1920 // (srl (ctlz x), 5) == 0 -> X != 0 1921 // (srl (ctlz x), 5) != 1 -> X != 0 1922 Cond = ISD::SETNE; 1923 } else { 1924 // (srl (ctlz x), 5) != 0 -> X == 0 1925 // (srl (ctlz x), 5) == 1 -> X == 0 1926 Cond = ISD::SETEQ; 1927 } 1928 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1929 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1930 Zero, Cond); 1931 } 1932 } 1933 1934 SDValue CTPOP = N0; 1935 // Look through truncs that don't change the value of a ctpop. 1936 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1937 CTPOP = N0.getOperand(0); 1938 1939 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1940 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1941 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1942 EVT CTVT = CTPOP.getValueType(); 1943 SDValue CTOp = CTPOP.getOperand(0); 1944 1945 // (ctpop x) u< 2 -> (x & x-1) == 0 1946 // (ctpop x) u> 1 -> (x & x-1) != 0 1947 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1948 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1949 DAG.getConstant(1, CTVT)); 1950 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1951 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1952 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1953 } 1954 1955 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1956 } 1957 1958 // (zext x) == C --> x == (trunc C) 1959 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1960 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1961 unsigned MinBits = N0.getValueSizeInBits(); 1962 SDValue PreZExt; 1963 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1964 // ZExt 1965 MinBits = N0->getOperand(0).getValueSizeInBits(); 1966 PreZExt = N0->getOperand(0); 1967 } else if (N0->getOpcode() == ISD::AND) { 1968 // DAGCombine turns costly ZExts into ANDs 1969 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1970 if ((C->getAPIntValue()+1).isPowerOf2()) { 1971 MinBits = C->getAPIntValue().countTrailingOnes(); 1972 PreZExt = N0->getOperand(0); 1973 } 1974 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1975 // ZEXTLOAD 1976 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1977 MinBits = LN0->getMemoryVT().getSizeInBits(); 1978 PreZExt = N0; 1979 } 1980 } 1981 1982 // Make sure we're not loosing bits from the constant. 1983 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 1984 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1985 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1986 // Will get folded away. 1987 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1988 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1989 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1990 } 1991 } 1992 } 1993 1994 // If the LHS is '(and load, const)', the RHS is 0, 1995 // the test is for equality or unsigned, and all 1 bits of the const are 1996 // in the same partial word, see if we can shorten the load. 1997 if (DCI.isBeforeLegalize() && 1998 N0.getOpcode() == ISD::AND && C1 == 0 && 1999 N0.getNode()->hasOneUse() && 2000 isa<LoadSDNode>(N0.getOperand(0)) && 2001 N0.getOperand(0).getNode()->hasOneUse() && 2002 isa<ConstantSDNode>(N0.getOperand(1))) { 2003 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 2004 APInt bestMask; 2005 unsigned bestWidth = 0, bestOffset = 0; 2006 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2007 unsigned origWidth = N0.getValueType().getSizeInBits(); 2008 unsigned maskWidth = origWidth; 2009 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2010 // 8 bits, but have to be careful... 2011 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2012 origWidth = Lod->getMemoryVT().getSizeInBits(); 2013 const APInt &Mask = 2014 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2015 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2016 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2017 for (unsigned offset=0; offset<origWidth/width; offset++) { 2018 if ((newMask & Mask) == Mask) { 2019 if (!TD->isLittleEndian()) 2020 bestOffset = (origWidth/width - offset - 1) * (width/8); 2021 else 2022 bestOffset = (uint64_t)offset * (width/8); 2023 bestMask = Mask.lshr(offset * (width/8) * 8); 2024 bestWidth = width; 2025 break; 2026 } 2027 newMask = newMask << width; 2028 } 2029 } 2030 } 2031 if (bestWidth) { 2032 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2033 if (newVT.isRound()) { 2034 EVT PtrType = Lod->getOperand(1).getValueType(); 2035 SDValue Ptr = Lod->getBasePtr(); 2036 if (bestOffset != 0) 2037 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2038 DAG.getConstant(bestOffset, PtrType)); 2039 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2040 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2041 Lod->getPointerInfo().getWithOffset(bestOffset), 2042 false, false, NewAlign); 2043 return DAG.getSetCC(dl, VT, 2044 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2045 DAG.getConstant(bestMask.trunc(bestWidth), 2046 newVT)), 2047 DAG.getConstant(0LL, newVT), Cond); 2048 } 2049 } 2050 } 2051 2052 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2053 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2054 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2055 2056 // If the comparison constant has bits in the upper part, the 2057 // zero-extended value could never match. 2058 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2059 C1.getBitWidth() - InSize))) { 2060 switch (Cond) { 2061 case ISD::SETUGT: 2062 case ISD::SETUGE: 2063 case ISD::SETEQ: return DAG.getConstant(0, VT); 2064 case ISD::SETULT: 2065 case ISD::SETULE: 2066 case ISD::SETNE: return DAG.getConstant(1, VT); 2067 case ISD::SETGT: 2068 case ISD::SETGE: 2069 // True if the sign bit of C1 is set. 2070 return DAG.getConstant(C1.isNegative(), VT); 2071 case ISD::SETLT: 2072 case ISD::SETLE: 2073 // True if the sign bit of C1 isn't set. 2074 return DAG.getConstant(C1.isNonNegative(), VT); 2075 default: 2076 break; 2077 } 2078 } 2079 2080 // Otherwise, we can perform the comparison with the low bits. 2081 switch (Cond) { 2082 case ISD::SETEQ: 2083 case ISD::SETNE: 2084 case ISD::SETUGT: 2085 case ISD::SETUGE: 2086 case ISD::SETULT: 2087 case ISD::SETULE: { 2088 EVT newVT = N0.getOperand(0).getValueType(); 2089 if (DCI.isBeforeLegalizeOps() || 2090 (isOperationLegal(ISD::SETCC, newVT) && 2091 getCondCodeAction(Cond, newVT)==Legal)) 2092 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2093 DAG.getConstant(C1.trunc(InSize), newVT), 2094 Cond); 2095 break; 2096 } 2097 default: 2098 break; // todo, be more careful with signed comparisons 2099 } 2100 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2101 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2102 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2103 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2104 EVT ExtDstTy = N0.getValueType(); 2105 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2106 2107 // If the constant doesn't fit into the number of bits for the source of 2108 // the sign extension, it is impossible for both sides to be equal. 2109 if (C1.getMinSignedBits() > ExtSrcTyBits) 2110 return DAG.getConstant(Cond == ISD::SETNE, VT); 2111 2112 SDValue ZextOp; 2113 EVT Op0Ty = N0.getOperand(0).getValueType(); 2114 if (Op0Ty == ExtSrcTy) { 2115 ZextOp = N0.getOperand(0); 2116 } else { 2117 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2118 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2119 DAG.getConstant(Imm, Op0Ty)); 2120 } 2121 if (!DCI.isCalledByLegalizer()) 2122 DCI.AddToWorklist(ZextOp.getNode()); 2123 // Otherwise, make this a use of a zext. 2124 return DAG.getSetCC(dl, VT, ZextOp, 2125 DAG.getConstant(C1 & APInt::getLowBitsSet( 2126 ExtDstTyBits, 2127 ExtSrcTyBits), 2128 ExtDstTy), 2129 Cond); 2130 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2131 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2132 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2133 if (N0.getOpcode() == ISD::SETCC && 2134 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2135 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2136 if (TrueWhenTrue) 2137 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2138 // Invert the condition. 2139 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2140 CC = ISD::getSetCCInverse(CC, 2141 N0.getOperand(0).getValueType().isInteger()); 2142 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2143 } 2144 2145 if ((N0.getOpcode() == ISD::XOR || 2146 (N0.getOpcode() == ISD::AND && 2147 N0.getOperand(0).getOpcode() == ISD::XOR && 2148 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2149 isa<ConstantSDNode>(N0.getOperand(1)) && 2150 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2151 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2152 // can only do this if the top bits are known zero. 2153 unsigned BitWidth = N0.getValueSizeInBits(); 2154 if (DAG.MaskedValueIsZero(N0, 2155 APInt::getHighBitsSet(BitWidth, 2156 BitWidth-1))) { 2157 // Okay, get the un-inverted input value. 2158 SDValue Val; 2159 if (N0.getOpcode() == ISD::XOR) 2160 Val = N0.getOperand(0); 2161 else { 2162 assert(N0.getOpcode() == ISD::AND && 2163 N0.getOperand(0).getOpcode() == ISD::XOR); 2164 // ((X^1)&1)^1 -> X & 1 2165 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2166 N0.getOperand(0).getOperand(0), 2167 N0.getOperand(1)); 2168 } 2169 2170 return DAG.getSetCC(dl, VT, Val, N1, 2171 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2172 } 2173 } else if (N1C->getAPIntValue() == 1 && 2174 (VT == MVT::i1 || 2175 getBooleanContents() == ZeroOrOneBooleanContent)) { 2176 SDValue Op0 = N0; 2177 if (Op0.getOpcode() == ISD::TRUNCATE) 2178 Op0 = Op0.getOperand(0); 2179 2180 if ((Op0.getOpcode() == ISD::XOR) && 2181 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2182 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2183 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2184 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2185 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2186 Cond); 2187 } else if (Op0.getOpcode() == ISD::AND && 2188 isa<ConstantSDNode>(Op0.getOperand(1)) && 2189 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2190 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2191 if (Op0.getValueType().bitsGT(VT)) 2192 Op0 = DAG.getNode(ISD::AND, dl, VT, 2193 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2194 DAG.getConstant(1, VT)); 2195 else if (Op0.getValueType().bitsLT(VT)) 2196 Op0 = DAG.getNode(ISD::AND, dl, VT, 2197 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2198 DAG.getConstant(1, VT)); 2199 2200 return DAG.getSetCC(dl, VT, Op0, 2201 DAG.getConstant(0, Op0.getValueType()), 2202 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2203 } 2204 } 2205 } 2206 2207 APInt MinVal, MaxVal; 2208 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2209 if (ISD::isSignedIntSetCC(Cond)) { 2210 MinVal = APInt::getSignedMinValue(OperandBitSize); 2211 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2212 } else { 2213 MinVal = APInt::getMinValue(OperandBitSize); 2214 MaxVal = APInt::getMaxValue(OperandBitSize); 2215 } 2216 2217 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2218 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2219 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2220 // X >= C0 --> X > (C0-1) 2221 return DAG.getSetCC(dl, VT, N0, 2222 DAG.getConstant(C1-1, N1.getValueType()), 2223 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2224 } 2225 2226 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2227 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2228 // X <= C0 --> X < (C0+1) 2229 return DAG.getSetCC(dl, VT, N0, 2230 DAG.getConstant(C1+1, N1.getValueType()), 2231 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2232 } 2233 2234 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2235 return DAG.getConstant(0, VT); // X < MIN --> false 2236 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2237 return DAG.getConstant(1, VT); // X >= MIN --> true 2238 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2239 return DAG.getConstant(0, VT); // X > MAX --> false 2240 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2241 return DAG.getConstant(1, VT); // X <= MAX --> true 2242 2243 // Canonicalize setgt X, Min --> setne X, Min 2244 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2245 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2246 // Canonicalize setlt X, Max --> setne X, Max 2247 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2248 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2249 2250 // If we have setult X, 1, turn it into seteq X, 0 2251 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2252 return DAG.getSetCC(dl, VT, N0, 2253 DAG.getConstant(MinVal, N0.getValueType()), 2254 ISD::SETEQ); 2255 // If we have setugt X, Max-1, turn it into seteq X, Max 2256 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2257 return DAG.getSetCC(dl, VT, N0, 2258 DAG.getConstant(MaxVal, N0.getValueType()), 2259 ISD::SETEQ); 2260 2261 // If we have "setcc X, C0", check to see if we can shrink the immediate 2262 // by changing cc. 2263 2264 // SETUGT X, SINTMAX -> SETLT X, 0 2265 if (Cond == ISD::SETUGT && 2266 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2267 return DAG.getSetCC(dl, VT, N0, 2268 DAG.getConstant(0, N1.getValueType()), 2269 ISD::SETLT); 2270 2271 // SETULT X, SINTMIN -> SETGT X, -1 2272 if (Cond == ISD::SETULT && 2273 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2274 SDValue ConstMinusOne = 2275 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2276 N1.getValueType()); 2277 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2278 } 2279 2280 // Fold bit comparisons when we can. 2281 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2282 (VT == N0.getValueType() || 2283 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2284 N0.getOpcode() == ISD::AND) 2285 if (ConstantSDNode *AndRHS = 2286 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2287 EVT ShiftTy = DCI.isBeforeLegalize() ? 2288 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2289 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2290 // Perform the xform if the AND RHS is a single bit. 2291 if (AndRHS->getAPIntValue().isPowerOf2()) { 2292 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2293 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2294 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2295 } 2296 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2297 // (X & 8) == 8 --> (X & 8) >> 3 2298 // Perform the xform if C1 is a single bit. 2299 if (C1.isPowerOf2()) { 2300 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2301 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2302 DAG.getConstant(C1.logBase2(), ShiftTy))); 2303 } 2304 } 2305 } 2306 } 2307 2308 if (isa<ConstantFPSDNode>(N0.getNode())) { 2309 // Constant fold or commute setcc. 2310 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2311 if (O.getNode()) return O; 2312 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2313 // If the RHS of an FP comparison is a constant, simplify it away in 2314 // some cases. 2315 if (CFP->getValueAPF().isNaN()) { 2316 // If an operand is known to be a nan, we can fold it. 2317 switch (ISD::getUnorderedFlavor(Cond)) { 2318 default: llvm_unreachable("Unknown flavor!"); 2319 case 0: // Known false. 2320 return DAG.getConstant(0, VT); 2321 case 1: // Known true. 2322 return DAG.getConstant(1, VT); 2323 case 2: // Undefined. 2324 return DAG.getUNDEF(VT); 2325 } 2326 } 2327 2328 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2329 // constant if knowing that the operand is non-nan is enough. We prefer to 2330 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2331 // materialize 0.0. 2332 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2333 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2334 2335 // If the condition is not legal, see if we can find an equivalent one 2336 // which is legal. 2337 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2338 // If the comparison was an awkward floating-point == or != and one of 2339 // the comparison operands is infinity or negative infinity, convert the 2340 // condition to a less-awkward <= or >=. 2341 if (CFP->getValueAPF().isInfinity()) { 2342 if (CFP->getValueAPF().isNegative()) { 2343 if (Cond == ISD::SETOEQ && 2344 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2345 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2346 if (Cond == ISD::SETUEQ && 2347 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2348 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2349 if (Cond == ISD::SETUNE && 2350 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2351 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2352 if (Cond == ISD::SETONE && 2353 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2354 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2355 } else { 2356 if (Cond == ISD::SETOEQ && 2357 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2358 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2359 if (Cond == ISD::SETUEQ && 2360 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2361 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2362 if (Cond == ISD::SETUNE && 2363 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2364 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2365 if (Cond == ISD::SETONE && 2366 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2367 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2368 } 2369 } 2370 } 2371 } 2372 2373 if (N0 == N1) { 2374 // We can always fold X == X for integer setcc's. 2375 if (N0.getValueType().isInteger()) 2376 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2377 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2378 if (UOF == 2) // FP operators that are undefined on NaNs. 2379 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2380 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2381 return DAG.getConstant(UOF, VT); 2382 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2383 // if it is not already. 2384 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2385 if (NewCond != Cond) 2386 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2387 } 2388 2389 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2390 N0.getValueType().isInteger()) { 2391 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2392 N0.getOpcode() == ISD::XOR) { 2393 // Simplify (X+Y) == (X+Z) --> Y == Z 2394 if (N0.getOpcode() == N1.getOpcode()) { 2395 if (N0.getOperand(0) == N1.getOperand(0)) 2396 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2397 if (N0.getOperand(1) == N1.getOperand(1)) 2398 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2399 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2400 // If X op Y == Y op X, try other combinations. 2401 if (N0.getOperand(0) == N1.getOperand(1)) 2402 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2403 Cond); 2404 if (N0.getOperand(1) == N1.getOperand(0)) 2405 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2406 Cond); 2407 } 2408 } 2409 2410 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2411 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2412 // Turn (X+C1) == C2 --> X == C2-C1 2413 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2414 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2415 DAG.getConstant(RHSC->getAPIntValue()- 2416 LHSR->getAPIntValue(), 2417 N0.getValueType()), Cond); 2418 } 2419 2420 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2421 if (N0.getOpcode() == ISD::XOR) 2422 // If we know that all of the inverted bits are zero, don't bother 2423 // performing the inversion. 2424 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2425 return 2426 DAG.getSetCC(dl, VT, N0.getOperand(0), 2427 DAG.getConstant(LHSR->getAPIntValue() ^ 2428 RHSC->getAPIntValue(), 2429 N0.getValueType()), 2430 Cond); 2431 } 2432 2433 // Turn (C1-X) == C2 --> X == C1-C2 2434 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2435 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2436 return 2437 DAG.getSetCC(dl, VT, N0.getOperand(1), 2438 DAG.getConstant(SUBC->getAPIntValue() - 2439 RHSC->getAPIntValue(), 2440 N0.getValueType()), 2441 Cond); 2442 } 2443 } 2444 } 2445 2446 // Simplify (X+Z) == X --> Z == 0 2447 if (N0.getOperand(0) == N1) 2448 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2449 DAG.getConstant(0, N0.getValueType()), Cond); 2450 if (N0.getOperand(1) == N1) { 2451 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2452 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2453 DAG.getConstant(0, N0.getValueType()), Cond); 2454 else if (N0.getNode()->hasOneUse()) { 2455 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2456 // (Z-X) == X --> Z == X<<1 2457 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2458 N1, 2459 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2460 if (!DCI.isCalledByLegalizer()) 2461 DCI.AddToWorklist(SH.getNode()); 2462 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2463 } 2464 } 2465 } 2466 2467 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2468 N1.getOpcode() == ISD::XOR) { 2469 // Simplify X == (X+Z) --> Z == 0 2470 if (N1.getOperand(0) == N0) { 2471 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2472 DAG.getConstant(0, N1.getValueType()), Cond); 2473 } else if (N1.getOperand(1) == N0) { 2474 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2475 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2476 DAG.getConstant(0, N1.getValueType()), Cond); 2477 } else if (N1.getNode()->hasOneUse()) { 2478 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2479 // X == (Z-X) --> X<<1 == Z 2480 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2481 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2482 if (!DCI.isCalledByLegalizer()) 2483 DCI.AddToWorklist(SH.getNode()); 2484 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2485 } 2486 } 2487 } 2488 2489 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2490 // Note that where y is variable and is known to have at most 2491 // one bit set (for example, if it is z&1) we cannot do this; 2492 // the expressions are not equivalent when y==0. 2493 if (N0.getOpcode() == ISD::AND) 2494 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2495 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2496 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2497 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2498 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2499 } 2500 } 2501 if (N1.getOpcode() == ISD::AND) 2502 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2503 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2504 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2505 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2506 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2507 } 2508 } 2509 } 2510 2511 // Fold away ALL boolean setcc's. 2512 SDValue Temp; 2513 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2514 switch (Cond) { 2515 default: llvm_unreachable("Unknown integer setcc!"); 2516 case ISD::SETEQ: // X == Y -> ~(X^Y) 2517 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2518 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2519 if (!DCI.isCalledByLegalizer()) 2520 DCI.AddToWorklist(Temp.getNode()); 2521 break; 2522 case ISD::SETNE: // X != Y --> (X^Y) 2523 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2524 break; 2525 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2526 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2527 Temp = DAG.getNOT(dl, N0, MVT::i1); 2528 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2529 if (!DCI.isCalledByLegalizer()) 2530 DCI.AddToWorklist(Temp.getNode()); 2531 break; 2532 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2533 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2534 Temp = DAG.getNOT(dl, N1, MVT::i1); 2535 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2536 if (!DCI.isCalledByLegalizer()) 2537 DCI.AddToWorklist(Temp.getNode()); 2538 break; 2539 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2540 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2541 Temp = DAG.getNOT(dl, N0, MVT::i1); 2542 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2543 if (!DCI.isCalledByLegalizer()) 2544 DCI.AddToWorklist(Temp.getNode()); 2545 break; 2546 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2547 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2548 Temp = DAG.getNOT(dl, N1, MVT::i1); 2549 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2550 break; 2551 } 2552 if (VT != MVT::i1) { 2553 if (!DCI.isCalledByLegalizer()) 2554 DCI.AddToWorklist(N0.getNode()); 2555 // FIXME: If running after legalize, we probably can't do this. 2556 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2557 } 2558 return N0; 2559 } 2560 2561 // Could not fold it. 2562 return SDValue(); 2563} 2564 2565/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2566/// node is a GlobalAddress + offset. 2567bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2568 int64_t &Offset) const { 2569 if (isa<GlobalAddressSDNode>(N)) { 2570 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2571 GA = GASD->getGlobal(); 2572 Offset += GASD->getOffset(); 2573 return true; 2574 } 2575 2576 if (N->getOpcode() == ISD::ADD) { 2577 SDValue N1 = N->getOperand(0); 2578 SDValue N2 = N->getOperand(1); 2579 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2580 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2581 if (V) { 2582 Offset += V->getSExtValue(); 2583 return true; 2584 } 2585 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2586 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2587 if (V) { 2588 Offset += V->getSExtValue(); 2589 return true; 2590 } 2591 } 2592 } 2593 2594 return false; 2595} 2596 2597 2598SDValue TargetLowering:: 2599PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2600 // Default implementation: no optimization. 2601 return SDValue(); 2602} 2603 2604//===----------------------------------------------------------------------===// 2605// Inline Assembler Implementation Methods 2606//===----------------------------------------------------------------------===// 2607 2608 2609TargetLowering::ConstraintType 2610TargetLowering::getConstraintType(const std::string &Constraint) const { 2611 // FIXME: lots more standard ones to handle. 2612 if (Constraint.size() == 1) { 2613 switch (Constraint[0]) { 2614 default: break; 2615 case 'r': return C_RegisterClass; 2616 case 'm': // memory 2617 case 'o': // offsetable 2618 case 'V': // not offsetable 2619 return C_Memory; 2620 case 'i': // Simple Integer or Relocatable Constant 2621 case 'n': // Simple Integer 2622 case 'E': // Floating Point Constant 2623 case 'F': // Floating Point Constant 2624 case 's': // Relocatable Constant 2625 case 'p': // Address. 2626 case 'X': // Allow ANY value. 2627 case 'I': // Target registers. 2628 case 'J': 2629 case 'K': 2630 case 'L': 2631 case 'M': 2632 case 'N': 2633 case 'O': 2634 case 'P': 2635 case '<': 2636 case '>': 2637 return C_Other; 2638 } 2639 } 2640 2641 if (Constraint.size() > 1 && Constraint[0] == '{' && 2642 Constraint[Constraint.size()-1] == '}') 2643 return C_Register; 2644 return C_Unknown; 2645} 2646 2647/// LowerXConstraint - try to replace an X constraint, which matches anything, 2648/// with another that has more specific requirements based on the type of the 2649/// corresponding operand. 2650const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2651 if (ConstraintVT.isInteger()) 2652 return "r"; 2653 if (ConstraintVT.isFloatingPoint()) 2654 return "f"; // works for many targets 2655 return 0; 2656} 2657 2658/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2659/// vector. If it is invalid, don't add anything to Ops. 2660void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2661 std::string &Constraint, 2662 std::vector<SDValue> &Ops, 2663 SelectionDAG &DAG) const { 2664 2665 if (Constraint.length() > 1) return; 2666 2667 char ConstraintLetter = Constraint[0]; 2668 switch (ConstraintLetter) { 2669 default: break; 2670 case 'X': // Allows any operand; labels (basic block) use this. 2671 if (Op.getOpcode() == ISD::BasicBlock) { 2672 Ops.push_back(Op); 2673 return; 2674 } 2675 // fall through 2676 case 'i': // Simple Integer or Relocatable Constant 2677 case 'n': // Simple Integer 2678 case 's': { // Relocatable Constant 2679 // These operands are interested in values of the form (GV+C), where C may 2680 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2681 // is possible and fine if either GV or C are missing. 2682 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2683 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2684 2685 // If we have "(add GV, C)", pull out GV/C 2686 if (Op.getOpcode() == ISD::ADD) { 2687 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2688 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2689 if (C == 0 || GA == 0) { 2690 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2691 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2692 } 2693 if (C == 0 || GA == 0) 2694 C = 0, GA = 0; 2695 } 2696 2697 // If we find a valid operand, map to the TargetXXX version so that the 2698 // value itself doesn't get selected. 2699 if (GA) { // Either &GV or &GV+C 2700 if (ConstraintLetter != 'n') { 2701 int64_t Offs = GA->getOffset(); 2702 if (C) Offs += C->getZExtValue(); 2703 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2704 C ? C->getDebugLoc() : DebugLoc(), 2705 Op.getValueType(), Offs)); 2706 return; 2707 } 2708 } 2709 if (C) { // just C, no GV. 2710 // Simple constants are not allowed for 's'. 2711 if (ConstraintLetter != 's') { 2712 // gcc prints these as sign extended. Sign extend value to 64 bits 2713 // now; without this it would get ZExt'd later in 2714 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2715 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2716 MVT::i64)); 2717 return; 2718 } 2719 } 2720 break; 2721 } 2722 } 2723} 2724 2725std::vector<unsigned> TargetLowering:: 2726getRegClassForInlineAsmConstraint(const std::string &Constraint, 2727 EVT VT) const { 2728 return std::vector<unsigned>(); 2729} 2730 2731 2732std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2733getRegForInlineAsmConstraint(const std::string &Constraint, 2734 EVT VT) const { 2735 if (Constraint[0] != '{') 2736 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2737 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2738 2739 // Remove the braces from around the name. 2740 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2741 2742 // Figure out which register class contains this reg. 2743 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2744 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2745 E = RI->regclass_end(); RCI != E; ++RCI) { 2746 const TargetRegisterClass *RC = *RCI; 2747 2748 // If none of the value types for this register class are valid, we 2749 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2750 bool isLegal = false; 2751 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2752 I != E; ++I) { 2753 if (isTypeLegal(*I)) { 2754 isLegal = true; 2755 break; 2756 } 2757 } 2758 2759 if (!isLegal) continue; 2760 2761 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2762 I != E; ++I) { 2763 if (RegName.equals_lower(RI->getName(*I))) 2764 return std::make_pair(*I, RC); 2765 } 2766 } 2767 2768 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2769} 2770 2771//===----------------------------------------------------------------------===// 2772// Constraint Selection. 2773 2774/// isMatchingInputConstraint - Return true of this is an input operand that is 2775/// a matching constraint like "4". 2776bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2777 assert(!ConstraintCode.empty() && "No known constraint!"); 2778 return isdigit(ConstraintCode[0]); 2779} 2780 2781/// getMatchedOperand - If this is an input matching constraint, this method 2782/// returns the output operand it matches. 2783unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2784 assert(!ConstraintCode.empty() && "No known constraint!"); 2785 return atoi(ConstraintCode.c_str()); 2786} 2787 2788 2789/// ParseConstraints - Split up the constraint string from the inline 2790/// assembly value into the specific constraints and their prefixes, 2791/// and also tie in the associated operand values. 2792/// If this returns an empty vector, and if the constraint string itself 2793/// isn't empty, there was an error parsing. 2794TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2795 ImmutableCallSite CS) const { 2796 /// ConstraintOperands - Information about all of the constraints. 2797 AsmOperandInfoVector ConstraintOperands; 2798 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2799 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2800 2801 // Do a prepass over the constraints, canonicalizing them, and building up the 2802 // ConstraintOperands list. 2803 InlineAsm::ConstraintInfoVector 2804 ConstraintInfos = IA->ParseConstraints(); 2805 2806 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2807 unsigned ResNo = 0; // ResNo - The result number of the next output. 2808 2809 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2810 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2811 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2812 2813 // Update multiple alternative constraint count. 2814 if (OpInfo.multipleAlternatives.size() > maCount) 2815 maCount = OpInfo.multipleAlternatives.size(); 2816 2817 OpInfo.ConstraintVT = MVT::Other; 2818 2819 // Compute the value type for each operand. 2820 switch (OpInfo.Type) { 2821 case InlineAsm::isOutput: 2822 // Indirect outputs just consume an argument. 2823 if (OpInfo.isIndirect) { 2824 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2825 break; 2826 } 2827 2828 // The return value of the call is this value. As such, there is no 2829 // corresponding argument. 2830 assert(!CS.getType()->isVoidTy() && 2831 "Bad inline asm!"); 2832 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2833 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2834 } else { 2835 assert(ResNo == 0 && "Asm only has one result!"); 2836 OpInfo.ConstraintVT = getValueType(CS.getType()); 2837 } 2838 ++ResNo; 2839 break; 2840 case InlineAsm::isInput: 2841 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2842 break; 2843 case InlineAsm::isClobber: 2844 // Nothing to do. 2845 break; 2846 } 2847 2848 if (OpInfo.CallOperandVal) { 2849 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2850 if (OpInfo.isIndirect) { 2851 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2852 if (!PtrTy) 2853 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2854 OpTy = PtrTy->getElementType(); 2855 } 2856 2857 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2858 if (const StructType *STy = dyn_cast<StructType>(OpTy)) 2859 if (STy->getNumElements() == 1) 2860 OpTy = STy->getElementType(0); 2861 2862 // If OpTy is not a single value, it may be a struct/union that we 2863 // can tile with integers. 2864 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2865 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2866 switch (BitSize) { 2867 default: break; 2868 case 1: 2869 case 8: 2870 case 16: 2871 case 32: 2872 case 64: 2873 case 128: 2874 OpInfo.ConstraintVT = 2875 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2876 break; 2877 } 2878 } else if (dyn_cast<PointerType>(OpTy)) { 2879 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2880 } else { 2881 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2882 } 2883 } 2884 } 2885 2886 // If we have multiple alternative constraints, select the best alternative. 2887 if (ConstraintInfos.size()) { 2888 if (maCount) { 2889 unsigned bestMAIndex = 0; 2890 int bestWeight = -1; 2891 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2892 int weight = -1; 2893 unsigned maIndex; 2894 // Compute the sums of the weights for each alternative, keeping track 2895 // of the best (highest weight) one so far. 2896 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2897 int weightSum = 0; 2898 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2899 cIndex != eIndex; ++cIndex) { 2900 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2901 if (OpInfo.Type == InlineAsm::isClobber) 2902 continue; 2903 2904 // If this is an output operand with a matching input operand, 2905 // look up the matching input. If their types mismatch, e.g. one 2906 // is an integer, the other is floating point, or their sizes are 2907 // different, flag it as an maCantMatch. 2908 if (OpInfo.hasMatchingInput()) { 2909 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2910 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2911 if ((OpInfo.ConstraintVT.isInteger() != 2912 Input.ConstraintVT.isInteger()) || 2913 (OpInfo.ConstraintVT.getSizeInBits() != 2914 Input.ConstraintVT.getSizeInBits())) { 2915 weightSum = -1; // Can't match. 2916 break; 2917 } 2918 } 2919 } 2920 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2921 if (weight == -1) { 2922 weightSum = -1; 2923 break; 2924 } 2925 weightSum += weight; 2926 } 2927 // Update best. 2928 if (weightSum > bestWeight) { 2929 bestWeight = weightSum; 2930 bestMAIndex = maIndex; 2931 } 2932 } 2933 2934 // Now select chosen alternative in each constraint. 2935 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2936 cIndex != eIndex; ++cIndex) { 2937 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2938 if (cInfo.Type == InlineAsm::isClobber) 2939 continue; 2940 cInfo.selectAlternative(bestMAIndex); 2941 } 2942 } 2943 } 2944 2945 // Check and hook up tied operands, choose constraint code to use. 2946 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2947 cIndex != eIndex; ++cIndex) { 2948 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2949 2950 // If this is an output operand with a matching input operand, look up the 2951 // matching input. If their types mismatch, e.g. one is an integer, the 2952 // other is floating point, or their sizes are different, flag it as an 2953 // error. 2954 if (OpInfo.hasMatchingInput()) { 2955 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2956 2957 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2958 if ((OpInfo.ConstraintVT.isInteger() != 2959 Input.ConstraintVT.isInteger()) || 2960 (OpInfo.ConstraintVT.getSizeInBits() != 2961 Input.ConstraintVT.getSizeInBits())) { 2962 report_fatal_error("Unsupported asm: input constraint" 2963 " with a matching output constraint of" 2964 " incompatible type!"); 2965 } 2966 } 2967 2968 } 2969 } 2970 2971 return ConstraintOperands; 2972} 2973 2974 2975/// getConstraintGenerality - Return an integer indicating how general CT 2976/// is. 2977static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2978 switch (CT) { 2979 default: llvm_unreachable("Unknown constraint type!"); 2980 case TargetLowering::C_Other: 2981 case TargetLowering::C_Unknown: 2982 return 0; 2983 case TargetLowering::C_Register: 2984 return 1; 2985 case TargetLowering::C_RegisterClass: 2986 return 2; 2987 case TargetLowering::C_Memory: 2988 return 3; 2989 } 2990} 2991 2992/// Examine constraint type and operand type and determine a weight value. 2993/// This object must already have been set up with the operand type 2994/// and the current alternative constraint selected. 2995TargetLowering::ConstraintWeight 2996 TargetLowering::getMultipleConstraintMatchWeight( 2997 AsmOperandInfo &info, int maIndex) const { 2998 InlineAsm::ConstraintCodeVector *rCodes; 2999 if (maIndex >= (int)info.multipleAlternatives.size()) 3000 rCodes = &info.Codes; 3001 else 3002 rCodes = &info.multipleAlternatives[maIndex].Codes; 3003 ConstraintWeight BestWeight = CW_Invalid; 3004 3005 // Loop over the options, keeping track of the most general one. 3006 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 3007 ConstraintWeight weight = 3008 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 3009 if (weight > BestWeight) 3010 BestWeight = weight; 3011 } 3012 3013 return BestWeight; 3014} 3015 3016/// Examine constraint type and operand type and determine a weight value. 3017/// This object must already have been set up with the operand type 3018/// and the current alternative constraint selected. 3019TargetLowering::ConstraintWeight 3020 TargetLowering::getSingleConstraintMatchWeight( 3021 AsmOperandInfo &info, const char *constraint) const { 3022 ConstraintWeight weight = CW_Invalid; 3023 Value *CallOperandVal = info.CallOperandVal; 3024 // If we don't have a value, we can't do a match, 3025 // but allow it at the lowest weight. 3026 if (CallOperandVal == NULL) 3027 return CW_Default; 3028 // Look at the constraint type. 3029 switch (*constraint) { 3030 case 'i': // immediate integer. 3031 case 'n': // immediate integer with a known value. 3032 if (isa<ConstantInt>(CallOperandVal)) 3033 weight = CW_Constant; 3034 break; 3035 case 's': // non-explicit intregal immediate. 3036 if (isa<GlobalValue>(CallOperandVal)) 3037 weight = CW_Constant; 3038 break; 3039 case 'E': // immediate float if host format. 3040 case 'F': // immediate float. 3041 if (isa<ConstantFP>(CallOperandVal)) 3042 weight = CW_Constant; 3043 break; 3044 case '<': // memory operand with autodecrement. 3045 case '>': // memory operand with autoincrement. 3046 case 'm': // memory operand. 3047 case 'o': // offsettable memory operand 3048 case 'V': // non-offsettable memory operand 3049 weight = CW_Memory; 3050 break; 3051 case 'r': // general register. 3052 case 'g': // general register, memory operand or immediate integer. 3053 // note: Clang converts "g" to "imr". 3054 if (CallOperandVal->getType()->isIntegerTy()) 3055 weight = CW_Register; 3056 break; 3057 case 'X': // any operand. 3058 default: 3059 weight = CW_Default; 3060 break; 3061 } 3062 return weight; 3063} 3064 3065/// ChooseConstraint - If there are multiple different constraints that we 3066/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3067/// This is somewhat tricky: constraints fall into four classes: 3068/// Other -> immediates and magic values 3069/// Register -> one specific register 3070/// RegisterClass -> a group of regs 3071/// Memory -> memory 3072/// Ideally, we would pick the most specific constraint possible: if we have 3073/// something that fits into a register, we would pick it. The problem here 3074/// is that if we have something that could either be in a register or in 3075/// memory that use of the register could cause selection of *other* 3076/// operands to fail: they might only succeed if we pick memory. Because of 3077/// this the heuristic we use is: 3078/// 3079/// 1) If there is an 'other' constraint, and if the operand is valid for 3080/// that constraint, use it. This makes us take advantage of 'i' 3081/// constraints when available. 3082/// 2) Otherwise, pick the most general constraint present. This prefers 3083/// 'm' over 'r', for example. 3084/// 3085static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3086 const TargetLowering &TLI, 3087 SDValue Op, SelectionDAG *DAG) { 3088 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3089 unsigned BestIdx = 0; 3090 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3091 int BestGenerality = -1; 3092 3093 // Loop over the options, keeping track of the most general one. 3094 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3095 TargetLowering::ConstraintType CType = 3096 TLI.getConstraintType(OpInfo.Codes[i]); 3097 3098 // If this is an 'other' constraint, see if the operand is valid for it. 3099 // For example, on X86 we might have an 'rI' constraint. If the operand 3100 // is an integer in the range [0..31] we want to use I (saving a load 3101 // of a register), otherwise we must use 'r'. 3102 if (CType == TargetLowering::C_Other && Op.getNode()) { 3103 assert(OpInfo.Codes[i].size() == 1 && 3104 "Unhandled multi-letter 'other' constraint"); 3105 std::vector<SDValue> ResultOps; 3106 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 3107 ResultOps, *DAG); 3108 if (!ResultOps.empty()) { 3109 BestType = CType; 3110 BestIdx = i; 3111 break; 3112 } 3113 } 3114 3115 // Things with matching constraints can only be registers, per gcc 3116 // documentation. This mainly affects "g" constraints. 3117 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3118 continue; 3119 3120 // This constraint letter is more general than the previous one, use it. 3121 int Generality = getConstraintGenerality(CType); 3122 if (Generality > BestGenerality) { 3123 BestType = CType; 3124 BestIdx = i; 3125 BestGenerality = Generality; 3126 } 3127 } 3128 3129 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3130 OpInfo.ConstraintType = BestType; 3131} 3132 3133/// ComputeConstraintToUse - Determines the constraint code and constraint 3134/// type to use for the specific AsmOperandInfo, setting 3135/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3136void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3137 SDValue Op, 3138 SelectionDAG *DAG) const { 3139 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3140 3141 // Single-letter constraints ('r') are very common. 3142 if (OpInfo.Codes.size() == 1) { 3143 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3144 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3145 } else { 3146 ChooseConstraint(OpInfo, *this, Op, DAG); 3147 } 3148 3149 // 'X' matches anything. 3150 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3151 // Labels and constants are handled elsewhere ('X' is the only thing 3152 // that matches labels). For Functions, the type here is the type of 3153 // the result, which is not what we want to look at; leave them alone. 3154 Value *v = OpInfo.CallOperandVal; 3155 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3156 OpInfo.CallOperandVal = v; 3157 return; 3158 } 3159 3160 // Otherwise, try to resolve it to something we know about by looking at 3161 // the actual operand type. 3162 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3163 OpInfo.ConstraintCode = Repl; 3164 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3165 } 3166 } 3167} 3168 3169//===----------------------------------------------------------------------===// 3170// Loop Strength Reduction hooks 3171//===----------------------------------------------------------------------===// 3172 3173/// isLegalAddressingMode - Return true if the addressing mode represented 3174/// by AM is legal for this target, for a load/store of the specified type. 3175bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3176 const Type *Ty) const { 3177 // The default implementation of this implements a conservative RISCy, r+r and 3178 // r+i addr mode. 3179 3180 // Allows a sign-extended 16-bit immediate field. 3181 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3182 return false; 3183 3184 // No global is ever allowed as a base. 3185 if (AM.BaseGV) 3186 return false; 3187 3188 // Only support r+r, 3189 switch (AM.Scale) { 3190 case 0: // "r+i" or just "i", depending on HasBaseReg. 3191 break; 3192 case 1: 3193 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3194 return false; 3195 // Otherwise we have r+r or r+i. 3196 break; 3197 case 2: 3198 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3199 return false; 3200 // Allow 2*r as r+r. 3201 break; 3202 } 3203 3204 return true; 3205} 3206 3207/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3208/// return a DAG expression to select that will generate the same value by 3209/// multiplying by a magic number. See: 3210/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3211SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3212 std::vector<SDNode*>* Created) const { 3213 EVT VT = N->getValueType(0); 3214 DebugLoc dl= N->getDebugLoc(); 3215 3216 // Check to see if we can do this. 3217 // FIXME: We should be more aggressive here. 3218 if (!isTypeLegal(VT)) 3219 return SDValue(); 3220 3221 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3222 APInt::ms magics = d.magic(); 3223 3224 // Multiply the numerator (operand 0) by the magic value 3225 // FIXME: We should support doing a MUL in a wider type 3226 SDValue Q; 3227 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3228 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3229 DAG.getConstant(magics.m, VT)); 3230 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3231 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3232 N->getOperand(0), 3233 DAG.getConstant(magics.m, VT)).getNode(), 1); 3234 else 3235 return SDValue(); // No mulhs or equvialent 3236 // If d > 0 and m < 0, add the numerator 3237 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3238 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3239 if (Created) 3240 Created->push_back(Q.getNode()); 3241 } 3242 // If d < 0 and m > 0, subtract the numerator. 3243 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3244 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3245 if (Created) 3246 Created->push_back(Q.getNode()); 3247 } 3248 // Shift right algebraic if shift value is nonzero 3249 if (magics.s > 0) { 3250 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3251 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3252 if (Created) 3253 Created->push_back(Q.getNode()); 3254 } 3255 // Extract the sign bit and add it to the quotient 3256 SDValue T = 3257 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3258 getShiftAmountTy(Q.getValueType()))); 3259 if (Created) 3260 Created->push_back(T.getNode()); 3261 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3262} 3263 3264/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3265/// return a DAG expression to select that will generate the same value by 3266/// multiplying by a magic number. See: 3267/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3268SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3269 std::vector<SDNode*>* Created) const { 3270 EVT VT = N->getValueType(0); 3271 DebugLoc dl = N->getDebugLoc(); 3272 3273 // Check to see if we can do this. 3274 // FIXME: We should be more aggressive here. 3275 if (!isTypeLegal(VT)) 3276 return SDValue(); 3277 3278 // FIXME: We should use a narrower constant when the upper 3279 // bits are known to be zero. 3280 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3281 APInt::mu magics = N1C.magicu(); 3282 3283 SDValue Q = N->getOperand(0); 3284 3285 // If the divisor is even, we can avoid using the expensive fixup by shifting 3286 // the divided value upfront. 3287 if (magics.a != 0 && !N1C[0]) { 3288 unsigned Shift = N1C.countTrailingZeros(); 3289 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3290 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3291 if (Created) 3292 Created->push_back(Q.getNode()); 3293 3294 // Get magic number for the shifted divisor. 3295 magics = N1C.lshr(Shift).magicu(Shift); 3296 assert(magics.a == 0 && "Should use cheap fixup now"); 3297 } 3298 3299 // Multiply the numerator (operand 0) by the magic value 3300 // FIXME: We should support doing a MUL in a wider type 3301 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3302 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3303 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3304 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3305 DAG.getConstant(magics.m, VT)).getNode(), 1); 3306 else 3307 return SDValue(); // No mulhu or equvialent 3308 if (Created) 3309 Created->push_back(Q.getNode()); 3310 3311 if (magics.a == 0) { 3312 assert(magics.s < N1C.getBitWidth() && 3313 "We shouldn't generate an undefined shift!"); 3314 return DAG.getNode(ISD::SRL, dl, VT, Q, 3315 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3316 } else { 3317 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3318 if (Created) 3319 Created->push_back(NPQ.getNode()); 3320 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3321 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3322 if (Created) 3323 Created->push_back(NPQ.getNode()); 3324 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3325 if (Created) 3326 Created->push_back(NPQ.getNode()); 3327 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3328 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3329 } 3330} 3331