TargetLowering.cpp revision 927411b7ce0b7852fe4f392d8cd4faaa3881f852
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/Target/TargetSubtarget.h" 22#include "llvm/GlobalVariable.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 178 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 179 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 180 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 181 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 182 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 183 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 184 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 185 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 186 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 187 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 188 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 189 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 190 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 191 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 192 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 193 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 194 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 195 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 196 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 197 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 198 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 199 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 200 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 201 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 202 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 203 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 204 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 205 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 206 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 207 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 208 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 209 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 210 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 211 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 212 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 213 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 214 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 215 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 216 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 217 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 218 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 219 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 220 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 221 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 222 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 223 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 224 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 225 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 226 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 227 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 228 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 229 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 230 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 231 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 232 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 233 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 234 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 235 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 236 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 237 Names[RTLIB::OEQ_F32] = "__eqsf2"; 238 Names[RTLIB::OEQ_F64] = "__eqdf2"; 239 Names[RTLIB::UNE_F32] = "__nesf2"; 240 Names[RTLIB::UNE_F64] = "__nedf2"; 241 Names[RTLIB::OGE_F32] = "__gesf2"; 242 Names[RTLIB::OGE_F64] = "__gedf2"; 243 Names[RTLIB::OLT_F32] = "__ltsf2"; 244 Names[RTLIB::OLT_F64] = "__ltdf2"; 245 Names[RTLIB::OLE_F32] = "__lesf2"; 246 Names[RTLIB::OLE_F64] = "__ledf2"; 247 Names[RTLIB::OGT_F32] = "__gtsf2"; 248 Names[RTLIB::OGT_F64] = "__gtdf2"; 249 Names[RTLIB::UO_F32] = "__unordsf2"; 250 Names[RTLIB::UO_F64] = "__unorddf2"; 251 Names[RTLIB::O_F32] = "__unordsf2"; 252 Names[RTLIB::O_F64] = "__unorddf2"; 253 Names[RTLIB::MEMCPY] = "memcpy"; 254 Names[RTLIB::MEMMOVE] = "memmove"; 255 Names[RTLIB::MEMSET] = "memset"; 256 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 257} 258 259/// InitLibcallCallingConvs - Set default libcall CallingConvs. 260/// 261static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 262 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 263 CCs[i] = CallingConv::C; 264 } 265} 266 267/// getFPEXT - Return the FPEXT_*_* value for the given types, or 268/// UNKNOWN_LIBCALL if there is none. 269RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 270 if (OpVT == MVT::f32) { 271 if (RetVT == MVT::f64) 272 return FPEXT_F32_F64; 273 } 274 275 return UNKNOWN_LIBCALL; 276} 277 278/// getFPROUND - Return the FPROUND_*_* value for the given types, or 279/// UNKNOWN_LIBCALL if there is none. 280RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 281 if (RetVT == MVT::f32) { 282 if (OpVT == MVT::f64) 283 return FPROUND_F64_F32; 284 if (OpVT == MVT::f80) 285 return FPROUND_F80_F32; 286 if (OpVT == MVT::ppcf128) 287 return FPROUND_PPCF128_F32; 288 } else if (RetVT == MVT::f64) { 289 if (OpVT == MVT::f80) 290 return FPROUND_F80_F64; 291 if (OpVT == MVT::ppcf128) 292 return FPROUND_PPCF128_F64; 293 } 294 295 return UNKNOWN_LIBCALL; 296} 297 298/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 299/// UNKNOWN_LIBCALL if there is none. 300RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 301 if (OpVT == MVT::f32) { 302 if (RetVT == MVT::i8) 303 return FPTOSINT_F32_I8; 304 if (RetVT == MVT::i16) 305 return FPTOSINT_F32_I16; 306 if (RetVT == MVT::i32) 307 return FPTOSINT_F32_I32; 308 if (RetVT == MVT::i64) 309 return FPTOSINT_F32_I64; 310 if (RetVT == MVT::i128) 311 return FPTOSINT_F32_I128; 312 } else if (OpVT == MVT::f64) { 313 if (RetVT == MVT::i32) 314 return FPTOSINT_F64_I32; 315 if (RetVT == MVT::i64) 316 return FPTOSINT_F64_I64; 317 if (RetVT == MVT::i128) 318 return FPTOSINT_F64_I128; 319 } else if (OpVT == MVT::f80) { 320 if (RetVT == MVT::i32) 321 return FPTOSINT_F80_I32; 322 if (RetVT == MVT::i64) 323 return FPTOSINT_F80_I64; 324 if (RetVT == MVT::i128) 325 return FPTOSINT_F80_I128; 326 } else if (OpVT == MVT::ppcf128) { 327 if (RetVT == MVT::i32) 328 return FPTOSINT_PPCF128_I32; 329 if (RetVT == MVT::i64) 330 return FPTOSINT_PPCF128_I64; 331 if (RetVT == MVT::i128) 332 return FPTOSINT_PPCF128_I128; 333 } 334 return UNKNOWN_LIBCALL; 335} 336 337/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 338/// UNKNOWN_LIBCALL if there is none. 339RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 340 if (OpVT == MVT::f32) { 341 if (RetVT == MVT::i8) 342 return FPTOUINT_F32_I8; 343 if (RetVT == MVT::i16) 344 return FPTOUINT_F32_I16; 345 if (RetVT == MVT::i32) 346 return FPTOUINT_F32_I32; 347 if (RetVT == MVT::i64) 348 return FPTOUINT_F32_I64; 349 if (RetVT == MVT::i128) 350 return FPTOUINT_F32_I128; 351 } else if (OpVT == MVT::f64) { 352 if (RetVT == MVT::i32) 353 return FPTOUINT_F64_I32; 354 if (RetVT == MVT::i64) 355 return FPTOUINT_F64_I64; 356 if (RetVT == MVT::i128) 357 return FPTOUINT_F64_I128; 358 } else if (OpVT == MVT::f80) { 359 if (RetVT == MVT::i32) 360 return FPTOUINT_F80_I32; 361 if (RetVT == MVT::i64) 362 return FPTOUINT_F80_I64; 363 if (RetVT == MVT::i128) 364 return FPTOUINT_F80_I128; 365 } else if (OpVT == MVT::ppcf128) { 366 if (RetVT == MVT::i32) 367 return FPTOUINT_PPCF128_I32; 368 if (RetVT == MVT::i64) 369 return FPTOUINT_PPCF128_I64; 370 if (RetVT == MVT::i128) 371 return FPTOUINT_PPCF128_I128; 372 } 373 return UNKNOWN_LIBCALL; 374} 375 376/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 377/// UNKNOWN_LIBCALL if there is none. 378RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 379 if (OpVT == MVT::i32) { 380 if (RetVT == MVT::f32) 381 return SINTTOFP_I32_F32; 382 else if (RetVT == MVT::f64) 383 return SINTTOFP_I32_F64; 384 else if (RetVT == MVT::f80) 385 return SINTTOFP_I32_F80; 386 else if (RetVT == MVT::ppcf128) 387 return SINTTOFP_I32_PPCF128; 388 } else if (OpVT == MVT::i64) { 389 if (RetVT == MVT::f32) 390 return SINTTOFP_I64_F32; 391 else if (RetVT == MVT::f64) 392 return SINTTOFP_I64_F64; 393 else if (RetVT == MVT::f80) 394 return SINTTOFP_I64_F80; 395 else if (RetVT == MVT::ppcf128) 396 return SINTTOFP_I64_PPCF128; 397 } else if (OpVT == MVT::i128) { 398 if (RetVT == MVT::f32) 399 return SINTTOFP_I128_F32; 400 else if (RetVT == MVT::f64) 401 return SINTTOFP_I128_F64; 402 else if (RetVT == MVT::f80) 403 return SINTTOFP_I128_F80; 404 else if (RetVT == MVT::ppcf128) 405 return SINTTOFP_I128_PPCF128; 406 } 407 return UNKNOWN_LIBCALL; 408} 409 410/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 411/// UNKNOWN_LIBCALL if there is none. 412RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 413 if (OpVT == MVT::i32) { 414 if (RetVT == MVT::f32) 415 return UINTTOFP_I32_F32; 416 else if (RetVT == MVT::f64) 417 return UINTTOFP_I32_F64; 418 else if (RetVT == MVT::f80) 419 return UINTTOFP_I32_F80; 420 else if (RetVT == MVT::ppcf128) 421 return UINTTOFP_I32_PPCF128; 422 } else if (OpVT == MVT::i64) { 423 if (RetVT == MVT::f32) 424 return UINTTOFP_I64_F32; 425 else if (RetVT == MVT::f64) 426 return UINTTOFP_I64_F64; 427 else if (RetVT == MVT::f80) 428 return UINTTOFP_I64_F80; 429 else if (RetVT == MVT::ppcf128) 430 return UINTTOFP_I64_PPCF128; 431 } else if (OpVT == MVT::i128) { 432 if (RetVT == MVT::f32) 433 return UINTTOFP_I128_F32; 434 else if (RetVT == MVT::f64) 435 return UINTTOFP_I128_F64; 436 else if (RetVT == MVT::f80) 437 return UINTTOFP_I128_F80; 438 else if (RetVT == MVT::ppcf128) 439 return UINTTOFP_I128_PPCF128; 440 } 441 return UNKNOWN_LIBCALL; 442} 443 444/// InitCmpLibcallCCs - Set default comparison libcall CC. 445/// 446static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 447 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 448 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 449 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 450 CCs[RTLIB::UNE_F32] = ISD::SETNE; 451 CCs[RTLIB::UNE_F64] = ISD::SETNE; 452 CCs[RTLIB::OGE_F32] = ISD::SETGE; 453 CCs[RTLIB::OGE_F64] = ISD::SETGE; 454 CCs[RTLIB::OLT_F32] = ISD::SETLT; 455 CCs[RTLIB::OLT_F64] = ISD::SETLT; 456 CCs[RTLIB::OLE_F32] = ISD::SETLE; 457 CCs[RTLIB::OLE_F64] = ISD::SETLE; 458 CCs[RTLIB::OGT_F32] = ISD::SETGT; 459 CCs[RTLIB::OGT_F64] = ISD::SETGT; 460 CCs[RTLIB::UO_F32] = ISD::SETNE; 461 CCs[RTLIB::UO_F64] = ISD::SETNE; 462 CCs[RTLIB::O_F32] = ISD::SETEQ; 463 CCs[RTLIB::O_F64] = ISD::SETEQ; 464} 465 466/// NOTE: The constructor takes ownership of TLOF. 467TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) 468 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 469 // All operations default to being supported. 470 memset(OpActions, 0, sizeof(OpActions)); 471 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 472 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 473 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 474 memset(ConvertActions, 0, sizeof(ConvertActions)); 475 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 476 477 // Set default actions for various operations. 478 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 479 // Default all indexed load / store to expand. 480 for (unsigned IM = (unsigned)ISD::PRE_INC; 481 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 482 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 483 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 484 } 485 486 // These operations default to expand. 487 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 488 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 489 } 490 491 // Most targets ignore the @llvm.prefetch intrinsic. 492 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 493 494 // ConstantFP nodes default to expand. Targets can either change this to 495 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 496 // to optimize expansions for certain constants. 497 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 498 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 499 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 500 501 // These library functions default to expand. 502 setOperationAction(ISD::FLOG , MVT::f64, Expand); 503 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 504 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 505 setOperationAction(ISD::FEXP , MVT::f64, Expand); 506 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 507 setOperationAction(ISD::FLOG , MVT::f32, Expand); 508 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 509 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 510 setOperationAction(ISD::FEXP , MVT::f32, Expand); 511 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 512 513 // Default ISD::TRAP to expand (which turns it into abort). 514 setOperationAction(ISD::TRAP, MVT::Other, Expand); 515 516 IsLittleEndian = TD->isLittleEndian(); 517 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 518 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 519 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 520 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 521 benefitFromCodePlacementOpt = false; 522 UseUnderscoreSetJmp = false; 523 UseUnderscoreLongJmp = false; 524 SelectIsExpensive = false; 525 IntDivIsCheap = false; 526 Pow2DivIsCheap = false; 527 StackPointerRegisterToSaveRestore = 0; 528 ExceptionPointerRegister = 0; 529 ExceptionSelectorRegister = 0; 530 BooleanContents = UndefinedBooleanContent; 531 SchedPreferenceInfo = SchedulingForLatency; 532 JumpBufSize = 0; 533 JumpBufAlignment = 0; 534 IfCvtBlockSizeLimit = 2; 535 IfCvtDupBlockSizeLimit = 0; 536 PrefLoopAlignment = 0; 537 538 InitLibcallNames(LibcallRoutineNames); 539 InitCmpLibcallCCs(CmpLibcallCCs); 540 InitLibcallCallingConvs(LibcallCallingConvs); 541} 542 543TargetLowering::~TargetLowering() { 544 delete &TLOF; 545} 546 547/// canOpTrap - Returns true if the operation can trap for the value type. 548/// VT must be a legal type. 549bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 550 assert(isTypeLegal(VT)); 551 switch (Op) { 552 default: 553 return false; 554 case ISD::FDIV: 555 case ISD::FREM: 556 case ISD::SDIV: 557 case ISD::UDIV: 558 case ISD::SREM: 559 case ISD::UREM: 560 return true; 561 } 562} 563 564 565static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 566 unsigned &NumIntermediates, 567 EVT &RegisterVT, 568 TargetLowering* TLI) { 569 // Figure out the right, legal destination reg to copy into. 570 unsigned NumElts = VT.getVectorNumElements(); 571 MVT EltTy = VT.getVectorElementType(); 572 573 unsigned NumVectorRegs = 1; 574 575 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 576 // could break down into LHS/RHS like LegalizeDAG does. 577 if (!isPowerOf2_32(NumElts)) { 578 NumVectorRegs = NumElts; 579 NumElts = 1; 580 } 581 582 // Divide the input until we get to a supported size. This will always 583 // end with a scalar if the target doesn't support vectors. 584 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 585 NumElts >>= 1; 586 NumVectorRegs <<= 1; 587 } 588 589 NumIntermediates = NumVectorRegs; 590 591 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 592 if (!TLI->isTypeLegal(NewVT)) 593 NewVT = EltTy; 594 IntermediateVT = NewVT; 595 596 EVT DestVT = TLI->getRegisterType(NewVT); 597 RegisterVT = DestVT; 598 if (EVT(DestVT).bitsLT(NewVT)) { 599 // Value is expanded, e.g. i64 -> i16. 600 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 601 } else { 602 // Otherwise, promotion or legal types use the same number of registers as 603 // the vector decimated to the appropriate level. 604 return NumVectorRegs; 605 } 606 607 return 1; 608} 609 610/// computeRegisterProperties - Once all of the register classes are added, 611/// this allows us to compute derived properties we expose. 612void TargetLowering::computeRegisterProperties() { 613 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 614 "Too many value types for ValueTypeActions to hold!"); 615 616 // Everything defaults to needing one register. 617 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 618 NumRegistersForVT[i] = 1; 619 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 620 } 621 // ...except isVoid, which doesn't need any registers. 622 NumRegistersForVT[MVT::isVoid] = 0; 623 624 // Find the largest integer register class. 625 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 626 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 627 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 628 629 // Every integer value type larger than this largest register takes twice as 630 // many registers to represent as the previous ValueType. 631 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 632 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 633 if (!ExpandedVT.isInteger()) 634 break; 635 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 636 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 637 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 638 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 639 } 640 641 // Inspect all of the ValueType's smaller than the largest integer 642 // register to see which ones need promotion. 643 unsigned LegalIntReg = LargestIntReg; 644 for (unsigned IntReg = LargestIntReg - 1; 645 IntReg >= (unsigned)MVT::i1; --IntReg) { 646 EVT IVT = (MVT::SimpleValueType)IntReg; 647 if (isTypeLegal(IVT)) { 648 LegalIntReg = IntReg; 649 } else { 650 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 651 (MVT::SimpleValueType)LegalIntReg; 652 ValueTypeActions.setTypeAction(IVT, Promote); 653 } 654 } 655 656 // ppcf128 type is really two f64's. 657 if (!isTypeLegal(MVT::ppcf128)) { 658 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 659 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 660 TransformToType[MVT::ppcf128] = MVT::f64; 661 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 662 } 663 664 // Decide how to handle f64. If the target does not have native f64 support, 665 // expand it to i64 and we will be generating soft float library calls. 666 if (!isTypeLegal(MVT::f64)) { 667 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 668 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 669 TransformToType[MVT::f64] = MVT::i64; 670 ValueTypeActions.setTypeAction(MVT::f64, Expand); 671 } 672 673 // Decide how to handle f32. If the target does not have native support for 674 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 675 if (!isTypeLegal(MVT::f32)) { 676 if (isTypeLegal(MVT::f64)) { 677 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 678 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 679 TransformToType[MVT::f32] = MVT::f64; 680 ValueTypeActions.setTypeAction(MVT::f32, Promote); 681 } else { 682 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 683 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 684 TransformToType[MVT::f32] = MVT::i32; 685 ValueTypeActions.setTypeAction(MVT::f32, Expand); 686 } 687 } 688 689 // Loop over all of the vector value types to see which need transformations. 690 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 691 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 692 MVT VT = (MVT::SimpleValueType)i; 693 if (!isTypeLegal(VT)) { 694 MVT IntermediateVT; 695 EVT RegisterVT; 696 unsigned NumIntermediates; 697 NumRegistersForVT[i] = 698 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 699 RegisterVT, this); 700 RegisterTypeForVT[i] = RegisterVT; 701 702 // Determine if there is a legal wider type. 703 bool IsLegalWiderType = false; 704 EVT EltVT = VT.getVectorElementType(); 705 unsigned NElts = VT.getVectorNumElements(); 706 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 707 EVT SVT = (MVT::SimpleValueType)nVT; 708 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 709 SVT.getVectorNumElements() > NElts && NElts != 1) { 710 TransformToType[i] = SVT; 711 ValueTypeActions.setTypeAction(VT, Promote); 712 IsLegalWiderType = true; 713 break; 714 } 715 } 716 if (!IsLegalWiderType) { 717 EVT NVT = VT.getPow2VectorType(); 718 if (NVT == VT) { 719 // Type is already a power of 2. The default action is to split. 720 TransformToType[i] = MVT::Other; 721 ValueTypeActions.setTypeAction(VT, Expand); 722 } else { 723 TransformToType[i] = NVT; 724 ValueTypeActions.setTypeAction(VT, Promote); 725 } 726 } 727 } 728 } 729} 730 731const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 732 return NULL; 733} 734 735 736MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 737 return PointerTy.SimpleTy; 738} 739 740MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 741 return MVT::i32; // return the default value 742} 743 744/// getVectorTypeBreakdown - Vector types are broken down into some number of 745/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 746/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 747/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 748/// 749/// This method returns the number of registers needed, and the VT for each 750/// register. It also returns the VT and quantity of the intermediate values 751/// before they are promoted/expanded. 752/// 753unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 754 EVT &IntermediateVT, 755 unsigned &NumIntermediates, 756 EVT &RegisterVT) const { 757 // Figure out the right, legal destination reg to copy into. 758 unsigned NumElts = VT.getVectorNumElements(); 759 EVT EltTy = VT.getVectorElementType(); 760 761 unsigned NumVectorRegs = 1; 762 763 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 764 // could break down into LHS/RHS like LegalizeDAG does. 765 if (!isPowerOf2_32(NumElts)) { 766 NumVectorRegs = NumElts; 767 NumElts = 1; 768 } 769 770 // Divide the input until we get to a supported size. This will always 771 // end with a scalar if the target doesn't support vectors. 772 while (NumElts > 1 && !isTypeLegal( 773 EVT::getVectorVT(Context, EltTy, NumElts))) { 774 NumElts >>= 1; 775 NumVectorRegs <<= 1; 776 } 777 778 NumIntermediates = NumVectorRegs; 779 780 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 781 if (!isTypeLegal(NewVT)) 782 NewVT = EltTy; 783 IntermediateVT = NewVT; 784 785 EVT DestVT = getRegisterType(Context, NewVT); 786 RegisterVT = DestVT; 787 if (DestVT.bitsLT(NewVT)) { 788 // Value is expanded, e.g. i64 -> i16. 789 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 790 } else { 791 // Otherwise, promotion or legal types use the same number of registers as 792 // the vector decimated to the appropriate level. 793 return NumVectorRegs; 794 } 795 796 return 1; 797} 798 799/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 800/// function arguments in the caller parameter area. This is the actual 801/// alignment, not its logarithm. 802unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 803 return TD->getCallFrameTypeAlignment(Ty); 804} 805 806/// getJumpTableEncoding - Return the entry encoding for a jump table in the 807/// current function. The returned value is a member of the 808/// MachineJumpTableInfo::JTEntryKind enum. 809unsigned TargetLowering::getJumpTableEncoding() const { 810 // In non-pic modes, just use the address of a block. 811 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 812 return MachineJumpTableInfo::EK_BlockAddress; 813 814 // In PIC mode, if the target supports a GPRel32 directive, use it. 815 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 816 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 817 818 // Otherwise, use a label difference. 819 return MachineJumpTableInfo::EK_LabelDifference32; 820} 821 822SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 823 SelectionDAG &DAG) const { 824 // If our PIC model is GP relative, use the global offset table as the base. 825 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 826 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 827 return Table; 828} 829 830/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 831/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 832/// MCExpr. 833const MCExpr * 834TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 835 unsigned JTI,MCContext &Ctx) const{ 836 // The normal PIC reloc base is the label at the start of the jump table. 837 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 838} 839 840bool 841TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 842 // Assume that everything is safe in static mode. 843 if (getTargetMachine().getRelocationModel() == Reloc::Static) 844 return true; 845 846 // In dynamic-no-pic mode, assume that known defined values are safe. 847 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 848 GA && 849 !GA->getGlobal()->isDeclaration() && 850 !GA->getGlobal()->isWeakForLinker()) 851 return true; 852 853 // Otherwise assume nothing is safe. 854 return false; 855} 856 857//===----------------------------------------------------------------------===// 858// Optimization Methods 859//===----------------------------------------------------------------------===// 860 861/// ShrinkDemandedConstant - Check to see if the specified operand of the 862/// specified instruction is a constant integer. If so, check to see if there 863/// are any bits set in the constant that are not demanded. If so, shrink the 864/// constant and return true. 865bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 866 const APInt &Demanded) { 867 DebugLoc dl = Op.getDebugLoc(); 868 869 // FIXME: ISD::SELECT, ISD::SELECT_CC 870 switch (Op.getOpcode()) { 871 default: break; 872 case ISD::XOR: 873 case ISD::AND: 874 case ISD::OR: { 875 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 876 if (!C) return false; 877 878 if (Op.getOpcode() == ISD::XOR && 879 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 880 return false; 881 882 // if we can expand it to have all bits set, do it 883 if (C->getAPIntValue().intersects(~Demanded)) { 884 EVT VT = Op.getValueType(); 885 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 886 DAG.getConstant(Demanded & 887 C->getAPIntValue(), 888 VT)); 889 return CombineTo(Op, New); 890 } 891 892 break; 893 } 894 } 895 896 return false; 897} 898 899/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 900/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 901/// cast, but it could be generalized for targets with other types of 902/// implicit widening casts. 903bool 904TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 905 unsigned BitWidth, 906 const APInt &Demanded, 907 DebugLoc dl) { 908 assert(Op.getNumOperands() == 2 && 909 "ShrinkDemandedOp only supports binary operators!"); 910 assert(Op.getNode()->getNumValues() == 1 && 911 "ShrinkDemandedOp only supports nodes with one result!"); 912 913 // Don't do this if the node has another user, which may require the 914 // full value. 915 if (!Op.getNode()->hasOneUse()) 916 return false; 917 918 // Search for the smallest integer type with free casts to and from 919 // Op's type. For expedience, just check power-of-2 integer types. 920 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 921 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 922 if (!isPowerOf2_32(SmallVTBits)) 923 SmallVTBits = NextPowerOf2(SmallVTBits); 924 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 925 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 926 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 927 TLI.isZExtFree(SmallVT, Op.getValueType())) { 928 // We found a type with free casts. 929 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 930 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 931 Op.getNode()->getOperand(0)), 932 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 933 Op.getNode()->getOperand(1))); 934 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 935 return CombineTo(Op, Z); 936 } 937 } 938 return false; 939} 940 941/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 942/// DemandedMask bits of the result of Op are ever used downstream. If we can 943/// use this information to simplify Op, create a new simplified DAG node and 944/// return true, returning the original and new nodes in Old and New. Otherwise, 945/// analyze the expression and return a mask of KnownOne and KnownZero bits for 946/// the expression (used to simplify the caller). The KnownZero/One bits may 947/// only be accurate for those bits in the DemandedMask. 948bool TargetLowering::SimplifyDemandedBits(SDValue Op, 949 const APInt &DemandedMask, 950 APInt &KnownZero, 951 APInt &KnownOne, 952 TargetLoweringOpt &TLO, 953 unsigned Depth) const { 954 unsigned BitWidth = DemandedMask.getBitWidth(); 955 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 956 "Mask size mismatches value type size!"); 957 APInt NewMask = DemandedMask; 958 DebugLoc dl = Op.getDebugLoc(); 959 960 // Don't know anything. 961 KnownZero = KnownOne = APInt(BitWidth, 0); 962 963 // Other users may use these bits. 964 if (!Op.getNode()->hasOneUse()) { 965 if (Depth != 0) { 966 // If not at the root, Just compute the KnownZero/KnownOne bits to 967 // simplify things downstream. 968 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 969 return false; 970 } 971 // If this is the root being simplified, allow it to have multiple uses, 972 // just set the NewMask to all bits. 973 NewMask = APInt::getAllOnesValue(BitWidth); 974 } else if (DemandedMask == 0) { 975 // Not demanding any bits from Op. 976 if (Op.getOpcode() != ISD::UNDEF) 977 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 978 return false; 979 } else if (Depth == 6) { // Limit search depth. 980 return false; 981 } 982 983 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 984 switch (Op.getOpcode()) { 985 case ISD::Constant: 986 // We know all of the bits for a constant! 987 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 988 KnownZero = ~KnownOne & NewMask; 989 return false; // Don't fall through, will infinitely loop. 990 case ISD::AND: 991 // If the RHS is a constant, check to see if the LHS would be zero without 992 // using the bits from the RHS. Below, we use knowledge about the RHS to 993 // simplify the LHS, here we're using information from the LHS to simplify 994 // the RHS. 995 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 996 APInt LHSZero, LHSOne; 997 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 998 LHSZero, LHSOne, Depth+1); 999 // If the LHS already has zeros where RHSC does, this and is dead. 1000 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1001 return TLO.CombineTo(Op, Op.getOperand(0)); 1002 // If any of the set bits in the RHS are known zero on the LHS, shrink 1003 // the constant. 1004 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1005 return true; 1006 } 1007 1008 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1009 KnownOne, TLO, Depth+1)) 1010 return true; 1011 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1012 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1013 KnownZero2, KnownOne2, TLO, Depth+1)) 1014 return true; 1015 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1016 1017 // If all of the demanded bits are known one on one side, return the other. 1018 // These bits cannot contribute to the result of the 'and'. 1019 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1020 return TLO.CombineTo(Op, Op.getOperand(0)); 1021 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1022 return TLO.CombineTo(Op, Op.getOperand(1)); 1023 // If all of the demanded bits in the inputs are known zeros, return zero. 1024 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1025 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1026 // If the RHS is a constant, see if we can simplify it. 1027 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1028 return true; 1029 // If the operation can be done in a smaller type, do so. 1030 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1031 return true; 1032 1033 // Output known-1 bits are only known if set in both the LHS & RHS. 1034 KnownOne &= KnownOne2; 1035 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1036 KnownZero |= KnownZero2; 1037 break; 1038 case ISD::OR: 1039 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1040 KnownOne, TLO, Depth+1)) 1041 return true; 1042 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1043 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1044 KnownZero2, KnownOne2, TLO, Depth+1)) 1045 return true; 1046 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1047 1048 // If all of the demanded bits are known zero on one side, return the other. 1049 // These bits cannot contribute to the result of the 'or'. 1050 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1051 return TLO.CombineTo(Op, Op.getOperand(0)); 1052 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1053 return TLO.CombineTo(Op, Op.getOperand(1)); 1054 // If all of the potentially set bits on one side are known to be set on 1055 // the other side, just use the 'other' side. 1056 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1057 return TLO.CombineTo(Op, Op.getOperand(0)); 1058 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1059 return TLO.CombineTo(Op, Op.getOperand(1)); 1060 // If the RHS is a constant, see if we can simplify it. 1061 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1062 return true; 1063 // If the operation can be done in a smaller type, do so. 1064 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1065 return true; 1066 1067 // Output known-0 bits are only known if clear in both the LHS & RHS. 1068 KnownZero &= KnownZero2; 1069 // Output known-1 are known to be set if set in either the LHS | RHS. 1070 KnownOne |= KnownOne2; 1071 break; 1072 case ISD::XOR: 1073 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1074 KnownOne, TLO, Depth+1)) 1075 return true; 1076 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1077 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1078 KnownOne2, TLO, Depth+1)) 1079 return true; 1080 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1081 1082 // If all of the demanded bits are known zero on one side, return the other. 1083 // These bits cannot contribute to the result of the 'xor'. 1084 if ((KnownZero & NewMask) == NewMask) 1085 return TLO.CombineTo(Op, Op.getOperand(0)); 1086 if ((KnownZero2 & NewMask) == NewMask) 1087 return TLO.CombineTo(Op, Op.getOperand(1)); 1088 // If the operation can be done in a smaller type, do so. 1089 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1090 return true; 1091 1092 // If all of the unknown bits are known to be zero on one side or the other 1093 // (but not both) turn this into an *inclusive* or. 1094 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1095 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1096 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1097 Op.getOperand(0), 1098 Op.getOperand(1))); 1099 1100 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1101 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1102 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1103 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1104 1105 // If all of the demanded bits on one side are known, and all of the set 1106 // bits on that side are also known to be set on the other side, turn this 1107 // into an AND, as we know the bits will be cleared. 1108 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1109 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1110 if ((KnownOne & KnownOne2) == KnownOne) { 1111 EVT VT = Op.getValueType(); 1112 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1113 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1114 Op.getOperand(0), ANDC)); 1115 } 1116 } 1117 1118 // If the RHS is a constant, see if we can simplify it. 1119 // for XOR, we prefer to force bits to 1 if they will make a -1. 1120 // if we can't force bits, try to shrink constant 1121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1122 APInt Expanded = C->getAPIntValue() | (~NewMask); 1123 // if we can expand it to have all bits set, do it 1124 if (Expanded.isAllOnesValue()) { 1125 if (Expanded != C->getAPIntValue()) { 1126 EVT VT = Op.getValueType(); 1127 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1128 TLO.DAG.getConstant(Expanded, VT)); 1129 return TLO.CombineTo(Op, New); 1130 } 1131 // if it already has all the bits set, nothing to change 1132 // but don't shrink either! 1133 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1134 return true; 1135 } 1136 } 1137 1138 KnownZero = KnownZeroOut; 1139 KnownOne = KnownOneOut; 1140 break; 1141 case ISD::SELECT: 1142 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1143 KnownOne, TLO, Depth+1)) 1144 return true; 1145 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1146 KnownOne2, TLO, Depth+1)) 1147 return true; 1148 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1149 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1150 1151 // If the operands are constants, see if we can simplify them. 1152 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1153 return true; 1154 1155 // Only known if known in both the LHS and RHS. 1156 KnownOne &= KnownOne2; 1157 KnownZero &= KnownZero2; 1158 break; 1159 case ISD::SELECT_CC: 1160 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1161 KnownOne, TLO, Depth+1)) 1162 return true; 1163 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1164 KnownOne2, TLO, Depth+1)) 1165 return true; 1166 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1167 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1168 1169 // If the operands are constants, see if we can simplify them. 1170 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1171 return true; 1172 1173 // Only known if known in both the LHS and RHS. 1174 KnownOne &= KnownOne2; 1175 KnownZero &= KnownZero2; 1176 break; 1177 case ISD::SHL: 1178 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1179 unsigned ShAmt = SA->getZExtValue(); 1180 SDValue InOp = Op.getOperand(0); 1181 1182 // If the shift count is an invalid immediate, don't do anything. 1183 if (ShAmt >= BitWidth) 1184 break; 1185 1186 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1187 // single shift. We can do this if the bottom bits (which are shifted 1188 // out) are never demanded. 1189 if (InOp.getOpcode() == ISD::SRL && 1190 isa<ConstantSDNode>(InOp.getOperand(1))) { 1191 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1192 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1193 unsigned Opc = ISD::SHL; 1194 int Diff = ShAmt-C1; 1195 if (Diff < 0) { 1196 Diff = -Diff; 1197 Opc = ISD::SRL; 1198 } 1199 1200 SDValue NewSA = 1201 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1202 EVT VT = Op.getValueType(); 1203 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1204 InOp.getOperand(0), NewSA)); 1205 } 1206 } 1207 1208 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1209 KnownZero, KnownOne, TLO, Depth+1)) 1210 return true; 1211 KnownZero <<= SA->getZExtValue(); 1212 KnownOne <<= SA->getZExtValue(); 1213 // low bits known zero. 1214 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1215 } 1216 break; 1217 case ISD::SRL: 1218 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1219 EVT VT = Op.getValueType(); 1220 unsigned ShAmt = SA->getZExtValue(); 1221 unsigned VTSize = VT.getSizeInBits(); 1222 SDValue InOp = Op.getOperand(0); 1223 1224 // If the shift count is an invalid immediate, don't do anything. 1225 if (ShAmt >= BitWidth) 1226 break; 1227 1228 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1229 // single shift. We can do this if the top bits (which are shifted out) 1230 // are never demanded. 1231 if (InOp.getOpcode() == ISD::SHL && 1232 isa<ConstantSDNode>(InOp.getOperand(1))) { 1233 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1234 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1235 unsigned Opc = ISD::SRL; 1236 int Diff = ShAmt-C1; 1237 if (Diff < 0) { 1238 Diff = -Diff; 1239 Opc = ISD::SHL; 1240 } 1241 1242 SDValue NewSA = 1243 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1244 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1245 InOp.getOperand(0), NewSA)); 1246 } 1247 } 1248 1249 // Compute the new bits that are at the top now. 1250 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1251 KnownZero, KnownOne, TLO, Depth+1)) 1252 return true; 1253 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1254 KnownZero = KnownZero.lshr(ShAmt); 1255 KnownOne = KnownOne.lshr(ShAmt); 1256 1257 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1258 KnownZero |= HighBits; // High bits known zero. 1259 } 1260 break; 1261 case ISD::SRA: 1262 // If this is an arithmetic shift right and only the low-bit is set, we can 1263 // always convert this into a logical shr, even if the shift amount is 1264 // variable. The low bit of the shift cannot be an input sign bit unless 1265 // the shift amount is >= the size of the datatype, which is undefined. 1266 if (DemandedMask == 1) 1267 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1268 Op.getOperand(0), Op.getOperand(1))); 1269 1270 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1271 EVT VT = Op.getValueType(); 1272 unsigned ShAmt = SA->getZExtValue(); 1273 1274 // If the shift count is an invalid immediate, don't do anything. 1275 if (ShAmt >= BitWidth) 1276 break; 1277 1278 APInt InDemandedMask = (NewMask << ShAmt); 1279 1280 // If any of the demanded bits are produced by the sign extension, we also 1281 // demand the input sign bit. 1282 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1283 if (HighBits.intersects(NewMask)) 1284 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1285 1286 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1287 KnownZero, KnownOne, TLO, Depth+1)) 1288 return true; 1289 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1290 KnownZero = KnownZero.lshr(ShAmt); 1291 KnownOne = KnownOne.lshr(ShAmt); 1292 1293 // Handle the sign bit, adjusted to where it is now in the mask. 1294 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1295 1296 // If the input sign bit is known to be zero, or if none of the top bits 1297 // are demanded, turn this into an unsigned shift right. 1298 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1299 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1300 Op.getOperand(0), 1301 Op.getOperand(1))); 1302 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1303 KnownOne |= HighBits; 1304 } 1305 } 1306 break; 1307 case ISD::SIGN_EXTEND_INREG: { 1308 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1309 1310 // Sign extension. Compute the demanded bits in the result that are not 1311 // present in the input. 1312 APInt NewBits = 1313 APInt::getHighBitsSet(BitWidth, 1314 BitWidth - EVT.getScalarType().getSizeInBits()) & 1315 NewMask; 1316 1317 // If none of the extended bits are demanded, eliminate the sextinreg. 1318 if (NewBits == 0) 1319 return TLO.CombineTo(Op, Op.getOperand(0)); 1320 1321 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1322 InSignBit.zext(BitWidth); 1323 APInt InputDemandedBits = 1324 APInt::getLowBitsSet(BitWidth, 1325 EVT.getScalarType().getSizeInBits()) & 1326 NewMask; 1327 1328 // Since the sign extended bits are demanded, we know that the sign 1329 // bit is demanded. 1330 InputDemandedBits |= InSignBit; 1331 1332 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1333 KnownZero, KnownOne, TLO, Depth+1)) 1334 return true; 1335 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1336 1337 // If the sign bit of the input is known set or clear, then we know the 1338 // top bits of the result. 1339 1340 // If the input sign bit is known zero, convert this into a zero extension. 1341 if (KnownZero.intersects(InSignBit)) 1342 return TLO.CombineTo(Op, 1343 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1344 1345 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1346 KnownOne |= NewBits; 1347 KnownZero &= ~NewBits; 1348 } else { // Input sign bit unknown 1349 KnownZero &= ~NewBits; 1350 KnownOne &= ~NewBits; 1351 } 1352 break; 1353 } 1354 case ISD::ZERO_EXTEND: { 1355 unsigned OperandBitWidth = 1356 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1357 APInt InMask = NewMask; 1358 InMask.trunc(OperandBitWidth); 1359 1360 // If none of the top bits are demanded, convert this into an any_extend. 1361 APInt NewBits = 1362 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1363 if (!NewBits.intersects(NewMask)) 1364 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1365 Op.getValueType(), 1366 Op.getOperand(0))); 1367 1368 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1369 KnownZero, KnownOne, TLO, Depth+1)) 1370 return true; 1371 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1372 KnownZero.zext(BitWidth); 1373 KnownOne.zext(BitWidth); 1374 KnownZero |= NewBits; 1375 break; 1376 } 1377 case ISD::SIGN_EXTEND: { 1378 EVT InVT = Op.getOperand(0).getValueType(); 1379 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1380 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1381 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1382 APInt NewBits = ~InMask & NewMask; 1383 1384 // If none of the top bits are demanded, convert this into an any_extend. 1385 if (NewBits == 0) 1386 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1387 Op.getValueType(), 1388 Op.getOperand(0))); 1389 1390 // Since some of the sign extended bits are demanded, we know that the sign 1391 // bit is demanded. 1392 APInt InDemandedBits = InMask & NewMask; 1393 InDemandedBits |= InSignBit; 1394 InDemandedBits.trunc(InBits); 1395 1396 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1397 KnownOne, TLO, Depth+1)) 1398 return true; 1399 KnownZero.zext(BitWidth); 1400 KnownOne.zext(BitWidth); 1401 1402 // If the sign bit is known zero, convert this to a zero extend. 1403 if (KnownZero.intersects(InSignBit)) 1404 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1405 Op.getValueType(), 1406 Op.getOperand(0))); 1407 1408 // If the sign bit is known one, the top bits match. 1409 if (KnownOne.intersects(InSignBit)) { 1410 KnownOne |= NewBits; 1411 KnownZero &= ~NewBits; 1412 } else { // Otherwise, top bits aren't known. 1413 KnownOne &= ~NewBits; 1414 KnownZero &= ~NewBits; 1415 } 1416 break; 1417 } 1418 case ISD::ANY_EXTEND: { 1419 unsigned OperandBitWidth = 1420 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1421 APInt InMask = NewMask; 1422 InMask.trunc(OperandBitWidth); 1423 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1424 KnownZero, KnownOne, TLO, Depth+1)) 1425 return true; 1426 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1427 KnownZero.zext(BitWidth); 1428 KnownOne.zext(BitWidth); 1429 break; 1430 } 1431 case ISD::TRUNCATE: { 1432 // Simplify the input, using demanded bit information, and compute the known 1433 // zero/one bits live out. 1434 unsigned OperandBitWidth = 1435 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1436 APInt TruncMask = NewMask; 1437 TruncMask.zext(OperandBitWidth); 1438 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1439 KnownZero, KnownOne, TLO, Depth+1)) 1440 return true; 1441 KnownZero.trunc(BitWidth); 1442 KnownOne.trunc(BitWidth); 1443 1444 // If the input is only used by this truncate, see if we can shrink it based 1445 // on the known demanded bits. 1446 if (Op.getOperand(0).getNode()->hasOneUse()) { 1447 SDValue In = Op.getOperand(0); 1448 switch (In.getOpcode()) { 1449 default: break; 1450 case ISD::SRL: 1451 // Shrink SRL by a constant if none of the high bits shifted in are 1452 // demanded. 1453 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1454 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1455 OperandBitWidth - BitWidth); 1456 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1457 HighBits.trunc(BitWidth); 1458 1459 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1460 // None of the shifted in bits are needed. Add a truncate of the 1461 // shift input, then shift it. 1462 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1463 Op.getValueType(), 1464 In.getOperand(0)); 1465 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1466 Op.getValueType(), 1467 NewTrunc, 1468 In.getOperand(1))); 1469 } 1470 } 1471 break; 1472 } 1473 } 1474 1475 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1476 break; 1477 } 1478 case ISD::AssertZext: { 1479 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1480 APInt InMask = APInt::getLowBitsSet(BitWidth, 1481 VT.getSizeInBits()); 1482 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1483 KnownZero, KnownOne, TLO, Depth+1)) 1484 return true; 1485 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1486 KnownZero |= ~InMask & NewMask; 1487 break; 1488 } 1489 case ISD::BIT_CONVERT: 1490#if 0 1491 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1492 // is demanded, turn this into a FGETSIGN. 1493 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1494 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1495 !MVT::isVector(Op.getOperand(0).getValueType())) { 1496 // Only do this xform if FGETSIGN is valid or if before legalize. 1497 if (!TLO.AfterLegalize || 1498 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1499 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1500 // place. We expect the SHL to be eliminated by other optimizations. 1501 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1502 Op.getOperand(0)); 1503 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1504 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1505 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1506 Sign, ShAmt)); 1507 } 1508 } 1509#endif 1510 break; 1511 case ISD::ADD: 1512 case ISD::MUL: 1513 case ISD::SUB: { 1514 // Add, Sub, and Mul don't demand any bits in positions beyond that 1515 // of the highest bit demanded of them. 1516 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1517 BitWidth - NewMask.countLeadingZeros()); 1518 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1519 KnownOne2, TLO, Depth+1)) 1520 return true; 1521 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1522 KnownOne2, TLO, Depth+1)) 1523 return true; 1524 // See if the operation should be performed at a smaller bit width. 1525 if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1526 return true; 1527 } 1528 // FALL THROUGH 1529 default: 1530 // Just use ComputeMaskedBits to compute output bits. 1531 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1532 break; 1533 } 1534 1535 // If we know the value of all of the demanded bits, return this as a 1536 // constant. 1537 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1538 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1539 1540 return false; 1541} 1542 1543/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1544/// in Mask are known to be either zero or one and return them in the 1545/// KnownZero/KnownOne bitsets. 1546void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1547 const APInt &Mask, 1548 APInt &KnownZero, 1549 APInt &KnownOne, 1550 const SelectionDAG &DAG, 1551 unsigned Depth) const { 1552 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1553 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1554 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1555 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1556 "Should use MaskedValueIsZero if you don't know whether Op" 1557 " is a target node!"); 1558 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1559} 1560 1561/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1562/// targets that want to expose additional information about sign bits to the 1563/// DAG Combiner. 1564unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1565 unsigned Depth) const { 1566 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1567 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1568 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1569 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1570 "Should use ComputeNumSignBits if you don't know whether Op" 1571 " is a target node!"); 1572 return 1; 1573} 1574 1575/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1576/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1577/// determine which bit is set. 1578/// 1579static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1580 // A left-shift of a constant one will have exactly one bit set, because 1581 // shifting the bit off the end is undefined. 1582 if (Val.getOpcode() == ISD::SHL) 1583 if (ConstantSDNode *C = 1584 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1585 if (C->getAPIntValue() == 1) 1586 return true; 1587 1588 // Similarly, a right-shift of a constant sign-bit will have exactly 1589 // one bit set. 1590 if (Val.getOpcode() == ISD::SRL) 1591 if (ConstantSDNode *C = 1592 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1593 if (C->getAPIntValue().isSignBit()) 1594 return true; 1595 1596 // More could be done here, though the above checks are enough 1597 // to handle some common cases. 1598 1599 // Fall back to ComputeMaskedBits to catch other known cases. 1600 EVT OpVT = Val.getValueType(); 1601 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1602 APInt Mask = APInt::getAllOnesValue(BitWidth); 1603 APInt KnownZero, KnownOne; 1604 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1605 return (KnownZero.countPopulation() == BitWidth - 1) && 1606 (KnownOne.countPopulation() == 1); 1607} 1608 1609/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1610/// and cc. If it is unable to simplify it, return a null SDValue. 1611SDValue 1612TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1613 ISD::CondCode Cond, bool foldBooleans, 1614 DAGCombinerInfo &DCI, DebugLoc dl) const { 1615 SelectionDAG &DAG = DCI.DAG; 1616 LLVMContext &Context = *DAG.getContext(); 1617 1618 // These setcc operations always fold. 1619 switch (Cond) { 1620 default: break; 1621 case ISD::SETFALSE: 1622 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1623 case ISD::SETTRUE: 1624 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1625 } 1626 1627 if (isa<ConstantSDNode>(N0.getNode())) { 1628 // Ensure that the constant occurs on the RHS, and fold constant 1629 // comparisons. 1630 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1631 } 1632 1633 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1634 const APInt &C1 = N1C->getAPIntValue(); 1635 1636 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1637 // equality comparison, then we're just comparing whether X itself is 1638 // zero. 1639 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1640 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1641 N0.getOperand(1).getOpcode() == ISD::Constant) { 1642 const APInt &ShAmt 1643 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1644 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1645 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1646 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1647 // (srl (ctlz x), 5) == 0 -> X != 0 1648 // (srl (ctlz x), 5) != 1 -> X != 0 1649 Cond = ISD::SETNE; 1650 } else { 1651 // (srl (ctlz x), 5) != 0 -> X == 0 1652 // (srl (ctlz x), 5) == 1 -> X == 0 1653 Cond = ISD::SETEQ; 1654 } 1655 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1656 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1657 Zero, Cond); 1658 } 1659 } 1660 1661 // If the LHS is '(and load, const)', the RHS is 0, 1662 // the test is for equality or unsigned, and all 1 bits of the const are 1663 // in the same partial word, see if we can shorten the load. 1664 if (DCI.isBeforeLegalize() && 1665 N0.getOpcode() == ISD::AND && C1 == 0 && 1666 N0.getNode()->hasOneUse() && 1667 isa<LoadSDNode>(N0.getOperand(0)) && 1668 N0.getOperand(0).getNode()->hasOneUse() && 1669 isa<ConstantSDNode>(N0.getOperand(1))) { 1670 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1671 APInt bestMask; 1672 unsigned bestWidth = 0, bestOffset = 0; 1673 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1674 unsigned origWidth = N0.getValueType().getSizeInBits(); 1675 unsigned maskWidth = origWidth; 1676 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1677 // 8 bits, but have to be careful... 1678 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1679 origWidth = Lod->getMemoryVT().getSizeInBits(); 1680 const APInt &Mask = 1681 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1682 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1683 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1684 for (unsigned offset=0; offset<origWidth/width; offset++) { 1685 if ((newMask & Mask) == Mask) { 1686 if (!TD->isLittleEndian()) 1687 bestOffset = (origWidth/width - offset - 1) * (width/8); 1688 else 1689 bestOffset = (uint64_t)offset * (width/8); 1690 bestMask = Mask.lshr(offset * (width/8) * 8); 1691 bestWidth = width; 1692 break; 1693 } 1694 newMask = newMask << width; 1695 } 1696 } 1697 } 1698 if (bestWidth) { 1699 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1700 if (newVT.isRound()) { 1701 EVT PtrType = Lod->getOperand(1).getValueType(); 1702 SDValue Ptr = Lod->getBasePtr(); 1703 if (bestOffset != 0) 1704 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1705 DAG.getConstant(bestOffset, PtrType)); 1706 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1707 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1708 Lod->getSrcValue(), 1709 Lod->getSrcValueOffset() + bestOffset, 1710 false, false, NewAlign); 1711 return DAG.getSetCC(dl, VT, 1712 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1713 DAG.getConstant(bestMask.trunc(bestWidth), 1714 newVT)), 1715 DAG.getConstant(0LL, newVT), Cond); 1716 } 1717 } 1718 } 1719 1720 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1721 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1722 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1723 1724 // If the comparison constant has bits in the upper part, the 1725 // zero-extended value could never match. 1726 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1727 C1.getBitWidth() - InSize))) { 1728 switch (Cond) { 1729 case ISD::SETUGT: 1730 case ISD::SETUGE: 1731 case ISD::SETEQ: return DAG.getConstant(0, VT); 1732 case ISD::SETULT: 1733 case ISD::SETULE: 1734 case ISD::SETNE: return DAG.getConstant(1, VT); 1735 case ISD::SETGT: 1736 case ISD::SETGE: 1737 // True if the sign bit of C1 is set. 1738 return DAG.getConstant(C1.isNegative(), VT); 1739 case ISD::SETLT: 1740 case ISD::SETLE: 1741 // True if the sign bit of C1 isn't set. 1742 return DAG.getConstant(C1.isNonNegative(), VT); 1743 default: 1744 break; 1745 } 1746 } 1747 1748 // Otherwise, we can perform the comparison with the low bits. 1749 switch (Cond) { 1750 case ISD::SETEQ: 1751 case ISD::SETNE: 1752 case ISD::SETUGT: 1753 case ISD::SETUGE: 1754 case ISD::SETULT: 1755 case ISD::SETULE: { 1756 EVT newVT = N0.getOperand(0).getValueType(); 1757 if (DCI.isBeforeLegalizeOps() || 1758 (isOperationLegal(ISD::SETCC, newVT) && 1759 getCondCodeAction(Cond, newVT)==Legal)) 1760 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1761 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1762 Cond); 1763 break; 1764 } 1765 default: 1766 break; // todo, be more careful with signed comparisons 1767 } 1768 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1769 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1770 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1771 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1772 EVT ExtDstTy = N0.getValueType(); 1773 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1774 1775 // If the extended part has any inconsistent bits, it cannot ever 1776 // compare equal. In other words, they have to be all ones or all 1777 // zeros. 1778 APInt ExtBits = 1779 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1780 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1781 return DAG.getConstant(Cond == ISD::SETNE, VT); 1782 1783 SDValue ZextOp; 1784 EVT Op0Ty = N0.getOperand(0).getValueType(); 1785 if (Op0Ty == ExtSrcTy) { 1786 ZextOp = N0.getOperand(0); 1787 } else { 1788 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1789 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1790 DAG.getConstant(Imm, Op0Ty)); 1791 } 1792 if (!DCI.isCalledByLegalizer()) 1793 DCI.AddToWorklist(ZextOp.getNode()); 1794 // Otherwise, make this a use of a zext. 1795 return DAG.getSetCC(dl, VT, ZextOp, 1796 DAG.getConstant(C1 & APInt::getLowBitsSet( 1797 ExtDstTyBits, 1798 ExtSrcTyBits), 1799 ExtDstTy), 1800 Cond); 1801 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1802 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1803 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1804 if (N0.getOpcode() == ISD::SETCC && 1805 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1806 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1807 if (TrueWhenTrue) 1808 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1809 // Invert the condition. 1810 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1811 CC = ISD::getSetCCInverse(CC, 1812 N0.getOperand(0).getValueType().isInteger()); 1813 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1814 } 1815 1816 if ((N0.getOpcode() == ISD::XOR || 1817 (N0.getOpcode() == ISD::AND && 1818 N0.getOperand(0).getOpcode() == ISD::XOR && 1819 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1820 isa<ConstantSDNode>(N0.getOperand(1)) && 1821 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1822 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1823 // can only do this if the top bits are known zero. 1824 unsigned BitWidth = N0.getValueSizeInBits(); 1825 if (DAG.MaskedValueIsZero(N0, 1826 APInt::getHighBitsSet(BitWidth, 1827 BitWidth-1))) { 1828 // Okay, get the un-inverted input value. 1829 SDValue Val; 1830 if (N0.getOpcode() == ISD::XOR) 1831 Val = N0.getOperand(0); 1832 else { 1833 assert(N0.getOpcode() == ISD::AND && 1834 N0.getOperand(0).getOpcode() == ISD::XOR); 1835 // ((X^1)&1)^1 -> X & 1 1836 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1837 N0.getOperand(0).getOperand(0), 1838 N0.getOperand(1)); 1839 } 1840 1841 return DAG.getSetCC(dl, VT, Val, N1, 1842 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1843 } 1844 } else if (N1C->getAPIntValue() == 1 && 1845 (VT == MVT::i1 || 1846 getBooleanContents() == ZeroOrOneBooleanContent)) { 1847 SDValue Op0 = N0; 1848 if (Op0.getOpcode() == ISD::TRUNCATE) 1849 Op0 = Op0.getOperand(0); 1850 1851 if ((Op0.getOpcode() == ISD::XOR) && 1852 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1853 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1854 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1855 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1856 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1857 Cond); 1858 } else if (Op0.getOpcode() == ISD::AND && 1859 isa<ConstantSDNode>(Op0.getOperand(1)) && 1860 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1861 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1862 if (Op0.getValueType() != VT) 1863 Op0 = DAG.getNode(ISD::AND, dl, VT, 1864 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1865 DAG.getConstant(1, VT)); 1866 return DAG.getSetCC(dl, VT, Op0, 1867 DAG.getConstant(0, Op0.getValueType()), 1868 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1869 } 1870 } 1871 } 1872 1873 APInt MinVal, MaxVal; 1874 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1875 if (ISD::isSignedIntSetCC(Cond)) { 1876 MinVal = APInt::getSignedMinValue(OperandBitSize); 1877 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1878 } else { 1879 MinVal = APInt::getMinValue(OperandBitSize); 1880 MaxVal = APInt::getMaxValue(OperandBitSize); 1881 } 1882 1883 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1884 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1885 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1886 // X >= C0 --> X > (C0-1) 1887 return DAG.getSetCC(dl, VT, N0, 1888 DAG.getConstant(C1-1, N1.getValueType()), 1889 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1890 } 1891 1892 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1893 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1894 // X <= C0 --> X < (C0+1) 1895 return DAG.getSetCC(dl, VT, N0, 1896 DAG.getConstant(C1+1, N1.getValueType()), 1897 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1898 } 1899 1900 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1901 return DAG.getConstant(0, VT); // X < MIN --> false 1902 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1903 return DAG.getConstant(1, VT); // X >= MIN --> true 1904 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1905 return DAG.getConstant(0, VT); // X > MAX --> false 1906 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1907 return DAG.getConstant(1, VT); // X <= MAX --> true 1908 1909 // Canonicalize setgt X, Min --> setne X, Min 1910 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1911 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1912 // Canonicalize setlt X, Max --> setne X, Max 1913 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1914 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1915 1916 // If we have setult X, 1, turn it into seteq X, 0 1917 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1918 return DAG.getSetCC(dl, VT, N0, 1919 DAG.getConstant(MinVal, N0.getValueType()), 1920 ISD::SETEQ); 1921 // If we have setugt X, Max-1, turn it into seteq X, Max 1922 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1923 return DAG.getSetCC(dl, VT, N0, 1924 DAG.getConstant(MaxVal, N0.getValueType()), 1925 ISD::SETEQ); 1926 1927 // If we have "setcc X, C0", check to see if we can shrink the immediate 1928 // by changing cc. 1929 1930 // SETUGT X, SINTMAX -> SETLT X, 0 1931 if (Cond == ISD::SETUGT && 1932 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1933 return DAG.getSetCC(dl, VT, N0, 1934 DAG.getConstant(0, N1.getValueType()), 1935 ISD::SETLT); 1936 1937 // SETULT X, SINTMIN -> SETGT X, -1 1938 if (Cond == ISD::SETULT && 1939 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1940 SDValue ConstMinusOne = 1941 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1942 N1.getValueType()); 1943 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1944 } 1945 1946 // Fold bit comparisons when we can. 1947 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1948 (VT == N0.getValueType() || 1949 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1950 N0.getOpcode() == ISD::AND) 1951 if (ConstantSDNode *AndRHS = 1952 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1953 EVT ShiftTy = DCI.isBeforeLegalize() ? 1954 getPointerTy() : getShiftAmountTy(); 1955 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1956 // Perform the xform if the AND RHS is a single bit. 1957 if (AndRHS->getAPIntValue().isPowerOf2()) { 1958 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1959 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1960 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1961 } 1962 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1963 // (X & 8) == 8 --> (X & 8) >> 3 1964 // Perform the xform if C1 is a single bit. 1965 if (C1.isPowerOf2()) { 1966 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1967 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1968 DAG.getConstant(C1.logBase2(), ShiftTy))); 1969 } 1970 } 1971 } 1972 } 1973 1974 if (isa<ConstantFPSDNode>(N0.getNode())) { 1975 // Constant fold or commute setcc. 1976 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1977 if (O.getNode()) return O; 1978 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1979 // If the RHS of an FP comparison is a constant, simplify it away in 1980 // some cases. 1981 if (CFP->getValueAPF().isNaN()) { 1982 // If an operand is known to be a nan, we can fold it. 1983 switch (ISD::getUnorderedFlavor(Cond)) { 1984 default: llvm_unreachable("Unknown flavor!"); 1985 case 0: // Known false. 1986 return DAG.getConstant(0, VT); 1987 case 1: // Known true. 1988 return DAG.getConstant(1, VT); 1989 case 2: // Undefined. 1990 return DAG.getUNDEF(VT); 1991 } 1992 } 1993 1994 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1995 // constant if knowing that the operand is non-nan is enough. We prefer to 1996 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1997 // materialize 0.0. 1998 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1999 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2000 2001 // If the condition is not legal, see if we can find an equivalent one 2002 // which is legal. 2003 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2004 // If the comparison was an awkward floating-point == or != and one of 2005 // the comparison operands is infinity or negative infinity, convert the 2006 // condition to a less-awkward <= or >=. 2007 if (CFP->getValueAPF().isInfinity()) { 2008 if (CFP->getValueAPF().isNegative()) { 2009 if (Cond == ISD::SETOEQ && 2010 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2011 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2012 if (Cond == ISD::SETUEQ && 2013 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2014 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2015 if (Cond == ISD::SETUNE && 2016 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2017 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2018 if (Cond == ISD::SETONE && 2019 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2020 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2021 } else { 2022 if (Cond == ISD::SETOEQ && 2023 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2024 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2025 if (Cond == ISD::SETUEQ && 2026 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2027 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2028 if (Cond == ISD::SETUNE && 2029 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2030 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2031 if (Cond == ISD::SETONE && 2032 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2033 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2034 } 2035 } 2036 } 2037 } 2038 2039 if (N0 == N1) { 2040 // We can always fold X == X for integer setcc's. 2041 if (N0.getValueType().isInteger()) 2042 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2043 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2044 if (UOF == 2) // FP operators that are undefined on NaNs. 2045 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2046 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2047 return DAG.getConstant(UOF, VT); 2048 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2049 // if it is not already. 2050 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2051 if (NewCond != Cond) 2052 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2053 } 2054 2055 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2056 N0.getValueType().isInteger()) { 2057 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2058 N0.getOpcode() == ISD::XOR) { 2059 // Simplify (X+Y) == (X+Z) --> Y == Z 2060 if (N0.getOpcode() == N1.getOpcode()) { 2061 if (N0.getOperand(0) == N1.getOperand(0)) 2062 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2063 if (N0.getOperand(1) == N1.getOperand(1)) 2064 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2065 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2066 // If X op Y == Y op X, try other combinations. 2067 if (N0.getOperand(0) == N1.getOperand(1)) 2068 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2069 Cond); 2070 if (N0.getOperand(1) == N1.getOperand(0)) 2071 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2072 Cond); 2073 } 2074 } 2075 2076 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2077 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2078 // Turn (X+C1) == C2 --> X == C2-C1 2079 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2080 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2081 DAG.getConstant(RHSC->getAPIntValue()- 2082 LHSR->getAPIntValue(), 2083 N0.getValueType()), Cond); 2084 } 2085 2086 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2087 if (N0.getOpcode() == ISD::XOR) 2088 // If we know that all of the inverted bits are zero, don't bother 2089 // performing the inversion. 2090 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2091 return 2092 DAG.getSetCC(dl, VT, N0.getOperand(0), 2093 DAG.getConstant(LHSR->getAPIntValue() ^ 2094 RHSC->getAPIntValue(), 2095 N0.getValueType()), 2096 Cond); 2097 } 2098 2099 // Turn (C1-X) == C2 --> X == C1-C2 2100 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2101 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2102 return 2103 DAG.getSetCC(dl, VT, N0.getOperand(1), 2104 DAG.getConstant(SUBC->getAPIntValue() - 2105 RHSC->getAPIntValue(), 2106 N0.getValueType()), 2107 Cond); 2108 } 2109 } 2110 } 2111 2112 // Simplify (X+Z) == X --> Z == 0 2113 if (N0.getOperand(0) == N1) 2114 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2115 DAG.getConstant(0, N0.getValueType()), Cond); 2116 if (N0.getOperand(1) == N1) { 2117 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2118 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2119 DAG.getConstant(0, N0.getValueType()), Cond); 2120 else if (N0.getNode()->hasOneUse()) { 2121 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2122 // (Z-X) == X --> Z == X<<1 2123 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2124 N1, 2125 DAG.getConstant(1, getShiftAmountTy())); 2126 if (!DCI.isCalledByLegalizer()) 2127 DCI.AddToWorklist(SH.getNode()); 2128 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2129 } 2130 } 2131 } 2132 2133 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2134 N1.getOpcode() == ISD::XOR) { 2135 // Simplify X == (X+Z) --> Z == 0 2136 if (N1.getOperand(0) == N0) { 2137 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2138 DAG.getConstant(0, N1.getValueType()), Cond); 2139 } else if (N1.getOperand(1) == N0) { 2140 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2141 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2142 DAG.getConstant(0, N1.getValueType()), Cond); 2143 } else if (N1.getNode()->hasOneUse()) { 2144 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2145 // X == (Z-X) --> X<<1 == Z 2146 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2147 DAG.getConstant(1, getShiftAmountTy())); 2148 if (!DCI.isCalledByLegalizer()) 2149 DCI.AddToWorklist(SH.getNode()); 2150 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2151 } 2152 } 2153 } 2154 2155 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2156 // Note that where y is variable and is known to have at most 2157 // one bit set (for example, if it is z&1) we cannot do this; 2158 // the expressions are not equivalent when y==0. 2159 if (N0.getOpcode() == ISD::AND) 2160 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2161 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2162 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2163 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2164 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2165 } 2166 } 2167 if (N1.getOpcode() == ISD::AND) 2168 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2169 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2170 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2171 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2172 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2173 } 2174 } 2175 } 2176 2177 // Fold away ALL boolean setcc's. 2178 SDValue Temp; 2179 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2180 switch (Cond) { 2181 default: llvm_unreachable("Unknown integer setcc!"); 2182 case ISD::SETEQ: // X == Y -> ~(X^Y) 2183 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2184 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2185 if (!DCI.isCalledByLegalizer()) 2186 DCI.AddToWorklist(Temp.getNode()); 2187 break; 2188 case ISD::SETNE: // X != Y --> (X^Y) 2189 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2190 break; 2191 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2192 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2193 Temp = DAG.getNOT(dl, N0, MVT::i1); 2194 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2195 if (!DCI.isCalledByLegalizer()) 2196 DCI.AddToWorklist(Temp.getNode()); 2197 break; 2198 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2199 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2200 Temp = DAG.getNOT(dl, N1, MVT::i1); 2201 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2202 if (!DCI.isCalledByLegalizer()) 2203 DCI.AddToWorklist(Temp.getNode()); 2204 break; 2205 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2206 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2207 Temp = DAG.getNOT(dl, N0, MVT::i1); 2208 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2209 if (!DCI.isCalledByLegalizer()) 2210 DCI.AddToWorklist(Temp.getNode()); 2211 break; 2212 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2213 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2214 Temp = DAG.getNOT(dl, N1, MVT::i1); 2215 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2216 break; 2217 } 2218 if (VT != MVT::i1) { 2219 if (!DCI.isCalledByLegalizer()) 2220 DCI.AddToWorklist(N0.getNode()); 2221 // FIXME: If running after legalize, we probably can't do this. 2222 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2223 } 2224 return N0; 2225 } 2226 2227 // Could not fold it. 2228 return SDValue(); 2229} 2230 2231/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2232/// node is a GlobalAddress + offset. 2233bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2234 int64_t &Offset) const { 2235 if (isa<GlobalAddressSDNode>(N)) { 2236 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2237 GA = GASD->getGlobal(); 2238 Offset += GASD->getOffset(); 2239 return true; 2240 } 2241 2242 if (N->getOpcode() == ISD::ADD) { 2243 SDValue N1 = N->getOperand(0); 2244 SDValue N2 = N->getOperand(1); 2245 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2246 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2247 if (V) { 2248 Offset += V->getSExtValue(); 2249 return true; 2250 } 2251 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2252 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2253 if (V) { 2254 Offset += V->getSExtValue(); 2255 return true; 2256 } 2257 } 2258 } 2259 return false; 2260} 2261 2262 2263SDValue TargetLowering:: 2264PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2265 // Default implementation: no optimization. 2266 return SDValue(); 2267} 2268 2269//===----------------------------------------------------------------------===// 2270// Inline Assembler Implementation Methods 2271//===----------------------------------------------------------------------===// 2272 2273 2274TargetLowering::ConstraintType 2275TargetLowering::getConstraintType(const std::string &Constraint) const { 2276 // FIXME: lots more standard ones to handle. 2277 if (Constraint.size() == 1) { 2278 switch (Constraint[0]) { 2279 default: break; 2280 case 'r': return C_RegisterClass; 2281 case 'm': // memory 2282 case 'o': // offsetable 2283 case 'V': // not offsetable 2284 return C_Memory; 2285 case 'i': // Simple Integer or Relocatable Constant 2286 case 'n': // Simple Integer 2287 case 's': // Relocatable Constant 2288 case 'X': // Allow ANY value. 2289 case 'I': // Target registers. 2290 case 'J': 2291 case 'K': 2292 case 'L': 2293 case 'M': 2294 case 'N': 2295 case 'O': 2296 case 'P': 2297 return C_Other; 2298 } 2299 } 2300 2301 if (Constraint.size() > 1 && Constraint[0] == '{' && 2302 Constraint[Constraint.size()-1] == '}') 2303 return C_Register; 2304 return C_Unknown; 2305} 2306 2307/// LowerXConstraint - try to replace an X constraint, which matches anything, 2308/// with another that has more specific requirements based on the type of the 2309/// corresponding operand. 2310const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2311 if (ConstraintVT.isInteger()) 2312 return "r"; 2313 if (ConstraintVT.isFloatingPoint()) 2314 return "f"; // works for many targets 2315 return 0; 2316} 2317 2318/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2319/// vector. If it is invalid, don't add anything to Ops. 2320void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2321 char ConstraintLetter, 2322 bool hasMemory, 2323 std::vector<SDValue> &Ops, 2324 SelectionDAG &DAG) const { 2325 switch (ConstraintLetter) { 2326 default: break; 2327 case 'X': // Allows any operand; labels (basic block) use this. 2328 if (Op.getOpcode() == ISD::BasicBlock) { 2329 Ops.push_back(Op); 2330 return; 2331 } 2332 // fall through 2333 case 'i': // Simple Integer or Relocatable Constant 2334 case 'n': // Simple Integer 2335 case 's': { // Relocatable Constant 2336 // These operands are interested in values of the form (GV+C), where C may 2337 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2338 // is possible and fine if either GV or C are missing. 2339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2340 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2341 2342 // If we have "(add GV, C)", pull out GV/C 2343 if (Op.getOpcode() == ISD::ADD) { 2344 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2345 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2346 if (C == 0 || GA == 0) { 2347 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2348 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2349 } 2350 if (C == 0 || GA == 0) 2351 C = 0, GA = 0; 2352 } 2353 2354 // If we find a valid operand, map to the TargetXXX version so that the 2355 // value itself doesn't get selected. 2356 if (GA) { // Either &GV or &GV+C 2357 if (ConstraintLetter != 'n') { 2358 int64_t Offs = GA->getOffset(); 2359 if (C) Offs += C->getZExtValue(); 2360 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2361 Op.getValueType(), Offs)); 2362 return; 2363 } 2364 } 2365 if (C) { // just C, no GV. 2366 // Simple constants are not allowed for 's'. 2367 if (ConstraintLetter != 's') { 2368 // gcc prints these as sign extended. Sign extend value to 64 bits 2369 // now; without this it would get ZExt'd later in 2370 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2371 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2372 MVT::i64)); 2373 return; 2374 } 2375 } 2376 break; 2377 } 2378 } 2379} 2380 2381std::vector<unsigned> TargetLowering:: 2382getRegClassForInlineAsmConstraint(const std::string &Constraint, 2383 EVT VT) const { 2384 return std::vector<unsigned>(); 2385} 2386 2387 2388std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2389getRegForInlineAsmConstraint(const std::string &Constraint, 2390 EVT VT) const { 2391 if (Constraint[0] != '{') 2392 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2393 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2394 2395 // Remove the braces from around the name. 2396 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2397 2398 // Figure out which register class contains this reg. 2399 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2400 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2401 E = RI->regclass_end(); RCI != E; ++RCI) { 2402 const TargetRegisterClass *RC = *RCI; 2403 2404 // If none of the value types for this register class are valid, we 2405 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2406 bool isLegal = false; 2407 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2408 I != E; ++I) { 2409 if (isTypeLegal(*I)) { 2410 isLegal = true; 2411 break; 2412 } 2413 } 2414 2415 if (!isLegal) continue; 2416 2417 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2418 I != E; ++I) { 2419 if (RegName.equals_lower(RI->getName(*I))) 2420 return std::make_pair(*I, RC); 2421 } 2422 } 2423 2424 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2425} 2426 2427//===----------------------------------------------------------------------===// 2428// Constraint Selection. 2429 2430/// isMatchingInputConstraint - Return true of this is an input operand that is 2431/// a matching constraint like "4". 2432bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2433 assert(!ConstraintCode.empty() && "No known constraint!"); 2434 return isdigit(ConstraintCode[0]); 2435} 2436 2437/// getMatchedOperand - If this is an input matching constraint, this method 2438/// returns the output operand it matches. 2439unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2440 assert(!ConstraintCode.empty() && "No known constraint!"); 2441 return atoi(ConstraintCode.c_str()); 2442} 2443 2444 2445/// getConstraintGenerality - Return an integer indicating how general CT 2446/// is. 2447static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2448 switch (CT) { 2449 default: llvm_unreachable("Unknown constraint type!"); 2450 case TargetLowering::C_Other: 2451 case TargetLowering::C_Unknown: 2452 return 0; 2453 case TargetLowering::C_Register: 2454 return 1; 2455 case TargetLowering::C_RegisterClass: 2456 return 2; 2457 case TargetLowering::C_Memory: 2458 return 3; 2459 } 2460} 2461 2462/// ChooseConstraint - If there are multiple different constraints that we 2463/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2464/// This is somewhat tricky: constraints fall into four classes: 2465/// Other -> immediates and magic values 2466/// Register -> one specific register 2467/// RegisterClass -> a group of regs 2468/// Memory -> memory 2469/// Ideally, we would pick the most specific constraint possible: if we have 2470/// something that fits into a register, we would pick it. The problem here 2471/// is that if we have something that could either be in a register or in 2472/// memory that use of the register could cause selection of *other* 2473/// operands to fail: they might only succeed if we pick memory. Because of 2474/// this the heuristic we use is: 2475/// 2476/// 1) If there is an 'other' constraint, and if the operand is valid for 2477/// that constraint, use it. This makes us take advantage of 'i' 2478/// constraints when available. 2479/// 2) Otherwise, pick the most general constraint present. This prefers 2480/// 'm' over 'r', for example. 2481/// 2482static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2483 bool hasMemory, const TargetLowering &TLI, 2484 SDValue Op, SelectionDAG *DAG) { 2485 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2486 unsigned BestIdx = 0; 2487 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2488 int BestGenerality = -1; 2489 2490 // Loop over the options, keeping track of the most general one. 2491 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2492 TargetLowering::ConstraintType CType = 2493 TLI.getConstraintType(OpInfo.Codes[i]); 2494 2495 // If this is an 'other' constraint, see if the operand is valid for it. 2496 // For example, on X86 we might have an 'rI' constraint. If the operand 2497 // is an integer in the range [0..31] we want to use I (saving a load 2498 // of a register), otherwise we must use 'r'. 2499 if (CType == TargetLowering::C_Other && Op.getNode()) { 2500 assert(OpInfo.Codes[i].size() == 1 && 2501 "Unhandled multi-letter 'other' constraint"); 2502 std::vector<SDValue> ResultOps; 2503 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2504 ResultOps, *DAG); 2505 if (!ResultOps.empty()) { 2506 BestType = CType; 2507 BestIdx = i; 2508 break; 2509 } 2510 } 2511 2512 // This constraint letter is more general than the previous one, use it. 2513 int Generality = getConstraintGenerality(CType); 2514 if (Generality > BestGenerality) { 2515 BestType = CType; 2516 BestIdx = i; 2517 BestGenerality = Generality; 2518 } 2519 } 2520 2521 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2522 OpInfo.ConstraintType = BestType; 2523} 2524 2525/// ComputeConstraintToUse - Determines the constraint code and constraint 2526/// type to use for the specific AsmOperandInfo, setting 2527/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2528void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2529 SDValue Op, 2530 bool hasMemory, 2531 SelectionDAG *DAG) const { 2532 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2533 2534 // Single-letter constraints ('r') are very common. 2535 if (OpInfo.Codes.size() == 1) { 2536 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2537 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2538 } else { 2539 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2540 } 2541 2542 // 'X' matches anything. 2543 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2544 // Labels and constants are handled elsewhere ('X' is the only thing 2545 // that matches labels). For Functions, the type here is the type of 2546 // the result, which is not what we want to look at; leave them alone. 2547 Value *v = OpInfo.CallOperandVal; 2548 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2549 OpInfo.CallOperandVal = v; 2550 return; 2551 } 2552 2553 // Otherwise, try to resolve it to something we know about by looking at 2554 // the actual operand type. 2555 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2556 OpInfo.ConstraintCode = Repl; 2557 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2558 } 2559 } 2560} 2561 2562//===----------------------------------------------------------------------===// 2563// Loop Strength Reduction hooks 2564//===----------------------------------------------------------------------===// 2565 2566/// isLegalAddressingMode - Return true if the addressing mode represented 2567/// by AM is legal for this target, for a load/store of the specified type. 2568bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2569 const Type *Ty) const { 2570 // The default implementation of this implements a conservative RISCy, r+r and 2571 // r+i addr mode. 2572 2573 // Allows a sign-extended 16-bit immediate field. 2574 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2575 return false; 2576 2577 // No global is ever allowed as a base. 2578 if (AM.BaseGV) 2579 return false; 2580 2581 // Only support r+r, 2582 switch (AM.Scale) { 2583 case 0: // "r+i" or just "i", depending on HasBaseReg. 2584 break; 2585 case 1: 2586 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2587 return false; 2588 // Otherwise we have r+r or r+i. 2589 break; 2590 case 2: 2591 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2592 return false; 2593 // Allow 2*r as r+r. 2594 break; 2595 } 2596 2597 return true; 2598} 2599 2600/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2601/// return a DAG expression to select that will generate the same value by 2602/// multiplying by a magic number. See: 2603/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2604SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2605 std::vector<SDNode*>* Created) const { 2606 EVT VT = N->getValueType(0); 2607 DebugLoc dl= N->getDebugLoc(); 2608 2609 // Check to see if we can do this. 2610 // FIXME: We should be more aggressive here. 2611 if (!isTypeLegal(VT)) 2612 return SDValue(); 2613 2614 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2615 APInt::ms magics = d.magic(); 2616 2617 // Multiply the numerator (operand 0) by the magic value 2618 // FIXME: We should support doing a MUL in a wider type 2619 SDValue Q; 2620 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2621 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2622 DAG.getConstant(magics.m, VT)); 2623 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2624 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2625 N->getOperand(0), 2626 DAG.getConstant(magics.m, VT)).getNode(), 1); 2627 else 2628 return SDValue(); // No mulhs or equvialent 2629 // If d > 0 and m < 0, add the numerator 2630 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2631 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2632 if (Created) 2633 Created->push_back(Q.getNode()); 2634 } 2635 // If d < 0 and m > 0, subtract the numerator. 2636 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2637 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2638 if (Created) 2639 Created->push_back(Q.getNode()); 2640 } 2641 // Shift right algebraic if shift value is nonzero 2642 if (magics.s > 0) { 2643 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2644 DAG.getConstant(magics.s, getShiftAmountTy())); 2645 if (Created) 2646 Created->push_back(Q.getNode()); 2647 } 2648 // Extract the sign bit and add it to the quotient 2649 SDValue T = 2650 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2651 getShiftAmountTy())); 2652 if (Created) 2653 Created->push_back(T.getNode()); 2654 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2655} 2656 2657/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2658/// return a DAG expression to select that will generate the same value by 2659/// multiplying by a magic number. See: 2660/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2661SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2662 std::vector<SDNode*>* Created) const { 2663 EVT VT = N->getValueType(0); 2664 DebugLoc dl = N->getDebugLoc(); 2665 2666 // Check to see if we can do this. 2667 // FIXME: We should be more aggressive here. 2668 if (!isTypeLegal(VT)) 2669 return SDValue(); 2670 2671 // FIXME: We should use a narrower constant when the upper 2672 // bits are known to be zero. 2673 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2674 APInt::mu magics = N1C->getAPIntValue().magicu(); 2675 2676 // Multiply the numerator (operand 0) by the magic value 2677 // FIXME: We should support doing a MUL in a wider type 2678 SDValue Q; 2679 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2680 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2681 DAG.getConstant(magics.m, VT)); 2682 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2683 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2684 N->getOperand(0), 2685 DAG.getConstant(magics.m, VT)).getNode(), 1); 2686 else 2687 return SDValue(); // No mulhu or equvialent 2688 if (Created) 2689 Created->push_back(Q.getNode()); 2690 2691 if (magics.a == 0) { 2692 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2693 "We shouldn't generate an undefined shift!"); 2694 return DAG.getNode(ISD::SRL, dl, VT, Q, 2695 DAG.getConstant(magics.s, getShiftAmountTy())); 2696 } else { 2697 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2698 if (Created) 2699 Created->push_back(NPQ.getNode()); 2700 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2701 DAG.getConstant(1, getShiftAmountTy())); 2702 if (Created) 2703 Created->push_back(NPQ.getNode()); 2704 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2705 if (Created) 2706 Created->push_back(NPQ.getNode()); 2707 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2708 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2709 } 2710} 2711