TargetLowering.cpp revision 970755e5197afb42a76a24a74cd6dc17721daf50 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/DataLayout.h"
18#include "llvm/Target/TargetLoweringObjectFile.h"
19#include "llvm/Target/TargetMachine.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/Analysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/ADT/BitVector.h"
29#include "llvm/ADT/STLExtras.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/MathExtras.h"
33#include <cctype>
34using namespace llvm;
35
36/// InitLibcallNames - Set default libcall names.
37///
38static void InitLibcallNames(const char **Names) {
39  Names[RTLIB::SHL_I16] = "__ashlhi3";
40  Names[RTLIB::SHL_I32] = "__ashlsi3";
41  Names[RTLIB::SHL_I64] = "__ashldi3";
42  Names[RTLIB::SHL_I128] = "__ashlti3";
43  Names[RTLIB::SRL_I16] = "__lshrhi3";
44  Names[RTLIB::SRL_I32] = "__lshrsi3";
45  Names[RTLIB::SRL_I64] = "__lshrdi3";
46  Names[RTLIB::SRL_I128] = "__lshrti3";
47  Names[RTLIB::SRA_I16] = "__ashrhi3";
48  Names[RTLIB::SRA_I32] = "__ashrsi3";
49  Names[RTLIB::SRA_I64] = "__ashrdi3";
50  Names[RTLIB::SRA_I128] = "__ashrti3";
51  Names[RTLIB::MUL_I8] = "__mulqi3";
52  Names[RTLIB::MUL_I16] = "__mulhi3";
53  Names[RTLIB::MUL_I32] = "__mulsi3";
54  Names[RTLIB::MUL_I64] = "__muldi3";
55  Names[RTLIB::MUL_I128] = "__multi3";
56  Names[RTLIB::MULO_I32] = "__mulosi4";
57  Names[RTLIB::MULO_I64] = "__mulodi4";
58  Names[RTLIB::MULO_I128] = "__muloti4";
59  Names[RTLIB::SDIV_I8] = "__divqi3";
60  Names[RTLIB::SDIV_I16] = "__divhi3";
61  Names[RTLIB::SDIV_I32] = "__divsi3";
62  Names[RTLIB::SDIV_I64] = "__divdi3";
63  Names[RTLIB::SDIV_I128] = "__divti3";
64  Names[RTLIB::UDIV_I8] = "__udivqi3";
65  Names[RTLIB::UDIV_I16] = "__udivhi3";
66  Names[RTLIB::UDIV_I32] = "__udivsi3";
67  Names[RTLIB::UDIV_I64] = "__udivdi3";
68  Names[RTLIB::UDIV_I128] = "__udivti3";
69  Names[RTLIB::SREM_I8] = "__modqi3";
70  Names[RTLIB::SREM_I16] = "__modhi3";
71  Names[RTLIB::SREM_I32] = "__modsi3";
72  Names[RTLIB::SREM_I64] = "__moddi3";
73  Names[RTLIB::SREM_I128] = "__modti3";
74  Names[RTLIB::UREM_I8] = "__umodqi3";
75  Names[RTLIB::UREM_I16] = "__umodhi3";
76  Names[RTLIB::UREM_I32] = "__umodsi3";
77  Names[RTLIB::UREM_I64] = "__umoddi3";
78  Names[RTLIB::UREM_I128] = "__umodti3";
79
80  // These are generally not available.
81  Names[RTLIB::SDIVREM_I8] = 0;
82  Names[RTLIB::SDIVREM_I16] = 0;
83  Names[RTLIB::SDIVREM_I32] = 0;
84  Names[RTLIB::SDIVREM_I64] = 0;
85  Names[RTLIB::SDIVREM_I128] = 0;
86  Names[RTLIB::UDIVREM_I8] = 0;
87  Names[RTLIB::UDIVREM_I16] = 0;
88  Names[RTLIB::UDIVREM_I32] = 0;
89  Names[RTLIB::UDIVREM_I64] = 0;
90  Names[RTLIB::UDIVREM_I128] = 0;
91
92  Names[RTLIB::NEG_I32] = "__negsi2";
93  Names[RTLIB::NEG_I64] = "__negdi2";
94  Names[RTLIB::ADD_F32] = "__addsf3";
95  Names[RTLIB::ADD_F64] = "__adddf3";
96  Names[RTLIB::ADD_F80] = "__addxf3";
97  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98  Names[RTLIB::SUB_F32] = "__subsf3";
99  Names[RTLIB::SUB_F64] = "__subdf3";
100  Names[RTLIB::SUB_F80] = "__subxf3";
101  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102  Names[RTLIB::MUL_F32] = "__mulsf3";
103  Names[RTLIB::MUL_F64] = "__muldf3";
104  Names[RTLIB::MUL_F80] = "__mulxf3";
105  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106  Names[RTLIB::DIV_F32] = "__divsf3";
107  Names[RTLIB::DIV_F64] = "__divdf3";
108  Names[RTLIB::DIV_F80] = "__divxf3";
109  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110  Names[RTLIB::REM_F32] = "fmodf";
111  Names[RTLIB::REM_F64] = "fmod";
112  Names[RTLIB::REM_F80] = "fmodl";
113  Names[RTLIB::REM_PPCF128] = "fmodl";
114  Names[RTLIB::FMA_F32] = "fmaf";
115  Names[RTLIB::FMA_F64] = "fma";
116  Names[RTLIB::FMA_F80] = "fmal";
117  Names[RTLIB::FMA_PPCF128] = "fmal";
118  Names[RTLIB::POWI_F32] = "__powisf2";
119  Names[RTLIB::POWI_F64] = "__powidf2";
120  Names[RTLIB::POWI_F80] = "__powixf2";
121  Names[RTLIB::POWI_PPCF128] = "__powitf2";
122  Names[RTLIB::SQRT_F32] = "sqrtf";
123  Names[RTLIB::SQRT_F64] = "sqrt";
124  Names[RTLIB::SQRT_F80] = "sqrtl";
125  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126  Names[RTLIB::LOG_F32] = "logf";
127  Names[RTLIB::LOG_F64] = "log";
128  Names[RTLIB::LOG_F80] = "logl";
129  Names[RTLIB::LOG_PPCF128] = "logl";
130  Names[RTLIB::LOG2_F32] = "log2f";
131  Names[RTLIB::LOG2_F64] = "log2";
132  Names[RTLIB::LOG2_F80] = "log2l";
133  Names[RTLIB::LOG2_PPCF128] = "log2l";
134  Names[RTLIB::LOG10_F32] = "log10f";
135  Names[RTLIB::LOG10_F64] = "log10";
136  Names[RTLIB::LOG10_F80] = "log10l";
137  Names[RTLIB::LOG10_PPCF128] = "log10l";
138  Names[RTLIB::EXP_F32] = "expf";
139  Names[RTLIB::EXP_F64] = "exp";
140  Names[RTLIB::EXP_F80] = "expl";
141  Names[RTLIB::EXP_PPCF128] = "expl";
142  Names[RTLIB::EXP2_F32] = "exp2f";
143  Names[RTLIB::EXP2_F64] = "exp2";
144  Names[RTLIB::EXP2_F80] = "exp2l";
145  Names[RTLIB::EXP2_PPCF128] = "exp2l";
146  Names[RTLIB::SIN_F32] = "sinf";
147  Names[RTLIB::SIN_F64] = "sin";
148  Names[RTLIB::SIN_F80] = "sinl";
149  Names[RTLIB::SIN_PPCF128] = "sinl";
150  Names[RTLIB::COS_F32] = "cosf";
151  Names[RTLIB::COS_F64] = "cos";
152  Names[RTLIB::COS_F80] = "cosl";
153  Names[RTLIB::COS_PPCF128] = "cosl";
154  Names[RTLIB::POW_F32] = "powf";
155  Names[RTLIB::POW_F64] = "pow";
156  Names[RTLIB::POW_F80] = "powl";
157  Names[RTLIB::POW_PPCF128] = "powl";
158  Names[RTLIB::CEIL_F32] = "ceilf";
159  Names[RTLIB::CEIL_F64] = "ceil";
160  Names[RTLIB::CEIL_F80] = "ceill";
161  Names[RTLIB::CEIL_PPCF128] = "ceill";
162  Names[RTLIB::TRUNC_F32] = "truncf";
163  Names[RTLIB::TRUNC_F64] = "trunc";
164  Names[RTLIB::TRUNC_F80] = "truncl";
165  Names[RTLIB::TRUNC_PPCF128] = "truncl";
166  Names[RTLIB::RINT_F32] = "rintf";
167  Names[RTLIB::RINT_F64] = "rint";
168  Names[RTLIB::RINT_F80] = "rintl";
169  Names[RTLIB::RINT_PPCF128] = "rintl";
170  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174  Names[RTLIB::FLOOR_F32] = "floorf";
175  Names[RTLIB::FLOOR_F64] = "floor";
176  Names[RTLIB::FLOOR_F80] = "floorl";
177  Names[RTLIB::FLOOR_PPCF128] = "floorl";
178  Names[RTLIB::COPYSIGN_F32] = "copysignf";
179  Names[RTLIB::COPYSIGN_F64] = "copysign";
180  Names[RTLIB::COPYSIGN_F80] = "copysignl";
181  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246  Names[RTLIB::OEQ_F32] = "__eqsf2";
247  Names[RTLIB::OEQ_F64] = "__eqdf2";
248  Names[RTLIB::UNE_F32] = "__nesf2";
249  Names[RTLIB::UNE_F64] = "__nedf2";
250  Names[RTLIB::OGE_F32] = "__gesf2";
251  Names[RTLIB::OGE_F64] = "__gedf2";
252  Names[RTLIB::OLT_F32] = "__ltsf2";
253  Names[RTLIB::OLT_F64] = "__ltdf2";
254  Names[RTLIB::OLE_F32] = "__lesf2";
255  Names[RTLIB::OLE_F64] = "__ledf2";
256  Names[RTLIB::OGT_F32] = "__gtsf2";
257  Names[RTLIB::OGT_F64] = "__gtdf2";
258  Names[RTLIB::UO_F32] = "__unordsf2";
259  Names[RTLIB::UO_F64] = "__unorddf2";
260  Names[RTLIB::O_F32] = "__unordsf2";
261  Names[RTLIB::O_F64] = "__unorddf2";
262  Names[RTLIB::MEMCPY] = "memcpy";
263  Names[RTLIB::MEMMOVE] = "memmove";
264  Names[RTLIB::MEMSET] = "memset";
265  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
293  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
298}
299
300/// InitLibcallCallingConvs - Set default libcall CallingConvs.
301///
302static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304    CCs[i] = CallingConv::C;
305  }
306}
307
308/// getFPEXT - Return the FPEXT_*_* value for the given types, or
309/// UNKNOWN_LIBCALL if there is none.
310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311  if (OpVT == MVT::f32) {
312    if (RetVT == MVT::f64)
313      return FPEXT_F32_F64;
314  }
315
316  return UNKNOWN_LIBCALL;
317}
318
319/// getFPROUND - Return the FPROUND_*_* value for the given types, or
320/// UNKNOWN_LIBCALL if there is none.
321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322  if (RetVT == MVT::f32) {
323    if (OpVT == MVT::f64)
324      return FPROUND_F64_F32;
325    if (OpVT == MVT::f80)
326      return FPROUND_F80_F32;
327    if (OpVT == MVT::ppcf128)
328      return FPROUND_PPCF128_F32;
329  } else if (RetVT == MVT::f64) {
330    if (OpVT == MVT::f80)
331      return FPROUND_F80_F64;
332    if (OpVT == MVT::ppcf128)
333      return FPROUND_PPCF128_F64;
334  }
335
336  return UNKNOWN_LIBCALL;
337}
338
339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340/// UNKNOWN_LIBCALL if there is none.
341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342  if (OpVT == MVT::f32) {
343    if (RetVT == MVT::i8)
344      return FPTOSINT_F32_I8;
345    if (RetVT == MVT::i16)
346      return FPTOSINT_F32_I16;
347    if (RetVT == MVT::i32)
348      return FPTOSINT_F32_I32;
349    if (RetVT == MVT::i64)
350      return FPTOSINT_F32_I64;
351    if (RetVT == MVT::i128)
352      return FPTOSINT_F32_I128;
353  } else if (OpVT == MVT::f64) {
354    if (RetVT == MVT::i8)
355      return FPTOSINT_F64_I8;
356    if (RetVT == MVT::i16)
357      return FPTOSINT_F64_I16;
358    if (RetVT == MVT::i32)
359      return FPTOSINT_F64_I32;
360    if (RetVT == MVT::i64)
361      return FPTOSINT_F64_I64;
362    if (RetVT == MVT::i128)
363      return FPTOSINT_F64_I128;
364  } else if (OpVT == MVT::f80) {
365    if (RetVT == MVT::i32)
366      return FPTOSINT_F80_I32;
367    if (RetVT == MVT::i64)
368      return FPTOSINT_F80_I64;
369    if (RetVT == MVT::i128)
370      return FPTOSINT_F80_I128;
371  } else if (OpVT == MVT::ppcf128) {
372    if (RetVT == MVT::i32)
373      return FPTOSINT_PPCF128_I32;
374    if (RetVT == MVT::i64)
375      return FPTOSINT_PPCF128_I64;
376    if (RetVT == MVT::i128)
377      return FPTOSINT_PPCF128_I128;
378  }
379  return UNKNOWN_LIBCALL;
380}
381
382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383/// UNKNOWN_LIBCALL if there is none.
384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385  if (OpVT == MVT::f32) {
386    if (RetVT == MVT::i8)
387      return FPTOUINT_F32_I8;
388    if (RetVT == MVT::i16)
389      return FPTOUINT_F32_I16;
390    if (RetVT == MVT::i32)
391      return FPTOUINT_F32_I32;
392    if (RetVT == MVT::i64)
393      return FPTOUINT_F32_I64;
394    if (RetVT == MVT::i128)
395      return FPTOUINT_F32_I128;
396  } else if (OpVT == MVT::f64) {
397    if (RetVT == MVT::i8)
398      return FPTOUINT_F64_I8;
399    if (RetVT == MVT::i16)
400      return FPTOUINT_F64_I16;
401    if (RetVT == MVT::i32)
402      return FPTOUINT_F64_I32;
403    if (RetVT == MVT::i64)
404      return FPTOUINT_F64_I64;
405    if (RetVT == MVT::i128)
406      return FPTOUINT_F64_I128;
407  } else if (OpVT == MVT::f80) {
408    if (RetVT == MVT::i32)
409      return FPTOUINT_F80_I32;
410    if (RetVT == MVT::i64)
411      return FPTOUINT_F80_I64;
412    if (RetVT == MVT::i128)
413      return FPTOUINT_F80_I128;
414  } else if (OpVT == MVT::ppcf128) {
415    if (RetVT == MVT::i32)
416      return FPTOUINT_PPCF128_I32;
417    if (RetVT == MVT::i64)
418      return FPTOUINT_PPCF128_I64;
419    if (RetVT == MVT::i128)
420      return FPTOUINT_PPCF128_I128;
421  }
422  return UNKNOWN_LIBCALL;
423}
424
425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426/// UNKNOWN_LIBCALL if there is none.
427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428  if (OpVT == MVT::i32) {
429    if (RetVT == MVT::f32)
430      return SINTTOFP_I32_F32;
431    else if (RetVT == MVT::f64)
432      return SINTTOFP_I32_F64;
433    else if (RetVT == MVT::f80)
434      return SINTTOFP_I32_F80;
435    else if (RetVT == MVT::ppcf128)
436      return SINTTOFP_I32_PPCF128;
437  } else if (OpVT == MVT::i64) {
438    if (RetVT == MVT::f32)
439      return SINTTOFP_I64_F32;
440    else if (RetVT == MVT::f64)
441      return SINTTOFP_I64_F64;
442    else if (RetVT == MVT::f80)
443      return SINTTOFP_I64_F80;
444    else if (RetVT == MVT::ppcf128)
445      return SINTTOFP_I64_PPCF128;
446  } else if (OpVT == MVT::i128) {
447    if (RetVT == MVT::f32)
448      return SINTTOFP_I128_F32;
449    else if (RetVT == MVT::f64)
450      return SINTTOFP_I128_F64;
451    else if (RetVT == MVT::f80)
452      return SINTTOFP_I128_F80;
453    else if (RetVT == MVT::ppcf128)
454      return SINTTOFP_I128_PPCF128;
455  }
456  return UNKNOWN_LIBCALL;
457}
458
459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460/// UNKNOWN_LIBCALL if there is none.
461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462  if (OpVT == MVT::i32) {
463    if (RetVT == MVT::f32)
464      return UINTTOFP_I32_F32;
465    else if (RetVT == MVT::f64)
466      return UINTTOFP_I32_F64;
467    else if (RetVT == MVT::f80)
468      return UINTTOFP_I32_F80;
469    else if (RetVT == MVT::ppcf128)
470      return UINTTOFP_I32_PPCF128;
471  } else if (OpVT == MVT::i64) {
472    if (RetVT == MVT::f32)
473      return UINTTOFP_I64_F32;
474    else if (RetVT == MVT::f64)
475      return UINTTOFP_I64_F64;
476    else if (RetVT == MVT::f80)
477      return UINTTOFP_I64_F80;
478    else if (RetVT == MVT::ppcf128)
479      return UINTTOFP_I64_PPCF128;
480  } else if (OpVT == MVT::i128) {
481    if (RetVT == MVT::f32)
482      return UINTTOFP_I128_F32;
483    else if (RetVT == MVT::f64)
484      return UINTTOFP_I128_F64;
485    else if (RetVT == MVT::f80)
486      return UINTTOFP_I128_F80;
487    else if (RetVT == MVT::ppcf128)
488      return UINTTOFP_I128_PPCF128;
489  }
490  return UNKNOWN_LIBCALL;
491}
492
493/// InitCmpLibcallCCs - Set default comparison libcall CC.
494///
495static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499  CCs[RTLIB::UNE_F32] = ISD::SETNE;
500  CCs[RTLIB::UNE_F64] = ISD::SETNE;
501  CCs[RTLIB::OGE_F32] = ISD::SETGE;
502  CCs[RTLIB::OGE_F64] = ISD::SETGE;
503  CCs[RTLIB::OLT_F32] = ISD::SETLT;
504  CCs[RTLIB::OLT_F64] = ISD::SETLT;
505  CCs[RTLIB::OLE_F32] = ISD::SETLE;
506  CCs[RTLIB::OLE_F64] = ISD::SETLE;
507  CCs[RTLIB::OGT_F32] = ISD::SETGT;
508  CCs[RTLIB::OGT_F64] = ISD::SETGT;
509  CCs[RTLIB::UO_F32] = ISD::SETNE;
510  CCs[RTLIB::UO_F64] = ISD::SETNE;
511  CCs[RTLIB::O_F32] = ISD::SETEQ;
512  CCs[RTLIB::O_F64] = ISD::SETEQ;
513}
514
515/// NOTE: The constructor takes ownership of TLOF.
516TargetLowering::TargetLowering(const TargetMachine &tm,
517                               const TargetLoweringObjectFile *tlof)
518  : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
519  // All operations default to being supported.
520  memset(OpActions, 0, sizeof(OpActions));
521  memset(LoadExtActions, 0, sizeof(LoadExtActions));
522  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524  memset(CondCodeActions, 0, sizeof(CondCodeActions));
525
526  // Set default actions for various operations.
527  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528    // Default all indexed load / store to expand.
529    for (unsigned IM = (unsigned)ISD::PRE_INC;
530         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
533    }
534
535    // These operations default to expand.
536    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
538  }
539
540  // Most targets ignore the @llvm.prefetch intrinsic.
541  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
542
543  // ConstantFP nodes default to expand.  Targets can either change this to
544  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545  // to optimize expansions for certain constants.
546  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
547  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
550
551  // These library functions default to expand.
552  setOperationAction(ISD::FLOG ,  MVT::f16, Expand);
553  setOperationAction(ISD::FLOG2,  MVT::f16, Expand);
554  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555  setOperationAction(ISD::FEXP ,  MVT::f16, Expand);
556  setOperationAction(ISD::FEXP2,  MVT::f16, Expand);
557  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559  setOperationAction(ISD::FCEIL,  MVT::f16, Expand);
560  setOperationAction(ISD::FRINT,  MVT::f16, Expand);
561  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
562  setOperationAction(ISD::FLOG ,  MVT::f32, Expand);
563  setOperationAction(ISD::FLOG2,  MVT::f32, Expand);
564  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565  setOperationAction(ISD::FEXP ,  MVT::f32, Expand);
566  setOperationAction(ISD::FEXP2,  MVT::f32, Expand);
567  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569  setOperationAction(ISD::FCEIL,  MVT::f32, Expand);
570  setOperationAction(ISD::FRINT,  MVT::f32, Expand);
571  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
572  setOperationAction(ISD::FLOG ,  MVT::f64, Expand);
573  setOperationAction(ISD::FLOG2,  MVT::f64, Expand);
574  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575  setOperationAction(ISD::FEXP ,  MVT::f64, Expand);
576  setOperationAction(ISD::FEXP2,  MVT::f64, Expand);
577  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579  setOperationAction(ISD::FCEIL,  MVT::f64, Expand);
580  setOperationAction(ISD::FRINT,  MVT::f64, Expand);
581  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
582
583  // Default ISD::TRAP to expand (which turns it into abort).
584  setOperationAction(ISD::TRAP, MVT::Other, Expand);
585
586  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
587  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
588  //
589  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
590
591  IsLittleEndian = TD->isLittleEndian();
592  PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
593  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
594  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
595  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
596  maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
597    = maxStoresPerMemmoveOptSize = 4;
598  benefitFromCodePlacementOpt = false;
599  UseUnderscoreSetJmp = false;
600  UseUnderscoreLongJmp = false;
601  SelectIsExpensive = false;
602  IntDivIsCheap = false;
603  Pow2DivIsCheap = false;
604  JumpIsExpensive = false;
605  predictableSelectIsExpensive = false;
606  StackPointerRegisterToSaveRestore = 0;
607  ExceptionPointerRegister = 0;
608  ExceptionSelectorRegister = 0;
609  BooleanContents = UndefinedBooleanContent;
610  BooleanVectorContents = UndefinedBooleanContent;
611  SchedPreferenceInfo = Sched::ILP;
612  JumpBufSize = 0;
613  JumpBufAlignment = 0;
614  MinFunctionAlignment = 0;
615  PrefFunctionAlignment = 0;
616  PrefLoopAlignment = 0;
617  MinStackArgumentAlignment = 1;
618  ShouldFoldAtomicFences = false;
619  InsertFencesForAtomic = false;
620  SupportJumpTables = true;
621  MinimumJumpTableEntries = 4;
622
623  InitLibcallNames(LibcallRoutineNames);
624  InitCmpLibcallCCs(CmpLibcallCCs);
625  InitLibcallCallingConvs(LibcallCallingConvs);
626}
627
628TargetLowering::~TargetLowering() {
629  delete &TLOF;
630}
631
632MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
633  return MVT::getIntegerVT(8*TD->getPointerSize(0));
634}
635
636/// canOpTrap - Returns true if the operation can trap for the value type.
637/// VT must be a legal type.
638bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
639  assert(isTypeLegal(VT));
640  switch (Op) {
641  default:
642    return false;
643  case ISD::FDIV:
644  case ISD::FREM:
645  case ISD::SDIV:
646  case ISD::UDIV:
647  case ISD::SREM:
648  case ISD::UREM:
649    return true;
650  }
651}
652
653
654static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
655                                          unsigned &NumIntermediates,
656                                          EVT &RegisterVT,
657                                          TargetLowering *TLI) {
658  // Figure out the right, legal destination reg to copy into.
659  unsigned NumElts = VT.getVectorNumElements();
660  MVT EltTy = VT.getVectorElementType();
661
662  unsigned NumVectorRegs = 1;
663
664  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
665  // could break down into LHS/RHS like LegalizeDAG does.
666  if (!isPowerOf2_32(NumElts)) {
667    NumVectorRegs = NumElts;
668    NumElts = 1;
669  }
670
671  // Divide the input until we get to a supported size.  This will always
672  // end with a scalar if the target doesn't support vectors.
673  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
674    NumElts >>= 1;
675    NumVectorRegs <<= 1;
676  }
677
678  NumIntermediates = NumVectorRegs;
679
680  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
681  if (!TLI->isTypeLegal(NewVT))
682    NewVT = EltTy;
683  IntermediateVT = NewVT;
684
685  unsigned NewVTSize = NewVT.getSizeInBits();
686
687  // Convert sizes such as i33 to i64.
688  if (!isPowerOf2_32(NewVTSize))
689    NewVTSize = NextPowerOf2(NewVTSize);
690
691  EVT DestVT = TLI->getRegisterType(NewVT);
692  RegisterVT = DestVT;
693  if (EVT(DestVT).bitsLT(NewVT))    // Value is expanded, e.g. i64 -> i16.
694    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
695
696  // Otherwise, promotion or legal types use the same number of registers as
697  // the vector decimated to the appropriate level.
698  return NumVectorRegs;
699}
700
701/// isLegalRC - Return true if the value types that can be represented by the
702/// specified register class are all legal.
703bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
704  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
705       I != E; ++I) {
706    if (isTypeLegal(*I))
707      return true;
708  }
709  return false;
710}
711
712/// findRepresentativeClass - Return the largest legal super-reg register class
713/// of the register class for the specified type and its associated "cost".
714std::pair<const TargetRegisterClass*, uint8_t>
715TargetLowering::findRepresentativeClass(EVT VT) const {
716  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
717  const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
718  if (!RC)
719    return std::make_pair(RC, 0);
720
721  // Compute the set of all super-register classes.
722  BitVector SuperRegRC(TRI->getNumRegClasses());
723  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
724    SuperRegRC.setBitsInMask(RCI.getMask());
725
726  // Find the first legal register class with the largest spill size.
727  const TargetRegisterClass *BestRC = RC;
728  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
729    const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
730    // We want the largest possible spill size.
731    if (SuperRC->getSize() <= BestRC->getSize())
732      continue;
733    if (!isLegalRC(SuperRC))
734      continue;
735    BestRC = SuperRC;
736  }
737  return std::make_pair(BestRC, 1);
738}
739
740/// computeRegisterProperties - Once all of the register classes are added,
741/// this allows us to compute derived properties we expose.
742void TargetLowering::computeRegisterProperties() {
743  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
744         "Too many value types for ValueTypeActions to hold!");
745
746  // Everything defaults to needing one register.
747  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
748    NumRegistersForVT[i] = 1;
749    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
750  }
751  // ...except isVoid, which doesn't need any registers.
752  NumRegistersForVT[MVT::isVoid] = 0;
753
754  // Find the largest integer register class.
755  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
756  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
757    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
758
759  // Every integer value type larger than this largest register takes twice as
760  // many registers to represent as the previous ValueType.
761  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
762    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
763    if (!ExpandedVT.isInteger())
764      break;
765    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
766    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
767    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
768    ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
769  }
770
771  // Inspect all of the ValueType's smaller than the largest integer
772  // register to see which ones need promotion.
773  unsigned LegalIntReg = LargestIntReg;
774  for (unsigned IntReg = LargestIntReg - 1;
775       IntReg >= (unsigned)MVT::i1; --IntReg) {
776    EVT IVT = (MVT::SimpleValueType)IntReg;
777    if (isTypeLegal(IVT)) {
778      LegalIntReg = IntReg;
779    } else {
780      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
781        (const MVT::SimpleValueType)LegalIntReg;
782      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
783    }
784  }
785
786  // ppcf128 type is really two f64's.
787  if (!isTypeLegal(MVT::ppcf128)) {
788    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
789    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
790    TransformToType[MVT::ppcf128] = MVT::f64;
791    ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
792  }
793
794  // Decide how to handle f64. If the target does not have native f64 support,
795  // expand it to i64 and we will be generating soft float library calls.
796  if (!isTypeLegal(MVT::f64)) {
797    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
798    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
799    TransformToType[MVT::f64] = MVT::i64;
800    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
801  }
802
803  // Decide how to handle f32. If the target does not have native support for
804  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
805  if (!isTypeLegal(MVT::f32)) {
806    if (isTypeLegal(MVT::f64)) {
807      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
808      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
809      TransformToType[MVT::f32] = MVT::f64;
810      ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
811    } else {
812      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
813      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
814      TransformToType[MVT::f32] = MVT::i32;
815      ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
816    }
817  }
818
819  // Loop over all of the vector value types to see which need transformations.
820  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
821       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
822    MVT VT = (MVT::SimpleValueType)i;
823    if (isTypeLegal(VT)) continue;
824
825    // Determine if there is a legal wider type.  If so, we should promote to
826    // that wider vector type.
827    EVT EltVT = VT.getVectorElementType();
828    unsigned NElts = VT.getVectorNumElements();
829    if (NElts != 1) {
830      bool IsLegalWiderType = false;
831      // First try to promote the elements of integer vectors. If no legal
832      // promotion was found, fallback to the widen-vector method.
833      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
834        EVT SVT = (MVT::SimpleValueType)nVT;
835        // Promote vectors of integers to vectors with the same number
836        // of elements, with a wider element type.
837        if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
838            && SVT.getVectorNumElements() == NElts &&
839            isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
840          TransformToType[i] = SVT;
841          RegisterTypeForVT[i] = SVT;
842          NumRegistersForVT[i] = 1;
843          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
844          IsLegalWiderType = true;
845          break;
846        }
847      }
848
849      if (IsLegalWiderType) continue;
850
851      // Try to widen the vector.
852      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
853        EVT SVT = (MVT::SimpleValueType)nVT;
854        if (SVT.getVectorElementType() == EltVT &&
855            SVT.getVectorNumElements() > NElts &&
856            isTypeLegal(SVT)) {
857          TransformToType[i] = SVT;
858          RegisterTypeForVT[i] = SVT;
859          NumRegistersForVT[i] = 1;
860          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
861          IsLegalWiderType = true;
862          break;
863        }
864      }
865      if (IsLegalWiderType) continue;
866    }
867
868    MVT IntermediateVT;
869    EVT RegisterVT;
870    unsigned NumIntermediates;
871    NumRegistersForVT[i] =
872      getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
873                                RegisterVT, this);
874    RegisterTypeForVT[i] = RegisterVT;
875
876    EVT NVT = VT.getPow2VectorType();
877    if (NVT == VT) {
878      // Type is already a power of 2.  The default action is to split.
879      TransformToType[i] = MVT::Other;
880      unsigned NumElts = VT.getVectorNumElements();
881      ValueTypeActions.setTypeAction(VT,
882            NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
883    } else {
884      TransformToType[i] = NVT;
885      ValueTypeActions.setTypeAction(VT, TypeWidenVector);
886    }
887  }
888
889  // Determine the 'representative' register class for each value type.
890  // An representative register class is the largest (meaning one which is
891  // not a sub-register class / subreg register class) legal register class for
892  // a group of value types. For example, on i386, i8, i16, and i32
893  // representative would be GR32; while on x86_64 it's GR64.
894  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
895    const TargetRegisterClass* RRC;
896    uint8_t Cost;
897    tie(RRC, Cost) =  findRepresentativeClass((MVT::SimpleValueType)i);
898    RepRegClassForVT[i] = RRC;
899    RepRegClassCostForVT[i] = Cost;
900  }
901}
902
903const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
904  return NULL;
905}
906
907EVT TargetLowering::getSetCCResultType(EVT VT) const {
908  assert(!VT.isVector() && "No default SetCC type for vectors!");
909  return getPointerTy(0).SimpleTy;
910}
911
912MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
913  return MVT::i32; // return the default value
914}
915
916/// getVectorTypeBreakdown - Vector types are broken down into some number of
917/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
918/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
919/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
920///
921/// This method returns the number of registers needed, and the VT for each
922/// register.  It also returns the VT and quantity of the intermediate values
923/// before they are promoted/expanded.
924///
925unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
926                                                EVT &IntermediateVT,
927                                                unsigned &NumIntermediates,
928                                                EVT &RegisterVT) const {
929  unsigned NumElts = VT.getVectorNumElements();
930
931  // If there is a wider vector type with the same element type as this one,
932  // or a promoted vector type that has the same number of elements which
933  // are wider, then we should convert to that legal vector type.
934  // This handles things like <2 x float> -> <4 x float> and
935  // <4 x i1> -> <4 x i32>.
936  LegalizeTypeAction TA = getTypeAction(Context, VT);
937  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
938    RegisterVT = getTypeToTransformTo(Context, VT);
939    if (isTypeLegal(RegisterVT)) {
940      IntermediateVT = RegisterVT;
941      NumIntermediates = 1;
942      return 1;
943    }
944  }
945
946  // Figure out the right, legal destination reg to copy into.
947  EVT EltTy = VT.getVectorElementType();
948
949  unsigned NumVectorRegs = 1;
950
951  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
952  // could break down into LHS/RHS like LegalizeDAG does.
953  if (!isPowerOf2_32(NumElts)) {
954    NumVectorRegs = NumElts;
955    NumElts = 1;
956  }
957
958  // Divide the input until we get to a supported size.  This will always
959  // end with a scalar if the target doesn't support vectors.
960  while (NumElts > 1 && !isTypeLegal(
961                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
962    NumElts >>= 1;
963    NumVectorRegs <<= 1;
964  }
965
966  NumIntermediates = NumVectorRegs;
967
968  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
969  if (!isTypeLegal(NewVT))
970    NewVT = EltTy;
971  IntermediateVT = NewVT;
972
973  EVT DestVT = getRegisterType(Context, NewVT);
974  RegisterVT = DestVT;
975  unsigned NewVTSize = NewVT.getSizeInBits();
976
977  // Convert sizes such as i33 to i64.
978  if (!isPowerOf2_32(NewVTSize))
979    NewVTSize = NextPowerOf2(NewVTSize);
980
981  if (DestVT.bitsLT(NewVT))   // Value is expanded, e.g. i64 -> i16.
982    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
983
984  // Otherwise, promotion or legal types use the same number of registers as
985  // the vector decimated to the appropriate level.
986  return NumVectorRegs;
987}
988
989/// Get the EVTs and ArgFlags collections that represent the legalized return
990/// type of the given function.  This does not require a DAG or a return value,
991/// and is suitable for use before any DAGs for the function are constructed.
992/// TODO: Move this out of TargetLowering.cpp.
993void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
994                         SmallVectorImpl<ISD::OutputArg> &Outs,
995                         const TargetLowering &TLI) {
996  SmallVector<EVT, 4> ValueVTs;
997  ComputeValueVTs(TLI, ReturnType, ValueVTs);
998  unsigned NumValues = ValueVTs.size();
999  if (NumValues == 0) return;
1000
1001  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1002    EVT VT = ValueVTs[j];
1003    ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1004
1005    if (attr.hasAttribute(Attributes::SExt))
1006      ExtendKind = ISD::SIGN_EXTEND;
1007    else if (attr.hasAttribute(Attributes::ZExt))
1008      ExtendKind = ISD::ZERO_EXTEND;
1009
1010    // FIXME: C calling convention requires the return type to be promoted to
1011    // at least 32-bit. But this is not necessary for non-C calling
1012    // conventions. The frontend should mark functions whose return values
1013    // require promoting with signext or zeroext attributes.
1014    if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1015      EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1016      if (VT.bitsLT(MinVT))
1017        VT = MinVT;
1018    }
1019
1020    unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1021    EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1022
1023    // 'inreg' on function refers to return value
1024    ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1025    if (attr.hasAttribute(Attributes::InReg))
1026      Flags.setInReg();
1027
1028    // Propagate extension type if any
1029    if (attr.hasAttribute(Attributes::SExt))
1030      Flags.setSExt();
1031    else if (attr.hasAttribute(Attributes::ZExt))
1032      Flags.setZExt();
1033
1034    for (unsigned i = 0; i < NumParts; ++i)
1035      Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1036  }
1037}
1038
1039/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1040/// function arguments in the caller parameter area.  This is the actual
1041/// alignment, not its logarithm.
1042unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1043  return TD->getCallFrameTypeAlignment(Ty);
1044}
1045
1046/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1047/// current function.  The returned value is a member of the
1048/// MachineJumpTableInfo::JTEntryKind enum.
1049unsigned TargetLowering::getJumpTableEncoding() const {
1050  // In non-pic modes, just use the address of a block.
1051  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1052    return MachineJumpTableInfo::EK_BlockAddress;
1053
1054  // In PIC mode, if the target supports a GPRel32 directive, use it.
1055  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1056    return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1057
1058  // Otherwise, use a label difference.
1059  return MachineJumpTableInfo::EK_LabelDifference32;
1060}
1061
1062SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1063                                                 SelectionDAG &DAG) const {
1064  // If our PIC model is GP relative, use the global offset table as the base.
1065  unsigned JTEncoding = getJumpTableEncoding();
1066
1067  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1068      (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1069    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
1070
1071  return Table;
1072}
1073
1074/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1075/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1076/// MCExpr.
1077const MCExpr *
1078TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1079                                             unsigned JTI,MCContext &Ctx) const{
1080  // The normal PIC reloc base is the label at the start of the jump table.
1081  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1082}
1083
1084bool
1085TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1086  // Assume that everything is safe in static mode.
1087  if (getTargetMachine().getRelocationModel() == Reloc::Static)
1088    return true;
1089
1090  // In dynamic-no-pic mode, assume that known defined values are safe.
1091  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1092      GA &&
1093      !GA->getGlobal()->isDeclaration() &&
1094      !GA->getGlobal()->isWeakForLinker())
1095    return true;
1096
1097  // Otherwise assume nothing is safe.
1098  return false;
1099}
1100
1101//===----------------------------------------------------------------------===//
1102//  Optimization Methods
1103//===----------------------------------------------------------------------===//
1104
1105/// ShrinkDemandedConstant - Check to see if the specified operand of the
1106/// specified instruction is a constant integer.  If so, check to see if there
1107/// are any bits set in the constant that are not demanded.  If so, shrink the
1108/// constant and return true.
1109bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1110                                                        const APInt &Demanded) {
1111  DebugLoc dl = Op.getDebugLoc();
1112
1113  // FIXME: ISD::SELECT, ISD::SELECT_CC
1114  switch (Op.getOpcode()) {
1115  default: break;
1116  case ISD::XOR:
1117  case ISD::AND:
1118  case ISD::OR: {
1119    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1120    if (!C) return false;
1121
1122    if (Op.getOpcode() == ISD::XOR &&
1123        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1124      return false;
1125
1126    // if we can expand it to have all bits set, do it
1127    if (C->getAPIntValue().intersects(~Demanded)) {
1128      EVT VT = Op.getValueType();
1129      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1130                                DAG.getConstant(Demanded &
1131                                                C->getAPIntValue(),
1132                                                VT));
1133      return CombineTo(Op, New);
1134    }
1135
1136    break;
1137  }
1138  }
1139
1140  return false;
1141}
1142
1143/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1144/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
1145/// cast, but it could be generalized for targets with other types of
1146/// implicit widening casts.
1147bool
1148TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1149                                                    unsigned BitWidth,
1150                                                    const APInt &Demanded,
1151                                                    DebugLoc dl) {
1152  assert(Op.getNumOperands() == 2 &&
1153         "ShrinkDemandedOp only supports binary operators!");
1154  assert(Op.getNode()->getNumValues() == 1 &&
1155         "ShrinkDemandedOp only supports nodes with one result!");
1156
1157  // Don't do this if the node has another user, which may require the
1158  // full value.
1159  if (!Op.getNode()->hasOneUse())
1160    return false;
1161
1162  // Search for the smallest integer type with free casts to and from
1163  // Op's type. For expedience, just check power-of-2 integer types.
1164  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1165  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1166  if (!isPowerOf2_32(SmallVTBits))
1167    SmallVTBits = NextPowerOf2(SmallVTBits);
1168  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1169    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1170    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1171        TLI.isZExtFree(SmallVT, Op.getValueType())) {
1172      // We found a type with free casts.
1173      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1174                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1175                                          Op.getNode()->getOperand(0)),
1176                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1177                                          Op.getNode()->getOperand(1)));
1178      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1179      return CombineTo(Op, Z);
1180    }
1181  }
1182  return false;
1183}
1184
1185/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
1186/// DemandedMask bits of the result of Op are ever used downstream.  If we can
1187/// use this information to simplify Op, create a new simplified DAG node and
1188/// return true, returning the original and new nodes in Old and New. Otherwise,
1189/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1190/// the expression (used to simplify the caller).  The KnownZero/One bits may
1191/// only be accurate for those bits in the DemandedMask.
1192bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1193                                          const APInt &DemandedMask,
1194                                          APInt &KnownZero,
1195                                          APInt &KnownOne,
1196                                          TargetLoweringOpt &TLO,
1197                                          unsigned Depth) const {
1198  unsigned BitWidth = DemandedMask.getBitWidth();
1199  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1200         "Mask size mismatches value type size!");
1201  APInt NewMask = DemandedMask;
1202  DebugLoc dl = Op.getDebugLoc();
1203
1204  // Don't know anything.
1205  KnownZero = KnownOne = APInt(BitWidth, 0);
1206
1207  // Other users may use these bits.
1208  if (!Op.getNode()->hasOneUse()) {
1209    if (Depth != 0) {
1210      // If not at the root, Just compute the KnownZero/KnownOne bits to
1211      // simplify things downstream.
1212      TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1213      return false;
1214    }
1215    // If this is the root being simplified, allow it to have multiple uses,
1216    // just set the NewMask to all bits.
1217    NewMask = APInt::getAllOnesValue(BitWidth);
1218  } else if (DemandedMask == 0) {
1219    // Not demanding any bits from Op.
1220    if (Op.getOpcode() != ISD::UNDEF)
1221      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1222    return false;
1223  } else if (Depth == 6) {        // Limit search depth.
1224    return false;
1225  }
1226
1227  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1228  switch (Op.getOpcode()) {
1229  case ISD::Constant:
1230    // We know all of the bits for a constant!
1231    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1232    KnownZero = ~KnownOne;
1233    return false;   // Don't fall through, will infinitely loop.
1234  case ISD::AND:
1235    // If the RHS is a constant, check to see if the LHS would be zero without
1236    // using the bits from the RHS.  Below, we use knowledge about the RHS to
1237    // simplify the LHS, here we're using information from the LHS to simplify
1238    // the RHS.
1239    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1240      APInt LHSZero, LHSOne;
1241      // Do not increment Depth here; that can cause an infinite loop.
1242      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1243      // If the LHS already has zeros where RHSC does, this and is dead.
1244      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1245        return TLO.CombineTo(Op, Op.getOperand(0));
1246      // If any of the set bits in the RHS are known zero on the LHS, shrink
1247      // the constant.
1248      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1249        return true;
1250    }
1251
1252    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1253                             KnownOne, TLO, Depth+1))
1254      return true;
1255    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1256    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1257                             KnownZero2, KnownOne2, TLO, Depth+1))
1258      return true;
1259    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1260
1261    // If all of the demanded bits are known one on one side, return the other.
1262    // These bits cannot contribute to the result of the 'and'.
1263    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1264      return TLO.CombineTo(Op, Op.getOperand(0));
1265    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1266      return TLO.CombineTo(Op, Op.getOperand(1));
1267    // If all of the demanded bits in the inputs are known zeros, return zero.
1268    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1269      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1270    // If the RHS is a constant, see if we can simplify it.
1271    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1272      return true;
1273    // If the operation can be done in a smaller type, do so.
1274    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1275      return true;
1276
1277    // Output known-1 bits are only known if set in both the LHS & RHS.
1278    KnownOne &= KnownOne2;
1279    // Output known-0 are known to be clear if zero in either the LHS | RHS.
1280    KnownZero |= KnownZero2;
1281    break;
1282  case ISD::OR:
1283    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1284                             KnownOne, TLO, Depth+1))
1285      return true;
1286    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1287    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1288                             KnownZero2, KnownOne2, TLO, Depth+1))
1289      return true;
1290    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1291
1292    // If all of the demanded bits are known zero on one side, return the other.
1293    // These bits cannot contribute to the result of the 'or'.
1294    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1295      return TLO.CombineTo(Op, Op.getOperand(0));
1296    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1297      return TLO.CombineTo(Op, Op.getOperand(1));
1298    // If all of the potentially set bits on one side are known to be set on
1299    // the other side, just use the 'other' side.
1300    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1301      return TLO.CombineTo(Op, Op.getOperand(0));
1302    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1303      return TLO.CombineTo(Op, Op.getOperand(1));
1304    // If the RHS is a constant, see if we can simplify it.
1305    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1306      return true;
1307    // If the operation can be done in a smaller type, do so.
1308    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1309      return true;
1310
1311    // Output known-0 bits are only known if clear in both the LHS & RHS.
1312    KnownZero &= KnownZero2;
1313    // Output known-1 are known to be set if set in either the LHS | RHS.
1314    KnownOne |= KnownOne2;
1315    break;
1316  case ISD::XOR:
1317    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1318                             KnownOne, TLO, Depth+1))
1319      return true;
1320    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1321    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1322                             KnownOne2, TLO, Depth+1))
1323      return true;
1324    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1325
1326    // If all of the demanded bits are known zero on one side, return the other.
1327    // These bits cannot contribute to the result of the 'xor'.
1328    if ((KnownZero & NewMask) == NewMask)
1329      return TLO.CombineTo(Op, Op.getOperand(0));
1330    if ((KnownZero2 & NewMask) == NewMask)
1331      return TLO.CombineTo(Op, Op.getOperand(1));
1332    // If the operation can be done in a smaller type, do so.
1333    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1334      return true;
1335
1336    // If all of the unknown bits are known to be zero on one side or the other
1337    // (but not both) turn this into an *inclusive* or.
1338    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1339    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1340      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1341                                               Op.getOperand(0),
1342                                               Op.getOperand(1)));
1343
1344    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1345    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1346    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1347    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1348
1349    // If all of the demanded bits on one side are known, and all of the set
1350    // bits on that side are also known to be set on the other side, turn this
1351    // into an AND, as we know the bits will be cleared.
1352    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1353    // NB: it is okay if more bits are known than are requested
1354    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1355      if (KnownOne == KnownOne2) { // set bits are the same on both sides
1356        EVT VT = Op.getValueType();
1357        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1358        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1359                                                 Op.getOperand(0), ANDC));
1360      }
1361    }
1362
1363    // If the RHS is a constant, see if we can simplify it.
1364    // for XOR, we prefer to force bits to 1 if they will make a -1.
1365    // if we can't force bits, try to shrink constant
1366    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1367      APInt Expanded = C->getAPIntValue() | (~NewMask);
1368      // if we can expand it to have all bits set, do it
1369      if (Expanded.isAllOnesValue()) {
1370        if (Expanded != C->getAPIntValue()) {
1371          EVT VT = Op.getValueType();
1372          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1373                                          TLO.DAG.getConstant(Expanded, VT));
1374          return TLO.CombineTo(Op, New);
1375        }
1376        // if it already has all the bits set, nothing to change
1377        // but don't shrink either!
1378      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1379        return true;
1380      }
1381    }
1382
1383    KnownZero = KnownZeroOut;
1384    KnownOne  = KnownOneOut;
1385    break;
1386  case ISD::SELECT:
1387    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1388                             KnownOne, TLO, Depth+1))
1389      return true;
1390    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1391                             KnownOne2, TLO, Depth+1))
1392      return true;
1393    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1394    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1395
1396    // If the operands are constants, see if we can simplify them.
1397    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1398      return true;
1399
1400    // Only known if known in both the LHS and RHS.
1401    KnownOne &= KnownOne2;
1402    KnownZero &= KnownZero2;
1403    break;
1404  case ISD::SELECT_CC:
1405    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1406                             KnownOne, TLO, Depth+1))
1407      return true;
1408    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1409                             KnownOne2, TLO, Depth+1))
1410      return true;
1411    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1412    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1413
1414    // If the operands are constants, see if we can simplify them.
1415    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1416      return true;
1417
1418    // Only known if known in both the LHS and RHS.
1419    KnownOne &= KnownOne2;
1420    KnownZero &= KnownZero2;
1421    break;
1422  case ISD::SHL:
1423    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1424      unsigned ShAmt = SA->getZExtValue();
1425      SDValue InOp = Op.getOperand(0);
1426
1427      // If the shift count is an invalid immediate, don't do anything.
1428      if (ShAmt >= BitWidth)
1429        break;
1430
1431      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1432      // single shift.  We can do this if the bottom bits (which are shifted
1433      // out) are never demanded.
1434      if (InOp.getOpcode() == ISD::SRL &&
1435          isa<ConstantSDNode>(InOp.getOperand(1))) {
1436        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1437          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1438          unsigned Opc = ISD::SHL;
1439          int Diff = ShAmt-C1;
1440          if (Diff < 0) {
1441            Diff = -Diff;
1442            Opc = ISD::SRL;
1443          }
1444
1445          SDValue NewSA =
1446            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1447          EVT VT = Op.getValueType();
1448          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1449                                                   InOp.getOperand(0), NewSA));
1450        }
1451      }
1452
1453      if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1454                               KnownZero, KnownOne, TLO, Depth+1))
1455        return true;
1456
1457      // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1458      // are not demanded. This will likely allow the anyext to be folded away.
1459      if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1460        SDValue InnerOp = InOp.getNode()->getOperand(0);
1461        EVT InnerVT = InnerOp.getValueType();
1462        unsigned InnerBits = InnerVT.getSizeInBits();
1463        if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1464            isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1465          EVT ShTy = getShiftAmountTy(InnerVT);
1466          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1467            ShTy = InnerVT;
1468          SDValue NarrowShl =
1469            TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1470                            TLO.DAG.getConstant(ShAmt, ShTy));
1471          return
1472            TLO.CombineTo(Op,
1473                          TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1474                                          NarrowShl));
1475        }
1476      }
1477
1478      KnownZero <<= SA->getZExtValue();
1479      KnownOne  <<= SA->getZExtValue();
1480      // low bits known zero.
1481      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1482    }
1483    break;
1484  case ISD::SRL:
1485    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1486      EVT VT = Op.getValueType();
1487      unsigned ShAmt = SA->getZExtValue();
1488      unsigned VTSize = VT.getSizeInBits();
1489      SDValue InOp = Op.getOperand(0);
1490
1491      // If the shift count is an invalid immediate, don't do anything.
1492      if (ShAmt >= BitWidth)
1493        break;
1494
1495      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1496      // single shift.  We can do this if the top bits (which are shifted out)
1497      // are never demanded.
1498      if (InOp.getOpcode() == ISD::SHL &&
1499          isa<ConstantSDNode>(InOp.getOperand(1))) {
1500        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1501          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1502          unsigned Opc = ISD::SRL;
1503          int Diff = ShAmt-C1;
1504          if (Diff < 0) {
1505            Diff = -Diff;
1506            Opc = ISD::SHL;
1507          }
1508
1509          SDValue NewSA =
1510            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1511          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1512                                                   InOp.getOperand(0), NewSA));
1513        }
1514      }
1515
1516      // Compute the new bits that are at the top now.
1517      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1518                               KnownZero, KnownOne, TLO, Depth+1))
1519        return true;
1520      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1521      KnownZero = KnownZero.lshr(ShAmt);
1522      KnownOne  = KnownOne.lshr(ShAmt);
1523
1524      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1525      KnownZero |= HighBits;  // High bits known zero.
1526    }
1527    break;
1528  case ISD::SRA:
1529    // If this is an arithmetic shift right and only the low-bit is set, we can
1530    // always convert this into a logical shr, even if the shift amount is
1531    // variable.  The low bit of the shift cannot be an input sign bit unless
1532    // the shift amount is >= the size of the datatype, which is undefined.
1533    if (NewMask == 1)
1534      return TLO.CombineTo(Op,
1535                           TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1536                                           Op.getOperand(0), Op.getOperand(1)));
1537
1538    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1539      EVT VT = Op.getValueType();
1540      unsigned ShAmt = SA->getZExtValue();
1541
1542      // If the shift count is an invalid immediate, don't do anything.
1543      if (ShAmt >= BitWidth)
1544        break;
1545
1546      APInt InDemandedMask = (NewMask << ShAmt);
1547
1548      // If any of the demanded bits are produced by the sign extension, we also
1549      // demand the input sign bit.
1550      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1551      if (HighBits.intersects(NewMask))
1552        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1553
1554      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1555                               KnownZero, KnownOne, TLO, Depth+1))
1556        return true;
1557      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1558      KnownZero = KnownZero.lshr(ShAmt);
1559      KnownOne  = KnownOne.lshr(ShAmt);
1560
1561      // Handle the sign bit, adjusted to where it is now in the mask.
1562      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1563
1564      // If the input sign bit is known to be zero, or if none of the top bits
1565      // are demanded, turn this into an unsigned shift right.
1566      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1567        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1568                                                 Op.getOperand(0),
1569                                                 Op.getOperand(1)));
1570      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1571        KnownOne |= HighBits;
1572      }
1573    }
1574    break;
1575  case ISD::SIGN_EXTEND_INREG: {
1576    EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1577
1578    APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1579    // If we only care about the highest bit, don't bother shifting right.
1580    if (MsbMask == DemandedMask) {
1581      unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1582      SDValue InOp = Op.getOperand(0);
1583
1584      // Compute the correct shift amount type, which must be getShiftAmountTy
1585      // for scalar types after legalization.
1586      EVT ShiftAmtTy = Op.getValueType();
1587      if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1588        ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1589
1590      SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1591      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1592                                            Op.getValueType(), InOp, ShiftAmt));
1593    }
1594
1595    // Sign extension.  Compute the demanded bits in the result that are not
1596    // present in the input.
1597    APInt NewBits =
1598      APInt::getHighBitsSet(BitWidth,
1599                            BitWidth - ExVT.getScalarType().getSizeInBits());
1600
1601    // If none of the extended bits are demanded, eliminate the sextinreg.
1602    if ((NewBits & NewMask) == 0)
1603      return TLO.CombineTo(Op, Op.getOperand(0));
1604
1605    APInt InSignBit =
1606      APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1607    APInt InputDemandedBits =
1608      APInt::getLowBitsSet(BitWidth,
1609                           ExVT.getScalarType().getSizeInBits()) &
1610      NewMask;
1611
1612    // Since the sign extended bits are demanded, we know that the sign
1613    // bit is demanded.
1614    InputDemandedBits |= InSignBit;
1615
1616    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1617                             KnownZero, KnownOne, TLO, Depth+1))
1618      return true;
1619    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1620
1621    // If the sign bit of the input is known set or clear, then we know the
1622    // top bits of the result.
1623
1624    // If the input sign bit is known zero, convert this into a zero extension.
1625    if (KnownZero.intersects(InSignBit))
1626      return TLO.CombineTo(Op,
1627                          TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1628
1629    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1630      KnownOne |= NewBits;
1631      KnownZero &= ~NewBits;
1632    } else {                       // Input sign bit unknown
1633      KnownZero &= ~NewBits;
1634      KnownOne &= ~NewBits;
1635    }
1636    break;
1637  }
1638  case ISD::ZERO_EXTEND: {
1639    unsigned OperandBitWidth =
1640      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1641    APInt InMask = NewMask.trunc(OperandBitWidth);
1642
1643    // If none of the top bits are demanded, convert this into an any_extend.
1644    APInt NewBits =
1645      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1646    if (!NewBits.intersects(NewMask))
1647      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1648                                               Op.getValueType(),
1649                                               Op.getOperand(0)));
1650
1651    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1652                             KnownZero, KnownOne, TLO, Depth+1))
1653      return true;
1654    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1655    KnownZero = KnownZero.zext(BitWidth);
1656    KnownOne = KnownOne.zext(BitWidth);
1657    KnownZero |= NewBits;
1658    break;
1659  }
1660  case ISD::SIGN_EXTEND: {
1661    EVT InVT = Op.getOperand(0).getValueType();
1662    unsigned InBits = InVT.getScalarType().getSizeInBits();
1663    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1664    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1665    APInt NewBits   = ~InMask & NewMask;
1666
1667    // If none of the top bits are demanded, convert this into an any_extend.
1668    if (NewBits == 0)
1669      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1670                                              Op.getValueType(),
1671                                              Op.getOperand(0)));
1672
1673    // Since some of the sign extended bits are demanded, we know that the sign
1674    // bit is demanded.
1675    APInt InDemandedBits = InMask & NewMask;
1676    InDemandedBits |= InSignBit;
1677    InDemandedBits = InDemandedBits.trunc(InBits);
1678
1679    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1680                             KnownOne, TLO, Depth+1))
1681      return true;
1682    KnownZero = KnownZero.zext(BitWidth);
1683    KnownOne = KnownOne.zext(BitWidth);
1684
1685    // If the sign bit is known zero, convert this to a zero extend.
1686    if (KnownZero.intersects(InSignBit))
1687      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1688                                               Op.getValueType(),
1689                                               Op.getOperand(0)));
1690
1691    // If the sign bit is known one, the top bits match.
1692    if (KnownOne.intersects(InSignBit)) {
1693      KnownOne |= NewBits;
1694      assert((KnownZero & NewBits) == 0);
1695    } else {   // Otherwise, top bits aren't known.
1696      assert((KnownOne & NewBits) == 0);
1697      assert((KnownZero & NewBits) == 0);
1698    }
1699    break;
1700  }
1701  case ISD::ANY_EXTEND: {
1702    unsigned OperandBitWidth =
1703      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1704    APInt InMask = NewMask.trunc(OperandBitWidth);
1705    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1706                             KnownZero, KnownOne, TLO, Depth+1))
1707      return true;
1708    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1709    KnownZero = KnownZero.zext(BitWidth);
1710    KnownOne = KnownOne.zext(BitWidth);
1711    break;
1712  }
1713  case ISD::TRUNCATE: {
1714    // Simplify the input, using demanded bit information, and compute the known
1715    // zero/one bits live out.
1716    unsigned OperandBitWidth =
1717      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1718    APInt TruncMask = NewMask.zext(OperandBitWidth);
1719    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1720                             KnownZero, KnownOne, TLO, Depth+1))
1721      return true;
1722    KnownZero = KnownZero.trunc(BitWidth);
1723    KnownOne = KnownOne.trunc(BitWidth);
1724
1725    // If the input is only used by this truncate, see if we can shrink it based
1726    // on the known demanded bits.
1727    if (Op.getOperand(0).getNode()->hasOneUse()) {
1728      SDValue In = Op.getOperand(0);
1729      switch (In.getOpcode()) {
1730      default: break;
1731      case ISD::SRL:
1732        // Shrink SRL by a constant if none of the high bits shifted in are
1733        // demanded.
1734        if (TLO.LegalTypes() &&
1735            !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1736          // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1737          // undesirable.
1738          break;
1739        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1740        if (!ShAmt)
1741          break;
1742        SDValue Shift = In.getOperand(1);
1743        if (TLO.LegalTypes()) {
1744          uint64_t ShVal = ShAmt->getZExtValue();
1745          Shift =
1746            TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1747        }
1748
1749        APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1750                                               OperandBitWidth - BitWidth);
1751        HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1752
1753        if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1754          // None of the shifted in bits are needed.  Add a truncate of the
1755          // shift input, then shift it.
1756          SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1757                                             Op.getValueType(),
1758                                             In.getOperand(0));
1759          return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1760                                                   Op.getValueType(),
1761                                                   NewTrunc,
1762                                                   Shift));
1763        }
1764        break;
1765      }
1766    }
1767
1768    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1769    break;
1770  }
1771  case ISD::AssertZext: {
1772    // AssertZext demands all of the high bits, plus any of the low bits
1773    // demanded by its users.
1774    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1775    APInt InMask = APInt::getLowBitsSet(BitWidth,
1776                                        VT.getSizeInBits());
1777    if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1778                             KnownZero, KnownOne, TLO, Depth+1))
1779      return true;
1780    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1781
1782    KnownZero |= ~InMask & NewMask;
1783    break;
1784  }
1785  case ISD::BITCAST:
1786    // If this is an FP->Int bitcast and if the sign bit is the only
1787    // thing demanded, turn this into a FGETSIGN.
1788    if (!TLO.LegalOperations() &&
1789        !Op.getValueType().isVector() &&
1790        !Op.getOperand(0).getValueType().isVector() &&
1791        NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1792        Op.getOperand(0).getValueType().isFloatingPoint()) {
1793      bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1794      bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1795      if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1796        EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1797        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1798        // place.  We expect the SHL to be eliminated by other optimizations.
1799        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1800        unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1801        if (!OpVTLegal && OpVTSizeInBits > 32)
1802          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1803        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1804        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1805        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1806                                                 Op.getValueType(),
1807                                                 Sign, ShAmt));
1808      }
1809    }
1810    break;
1811  case ISD::ADD:
1812  case ISD::MUL:
1813  case ISD::SUB: {
1814    // Add, Sub, and Mul don't demand any bits in positions beyond that
1815    // of the highest bit demanded of them.
1816    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1817                                        BitWidth - NewMask.countLeadingZeros());
1818    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1819                             KnownOne2, TLO, Depth+1))
1820      return true;
1821    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1822                             KnownOne2, TLO, Depth+1))
1823      return true;
1824    // See if the operation should be performed at a smaller bit width.
1825    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1826      return true;
1827  }
1828  // FALL THROUGH
1829  default:
1830    // Just use ComputeMaskedBits to compute output bits.
1831    TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1832    break;
1833  }
1834
1835  // If we know the value of all of the demanded bits, return this as a
1836  // constant.
1837  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1838    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1839
1840  return false;
1841}
1842
1843/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1844/// in Mask are known to be either zero or one and return them in the
1845/// KnownZero/KnownOne bitsets.
1846void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1847                                                    APInt &KnownZero,
1848                                                    APInt &KnownOne,
1849                                                    const SelectionDAG &DAG,
1850                                                    unsigned Depth) const {
1851  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1852          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1853          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1854          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1855         "Should use MaskedValueIsZero if you don't know whether Op"
1856         " is a target node!");
1857  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1858}
1859
1860/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1861/// targets that want to expose additional information about sign bits to the
1862/// DAG Combiner.
1863unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1864                                                         unsigned Depth) const {
1865  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1866          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1867          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1868          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1869         "Should use ComputeNumSignBits if you don't know whether Op"
1870         " is a target node!");
1871  return 1;
1872}
1873
1874/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1875/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1876/// determine which bit is set.
1877///
1878static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1879  // A left-shift of a constant one will have exactly one bit set, because
1880  // shifting the bit off the end is undefined.
1881  if (Val.getOpcode() == ISD::SHL)
1882    if (ConstantSDNode *C =
1883         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1884      if (C->getAPIntValue() == 1)
1885        return true;
1886
1887  // Similarly, a right-shift of a constant sign-bit will have exactly
1888  // one bit set.
1889  if (Val.getOpcode() == ISD::SRL)
1890    if (ConstantSDNode *C =
1891         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1892      if (C->getAPIntValue().isSignBit())
1893        return true;
1894
1895  // More could be done here, though the above checks are enough
1896  // to handle some common cases.
1897
1898  // Fall back to ComputeMaskedBits to catch other known cases.
1899  EVT OpVT = Val.getValueType();
1900  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1901  APInt KnownZero, KnownOne;
1902  DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1903  return (KnownZero.countPopulation() == BitWidth - 1) &&
1904         (KnownOne.countPopulation() == 1);
1905}
1906
1907/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1908/// and cc. If it is unable to simplify it, return a null SDValue.
1909SDValue
1910TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1911                              ISD::CondCode Cond, bool foldBooleans,
1912                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1913  SelectionDAG &DAG = DCI.DAG;
1914
1915  // These setcc operations always fold.
1916  switch (Cond) {
1917  default: break;
1918  case ISD::SETFALSE:
1919  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1920  case ISD::SETTRUE:
1921  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1922  }
1923
1924  // Ensure that the constant occurs on the RHS, and fold constant
1925  // comparisons.
1926  if (isa<ConstantSDNode>(N0.getNode()))
1927    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1928
1929  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1930    const APInt &C1 = N1C->getAPIntValue();
1931
1932    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1933    // equality comparison, then we're just comparing whether X itself is
1934    // zero.
1935    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1936        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1937        N0.getOperand(1).getOpcode() == ISD::Constant) {
1938      const APInt &ShAmt
1939        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1940      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1941          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1942        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1943          // (srl (ctlz x), 5) == 0  -> X != 0
1944          // (srl (ctlz x), 5) != 1  -> X != 0
1945          Cond = ISD::SETNE;
1946        } else {
1947          // (srl (ctlz x), 5) != 0  -> X == 0
1948          // (srl (ctlz x), 5) == 1  -> X == 0
1949          Cond = ISD::SETEQ;
1950        }
1951        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1952        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1953                            Zero, Cond);
1954      }
1955    }
1956
1957    SDValue CTPOP = N0;
1958    // Look through truncs that don't change the value of a ctpop.
1959    if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1960      CTPOP = N0.getOperand(0);
1961
1962    if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1963        (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1964                        Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1965      EVT CTVT = CTPOP.getValueType();
1966      SDValue CTOp = CTPOP.getOperand(0);
1967
1968      // (ctpop x) u< 2 -> (x & x-1) == 0
1969      // (ctpop x) u> 1 -> (x & x-1) != 0
1970      if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1971        SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1972                                  DAG.getConstant(1, CTVT));
1973        SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1974        ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1975        return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1976      }
1977
1978      // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1979    }
1980
1981    // (zext x) == C --> x == (trunc C)
1982    if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1983        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1984      unsigned MinBits = N0.getValueSizeInBits();
1985      SDValue PreZExt;
1986      if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1987        // ZExt
1988        MinBits = N0->getOperand(0).getValueSizeInBits();
1989        PreZExt = N0->getOperand(0);
1990      } else if (N0->getOpcode() == ISD::AND) {
1991        // DAGCombine turns costly ZExts into ANDs
1992        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1993          if ((C->getAPIntValue()+1).isPowerOf2()) {
1994            MinBits = C->getAPIntValue().countTrailingOnes();
1995            PreZExt = N0->getOperand(0);
1996          }
1997      } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1998        // ZEXTLOAD
1999        if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2000          MinBits = LN0->getMemoryVT().getSizeInBits();
2001          PreZExt = N0;
2002        }
2003      }
2004
2005      // Make sure we're not losing bits from the constant.
2006      if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2007        EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2008        if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2009          // Will get folded away.
2010          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2011          SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2012          return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2013        }
2014      }
2015    }
2016
2017    // If the LHS is '(and load, const)', the RHS is 0,
2018    // the test is for equality or unsigned, and all 1 bits of the const are
2019    // in the same partial word, see if we can shorten the load.
2020    if (DCI.isBeforeLegalize() &&
2021        N0.getOpcode() == ISD::AND && C1 == 0 &&
2022        N0.getNode()->hasOneUse() &&
2023        isa<LoadSDNode>(N0.getOperand(0)) &&
2024        N0.getOperand(0).getNode()->hasOneUse() &&
2025        isa<ConstantSDNode>(N0.getOperand(1))) {
2026      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2027      APInt bestMask;
2028      unsigned bestWidth = 0, bestOffset = 0;
2029      if (!Lod->isVolatile() && Lod->isUnindexed()) {
2030        unsigned origWidth = N0.getValueType().getSizeInBits();
2031        unsigned maskWidth = origWidth;
2032        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2033        // 8 bits, but have to be careful...
2034        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2035          origWidth = Lod->getMemoryVT().getSizeInBits();
2036        const APInt &Mask =
2037          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2038        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2039          APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2040          for (unsigned offset=0; offset<origWidth/width; offset++) {
2041            if ((newMask & Mask) == Mask) {
2042              if (!TD->isLittleEndian())
2043                bestOffset = (origWidth/width - offset - 1) * (width/8);
2044              else
2045                bestOffset = (uint64_t)offset * (width/8);
2046              bestMask = Mask.lshr(offset * (width/8) * 8);
2047              bestWidth = width;
2048              break;
2049            }
2050            newMask = newMask << width;
2051          }
2052        }
2053      }
2054      if (bestWidth) {
2055        EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2056        if (newVT.isRound()) {
2057          EVT PtrType = Lod->getOperand(1).getValueType();
2058          SDValue Ptr = Lod->getBasePtr();
2059          if (bestOffset != 0)
2060            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2061                              DAG.getConstant(bestOffset, PtrType));
2062          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2063          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2064                                Lod->getPointerInfo().getWithOffset(bestOffset),
2065                                        false, false, false, NewAlign);
2066          return DAG.getSetCC(dl, VT,
2067                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2068                                      DAG.getConstant(bestMask.trunc(bestWidth),
2069                                                      newVT)),
2070                              DAG.getConstant(0LL, newVT), Cond);
2071        }
2072      }
2073    }
2074
2075    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2076    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2077      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2078
2079      // If the comparison constant has bits in the upper part, the
2080      // zero-extended value could never match.
2081      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2082                                              C1.getBitWidth() - InSize))) {
2083        switch (Cond) {
2084        case ISD::SETUGT:
2085        case ISD::SETUGE:
2086        case ISD::SETEQ: return DAG.getConstant(0, VT);
2087        case ISD::SETULT:
2088        case ISD::SETULE:
2089        case ISD::SETNE: return DAG.getConstant(1, VT);
2090        case ISD::SETGT:
2091        case ISD::SETGE:
2092          // True if the sign bit of C1 is set.
2093          return DAG.getConstant(C1.isNegative(), VT);
2094        case ISD::SETLT:
2095        case ISD::SETLE:
2096          // True if the sign bit of C1 isn't set.
2097          return DAG.getConstant(C1.isNonNegative(), VT);
2098        default:
2099          break;
2100        }
2101      }
2102
2103      // Otherwise, we can perform the comparison with the low bits.
2104      switch (Cond) {
2105      case ISD::SETEQ:
2106      case ISD::SETNE:
2107      case ISD::SETUGT:
2108      case ISD::SETUGE:
2109      case ISD::SETULT:
2110      case ISD::SETULE: {
2111        EVT newVT = N0.getOperand(0).getValueType();
2112        if (DCI.isBeforeLegalizeOps() ||
2113            (isOperationLegal(ISD::SETCC, newVT) &&
2114              getCondCodeAction(Cond, newVT)==Legal))
2115          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2116                              DAG.getConstant(C1.trunc(InSize), newVT),
2117                              Cond);
2118        break;
2119      }
2120      default:
2121        break;   // todo, be more careful with signed comparisons
2122      }
2123    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2124               (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2125      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2126      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2127      EVT ExtDstTy = N0.getValueType();
2128      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2129
2130      // If the constant doesn't fit into the number of bits for the source of
2131      // the sign extension, it is impossible for both sides to be equal.
2132      if (C1.getMinSignedBits() > ExtSrcTyBits)
2133        return DAG.getConstant(Cond == ISD::SETNE, VT);
2134
2135      SDValue ZextOp;
2136      EVT Op0Ty = N0.getOperand(0).getValueType();
2137      if (Op0Ty == ExtSrcTy) {
2138        ZextOp = N0.getOperand(0);
2139      } else {
2140        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2141        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2142                              DAG.getConstant(Imm, Op0Ty));
2143      }
2144      if (!DCI.isCalledByLegalizer())
2145        DCI.AddToWorklist(ZextOp.getNode());
2146      // Otherwise, make this a use of a zext.
2147      return DAG.getSetCC(dl, VT, ZextOp,
2148                          DAG.getConstant(C1 & APInt::getLowBitsSet(
2149                                                              ExtDstTyBits,
2150                                                              ExtSrcTyBits),
2151                                          ExtDstTy),
2152                          Cond);
2153    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2154                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2155      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2156      if (N0.getOpcode() == ISD::SETCC &&
2157          isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2158        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2159        if (TrueWhenTrue)
2160          return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2161        // Invert the condition.
2162        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2163        CC = ISD::getSetCCInverse(CC,
2164                                  N0.getOperand(0).getValueType().isInteger());
2165        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2166      }
2167
2168      if ((N0.getOpcode() == ISD::XOR ||
2169           (N0.getOpcode() == ISD::AND &&
2170            N0.getOperand(0).getOpcode() == ISD::XOR &&
2171            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2172          isa<ConstantSDNode>(N0.getOperand(1)) &&
2173          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2174        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
2175        // can only do this if the top bits are known zero.
2176        unsigned BitWidth = N0.getValueSizeInBits();
2177        if (DAG.MaskedValueIsZero(N0,
2178                                  APInt::getHighBitsSet(BitWidth,
2179                                                        BitWidth-1))) {
2180          // Okay, get the un-inverted input value.
2181          SDValue Val;
2182          if (N0.getOpcode() == ISD::XOR)
2183            Val = N0.getOperand(0);
2184          else {
2185            assert(N0.getOpcode() == ISD::AND &&
2186                    N0.getOperand(0).getOpcode() == ISD::XOR);
2187            // ((X^1)&1)^1 -> X & 1
2188            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2189                              N0.getOperand(0).getOperand(0),
2190                              N0.getOperand(1));
2191          }
2192
2193          return DAG.getSetCC(dl, VT, Val, N1,
2194                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2195        }
2196      } else if (N1C->getAPIntValue() == 1 &&
2197                 (VT == MVT::i1 ||
2198                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2199        SDValue Op0 = N0;
2200        if (Op0.getOpcode() == ISD::TRUNCATE)
2201          Op0 = Op0.getOperand(0);
2202
2203        if ((Op0.getOpcode() == ISD::XOR) &&
2204            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2205            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2206          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2207          Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2208          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2209                              Cond);
2210        } else if (Op0.getOpcode() == ISD::AND &&
2211                isa<ConstantSDNode>(Op0.getOperand(1)) &&
2212                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2213          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2214          if (Op0.getValueType().bitsGT(VT))
2215            Op0 = DAG.getNode(ISD::AND, dl, VT,
2216                          DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2217                          DAG.getConstant(1, VT));
2218          else if (Op0.getValueType().bitsLT(VT))
2219            Op0 = DAG.getNode(ISD::AND, dl, VT,
2220                        DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2221                        DAG.getConstant(1, VT));
2222
2223          return DAG.getSetCC(dl, VT, Op0,
2224                              DAG.getConstant(0, Op0.getValueType()),
2225                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2226        }
2227      }
2228    }
2229
2230    APInt MinVal, MaxVal;
2231    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2232    if (ISD::isSignedIntSetCC(Cond)) {
2233      MinVal = APInt::getSignedMinValue(OperandBitSize);
2234      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2235    } else {
2236      MinVal = APInt::getMinValue(OperandBitSize);
2237      MaxVal = APInt::getMaxValue(OperandBitSize);
2238    }
2239
2240    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2241    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2242      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2243      // X >= C0 --> X > (C0-1)
2244      return DAG.getSetCC(dl, VT, N0,
2245                          DAG.getConstant(C1-1, N1.getValueType()),
2246                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2247    }
2248
2249    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2250      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2251      // X <= C0 --> X < (C0+1)
2252      return DAG.getSetCC(dl, VT, N0,
2253                          DAG.getConstant(C1+1, N1.getValueType()),
2254                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2255    }
2256
2257    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2258      return DAG.getConstant(0, VT);      // X < MIN --> false
2259    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2260      return DAG.getConstant(1, VT);      // X >= MIN --> true
2261    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2262      return DAG.getConstant(0, VT);      // X > MAX --> false
2263    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2264      return DAG.getConstant(1, VT);      // X <= MAX --> true
2265
2266    // Canonicalize setgt X, Min --> setne X, Min
2267    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2268      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2269    // Canonicalize setlt X, Max --> setne X, Max
2270    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2271      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2272
2273    // If we have setult X, 1, turn it into seteq X, 0
2274    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2275      return DAG.getSetCC(dl, VT, N0,
2276                          DAG.getConstant(MinVal, N0.getValueType()),
2277                          ISD::SETEQ);
2278    // If we have setugt X, Max-1, turn it into seteq X, Max
2279    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2280      return DAG.getSetCC(dl, VT, N0,
2281                          DAG.getConstant(MaxVal, N0.getValueType()),
2282                          ISD::SETEQ);
2283
2284    // If we have "setcc X, C0", check to see if we can shrink the immediate
2285    // by changing cc.
2286
2287    // SETUGT X, SINTMAX  -> SETLT X, 0
2288    if (Cond == ISD::SETUGT &&
2289        C1 == APInt::getSignedMaxValue(OperandBitSize))
2290      return DAG.getSetCC(dl, VT, N0,
2291                          DAG.getConstant(0, N1.getValueType()),
2292                          ISD::SETLT);
2293
2294    // SETULT X, SINTMIN  -> SETGT X, -1
2295    if (Cond == ISD::SETULT &&
2296        C1 == APInt::getSignedMinValue(OperandBitSize)) {
2297      SDValue ConstMinusOne =
2298          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2299                          N1.getValueType());
2300      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2301    }
2302
2303    // Fold bit comparisons when we can.
2304    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2305        (VT == N0.getValueType() ||
2306         (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2307        N0.getOpcode() == ISD::AND)
2308      if (ConstantSDNode *AndRHS =
2309                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2310        EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2311          getPointerTy() : getShiftAmountTy(N0.getValueType());
2312        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2313          // Perform the xform if the AND RHS is a single bit.
2314          if (AndRHS->getAPIntValue().isPowerOf2()) {
2315            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2316                              DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2317                   DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2318          }
2319        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2320          // (X & 8) == 8  -->  (X & 8) >> 3
2321          // Perform the xform if C1 is a single bit.
2322          if (C1.isPowerOf2()) {
2323            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2324                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2325                                      DAG.getConstant(C1.logBase2(), ShiftTy)));
2326          }
2327        }
2328      }
2329
2330    if (C1.getMinSignedBits() <= 64 &&
2331        !isLegalICmpImmediate(C1.getSExtValue())) {
2332      // (X & -256) == 256 -> (X >> 8) == 1
2333      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2334          N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2335        if (ConstantSDNode *AndRHS =
2336            dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2337          const APInt &AndRHSC = AndRHS->getAPIntValue();
2338          if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2339            unsigned ShiftBits = AndRHSC.countTrailingZeros();
2340            EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2341              getPointerTy() : getShiftAmountTy(N0.getValueType());
2342            EVT CmpTy = N0.getValueType();
2343            SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2344                                        DAG.getConstant(ShiftBits, ShiftTy));
2345            SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2346            return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2347          }
2348        }
2349      } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2350                 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2351        bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2352        // X <  0x100000000 -> (X >> 32) <  1
2353        // X >= 0x100000000 -> (X >> 32) >= 1
2354        // X <= 0x0ffffffff -> (X >> 32) <  1
2355        // X >  0x0ffffffff -> (X >> 32) >= 1
2356        unsigned ShiftBits;
2357        APInt NewC = C1;
2358        ISD::CondCode NewCond = Cond;
2359        if (AdjOne) {
2360          ShiftBits = C1.countTrailingOnes();
2361          NewC = NewC + 1;
2362          NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2363        } else {
2364          ShiftBits = C1.countTrailingZeros();
2365        }
2366        NewC = NewC.lshr(ShiftBits);
2367        if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
2368          EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2369            getPointerTy() : getShiftAmountTy(N0.getValueType());
2370          EVT CmpTy = N0.getValueType();
2371          SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2372                                      DAG.getConstant(ShiftBits, ShiftTy));
2373          SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2374          return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2375        }
2376      }
2377    }
2378  }
2379
2380  if (isa<ConstantFPSDNode>(N0.getNode())) {
2381    // Constant fold or commute setcc.
2382    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2383    if (O.getNode()) return O;
2384  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2385    // If the RHS of an FP comparison is a constant, simplify it away in
2386    // some cases.
2387    if (CFP->getValueAPF().isNaN()) {
2388      // If an operand is known to be a nan, we can fold it.
2389      switch (ISD::getUnorderedFlavor(Cond)) {
2390      default: llvm_unreachable("Unknown flavor!");
2391      case 0:  // Known false.
2392        return DAG.getConstant(0, VT);
2393      case 1:  // Known true.
2394        return DAG.getConstant(1, VT);
2395      case 2:  // Undefined.
2396        return DAG.getUNDEF(VT);
2397      }
2398    }
2399
2400    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
2401    // constant if knowing that the operand is non-nan is enough.  We prefer to
2402    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2403    // materialize 0.0.
2404    if (Cond == ISD::SETO || Cond == ISD::SETUO)
2405      return DAG.getSetCC(dl, VT, N0, N0, Cond);
2406
2407    // If the condition is not legal, see if we can find an equivalent one
2408    // which is legal.
2409    if (!isCondCodeLegal(Cond, N0.getValueType())) {
2410      // If the comparison was an awkward floating-point == or != and one of
2411      // the comparison operands is infinity or negative infinity, convert the
2412      // condition to a less-awkward <= or >=.
2413      if (CFP->getValueAPF().isInfinity()) {
2414        if (CFP->getValueAPF().isNegative()) {
2415          if (Cond == ISD::SETOEQ &&
2416              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2417            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2418          if (Cond == ISD::SETUEQ &&
2419              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2420            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2421          if (Cond == ISD::SETUNE &&
2422              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2423            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2424          if (Cond == ISD::SETONE &&
2425              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2426            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2427        } else {
2428          if (Cond == ISD::SETOEQ &&
2429              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2430            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2431          if (Cond == ISD::SETUEQ &&
2432              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2433            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2434          if (Cond == ISD::SETUNE &&
2435              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2436            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2437          if (Cond == ISD::SETONE &&
2438              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2439            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2440        }
2441      }
2442    }
2443  }
2444
2445  if (N0 == N1) {
2446    // The sext(setcc()) => setcc() optimization relies on the appropriate
2447    // constant being emitted.
2448    uint64_t EqVal = 0;
2449    switch (getBooleanContents(N0.getValueType().isVector())) {
2450    case UndefinedBooleanContent:
2451    case ZeroOrOneBooleanContent:
2452      EqVal = ISD::isTrueWhenEqual(Cond);
2453      break;
2454    case ZeroOrNegativeOneBooleanContent:
2455      EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2456      break;
2457    }
2458
2459    // We can always fold X == X for integer setcc's.
2460    if (N0.getValueType().isInteger()) {
2461      return DAG.getConstant(EqVal, VT);
2462    }
2463    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2464    if (UOF == 2)   // FP operators that are undefined on NaNs.
2465      return DAG.getConstant(EqVal, VT);
2466    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2467      return DAG.getConstant(EqVal, VT);
2468    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2469    // if it is not already.
2470    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2471    if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2472          getCondCodeAction(NewCond, N0.getValueType()) == Legal))
2473      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2474  }
2475
2476  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2477      N0.getValueType().isInteger()) {
2478    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2479        N0.getOpcode() == ISD::XOR) {
2480      // Simplify (X+Y) == (X+Z) -->  Y == Z
2481      if (N0.getOpcode() == N1.getOpcode()) {
2482        if (N0.getOperand(0) == N1.getOperand(0))
2483          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2484        if (N0.getOperand(1) == N1.getOperand(1))
2485          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2486        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2487          // If X op Y == Y op X, try other combinations.
2488          if (N0.getOperand(0) == N1.getOperand(1))
2489            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2490                                Cond);
2491          if (N0.getOperand(1) == N1.getOperand(0))
2492            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2493                                Cond);
2494        }
2495      }
2496
2497      // If RHS is a legal immediate value for a compare instruction, we need
2498      // to be careful about increasing register pressure needlessly.
2499      bool LegalRHSImm = false;
2500
2501      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2502        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2503          // Turn (X+C1) == C2 --> X == C2-C1
2504          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2505            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2506                                DAG.getConstant(RHSC->getAPIntValue()-
2507                                                LHSR->getAPIntValue(),
2508                                N0.getValueType()), Cond);
2509          }
2510
2511          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2512          if (N0.getOpcode() == ISD::XOR)
2513            // If we know that all of the inverted bits are zero, don't bother
2514            // performing the inversion.
2515            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2516              return
2517                DAG.getSetCC(dl, VT, N0.getOperand(0),
2518                             DAG.getConstant(LHSR->getAPIntValue() ^
2519                                               RHSC->getAPIntValue(),
2520                                             N0.getValueType()),
2521                             Cond);
2522        }
2523
2524        // Turn (C1-X) == C2 --> X == C1-C2
2525        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2526          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2527            return
2528              DAG.getSetCC(dl, VT, N0.getOperand(1),
2529                           DAG.getConstant(SUBC->getAPIntValue() -
2530                                             RHSC->getAPIntValue(),
2531                                           N0.getValueType()),
2532                           Cond);
2533          }
2534        }
2535
2536        // Could RHSC fold directly into a compare?
2537        if (RHSC->getValueType(0).getSizeInBits() <= 64)
2538          LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2539      }
2540
2541      // Simplify (X+Z) == X -->  Z == 0
2542      // Don't do this if X is an immediate that can fold into a cmp
2543      // instruction and X+Z has other uses. It could be an induction variable
2544      // chain, and the transform would increase register pressure.
2545      if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2546        if (N0.getOperand(0) == N1)
2547          return DAG.getSetCC(dl, VT, N0.getOperand(1),
2548                              DAG.getConstant(0, N0.getValueType()), Cond);
2549        if (N0.getOperand(1) == N1) {
2550          if (DAG.isCommutativeBinOp(N0.getOpcode()))
2551            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2552                                DAG.getConstant(0, N0.getValueType()), Cond);
2553          else if (N0.getNode()->hasOneUse()) {
2554            assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2555            // (Z-X) == X  --> Z == X<<1
2556            SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2557                       DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2558            if (!DCI.isCalledByLegalizer())
2559              DCI.AddToWorklist(SH.getNode());
2560            return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2561          }
2562        }
2563      }
2564    }
2565
2566    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2567        N1.getOpcode() == ISD::XOR) {
2568      // Simplify  X == (X+Z) -->  Z == 0
2569      if (N1.getOperand(0) == N0) {
2570        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2571                        DAG.getConstant(0, N1.getValueType()), Cond);
2572      } else if (N1.getOperand(1) == N0) {
2573        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2574          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2575                          DAG.getConstant(0, N1.getValueType()), Cond);
2576        } else if (N1.getNode()->hasOneUse()) {
2577          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2578          // X == (Z-X)  --> X<<1 == Z
2579          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2580                       DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2581          if (!DCI.isCalledByLegalizer())
2582            DCI.AddToWorklist(SH.getNode());
2583          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2584        }
2585      }
2586    }
2587
2588    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2589    // Note that where y is variable and is known to have at most
2590    // one bit set (for example, if it is z&1) we cannot do this;
2591    // the expressions are not equivalent when y==0.
2592    if (N0.getOpcode() == ISD::AND)
2593      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2594        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2595          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2596          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2597          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2598        }
2599      }
2600    if (N1.getOpcode() == ISD::AND)
2601      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2602        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2603          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2604          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2605          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2606        }
2607      }
2608  }
2609
2610  // Fold away ALL boolean setcc's.
2611  SDValue Temp;
2612  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2613    switch (Cond) {
2614    default: llvm_unreachable("Unknown integer setcc!");
2615    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2616      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2617      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2618      if (!DCI.isCalledByLegalizer())
2619        DCI.AddToWorklist(Temp.getNode());
2620      break;
2621    case ISD::SETNE:  // X != Y   -->  (X^Y)
2622      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2623      break;
2624    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2625    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2626      Temp = DAG.getNOT(dl, N0, MVT::i1);
2627      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2628      if (!DCI.isCalledByLegalizer())
2629        DCI.AddToWorklist(Temp.getNode());
2630      break;
2631    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2632    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2633      Temp = DAG.getNOT(dl, N1, MVT::i1);
2634      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2635      if (!DCI.isCalledByLegalizer())
2636        DCI.AddToWorklist(Temp.getNode());
2637      break;
2638    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2639    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2640      Temp = DAG.getNOT(dl, N0, MVT::i1);
2641      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2642      if (!DCI.isCalledByLegalizer())
2643        DCI.AddToWorklist(Temp.getNode());
2644      break;
2645    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2646    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2647      Temp = DAG.getNOT(dl, N1, MVT::i1);
2648      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2649      break;
2650    }
2651    if (VT != MVT::i1) {
2652      if (!DCI.isCalledByLegalizer())
2653        DCI.AddToWorklist(N0.getNode());
2654      // FIXME: If running after legalize, we probably can't do this.
2655      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2656    }
2657    return N0;
2658  }
2659
2660  // Could not fold it.
2661  return SDValue();
2662}
2663
2664/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2665/// node is a GlobalAddress + offset.
2666bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2667                                    int64_t &Offset) const {
2668  if (isa<GlobalAddressSDNode>(N)) {
2669    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2670    GA = GASD->getGlobal();
2671    Offset += GASD->getOffset();
2672    return true;
2673  }
2674
2675  if (N->getOpcode() == ISD::ADD) {
2676    SDValue N1 = N->getOperand(0);
2677    SDValue N2 = N->getOperand(1);
2678    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2679      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2680      if (V) {
2681        Offset += V->getSExtValue();
2682        return true;
2683      }
2684    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2685      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2686      if (V) {
2687        Offset += V->getSExtValue();
2688        return true;
2689      }
2690    }
2691  }
2692
2693  return false;
2694}
2695
2696
2697SDValue TargetLowering::
2698PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2699  // Default implementation: no optimization.
2700  return SDValue();
2701}
2702
2703//===----------------------------------------------------------------------===//
2704//  Inline Assembler Implementation Methods
2705//===----------------------------------------------------------------------===//
2706
2707
2708TargetLowering::ConstraintType
2709TargetLowering::getConstraintType(const std::string &Constraint) const {
2710  if (Constraint.size() == 1) {
2711    switch (Constraint[0]) {
2712    default: break;
2713    case 'r': return C_RegisterClass;
2714    case 'm':    // memory
2715    case 'o':    // offsetable
2716    case 'V':    // not offsetable
2717      return C_Memory;
2718    case 'i':    // Simple Integer or Relocatable Constant
2719    case 'n':    // Simple Integer
2720    case 'E':    // Floating Point Constant
2721    case 'F':    // Floating Point Constant
2722    case 's':    // Relocatable Constant
2723    case 'p':    // Address.
2724    case 'X':    // Allow ANY value.
2725    case 'I':    // Target registers.
2726    case 'J':
2727    case 'K':
2728    case 'L':
2729    case 'M':
2730    case 'N':
2731    case 'O':
2732    case 'P':
2733    case '<':
2734    case '>':
2735      return C_Other;
2736    }
2737  }
2738
2739  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2740      Constraint[Constraint.size()-1] == '}')
2741    return C_Register;
2742  return C_Unknown;
2743}
2744
2745/// LowerXConstraint - try to replace an X constraint, which matches anything,
2746/// with another that has more specific requirements based on the type of the
2747/// corresponding operand.
2748const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2749  if (ConstraintVT.isInteger())
2750    return "r";
2751  if (ConstraintVT.isFloatingPoint())
2752    return "f";      // works for many targets
2753  return 0;
2754}
2755
2756/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2757/// vector.  If it is invalid, don't add anything to Ops.
2758void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2759                                                  std::string &Constraint,
2760                                                  std::vector<SDValue> &Ops,
2761                                                  SelectionDAG &DAG) const {
2762
2763  if (Constraint.length() > 1) return;
2764
2765  char ConstraintLetter = Constraint[0];
2766  switch (ConstraintLetter) {
2767  default: break;
2768  case 'X':     // Allows any operand; labels (basic block) use this.
2769    if (Op.getOpcode() == ISD::BasicBlock) {
2770      Ops.push_back(Op);
2771      return;
2772    }
2773    // fall through
2774  case 'i':    // Simple Integer or Relocatable Constant
2775  case 'n':    // Simple Integer
2776  case 's': {  // Relocatable Constant
2777    // These operands are interested in values of the form (GV+C), where C may
2778    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2779    // is possible and fine if either GV or C are missing.
2780    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2781    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2782
2783    // If we have "(add GV, C)", pull out GV/C
2784    if (Op.getOpcode() == ISD::ADD) {
2785      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2786      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2787      if (C == 0 || GA == 0) {
2788        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2789        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2790      }
2791      if (C == 0 || GA == 0)
2792        C = 0, GA = 0;
2793    }
2794
2795    // If we find a valid operand, map to the TargetXXX version so that the
2796    // value itself doesn't get selected.
2797    if (GA) {   // Either &GV   or   &GV+C
2798      if (ConstraintLetter != 'n') {
2799        int64_t Offs = GA->getOffset();
2800        if (C) Offs += C->getZExtValue();
2801        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2802                                                 C ? C->getDebugLoc() : DebugLoc(),
2803                                                 Op.getValueType(), Offs));
2804        return;
2805      }
2806    }
2807    if (C) {   // just C, no GV.
2808      // Simple constants are not allowed for 's'.
2809      if (ConstraintLetter != 's') {
2810        // gcc prints these as sign extended.  Sign extend value to 64 bits
2811        // now; without this it would get ZExt'd later in
2812        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2813        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2814                                            MVT::i64));
2815        return;
2816      }
2817    }
2818    break;
2819  }
2820  }
2821}
2822
2823std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2824getRegForInlineAsmConstraint(const std::string &Constraint,
2825                             EVT VT) const {
2826  if (Constraint[0] != '{')
2827    return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2828  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2829
2830  // Remove the braces from around the name.
2831  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2832
2833  // Figure out which register class contains this reg.
2834  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2835  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2836       E = RI->regclass_end(); RCI != E; ++RCI) {
2837    const TargetRegisterClass *RC = *RCI;
2838
2839    // If none of the value types for this register class are valid, we
2840    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2841    if (!isLegalRC(RC))
2842      continue;
2843
2844    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2845         I != E; ++I) {
2846      if (RegName.equals_lower(RI->getName(*I)))
2847        return std::make_pair(*I, RC);
2848    }
2849  }
2850
2851  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2852}
2853
2854//===----------------------------------------------------------------------===//
2855// Constraint Selection.
2856
2857/// isMatchingInputConstraint - Return true of this is an input operand that is
2858/// a matching constraint like "4".
2859bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2860  assert(!ConstraintCode.empty() && "No known constraint!");
2861  return isdigit(ConstraintCode[0]);
2862}
2863
2864/// getMatchedOperand - If this is an input matching constraint, this method
2865/// returns the output operand it matches.
2866unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2867  assert(!ConstraintCode.empty() && "No known constraint!");
2868  return atoi(ConstraintCode.c_str());
2869}
2870
2871
2872/// ParseConstraints - Split up the constraint string from the inline
2873/// assembly value into the specific constraints and their prefixes,
2874/// and also tie in the associated operand values.
2875/// If this returns an empty vector, and if the constraint string itself
2876/// isn't empty, there was an error parsing.
2877TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2878    ImmutableCallSite CS) const {
2879  /// ConstraintOperands - Information about all of the constraints.
2880  AsmOperandInfoVector ConstraintOperands;
2881  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2882  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2883
2884  // Do a prepass over the constraints, canonicalizing them, and building up the
2885  // ConstraintOperands list.
2886  InlineAsm::ConstraintInfoVector
2887    ConstraintInfos = IA->ParseConstraints();
2888
2889  unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
2890  unsigned ResNo = 0;   // ResNo - The result number of the next output.
2891
2892  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2893    ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2894    AsmOperandInfo &OpInfo = ConstraintOperands.back();
2895
2896    // Update multiple alternative constraint count.
2897    if (OpInfo.multipleAlternatives.size() > maCount)
2898      maCount = OpInfo.multipleAlternatives.size();
2899
2900    OpInfo.ConstraintVT = MVT::Other;
2901
2902    // Compute the value type for each operand.
2903    switch (OpInfo.Type) {
2904    case InlineAsm::isOutput:
2905      // Indirect outputs just consume an argument.
2906      if (OpInfo.isIndirect) {
2907        OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2908        break;
2909      }
2910
2911      // The return value of the call is this value.  As such, there is no
2912      // corresponding argument.
2913      assert(!CS.getType()->isVoidTy() &&
2914             "Bad inline asm!");
2915      if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2916        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2917      } else {
2918        assert(ResNo == 0 && "Asm only has one result!");
2919        OpInfo.ConstraintVT = getValueType(CS.getType());
2920      }
2921      ++ResNo;
2922      break;
2923    case InlineAsm::isInput:
2924      OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2925      break;
2926    case InlineAsm::isClobber:
2927      // Nothing to do.
2928      break;
2929    }
2930
2931    if (OpInfo.CallOperandVal) {
2932      llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2933      if (OpInfo.isIndirect) {
2934        llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2935        if (!PtrTy)
2936          report_fatal_error("Indirect operand for inline asm not a pointer!");
2937        OpTy = PtrTy->getElementType();
2938      }
2939
2940      // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2941      if (StructType *STy = dyn_cast<StructType>(OpTy))
2942        if (STy->getNumElements() == 1)
2943          OpTy = STy->getElementType(0);
2944
2945      // If OpTy is not a single value, it may be a struct/union that we
2946      // can tile with integers.
2947      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2948        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2949        switch (BitSize) {
2950        default: break;
2951        case 1:
2952        case 8:
2953        case 16:
2954        case 32:
2955        case 64:
2956        case 128:
2957          OpInfo.ConstraintVT =
2958              EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2959          break;
2960        }
2961      } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2962        OpInfo.ConstraintVT = MVT::getIntegerVT(
2963            8*TD->getPointerSize(PT->getAddressSpace()));
2964      } else {
2965        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2966      }
2967    }
2968  }
2969
2970  // If we have multiple alternative constraints, select the best alternative.
2971  if (ConstraintInfos.size()) {
2972    if (maCount) {
2973      unsigned bestMAIndex = 0;
2974      int bestWeight = -1;
2975      // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
2976      int weight = -1;
2977      unsigned maIndex;
2978      // Compute the sums of the weights for each alternative, keeping track
2979      // of the best (highest weight) one so far.
2980      for (maIndex = 0; maIndex < maCount; ++maIndex) {
2981        int weightSum = 0;
2982        for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2983            cIndex != eIndex; ++cIndex) {
2984          AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2985          if (OpInfo.Type == InlineAsm::isClobber)
2986            continue;
2987
2988          // If this is an output operand with a matching input operand,
2989          // look up the matching input. If their types mismatch, e.g. one
2990          // is an integer, the other is floating point, or their sizes are
2991          // different, flag it as an maCantMatch.
2992          if (OpInfo.hasMatchingInput()) {
2993            AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2994            if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2995              if ((OpInfo.ConstraintVT.isInteger() !=
2996                   Input.ConstraintVT.isInteger()) ||
2997                  (OpInfo.ConstraintVT.getSizeInBits() !=
2998                   Input.ConstraintVT.getSizeInBits())) {
2999                weightSum = -1;  // Can't match.
3000                break;
3001              }
3002            }
3003          }
3004          weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
3005          if (weight == -1) {
3006            weightSum = -1;
3007            break;
3008          }
3009          weightSum += weight;
3010        }
3011        // Update best.
3012        if (weightSum > bestWeight) {
3013          bestWeight = weightSum;
3014          bestMAIndex = maIndex;
3015        }
3016      }
3017
3018      // Now select chosen alternative in each constraint.
3019      for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3020          cIndex != eIndex; ++cIndex) {
3021        AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3022        if (cInfo.Type == InlineAsm::isClobber)
3023          continue;
3024        cInfo.selectAlternative(bestMAIndex);
3025      }
3026    }
3027  }
3028
3029  // Check and hook up tied operands, choose constraint code to use.
3030  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3031      cIndex != eIndex; ++cIndex) {
3032    AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3033
3034    // If this is an output operand with a matching input operand, look up the
3035    // matching input. If their types mismatch, e.g. one is an integer, the
3036    // other is floating point, or their sizes are different, flag it as an
3037    // error.
3038    if (OpInfo.hasMatchingInput()) {
3039      AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3040
3041      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3042        std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3043          getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3044                                       OpInfo.ConstraintVT);
3045        std::pair<unsigned, const TargetRegisterClass*> InputRC =
3046          getRegForInlineAsmConstraint(Input.ConstraintCode,
3047                                       Input.ConstraintVT);
3048        if ((OpInfo.ConstraintVT.isInteger() !=
3049             Input.ConstraintVT.isInteger()) ||
3050            (MatchRC.second != InputRC.second)) {
3051          report_fatal_error("Unsupported asm: input constraint"
3052                             " with a matching output constraint of"
3053                             " incompatible type!");
3054        }
3055      }
3056
3057    }
3058  }
3059
3060  return ConstraintOperands;
3061}
3062
3063
3064/// getConstraintGenerality - Return an integer indicating how general CT
3065/// is.
3066static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3067  switch (CT) {
3068  case TargetLowering::C_Other:
3069  case TargetLowering::C_Unknown:
3070    return 0;
3071  case TargetLowering::C_Register:
3072    return 1;
3073  case TargetLowering::C_RegisterClass:
3074    return 2;
3075  case TargetLowering::C_Memory:
3076    return 3;
3077  }
3078  llvm_unreachable("Invalid constraint type");
3079}
3080
3081/// Examine constraint type and operand type and determine a weight value.
3082/// This object must already have been set up with the operand type
3083/// and the current alternative constraint selected.
3084TargetLowering::ConstraintWeight
3085  TargetLowering::getMultipleConstraintMatchWeight(
3086    AsmOperandInfo &info, int maIndex) const {
3087  InlineAsm::ConstraintCodeVector *rCodes;
3088  if (maIndex >= (int)info.multipleAlternatives.size())
3089    rCodes = &info.Codes;
3090  else
3091    rCodes = &info.multipleAlternatives[maIndex].Codes;
3092  ConstraintWeight BestWeight = CW_Invalid;
3093
3094  // Loop over the options, keeping track of the most general one.
3095  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3096    ConstraintWeight weight =
3097      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3098    if (weight > BestWeight)
3099      BestWeight = weight;
3100  }
3101
3102  return BestWeight;
3103}
3104
3105/// Examine constraint type and operand type and determine a weight value.
3106/// This object must already have been set up with the operand type
3107/// and the current alternative constraint selected.
3108TargetLowering::ConstraintWeight
3109  TargetLowering::getSingleConstraintMatchWeight(
3110    AsmOperandInfo &info, const char *constraint) const {
3111  ConstraintWeight weight = CW_Invalid;
3112  Value *CallOperandVal = info.CallOperandVal;
3113    // If we don't have a value, we can't do a match,
3114    // but allow it at the lowest weight.
3115  if (CallOperandVal == NULL)
3116    return CW_Default;
3117  // Look at the constraint type.
3118  switch (*constraint) {
3119    case 'i': // immediate integer.
3120    case 'n': // immediate integer with a known value.
3121      if (isa<ConstantInt>(CallOperandVal))
3122        weight = CW_Constant;
3123      break;
3124    case 's': // non-explicit intregal immediate.
3125      if (isa<GlobalValue>(CallOperandVal))
3126        weight = CW_Constant;
3127      break;
3128    case 'E': // immediate float if host format.
3129    case 'F': // immediate float.
3130      if (isa<ConstantFP>(CallOperandVal))
3131        weight = CW_Constant;
3132      break;
3133    case '<': // memory operand with autodecrement.
3134    case '>': // memory operand with autoincrement.
3135    case 'm': // memory operand.
3136    case 'o': // offsettable memory operand
3137    case 'V': // non-offsettable memory operand
3138      weight = CW_Memory;
3139      break;
3140    case 'r': // general register.
3141    case 'g': // general register, memory operand or immediate integer.
3142              // note: Clang converts "g" to "imr".
3143      if (CallOperandVal->getType()->isIntegerTy())
3144        weight = CW_Register;
3145      break;
3146    case 'X': // any operand.
3147    default:
3148      weight = CW_Default;
3149      break;
3150  }
3151  return weight;
3152}
3153
3154/// ChooseConstraint - If there are multiple different constraints that we
3155/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3156/// This is somewhat tricky: constraints fall into four classes:
3157///    Other         -> immediates and magic values
3158///    Register      -> one specific register
3159///    RegisterClass -> a group of regs
3160///    Memory        -> memory
3161/// Ideally, we would pick the most specific constraint possible: if we have
3162/// something that fits into a register, we would pick it.  The problem here
3163/// is that if we have something that could either be in a register or in
3164/// memory that use of the register could cause selection of *other*
3165/// operands to fail: they might only succeed if we pick memory.  Because of
3166/// this the heuristic we use is:
3167///
3168///  1) If there is an 'other' constraint, and if the operand is valid for
3169///     that constraint, use it.  This makes us take advantage of 'i'
3170///     constraints when available.
3171///  2) Otherwise, pick the most general constraint present.  This prefers
3172///     'm' over 'r', for example.
3173///
3174static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3175                             const TargetLowering &TLI,
3176                             SDValue Op, SelectionDAG *DAG) {
3177  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3178  unsigned BestIdx = 0;
3179  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3180  int BestGenerality = -1;
3181
3182  // Loop over the options, keeping track of the most general one.
3183  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3184    TargetLowering::ConstraintType CType =
3185      TLI.getConstraintType(OpInfo.Codes[i]);
3186
3187    // If this is an 'other' constraint, see if the operand is valid for it.
3188    // For example, on X86 we might have an 'rI' constraint.  If the operand
3189    // is an integer in the range [0..31] we want to use I (saving a load
3190    // of a register), otherwise we must use 'r'.
3191    if (CType == TargetLowering::C_Other && Op.getNode()) {
3192      assert(OpInfo.Codes[i].size() == 1 &&
3193             "Unhandled multi-letter 'other' constraint");
3194      std::vector<SDValue> ResultOps;
3195      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3196                                       ResultOps, *DAG);
3197      if (!ResultOps.empty()) {
3198        BestType = CType;
3199        BestIdx = i;
3200        break;
3201      }
3202    }
3203
3204    // Things with matching constraints can only be registers, per gcc
3205    // documentation.  This mainly affects "g" constraints.
3206    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3207      continue;
3208
3209    // This constraint letter is more general than the previous one, use it.
3210    int Generality = getConstraintGenerality(CType);
3211    if (Generality > BestGenerality) {
3212      BestType = CType;
3213      BestIdx = i;
3214      BestGenerality = Generality;
3215    }
3216  }
3217
3218  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3219  OpInfo.ConstraintType = BestType;
3220}
3221
3222/// ComputeConstraintToUse - Determines the constraint code and constraint
3223/// type to use for the specific AsmOperandInfo, setting
3224/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3225void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3226                                            SDValue Op,
3227                                            SelectionDAG *DAG) const {
3228  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3229
3230  // Single-letter constraints ('r') are very common.
3231  if (OpInfo.Codes.size() == 1) {
3232    OpInfo.ConstraintCode = OpInfo.Codes[0];
3233    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3234  } else {
3235    ChooseConstraint(OpInfo, *this, Op, DAG);
3236  }
3237
3238  // 'X' matches anything.
3239  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3240    // Labels and constants are handled elsewhere ('X' is the only thing
3241    // that matches labels).  For Functions, the type here is the type of
3242    // the result, which is not what we want to look at; leave them alone.
3243    Value *v = OpInfo.CallOperandVal;
3244    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3245      OpInfo.CallOperandVal = v;
3246      return;
3247    }
3248
3249    // Otherwise, try to resolve it to something we know about by looking at
3250    // the actual operand type.
3251    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3252      OpInfo.ConstraintCode = Repl;
3253      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3254    }
3255  }
3256}
3257
3258//===----------------------------------------------------------------------===//
3259//  Loop Strength Reduction hooks
3260//===----------------------------------------------------------------------===//
3261
3262/// isLegalAddressingMode - Return true if the addressing mode represented
3263/// by AM is legal for this target, for a load/store of the specified type.
3264bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3265                                           Type *Ty) const {
3266  // The default implementation of this implements a conservative RISCy, r+r and
3267  // r+i addr mode.
3268
3269  // Allows a sign-extended 16-bit immediate field.
3270  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3271    return false;
3272
3273  // No global is ever allowed as a base.
3274  if (AM.BaseGV)
3275    return false;
3276
3277  // Only support r+r,
3278  switch (AM.Scale) {
3279  case 0:  // "r+i" or just "i", depending on HasBaseReg.
3280    break;
3281  case 1:
3282    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
3283      return false;
3284    // Otherwise we have r+r or r+i.
3285    break;
3286  case 2:
3287    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
3288      return false;
3289    // Allow 2*r as r+r.
3290    break;
3291  }
3292
3293  return true;
3294}
3295
3296/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3297/// with the multiplicative inverse of the constant.
3298SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3299                                       SelectionDAG &DAG) const {
3300  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3301  APInt d = C->getAPIntValue();
3302  assert(d != 0 && "Division by zero!");
3303
3304  // Shift the value upfront if it is even, so the LSB is one.
3305  unsigned ShAmt = d.countTrailingZeros();
3306  if (ShAmt) {
3307    // TODO: For UDIV use SRL instead of SRA.
3308    SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3309    Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3310    d = d.ashr(ShAmt);
3311  }
3312
3313  // Calculate the multiplicative inverse, using Newton's method.
3314  APInt t, xn = d;
3315  while ((t = d*xn) != 1)
3316    xn *= APInt(d.getBitWidth(), 2) - t;
3317
3318  Op2 = DAG.getConstant(xn, Op1.getValueType());
3319  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3320}
3321
3322/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3323/// return a DAG expression to select that will generate the same value by
3324/// multiplying by a magic number.  See:
3325/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3326SDValue TargetLowering::
3327BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3328          std::vector<SDNode*>* Created) const {
3329  EVT VT = N->getValueType(0);
3330  DebugLoc dl= N->getDebugLoc();
3331
3332  // Check to see if we can do this.
3333  // FIXME: We should be more aggressive here.
3334  if (!isTypeLegal(VT))
3335    return SDValue();
3336
3337  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3338  APInt::ms magics = d.magic();
3339
3340  // Multiply the numerator (operand 0) by the magic value
3341  // FIXME: We should support doing a MUL in a wider type
3342  SDValue Q;
3343  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3344                            isOperationLegalOrCustom(ISD::MULHS, VT))
3345    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3346                    DAG.getConstant(magics.m, VT));
3347  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3348                                 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3349    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3350                              N->getOperand(0),
3351                              DAG.getConstant(magics.m, VT)).getNode(), 1);
3352  else
3353    return SDValue();       // No mulhs or equvialent
3354  // If d > 0 and m < 0, add the numerator
3355  if (d.isStrictlyPositive() && magics.m.isNegative()) {
3356    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3357    if (Created)
3358      Created->push_back(Q.getNode());
3359  }
3360  // If d < 0 and m > 0, subtract the numerator.
3361  if (d.isNegative() && magics.m.isStrictlyPositive()) {
3362    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3363    if (Created)
3364      Created->push_back(Q.getNode());
3365  }
3366  // Shift right algebraic if shift value is nonzero
3367  if (magics.s > 0) {
3368    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3369                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3370    if (Created)
3371      Created->push_back(Q.getNode());
3372  }
3373  // Extract the sign bit and add it to the quotient
3374  SDValue T =
3375    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3376                                           getShiftAmountTy(Q.getValueType())));
3377  if (Created)
3378    Created->push_back(T.getNode());
3379  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3380}
3381
3382/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3383/// return a DAG expression to select that will generate the same value by
3384/// multiplying by a magic number.  See:
3385/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3386SDValue TargetLowering::
3387BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3388          std::vector<SDNode*>* Created) const {
3389  EVT VT = N->getValueType(0);
3390  DebugLoc dl = N->getDebugLoc();
3391
3392  // Check to see if we can do this.
3393  // FIXME: We should be more aggressive here.
3394  if (!isTypeLegal(VT))
3395    return SDValue();
3396
3397  // FIXME: We should use a narrower constant when the upper
3398  // bits are known to be zero.
3399  const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3400  APInt::mu magics = N1C.magicu();
3401
3402  SDValue Q = N->getOperand(0);
3403
3404  // If the divisor is even, we can avoid using the expensive fixup by shifting
3405  // the divided value upfront.
3406  if (magics.a != 0 && !N1C[0]) {
3407    unsigned Shift = N1C.countTrailingZeros();
3408    Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3409                    DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3410    if (Created)
3411      Created->push_back(Q.getNode());
3412
3413    // Get magic number for the shifted divisor.
3414    magics = N1C.lshr(Shift).magicu(Shift);
3415    assert(magics.a == 0 && "Should use cheap fixup now");
3416  }
3417
3418  // Multiply the numerator (operand 0) by the magic value
3419  // FIXME: We should support doing a MUL in a wider type
3420  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3421                            isOperationLegalOrCustom(ISD::MULHU, VT))
3422    Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3423  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3424                                 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3425    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3426                            DAG.getConstant(magics.m, VT)).getNode(), 1);
3427  else
3428    return SDValue();       // No mulhu or equvialent
3429  if (Created)
3430    Created->push_back(Q.getNode());
3431
3432  if (magics.a == 0) {
3433    assert(magics.s < N1C.getBitWidth() &&
3434           "We shouldn't generate an undefined shift!");
3435    return DAG.getNode(ISD::SRL, dl, VT, Q,
3436                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3437  } else {
3438    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3439    if (Created)
3440      Created->push_back(NPQ.getNode());
3441    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3442                      DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3443    if (Created)
3444      Created->push_back(NPQ.getNode());
3445    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3446    if (Created)
3447      Created->push_back(NPQ.getNode());
3448    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3449             DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
3450  }
3451}
3452