TargetLowering.cpp revision 97d116346cdf47ce0c8536a69ff6c606309cb4c0
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I16] = "__ashli16"; 33 Names[RTLIB::SHL_I32] = "__ashlsi3"; 34 Names[RTLIB::SHL_I64] = "__ashldi3"; 35 Names[RTLIB::SHL_I128] = "__ashlti3"; 36 Names[RTLIB::SRL_I16] = "__lshri16"; 37 Names[RTLIB::SRL_I32] = "__lshrsi3"; 38 Names[RTLIB::SRL_I64] = "__lshrdi3"; 39 Names[RTLIB::SRL_I128] = "__lshrti3"; 40 Names[RTLIB::SRA_I16] = "__ashri16"; 41 Names[RTLIB::SRA_I32] = "__ashrsi3"; 42 Names[RTLIB::SRA_I64] = "__ashrdi3"; 43 Names[RTLIB::SRA_I128] = "__ashrti3"; 44 Names[RTLIB::MUL_I16] = "__muli16"; 45 Names[RTLIB::MUL_I32] = "__mulsi3"; 46 Names[RTLIB::MUL_I64] = "__muldi3"; 47 Names[RTLIB::MUL_I128] = "__multi3"; 48 Names[RTLIB::SDIV_I32] = "__divsi3"; 49 Names[RTLIB::SDIV_I64] = "__divdi3"; 50 Names[RTLIB::SDIV_I128] = "__divti3"; 51 Names[RTLIB::UDIV_I32] = "__udivsi3"; 52 Names[RTLIB::UDIV_I64] = "__udivdi3"; 53 Names[RTLIB::UDIV_I128] = "__udivti3"; 54 Names[RTLIB::SREM_I32] = "__modsi3"; 55 Names[RTLIB::SREM_I64] = "__moddi3"; 56 Names[RTLIB::SREM_I128] = "__modti3"; 57 Names[RTLIB::UREM_I32] = "__umodsi3"; 58 Names[RTLIB::UREM_I64] = "__umoddi3"; 59 Names[RTLIB::UREM_I128] = "__umodti3"; 60 Names[RTLIB::NEG_I32] = "__negsi2"; 61 Names[RTLIB::NEG_I64] = "__negdi2"; 62 Names[RTLIB::ADD_F32] = "__addsf3"; 63 Names[RTLIB::ADD_F64] = "__adddf3"; 64 Names[RTLIB::ADD_F80] = "__addxf3"; 65 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 66 Names[RTLIB::SUB_F32] = "__subsf3"; 67 Names[RTLIB::SUB_F64] = "__subdf3"; 68 Names[RTLIB::SUB_F80] = "__subxf3"; 69 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 70 Names[RTLIB::MUL_F32] = "__mulsf3"; 71 Names[RTLIB::MUL_F64] = "__muldf3"; 72 Names[RTLIB::MUL_F80] = "__mulxf3"; 73 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 74 Names[RTLIB::DIV_F32] = "__divsf3"; 75 Names[RTLIB::DIV_F64] = "__divdf3"; 76 Names[RTLIB::DIV_F80] = "__divxf3"; 77 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 78 Names[RTLIB::REM_F32] = "fmodf"; 79 Names[RTLIB::REM_F64] = "fmod"; 80 Names[RTLIB::REM_F80] = "fmodl"; 81 Names[RTLIB::REM_PPCF128] = "fmodl"; 82 Names[RTLIB::POWI_F32] = "__powisf2"; 83 Names[RTLIB::POWI_F64] = "__powidf2"; 84 Names[RTLIB::POWI_F80] = "__powixf2"; 85 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 86 Names[RTLIB::SQRT_F32] = "sqrtf"; 87 Names[RTLIB::SQRT_F64] = "sqrt"; 88 Names[RTLIB::SQRT_F80] = "sqrtl"; 89 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 90 Names[RTLIB::LOG_F32] = "logf"; 91 Names[RTLIB::LOG_F64] = "log"; 92 Names[RTLIB::LOG_F80] = "logl"; 93 Names[RTLIB::LOG_PPCF128] = "logl"; 94 Names[RTLIB::LOG2_F32] = "log2f"; 95 Names[RTLIB::LOG2_F64] = "log2"; 96 Names[RTLIB::LOG2_F80] = "log2l"; 97 Names[RTLIB::LOG2_PPCF128] = "log2l"; 98 Names[RTLIB::LOG10_F32] = "log10f"; 99 Names[RTLIB::LOG10_F64] = "log10"; 100 Names[RTLIB::LOG10_F80] = "log10l"; 101 Names[RTLIB::LOG10_PPCF128] = "log10l"; 102 Names[RTLIB::EXP_F32] = "expf"; 103 Names[RTLIB::EXP_F64] = "exp"; 104 Names[RTLIB::EXP_F80] = "expl"; 105 Names[RTLIB::EXP_PPCF128] = "expl"; 106 Names[RTLIB::EXP2_F32] = "exp2f"; 107 Names[RTLIB::EXP2_F64] = "exp2"; 108 Names[RTLIB::EXP2_F80] = "exp2l"; 109 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 110 Names[RTLIB::SIN_F32] = "sinf"; 111 Names[RTLIB::SIN_F64] = "sin"; 112 Names[RTLIB::SIN_F80] = "sinl"; 113 Names[RTLIB::SIN_PPCF128] = "sinl"; 114 Names[RTLIB::COS_F32] = "cosf"; 115 Names[RTLIB::COS_F64] = "cos"; 116 Names[RTLIB::COS_F80] = "cosl"; 117 Names[RTLIB::COS_PPCF128] = "cosl"; 118 Names[RTLIB::POW_F32] = "powf"; 119 Names[RTLIB::POW_F64] = "pow"; 120 Names[RTLIB::POW_F80] = "powl"; 121 Names[RTLIB::POW_PPCF128] = "powl"; 122 Names[RTLIB::CEIL_F32] = "ceilf"; 123 Names[RTLIB::CEIL_F64] = "ceil"; 124 Names[RTLIB::CEIL_F80] = "ceill"; 125 Names[RTLIB::CEIL_PPCF128] = "ceill"; 126 Names[RTLIB::TRUNC_F32] = "truncf"; 127 Names[RTLIB::TRUNC_F64] = "trunc"; 128 Names[RTLIB::TRUNC_F80] = "truncl"; 129 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 130 Names[RTLIB::RINT_F32] = "rintf"; 131 Names[RTLIB::RINT_F64] = "rint"; 132 Names[RTLIB::RINT_F80] = "rintl"; 133 Names[RTLIB::RINT_PPCF128] = "rintl"; 134 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 135 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 136 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 137 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 138 Names[RTLIB::FLOOR_F32] = "floorf"; 139 Names[RTLIB::FLOOR_F64] = "floor"; 140 Names[RTLIB::FLOOR_F80] = "floorl"; 141 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 142 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 143 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 144 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 145 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 146 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 147 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 148 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 149 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 150 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 151 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 152 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 153 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 154 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 155 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 156 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 157 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 158 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 159 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 160 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 161 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 162 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 163 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 164 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 165 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 166 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 167 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 168 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 169 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 170 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 171 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 172 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 173 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 174 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 175 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 176 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 177 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 178 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 179 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 180 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 181 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 182 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 183 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 184 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 185 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 186 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 187 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 188 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 189 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 190 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 191 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 192 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 193 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 194 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 195 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 196 Names[RTLIB::OEQ_F32] = "__eqsf2"; 197 Names[RTLIB::OEQ_F64] = "__eqdf2"; 198 Names[RTLIB::UNE_F32] = "__nesf2"; 199 Names[RTLIB::UNE_F64] = "__nedf2"; 200 Names[RTLIB::OGE_F32] = "__gesf2"; 201 Names[RTLIB::OGE_F64] = "__gedf2"; 202 Names[RTLIB::OLT_F32] = "__ltsf2"; 203 Names[RTLIB::OLT_F64] = "__ltdf2"; 204 Names[RTLIB::OLE_F32] = "__lesf2"; 205 Names[RTLIB::OLE_F64] = "__ledf2"; 206 Names[RTLIB::OGT_F32] = "__gtsf2"; 207 Names[RTLIB::OGT_F64] = "__gtdf2"; 208 Names[RTLIB::UO_F32] = "__unordsf2"; 209 Names[RTLIB::UO_F64] = "__unorddf2"; 210 Names[RTLIB::O_F32] = "__unordsf2"; 211 Names[RTLIB::O_F64] = "__unorddf2"; 212} 213 214/// getFPEXT - Return the FPEXT_*_* value for the given types, or 215/// UNKNOWN_LIBCALL if there is none. 216RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 217 if (OpVT == MVT::f32) { 218 if (RetVT == MVT::f64) 219 return FPEXT_F32_F64; 220 } 221 return UNKNOWN_LIBCALL; 222} 223 224/// getFPROUND - Return the FPROUND_*_* value for the given types, or 225/// UNKNOWN_LIBCALL if there is none. 226RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 227 if (RetVT == MVT::f32) { 228 if (OpVT == MVT::f64) 229 return FPROUND_F64_F32; 230 if (OpVT == MVT::f80) 231 return FPROUND_F80_F32; 232 if (OpVT == MVT::ppcf128) 233 return FPROUND_PPCF128_F32; 234 } else if (RetVT == MVT::f64) { 235 if (OpVT == MVT::f80) 236 return FPROUND_F80_F64; 237 if (OpVT == MVT::ppcf128) 238 return FPROUND_PPCF128_F64; 239 } 240 return UNKNOWN_LIBCALL; 241} 242 243/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 244/// UNKNOWN_LIBCALL if there is none. 245RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 246 if (OpVT == MVT::f32) { 247 if (RetVT == MVT::i32) 248 return FPTOSINT_F32_I32; 249 if (RetVT == MVT::i64) 250 return FPTOSINT_F32_I64; 251 if (RetVT == MVT::i128) 252 return FPTOSINT_F32_I128; 253 } else if (OpVT == MVT::f64) { 254 if (RetVT == MVT::i32) 255 return FPTOSINT_F64_I32; 256 if (RetVT == MVT::i64) 257 return FPTOSINT_F64_I64; 258 if (RetVT == MVT::i128) 259 return FPTOSINT_F64_I128; 260 } else if (OpVT == MVT::f80) { 261 if (RetVT == MVT::i32) 262 return FPTOSINT_F80_I32; 263 if (RetVT == MVT::i64) 264 return FPTOSINT_F80_I64; 265 if (RetVT == MVT::i128) 266 return FPTOSINT_F80_I128; 267 } else if (OpVT == MVT::ppcf128) { 268 if (RetVT == MVT::i32) 269 return FPTOSINT_PPCF128_I32; 270 if (RetVT == MVT::i64) 271 return FPTOSINT_PPCF128_I64; 272 if (RetVT == MVT::i128) 273 return FPTOSINT_PPCF128_I128; 274 } 275 return UNKNOWN_LIBCALL; 276} 277 278/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 279/// UNKNOWN_LIBCALL if there is none. 280RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 281 if (OpVT == MVT::f32) { 282 if (RetVT == MVT::i32) 283 return FPTOUINT_F32_I32; 284 if (RetVT == MVT::i64) 285 return FPTOUINT_F32_I64; 286 if (RetVT == MVT::i128) 287 return FPTOUINT_F32_I128; 288 } else if (OpVT == MVT::f64) { 289 if (RetVT == MVT::i32) 290 return FPTOUINT_F64_I32; 291 if (RetVT == MVT::i64) 292 return FPTOUINT_F64_I64; 293 if (RetVT == MVT::i128) 294 return FPTOUINT_F64_I128; 295 } else if (OpVT == MVT::f80) { 296 if (RetVT == MVT::i32) 297 return FPTOUINT_F80_I32; 298 if (RetVT == MVT::i64) 299 return FPTOUINT_F80_I64; 300 if (RetVT == MVT::i128) 301 return FPTOUINT_F80_I128; 302 } else if (OpVT == MVT::ppcf128) { 303 if (RetVT == MVT::i32) 304 return FPTOUINT_PPCF128_I32; 305 if (RetVT == MVT::i64) 306 return FPTOUINT_PPCF128_I64; 307 if (RetVT == MVT::i128) 308 return FPTOUINT_PPCF128_I128; 309 } 310 return UNKNOWN_LIBCALL; 311} 312 313/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 314/// UNKNOWN_LIBCALL if there is none. 315RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 316 if (OpVT == MVT::i32) { 317 if (RetVT == MVT::f32) 318 return SINTTOFP_I32_F32; 319 else if (RetVT == MVT::f64) 320 return SINTTOFP_I32_F64; 321 else if (RetVT == MVT::f80) 322 return SINTTOFP_I32_F80; 323 else if (RetVT == MVT::ppcf128) 324 return SINTTOFP_I32_PPCF128; 325 } else if (OpVT == MVT::i64) { 326 if (RetVT == MVT::f32) 327 return SINTTOFP_I64_F32; 328 else if (RetVT == MVT::f64) 329 return SINTTOFP_I64_F64; 330 else if (RetVT == MVT::f80) 331 return SINTTOFP_I64_F80; 332 else if (RetVT == MVT::ppcf128) 333 return SINTTOFP_I64_PPCF128; 334 } else if (OpVT == MVT::i128) { 335 if (RetVT == MVT::f32) 336 return SINTTOFP_I128_F32; 337 else if (RetVT == MVT::f64) 338 return SINTTOFP_I128_F64; 339 else if (RetVT == MVT::f80) 340 return SINTTOFP_I128_F80; 341 else if (RetVT == MVT::ppcf128) 342 return SINTTOFP_I128_PPCF128; 343 } 344 return UNKNOWN_LIBCALL; 345} 346 347/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 348/// UNKNOWN_LIBCALL if there is none. 349RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 350 if (OpVT == MVT::i32) { 351 if (RetVT == MVT::f32) 352 return UINTTOFP_I32_F32; 353 else if (RetVT == MVT::f64) 354 return UINTTOFP_I32_F64; 355 else if (RetVT == MVT::f80) 356 return UINTTOFP_I32_F80; 357 else if (RetVT == MVT::ppcf128) 358 return UINTTOFP_I32_PPCF128; 359 } else if (OpVT == MVT::i64) { 360 if (RetVT == MVT::f32) 361 return UINTTOFP_I64_F32; 362 else if (RetVT == MVT::f64) 363 return UINTTOFP_I64_F64; 364 else if (RetVT == MVT::f80) 365 return UINTTOFP_I64_F80; 366 else if (RetVT == MVT::ppcf128) 367 return UINTTOFP_I64_PPCF128; 368 } else if (OpVT == MVT::i128) { 369 if (RetVT == MVT::f32) 370 return UINTTOFP_I128_F32; 371 else if (RetVT == MVT::f64) 372 return UINTTOFP_I128_F64; 373 else if (RetVT == MVT::f80) 374 return UINTTOFP_I128_F80; 375 else if (RetVT == MVT::ppcf128) 376 return UINTTOFP_I128_PPCF128; 377 } 378 return UNKNOWN_LIBCALL; 379} 380 381/// InitCmpLibcallCCs - Set default comparison libcall CC. 382/// 383static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 384 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 385 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 386 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 387 CCs[RTLIB::UNE_F32] = ISD::SETNE; 388 CCs[RTLIB::UNE_F64] = ISD::SETNE; 389 CCs[RTLIB::OGE_F32] = ISD::SETGE; 390 CCs[RTLIB::OGE_F64] = ISD::SETGE; 391 CCs[RTLIB::OLT_F32] = ISD::SETLT; 392 CCs[RTLIB::OLT_F64] = ISD::SETLT; 393 CCs[RTLIB::OLE_F32] = ISD::SETLE; 394 CCs[RTLIB::OLE_F64] = ISD::SETLE; 395 CCs[RTLIB::OGT_F32] = ISD::SETGT; 396 CCs[RTLIB::OGT_F64] = ISD::SETGT; 397 CCs[RTLIB::UO_F32] = ISD::SETNE; 398 CCs[RTLIB::UO_F64] = ISD::SETNE; 399 CCs[RTLIB::O_F32] = ISD::SETEQ; 400 CCs[RTLIB::O_F64] = ISD::SETEQ; 401} 402 403TargetLowering::TargetLowering(TargetMachine &tm) 404 : TM(tm), TD(TM.getTargetData()) { 405 // All operations default to being supported. 406 memset(OpActions, 0, sizeof(OpActions)); 407 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 408 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 409 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 410 memset(ConvertActions, 0, sizeof(ConvertActions)); 411 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 412 413 // Set default actions for various operations. 414 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 415 // Default all indexed load / store to expand. 416 for (unsigned IM = (unsigned)ISD::PRE_INC; 417 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 418 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 419 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 420 } 421 422 // These operations default to expand. 423 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 424 } 425 426 // Most targets ignore the @llvm.prefetch intrinsic. 427 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 428 429 // ConstantFP nodes default to expand. Targets can either change this to 430 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 431 // to optimize expansions for certain constants. 432 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 433 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 434 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 435 436 // These library functions default to expand. 437 setOperationAction(ISD::FLOG , MVT::f64, Expand); 438 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 439 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 440 setOperationAction(ISD::FEXP , MVT::f64, Expand); 441 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 442 setOperationAction(ISD::FLOG , MVT::f32, Expand); 443 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 444 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 445 setOperationAction(ISD::FEXP , MVT::f32, Expand); 446 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 447 448 // Default ISD::TRAP to expand (which turns it into abort). 449 setOperationAction(ISD::TRAP, MVT::Other, Expand); 450 451 IsLittleEndian = TD->isLittleEndian(); 452 UsesGlobalOffsetTable = false; 453 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 454 ShiftAmtHandling = Undefined; 455 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 456 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 457 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 458 allowUnalignedMemoryAccesses = false; 459 UseUnderscoreSetJmp = false; 460 UseUnderscoreLongJmp = false; 461 SelectIsExpensive = false; 462 IntDivIsCheap = false; 463 Pow2DivIsCheap = false; 464 StackPointerRegisterToSaveRestore = 0; 465 ExceptionPointerRegister = 0; 466 ExceptionSelectorRegister = 0; 467 BooleanContents = UndefinedBooleanContent; 468 SchedPreferenceInfo = SchedulingForLatency; 469 JumpBufSize = 0; 470 JumpBufAlignment = 0; 471 IfCvtBlockSizeLimit = 2; 472 IfCvtDupBlockSizeLimit = 0; 473 PrefLoopAlignment = 0; 474 475 InitLibcallNames(LibcallRoutineNames); 476 InitCmpLibcallCCs(CmpLibcallCCs); 477 478 // Tell Legalize whether the assembler supports DEBUG_LOC. 479 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 480 if (!TASM || !TASM->hasDotLocAndDotFile()) 481 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 482} 483 484TargetLowering::~TargetLowering() {} 485 486/// computeRegisterProperties - Once all of the register classes are added, 487/// this allows us to compute derived properties we expose. 488void TargetLowering::computeRegisterProperties() { 489 assert(MVT::LAST_VALUETYPE <= 32 && 490 "Too many value types for ValueTypeActions to hold!"); 491 492 // Everything defaults to needing one register. 493 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 494 NumRegistersForVT[i] = 1; 495 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 496 } 497 // ...except isVoid, which doesn't need any registers. 498 NumRegistersForVT[MVT::isVoid] = 0; 499 500 // Find the largest integer register class. 501 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 502 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 503 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 504 505 // Every integer value type larger than this largest register takes twice as 506 // many registers to represent as the previous ValueType. 507 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 508 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 509 if (!EVT.isInteger()) 510 break; 511 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 512 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 513 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 514 ValueTypeActions.setTypeAction(EVT, Expand); 515 } 516 517 // Inspect all of the ValueType's smaller than the largest integer 518 // register to see which ones need promotion. 519 unsigned LegalIntReg = LargestIntReg; 520 for (unsigned IntReg = LargestIntReg - 1; 521 IntReg >= (unsigned)MVT::i1; --IntReg) { 522 MVT IVT = (MVT::SimpleValueType)IntReg; 523 if (isTypeLegal(IVT)) { 524 LegalIntReg = IntReg; 525 } else { 526 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 527 (MVT::SimpleValueType)LegalIntReg; 528 ValueTypeActions.setTypeAction(IVT, Promote); 529 } 530 } 531 532 // ppcf128 type is really two f64's. 533 if (!isTypeLegal(MVT::ppcf128)) { 534 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 535 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 536 TransformToType[MVT::ppcf128] = MVT::f64; 537 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 538 } 539 540 // Decide how to handle f64. If the target does not have native f64 support, 541 // expand it to i64 and we will be generating soft float library calls. 542 if (!isTypeLegal(MVT::f64)) { 543 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 544 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 545 TransformToType[MVT::f64] = MVT::i64; 546 ValueTypeActions.setTypeAction(MVT::f64, Expand); 547 } 548 549 // Decide how to handle f32. If the target does not have native support for 550 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 551 if (!isTypeLegal(MVT::f32)) { 552 if (isTypeLegal(MVT::f64)) { 553 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 554 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 555 TransformToType[MVT::f32] = MVT::f64; 556 ValueTypeActions.setTypeAction(MVT::f32, Promote); 557 } else { 558 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 559 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 560 TransformToType[MVT::f32] = MVT::i32; 561 ValueTypeActions.setTypeAction(MVT::f32, Expand); 562 } 563 } 564 565 // Loop over all of the vector value types to see which need transformations. 566 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 567 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 568 MVT VT = (MVT::SimpleValueType)i; 569 if (!isTypeLegal(VT)) { 570 MVT IntermediateVT, RegisterVT; 571 unsigned NumIntermediates; 572 NumRegistersForVT[i] = 573 getVectorTypeBreakdown(VT, 574 IntermediateVT, NumIntermediates, 575 RegisterVT); 576 RegisterTypeForVT[i] = RegisterVT; 577 578 // Determine if there is a legal wider type. 579 bool IsLegalWiderType = false; 580 MVT EltVT = VT.getVectorElementType(); 581 unsigned NElts = VT.getVectorNumElements(); 582 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 583 MVT SVT = (MVT::SimpleValueType)nVT; 584 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 585 SVT.getVectorNumElements() > NElts) { 586 TransformToType[i] = SVT; 587 ValueTypeActions.setTypeAction(VT, Promote); 588 IsLegalWiderType = true; 589 break; 590 } 591 } 592 if (!IsLegalWiderType) { 593 MVT NVT = VT.getPow2VectorType(); 594 if (NVT == VT) { 595 // Type is already a power of 2. The default action is to split. 596 TransformToType[i] = MVT::Other; 597 ValueTypeActions.setTypeAction(VT, Expand); 598 } else { 599 TransformToType[i] = NVT; 600 ValueTypeActions.setTypeAction(VT, Promote); 601 } 602 } 603 } 604 } 605} 606 607const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 608 return NULL; 609} 610 611 612MVT TargetLowering::getSetCCResultType(MVT VT) const { 613 return getValueType(TD->getIntPtrType()); 614} 615 616 617/// getVectorTypeBreakdown - Vector types are broken down into some number of 618/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 619/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 620/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 621/// 622/// This method returns the number of registers needed, and the VT for each 623/// register. It also returns the VT and quantity of the intermediate values 624/// before they are promoted/expanded. 625/// 626unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 627 MVT &IntermediateVT, 628 unsigned &NumIntermediates, 629 MVT &RegisterVT) const { 630 // Figure out the right, legal destination reg to copy into. 631 unsigned NumElts = VT.getVectorNumElements(); 632 MVT EltTy = VT.getVectorElementType(); 633 634 unsigned NumVectorRegs = 1; 635 636 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 637 // could break down into LHS/RHS like LegalizeDAG does. 638 if (!isPowerOf2_32(NumElts)) { 639 NumVectorRegs = NumElts; 640 NumElts = 1; 641 } 642 643 // Divide the input until we get to a supported size. This will always 644 // end with a scalar if the target doesn't support vectors. 645 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 646 NumElts >>= 1; 647 NumVectorRegs <<= 1; 648 } 649 650 NumIntermediates = NumVectorRegs; 651 652 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 653 if (!isTypeLegal(NewVT)) 654 NewVT = EltTy; 655 IntermediateVT = NewVT; 656 657 MVT DestVT = getTypeToTransformTo(NewVT); 658 RegisterVT = DestVT; 659 if (DestVT.bitsLT(NewVT)) { 660 // Value is expanded, e.g. i64 -> i16. 661 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 662 } else { 663 // Otherwise, promotion or legal types use the same number of registers as 664 // the vector decimated to the appropriate level. 665 return NumVectorRegs; 666 } 667 668 return 1; 669} 670 671/// getWidenVectorType: given a vector type, returns the type to widen to 672/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 673/// If there is no vector type that we want to widen to, returns MVT::Other 674/// When and where to widen is target dependent based on the cost of 675/// scalarizing vs using the wider vector type. 676MVT TargetLowering::getWidenVectorType(MVT VT) const { 677 assert(VT.isVector()); 678 if (isTypeLegal(VT)) 679 return VT; 680 681 // Default is not to widen until moved to LegalizeTypes 682 return MVT::Other; 683} 684 685/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 686/// function arguments in the caller parameter area. This is the actual 687/// alignment, not its logarithm. 688unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 689 return TD->getCallFrameTypeAlignment(Ty); 690} 691 692SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 693 SelectionDAG &DAG) const { 694 if (usesGlobalOffsetTable()) 695 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 696 return Table; 697} 698 699bool 700TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 701 // Assume that everything is safe in static mode. 702 if (getTargetMachine().getRelocationModel() == Reloc::Static) 703 return true; 704 705 // In dynamic-no-pic mode, assume that known defined values are safe. 706 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 707 GA && 708 !GA->getGlobal()->isDeclaration() && 709 !GA->getGlobal()->mayBeOverridden()) 710 return true; 711 712 // Otherwise assume nothing is safe. 713 return false; 714} 715 716//===----------------------------------------------------------------------===// 717// Optimization Methods 718//===----------------------------------------------------------------------===// 719 720/// ShrinkDemandedConstant - Check to see if the specified operand of the 721/// specified instruction is a constant integer. If so, check to see if there 722/// are any bits set in the constant that are not demanded. If so, shrink the 723/// constant and return true. 724bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 725 const APInt &Demanded) { 726 DebugLoc dl = Op.getDebugLoc(); 727 // FIXME: ISD::SELECT, ISD::SELECT_CC 728 switch (Op.getOpcode()) { 729 default: break; 730 case ISD::AND: 731 case ISD::OR: 732 case ISD::XOR: 733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 734 if (C->getAPIntValue().intersects(~Demanded)) { 735 MVT VT = Op.getValueType(); 736 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 737 DAG.getConstant(Demanded & 738 C->getAPIntValue(), 739 VT)); 740 return CombineTo(Op, New); 741 } 742 break; 743 } 744 return false; 745} 746 747/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 748/// DemandedMask bits of the result of Op are ever used downstream. If we can 749/// use this information to simplify Op, create a new simplified DAG node and 750/// return true, returning the original and new nodes in Old and New. Otherwise, 751/// analyze the expression and return a mask of KnownOne and KnownZero bits for 752/// the expression (used to simplify the caller). The KnownZero/One bits may 753/// only be accurate for those bits in the DemandedMask. 754bool TargetLowering::SimplifyDemandedBits(SDValue Op, 755 const APInt &DemandedMask, 756 APInt &KnownZero, 757 APInt &KnownOne, 758 TargetLoweringOpt &TLO, 759 unsigned Depth) const { 760 unsigned BitWidth = DemandedMask.getBitWidth(); 761 assert(Op.getValueSizeInBits() == BitWidth && 762 "Mask size mismatches value type size!"); 763 APInt NewMask = DemandedMask; 764 DebugLoc dl = Op.getDebugLoc(); 765 766 // Don't know anything. 767 KnownZero = KnownOne = APInt(BitWidth, 0); 768 769 // Other users may use these bits. 770 if (!Op.getNode()->hasOneUse()) { 771 if (Depth != 0) { 772 // If not at the root, Just compute the KnownZero/KnownOne bits to 773 // simplify things downstream. 774 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 775 return false; 776 } 777 // If this is the root being simplified, allow it to have multiple uses, 778 // just set the NewMask to all bits. 779 NewMask = APInt::getAllOnesValue(BitWidth); 780 } else if (DemandedMask == 0) { 781 // Not demanding any bits from Op. 782 if (Op.getOpcode() != ISD::UNDEF) 783 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 784 return false; 785 } else if (Depth == 6) { // Limit search depth. 786 return false; 787 } 788 789 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 790 switch (Op.getOpcode()) { 791 case ISD::Constant: 792 // We know all of the bits for a constant! 793 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 794 KnownZero = ~KnownOne & NewMask; 795 return false; // Don't fall through, will infinitely loop. 796 case ISD::AND: 797 // If the RHS is a constant, check to see if the LHS would be zero without 798 // using the bits from the RHS. Below, we use knowledge about the RHS to 799 // simplify the LHS, here we're using information from the LHS to simplify 800 // the RHS. 801 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 802 APInt LHSZero, LHSOne; 803 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 804 LHSZero, LHSOne, Depth+1); 805 // If the LHS already has zeros where RHSC does, this and is dead. 806 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 807 return TLO.CombineTo(Op, Op.getOperand(0)); 808 // If any of the set bits in the RHS are known zero on the LHS, shrink 809 // the constant. 810 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 811 return true; 812 } 813 814 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 815 KnownOne, TLO, Depth+1)) 816 return true; 817 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 818 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 819 KnownZero2, KnownOne2, TLO, Depth+1)) 820 return true; 821 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 822 823 // If all of the demanded bits are known one on one side, return the other. 824 // These bits cannot contribute to the result of the 'and'. 825 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 826 return TLO.CombineTo(Op, Op.getOperand(0)); 827 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 828 return TLO.CombineTo(Op, Op.getOperand(1)); 829 // If all of the demanded bits in the inputs are known zeros, return zero. 830 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 831 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 832 // If the RHS is a constant, see if we can simplify it. 833 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 834 return true; 835 836 // Output known-1 bits are only known if set in both the LHS & RHS. 837 KnownOne &= KnownOne2; 838 // Output known-0 are known to be clear if zero in either the LHS | RHS. 839 KnownZero |= KnownZero2; 840 break; 841 case ISD::OR: 842 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 843 KnownOne, TLO, Depth+1)) 844 return true; 845 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 846 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 847 KnownZero2, KnownOne2, TLO, Depth+1)) 848 return true; 849 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 850 851 // If all of the demanded bits are known zero on one side, return the other. 852 // These bits cannot contribute to the result of the 'or'. 853 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 854 return TLO.CombineTo(Op, Op.getOperand(0)); 855 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 856 return TLO.CombineTo(Op, Op.getOperand(1)); 857 // If all of the potentially set bits on one side are known to be set on 858 // the other side, just use the 'other' side. 859 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 860 return TLO.CombineTo(Op, Op.getOperand(0)); 861 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 862 return TLO.CombineTo(Op, Op.getOperand(1)); 863 // If the RHS is a constant, see if we can simplify it. 864 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 865 return true; 866 867 // Output known-0 bits are only known if clear in both the LHS & RHS. 868 KnownZero &= KnownZero2; 869 // Output known-1 are known to be set if set in either the LHS | RHS. 870 KnownOne |= KnownOne2; 871 break; 872 case ISD::XOR: 873 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 874 KnownOne, TLO, Depth+1)) 875 return true; 876 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 877 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 878 KnownOne2, TLO, Depth+1)) 879 return true; 880 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 881 882 // If all of the demanded bits are known zero on one side, return the other. 883 // These bits cannot contribute to the result of the 'xor'. 884 if ((KnownZero & NewMask) == NewMask) 885 return TLO.CombineTo(Op, Op.getOperand(0)); 886 if ((KnownZero2 & NewMask) == NewMask) 887 return TLO.CombineTo(Op, Op.getOperand(1)); 888 889 // If all of the unknown bits are known to be zero on one side or the other 890 // (but not both) turn this into an *inclusive* or. 891 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 892 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 893 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 894 Op.getOperand(0), 895 Op.getOperand(1))); 896 897 // Output known-0 bits are known if clear or set in both the LHS & RHS. 898 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 899 // Output known-1 are known to be set if set in only one of the LHS, RHS. 900 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 901 902 // If all of the demanded bits on one side are known, and all of the set 903 // bits on that side are also known to be set on the other side, turn this 904 // into an AND, as we know the bits will be cleared. 905 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 906 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 907 if ((KnownOne & KnownOne2) == KnownOne) { 908 MVT VT = Op.getValueType(); 909 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 910 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 911 Op.getOperand(0), ANDC)); 912 } 913 } 914 915 // If the RHS is a constant, see if we can simplify it. 916 // for XOR, we prefer to force bits to 1 if they will make a -1. 917 // if we can't force bits, try to shrink constant 918 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 919 APInt Expanded = C->getAPIntValue() | (~NewMask); 920 // if we can expand it to have all bits set, do it 921 if (Expanded.isAllOnesValue()) { 922 if (Expanded != C->getAPIntValue()) { 923 MVT VT = Op.getValueType(); 924 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 925 TLO.DAG.getConstant(Expanded, VT)); 926 return TLO.CombineTo(Op, New); 927 } 928 // if it already has all the bits set, nothing to change 929 // but don't shrink either! 930 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 931 return true; 932 } 933 } 934 935 KnownZero = KnownZeroOut; 936 KnownOne = KnownOneOut; 937 break; 938 case ISD::SELECT: 939 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 940 KnownOne, TLO, Depth+1)) 941 return true; 942 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 943 KnownOne2, TLO, Depth+1)) 944 return true; 945 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 946 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 947 948 // If the operands are constants, see if we can simplify them. 949 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 950 return true; 951 952 // Only known if known in both the LHS and RHS. 953 KnownOne &= KnownOne2; 954 KnownZero &= KnownZero2; 955 break; 956 case ISD::SELECT_CC: 957 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 958 KnownOne, TLO, Depth+1)) 959 return true; 960 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 961 KnownOne2, TLO, Depth+1)) 962 return true; 963 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 964 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 965 966 // If the operands are constants, see if we can simplify them. 967 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 968 return true; 969 970 // Only known if known in both the LHS and RHS. 971 KnownOne &= KnownOne2; 972 KnownZero &= KnownZero2; 973 break; 974 case ISD::SHL: 975 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 976 unsigned ShAmt = SA->getZExtValue(); 977 SDValue InOp = Op.getOperand(0); 978 979 // If the shift count is an invalid immediate, don't do anything. 980 if (ShAmt >= BitWidth) 981 break; 982 983 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 984 // single shift. We can do this if the bottom bits (which are shifted 985 // out) are never demanded. 986 if (InOp.getOpcode() == ISD::SRL && 987 isa<ConstantSDNode>(InOp.getOperand(1))) { 988 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 989 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 990 unsigned Opc = ISD::SHL; 991 int Diff = ShAmt-C1; 992 if (Diff < 0) { 993 Diff = -Diff; 994 Opc = ISD::SRL; 995 } 996 997 SDValue NewSA = 998 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 999 MVT VT = Op.getValueType(); 1000 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1001 InOp.getOperand(0), NewSA)); 1002 } 1003 } 1004 1005 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1006 KnownZero, KnownOne, TLO, Depth+1)) 1007 return true; 1008 KnownZero <<= SA->getZExtValue(); 1009 KnownOne <<= SA->getZExtValue(); 1010 // low bits known zero. 1011 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1012 } 1013 break; 1014 case ISD::SRL: 1015 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1016 MVT VT = Op.getValueType(); 1017 unsigned ShAmt = SA->getZExtValue(); 1018 unsigned VTSize = VT.getSizeInBits(); 1019 SDValue InOp = Op.getOperand(0); 1020 1021 // If the shift count is an invalid immediate, don't do anything. 1022 if (ShAmt >= BitWidth) 1023 break; 1024 1025 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1026 // single shift. We can do this if the top bits (which are shifted out) 1027 // are never demanded. 1028 if (InOp.getOpcode() == ISD::SHL && 1029 isa<ConstantSDNode>(InOp.getOperand(1))) { 1030 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1031 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1032 unsigned Opc = ISD::SRL; 1033 int Diff = ShAmt-C1; 1034 if (Diff < 0) { 1035 Diff = -Diff; 1036 Opc = ISD::SHL; 1037 } 1038 1039 SDValue NewSA = 1040 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1041 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1042 InOp.getOperand(0), NewSA)); 1043 } 1044 } 1045 1046 // Compute the new bits that are at the top now. 1047 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1048 KnownZero, KnownOne, TLO, Depth+1)) 1049 return true; 1050 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1051 KnownZero = KnownZero.lshr(ShAmt); 1052 KnownOne = KnownOne.lshr(ShAmt); 1053 1054 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1055 KnownZero |= HighBits; // High bits known zero. 1056 } 1057 break; 1058 case ISD::SRA: 1059 // If this is an arithmetic shift right and only the low-bit is set, we can 1060 // always convert this into a logical shr, even if the shift amount is 1061 // variable. The low bit of the shift cannot be an input sign bit unless 1062 // the shift amount is >= the size of the datatype, which is undefined. 1063 if (DemandedMask == 1) 1064 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1065 Op.getOperand(0), Op.getOperand(1))); 1066 1067 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1068 MVT VT = Op.getValueType(); 1069 unsigned ShAmt = SA->getZExtValue(); 1070 1071 // If the shift count is an invalid immediate, don't do anything. 1072 if (ShAmt >= BitWidth) 1073 break; 1074 1075 APInt InDemandedMask = (NewMask << ShAmt); 1076 1077 // If any of the demanded bits are produced by the sign extension, we also 1078 // demand the input sign bit. 1079 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1080 if (HighBits.intersects(NewMask)) 1081 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1082 1083 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1084 KnownZero, KnownOne, TLO, Depth+1)) 1085 return true; 1086 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1087 KnownZero = KnownZero.lshr(ShAmt); 1088 KnownOne = KnownOne.lshr(ShAmt); 1089 1090 // Handle the sign bit, adjusted to where it is now in the mask. 1091 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1092 1093 // If the input sign bit is known to be zero, or if none of the top bits 1094 // are demanded, turn this into an unsigned shift right. 1095 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1096 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1097 Op.getOperand(0), 1098 Op.getOperand(1))); 1099 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1100 KnownOne |= HighBits; 1101 } 1102 } 1103 break; 1104 case ISD::SIGN_EXTEND_INREG: { 1105 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1106 1107 // Sign extension. Compute the demanded bits in the result that are not 1108 // present in the input. 1109 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1110 BitWidth - EVT.getSizeInBits()) & 1111 NewMask; 1112 1113 // If none of the extended bits are demanded, eliminate the sextinreg. 1114 if (NewBits == 0) 1115 return TLO.CombineTo(Op, Op.getOperand(0)); 1116 1117 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1118 InSignBit.zext(BitWidth); 1119 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1120 EVT.getSizeInBits()) & 1121 NewMask; 1122 1123 // Since the sign extended bits are demanded, we know that the sign 1124 // bit is demanded. 1125 InputDemandedBits |= InSignBit; 1126 1127 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1128 KnownZero, KnownOne, TLO, Depth+1)) 1129 return true; 1130 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1131 1132 // If the sign bit of the input is known set or clear, then we know the 1133 // top bits of the result. 1134 1135 // If the input sign bit is known zero, convert this into a zero extension. 1136 if (KnownZero.intersects(InSignBit)) 1137 return TLO.CombineTo(Op, 1138 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1139 1140 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1141 KnownOne |= NewBits; 1142 KnownZero &= ~NewBits; 1143 } else { // Input sign bit unknown 1144 KnownZero &= ~NewBits; 1145 KnownOne &= ~NewBits; 1146 } 1147 break; 1148 } 1149 case ISD::ZERO_EXTEND: { 1150 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1151 APInt InMask = NewMask; 1152 InMask.trunc(OperandBitWidth); 1153 1154 // If none of the top bits are demanded, convert this into an any_extend. 1155 APInt NewBits = 1156 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1157 if (!NewBits.intersects(NewMask)) 1158 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1159 Op.getValueType(), 1160 Op.getOperand(0))); 1161 1162 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1163 KnownZero, KnownOne, TLO, Depth+1)) 1164 return true; 1165 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1166 KnownZero.zext(BitWidth); 1167 KnownOne.zext(BitWidth); 1168 KnownZero |= NewBits; 1169 break; 1170 } 1171 case ISD::SIGN_EXTEND: { 1172 MVT InVT = Op.getOperand(0).getValueType(); 1173 unsigned InBits = InVT.getSizeInBits(); 1174 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1175 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1176 APInt NewBits = ~InMask & NewMask; 1177 1178 // If none of the top bits are demanded, convert this into an any_extend. 1179 if (NewBits == 0) 1180 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1181 Op.getValueType(), 1182 Op.getOperand(0))); 1183 1184 // Since some of the sign extended bits are demanded, we know that the sign 1185 // bit is demanded. 1186 APInt InDemandedBits = InMask & NewMask; 1187 InDemandedBits |= InSignBit; 1188 InDemandedBits.trunc(InBits); 1189 1190 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1191 KnownOne, TLO, Depth+1)) 1192 return true; 1193 KnownZero.zext(BitWidth); 1194 KnownOne.zext(BitWidth); 1195 1196 // If the sign bit is known zero, convert this to a zero extend. 1197 if (KnownZero.intersects(InSignBit)) 1198 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1199 Op.getValueType(), 1200 Op.getOperand(0))); 1201 1202 // If the sign bit is known one, the top bits match. 1203 if (KnownOne.intersects(InSignBit)) { 1204 KnownOne |= NewBits; 1205 KnownZero &= ~NewBits; 1206 } else { // Otherwise, top bits aren't known. 1207 KnownOne &= ~NewBits; 1208 KnownZero &= ~NewBits; 1209 } 1210 break; 1211 } 1212 case ISD::ANY_EXTEND: { 1213 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1214 APInt InMask = NewMask; 1215 InMask.trunc(OperandBitWidth); 1216 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1217 KnownZero, KnownOne, TLO, Depth+1)) 1218 return true; 1219 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1220 KnownZero.zext(BitWidth); 1221 KnownOne.zext(BitWidth); 1222 break; 1223 } 1224 case ISD::TRUNCATE: { 1225 // Simplify the input, using demanded bit information, and compute the known 1226 // zero/one bits live out. 1227 APInt TruncMask = NewMask; 1228 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1229 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1230 KnownZero, KnownOne, TLO, Depth+1)) 1231 return true; 1232 KnownZero.trunc(BitWidth); 1233 KnownOne.trunc(BitWidth); 1234 1235 // If the input is only used by this truncate, see if we can shrink it based 1236 // on the known demanded bits. 1237 if (Op.getOperand(0).getNode()->hasOneUse()) { 1238 SDValue In = Op.getOperand(0); 1239 unsigned InBitWidth = In.getValueSizeInBits(); 1240 switch (In.getOpcode()) { 1241 default: break; 1242 case ISD::SRL: 1243 // Shrink SRL by a constant if none of the high bits shifted in are 1244 // demanded. 1245 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1246 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1247 InBitWidth - BitWidth); 1248 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1249 HighBits.trunc(BitWidth); 1250 1251 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1252 // None of the shifted in bits are needed. Add a truncate of the 1253 // shift input, then shift it. 1254 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1255 Op.getValueType(), 1256 In.getOperand(0)); 1257 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1258 Op.getValueType(), 1259 NewTrunc, 1260 In.getOperand(1))); 1261 } 1262 } 1263 break; 1264 } 1265 } 1266 1267 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1268 break; 1269 } 1270 case ISD::AssertZext: { 1271 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1272 APInt InMask = APInt::getLowBitsSet(BitWidth, 1273 VT.getSizeInBits()); 1274 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1275 KnownZero, KnownOne, TLO, Depth+1)) 1276 return true; 1277 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1278 KnownZero |= ~InMask & NewMask; 1279 break; 1280 } 1281 case ISD::BIT_CONVERT: 1282#if 0 1283 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1284 // is demanded, turn this into a FGETSIGN. 1285 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1286 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1287 !MVT::isVector(Op.getOperand(0).getValueType())) { 1288 // Only do this xform if FGETSIGN is valid or if before legalize. 1289 if (!TLO.AfterLegalize || 1290 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1291 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1292 // place. We expect the SHL to be eliminated by other optimizations. 1293 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1294 Op.getOperand(0)); 1295 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1296 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1297 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1298 Sign, ShAmt)); 1299 } 1300 } 1301#endif 1302 break; 1303 default: 1304 // Just use ComputeMaskedBits to compute output bits. 1305 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1306 break; 1307 } 1308 1309 // If we know the value of all of the demanded bits, return this as a 1310 // constant. 1311 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1312 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1313 1314 return false; 1315} 1316 1317/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1318/// in Mask are known to be either zero or one and return them in the 1319/// KnownZero/KnownOne bitsets. 1320void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1321 const APInt &Mask, 1322 APInt &KnownZero, 1323 APInt &KnownOne, 1324 const SelectionDAG &DAG, 1325 unsigned Depth) const { 1326 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1327 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1328 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1329 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1330 "Should use MaskedValueIsZero if you don't know whether Op" 1331 " is a target node!"); 1332 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1333} 1334 1335/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1336/// targets that want to expose additional information about sign bits to the 1337/// DAG Combiner. 1338unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1339 unsigned Depth) const { 1340 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1341 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1342 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1343 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1344 "Should use ComputeNumSignBits if you don't know whether Op" 1345 " is a target node!"); 1346 return 1; 1347} 1348 1349/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1350/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1351/// determine which bit is set. 1352/// 1353static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1354 // A left-shift of a constant one will have exactly one bit set, because 1355 // shifting the bit off the end is undefined. 1356 if (Val.getOpcode() == ISD::SHL) 1357 if (ConstantSDNode *C = 1358 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1359 if (C->getAPIntValue() == 1) 1360 return true; 1361 1362 // Similarly, a right-shift of a constant sign-bit will have exactly 1363 // one bit set. 1364 if (Val.getOpcode() == ISD::SRL) 1365 if (ConstantSDNode *C = 1366 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1367 if (C->getAPIntValue().isSignBit()) 1368 return true; 1369 1370 // More could be done here, though the above checks are enough 1371 // to handle some common cases. 1372 1373 // Fall back to ComputeMaskedBits to catch other known cases. 1374 MVT OpVT = Val.getValueType(); 1375 unsigned BitWidth = OpVT.getSizeInBits(); 1376 APInt Mask = APInt::getAllOnesValue(BitWidth); 1377 APInt KnownZero, KnownOne; 1378 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1379 return (KnownZero.countPopulation() == BitWidth - 1) && 1380 (KnownOne.countPopulation() == 1); 1381} 1382 1383/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1384/// and cc. If it is unable to simplify it, return a null SDValue. 1385SDValue 1386TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1387 ISD::CondCode Cond, bool foldBooleans, 1388 DAGCombinerInfo &DCI, DebugLoc dl) const { 1389 SelectionDAG &DAG = DCI.DAG; 1390 1391 // These setcc operations always fold. 1392 switch (Cond) { 1393 default: break; 1394 case ISD::SETFALSE: 1395 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1396 case ISD::SETTRUE: 1397 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1398 } 1399 1400 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1401 const APInt &C1 = N1C->getAPIntValue(); 1402 if (isa<ConstantSDNode>(N0.getNode())) { 1403 return DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1404 } else { 1405 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1406 // equality comparison, then we're just comparing whether X itself is 1407 // zero. 1408 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1409 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1410 N0.getOperand(1).getOpcode() == ISD::Constant) { 1411 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1412 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1413 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1414 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1415 // (srl (ctlz x), 5) == 0 -> X != 0 1416 // (srl (ctlz x), 5) != 1 -> X != 0 1417 Cond = ISD::SETNE; 1418 } else { 1419 // (srl (ctlz x), 5) != 0 -> X == 0 1420 // (srl (ctlz x), 5) == 1 -> X == 0 1421 Cond = ISD::SETEQ; 1422 } 1423 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1424 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1425 Zero, Cond); 1426 } 1427 } 1428 1429 // If the LHS is '(and load, const)', the RHS is 0, 1430 // the test is for equality or unsigned, and all 1 bits of the const are 1431 // in the same partial word, see if we can shorten the load. 1432 if (DCI.isBeforeLegalize() && 1433 N0.getOpcode() == ISD::AND && C1 == 0 && 1434 isa<LoadSDNode>(N0.getOperand(0)) && 1435 N0.getOperand(0).getNode()->hasOneUse() && 1436 isa<ConstantSDNode>(N0.getOperand(1))) { 1437 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1438 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1439 uint64_t bestMask = 0; 1440 unsigned bestWidth = 0, bestOffset = 0; 1441 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1442 unsigned origWidth = N0.getValueType().getSizeInBits(); 1443 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1444 // 8 bits, but have to be careful... 1445 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1446 origWidth = Lod->getMemoryVT().getSizeInBits(); 1447 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1448 uint64_t newMask = (1ULL << width) - 1; 1449 for (unsigned offset=0; offset<origWidth/width; offset++) { 1450 if ((newMask & Mask)==Mask) { 1451 if (!TD->isLittleEndian()) 1452 bestOffset = (origWidth/width - offset - 1) * (width/8); 1453 else 1454 bestOffset = (uint64_t)offset * (width/8); 1455 bestMask = Mask >> (offset * (width/8) * 8); 1456 bestWidth = width; 1457 break; 1458 } 1459 newMask = newMask << width; 1460 } 1461 } 1462 } 1463 if (bestWidth) { 1464 MVT newVT = MVT::getIntegerVT(bestWidth); 1465 if (newVT.isRound()) { 1466 MVT PtrType = Lod->getOperand(1).getValueType(); 1467 SDValue Ptr = Lod->getBasePtr(); 1468 if (bestOffset != 0) 1469 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1470 DAG.getConstant(bestOffset, PtrType)); 1471 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1472 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1473 Lod->getSrcValue(), 1474 Lod->getSrcValueOffset() + bestOffset, 1475 false, NewAlign); 1476 return DAG.getSetCC(dl, VT, 1477 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1478 DAG.getConstant(bestMask, newVT)), 1479 DAG.getConstant(0LL, newVT), Cond); 1480 } 1481 } 1482 } 1483 1484 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1485 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1486 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1487 1488 // If the comparison constant has bits in the upper part, the 1489 // zero-extended value could never match. 1490 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1491 C1.getBitWidth() - InSize))) { 1492 switch (Cond) { 1493 case ISD::SETUGT: 1494 case ISD::SETUGE: 1495 case ISD::SETEQ: return DAG.getConstant(0, VT); 1496 case ISD::SETULT: 1497 case ISD::SETULE: 1498 case ISD::SETNE: return DAG.getConstant(1, VT); 1499 case ISD::SETGT: 1500 case ISD::SETGE: 1501 // True if the sign bit of C1 is set. 1502 return DAG.getConstant(C1.isNegative(), VT); 1503 case ISD::SETLT: 1504 case ISD::SETLE: 1505 // True if the sign bit of C1 isn't set. 1506 return DAG.getConstant(C1.isNonNegative(), VT); 1507 default: 1508 break; 1509 } 1510 } 1511 1512 // Otherwise, we can perform the comparison with the low bits. 1513 switch (Cond) { 1514 case ISD::SETEQ: 1515 case ISD::SETNE: 1516 case ISD::SETUGT: 1517 case ISD::SETUGE: 1518 case ISD::SETULT: 1519 case ISD::SETULE: 1520 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1521 DAG.getConstant(APInt(C1).trunc(InSize), 1522 N0.getOperand(0).getValueType()), 1523 Cond); 1524 default: 1525 break; // todo, be more careful with signed comparisons 1526 } 1527 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1528 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1529 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1530 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1531 MVT ExtDstTy = N0.getValueType(); 1532 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1533 1534 // If the extended part has any inconsistent bits, it cannot ever 1535 // compare equal. In other words, they have to be all ones or all 1536 // zeros. 1537 APInt ExtBits = 1538 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1539 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1540 return DAG.getConstant(Cond == ISD::SETNE, VT); 1541 1542 SDValue ZextOp; 1543 MVT Op0Ty = N0.getOperand(0).getValueType(); 1544 if (Op0Ty == ExtSrcTy) { 1545 ZextOp = N0.getOperand(0); 1546 } else { 1547 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1548 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1549 DAG.getConstant(Imm, Op0Ty)); 1550 } 1551 if (!DCI.isCalledByLegalizer()) 1552 DCI.AddToWorklist(ZextOp.getNode()); 1553 // Otherwise, make this a use of a zext. 1554 return DAG.getSetCC(dl, VT, ZextOp, 1555 DAG.getConstant(C1 & APInt::getLowBitsSet( 1556 ExtDstTyBits, 1557 ExtSrcTyBits), 1558 ExtDstTy), 1559 Cond); 1560 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1561 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1562 1563 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1564 if (N0.getOpcode() == ISD::SETCC) { 1565 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1566 if (TrueWhenTrue) 1567 return N0; 1568 1569 // Invert the condition. 1570 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1571 CC = ISD::getSetCCInverse(CC, 1572 N0.getOperand(0).getValueType().isInteger()); 1573 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1574 } 1575 1576 if ((N0.getOpcode() == ISD::XOR || 1577 (N0.getOpcode() == ISD::AND && 1578 N0.getOperand(0).getOpcode() == ISD::XOR && 1579 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1580 isa<ConstantSDNode>(N0.getOperand(1)) && 1581 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1582 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1583 // can only do this if the top bits are known zero. 1584 unsigned BitWidth = N0.getValueSizeInBits(); 1585 if (DAG.MaskedValueIsZero(N0, 1586 APInt::getHighBitsSet(BitWidth, 1587 BitWidth-1))) { 1588 // Okay, get the un-inverted input value. 1589 SDValue Val; 1590 if (N0.getOpcode() == ISD::XOR) 1591 Val = N0.getOperand(0); 1592 else { 1593 assert(N0.getOpcode() == ISD::AND && 1594 N0.getOperand(0).getOpcode() == ISD::XOR); 1595 // ((X^1)&1)^1 -> X & 1 1596 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1597 N0.getOperand(0).getOperand(0), 1598 N0.getOperand(1)); 1599 } 1600 return DAG.getSetCC(dl, VT, Val, N1, 1601 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1602 } 1603 } 1604 } 1605 1606 APInt MinVal, MaxVal; 1607 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1608 if (ISD::isSignedIntSetCC(Cond)) { 1609 MinVal = APInt::getSignedMinValue(OperandBitSize); 1610 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1611 } else { 1612 MinVal = APInt::getMinValue(OperandBitSize); 1613 MaxVal = APInt::getMaxValue(OperandBitSize); 1614 } 1615 1616 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1617 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1618 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1619 // X >= C0 --> X > (C0-1) 1620 return DAG.getSetCC(dl, VT, N0, 1621 DAG.getConstant(C1-1, N1.getValueType()), 1622 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1623 } 1624 1625 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1626 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1627 // X <= C0 --> X < (C0+1) 1628 return DAG.getSetCC(dl, VT, N0, 1629 DAG.getConstant(C1+1, N1.getValueType()), 1630 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1631 } 1632 1633 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1634 return DAG.getConstant(0, VT); // X < MIN --> false 1635 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1636 return DAG.getConstant(1, VT); // X >= MIN --> true 1637 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1638 return DAG.getConstant(0, VT); // X > MAX --> false 1639 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1640 return DAG.getConstant(1, VT); // X <= MAX --> true 1641 1642 // Canonicalize setgt X, Min --> setne X, Min 1643 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1644 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1645 // Canonicalize setlt X, Max --> setne X, Max 1646 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1647 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1648 1649 // If we have setult X, 1, turn it into seteq X, 0 1650 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1651 return DAG.getSetCC(dl, VT, N0, 1652 DAG.getConstant(MinVal, N0.getValueType()), 1653 ISD::SETEQ); 1654 // If we have setugt X, Max-1, turn it into seteq X, Max 1655 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1656 return DAG.getSetCC(dl, VT, N0, 1657 DAG.getConstant(MaxVal, N0.getValueType()), 1658 ISD::SETEQ); 1659 1660 // If we have "setcc X, C0", check to see if we can shrink the immediate 1661 // by changing cc. 1662 1663 // SETUGT X, SINTMAX -> SETLT X, 0 1664 if (Cond == ISD::SETUGT && 1665 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1666 return DAG.getSetCC(dl, VT, N0, 1667 DAG.getConstant(0, N1.getValueType()), 1668 ISD::SETLT); 1669 1670 // SETULT X, SINTMIN -> SETGT X, -1 1671 if (Cond == ISD::SETULT && 1672 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1673 SDValue ConstMinusOne = 1674 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1675 N1.getValueType()); 1676 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1677 } 1678 1679 // Fold bit comparisons when we can. 1680 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1681 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1682 if (ConstantSDNode *AndRHS = 1683 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1684 MVT ShiftTy = DCI.isBeforeLegalize() ? 1685 getPointerTy() : getShiftAmountTy(); 1686 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1687 // Perform the xform if the AND RHS is a single bit. 1688 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1689 return DAG.getNode(ISD::SRL, dl, VT, N0, 1690 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1691 ShiftTy)); 1692 } 1693 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1694 // (X & 8) == 8 --> (X & 8) >> 3 1695 // Perform the xform if C1 is a single bit. 1696 if (C1.isPowerOf2()) { 1697 return DAG.getNode(ISD::SRL, dl, VT, N0, 1698 DAG.getConstant(C1.logBase2(), ShiftTy)); 1699 } 1700 } 1701 } 1702 } 1703 } else if (isa<ConstantSDNode>(N0.getNode())) { 1704 // Ensure that the constant occurs on the RHS. 1705 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1706 } 1707 1708 if (isa<ConstantFPSDNode>(N0.getNode())) { 1709 // Constant fold or commute setcc. 1710 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1711 if (O.getNode()) return O; 1712 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1713 // If the RHS of an FP comparison is a constant, simplify it away in 1714 // some cases. 1715 if (CFP->getValueAPF().isNaN()) { 1716 // If an operand is known to be a nan, we can fold it. 1717 switch (ISD::getUnorderedFlavor(Cond)) { 1718 default: assert(0 && "Unknown flavor!"); 1719 case 0: // Known false. 1720 return DAG.getConstant(0, VT); 1721 case 1: // Known true. 1722 return DAG.getConstant(1, VT); 1723 case 2: // Undefined. 1724 return DAG.getUNDEF(VT); 1725 } 1726 } 1727 1728 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1729 // constant if knowing that the operand is non-nan is enough. We prefer to 1730 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1731 // materialize 0.0. 1732 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1733 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1734 } 1735 1736 if (N0 == N1) { 1737 // We can always fold X == X for integer setcc's. 1738 if (N0.getValueType().isInteger()) 1739 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1740 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1741 if (UOF == 2) // FP operators that are undefined on NaNs. 1742 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1743 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1744 return DAG.getConstant(UOF, VT); 1745 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1746 // if it is not already. 1747 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1748 if (NewCond != Cond) 1749 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1750 } 1751 1752 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1753 N0.getValueType().isInteger()) { 1754 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1755 N0.getOpcode() == ISD::XOR) { 1756 // Simplify (X+Y) == (X+Z) --> Y == Z 1757 if (N0.getOpcode() == N1.getOpcode()) { 1758 if (N0.getOperand(0) == N1.getOperand(0)) 1759 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1760 if (N0.getOperand(1) == N1.getOperand(1)) 1761 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1762 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1763 // If X op Y == Y op X, try other combinations. 1764 if (N0.getOperand(0) == N1.getOperand(1)) 1765 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1766 Cond); 1767 if (N0.getOperand(1) == N1.getOperand(0)) 1768 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1769 Cond); 1770 } 1771 } 1772 1773 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1774 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1775 // Turn (X+C1) == C2 --> X == C2-C1 1776 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1777 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1778 DAG.getConstant(RHSC->getAPIntValue()- 1779 LHSR->getAPIntValue(), 1780 N0.getValueType()), Cond); 1781 } 1782 1783 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1784 if (N0.getOpcode() == ISD::XOR) 1785 // If we know that all of the inverted bits are zero, don't bother 1786 // performing the inversion. 1787 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1788 return 1789 DAG.getSetCC(dl, VT, N0.getOperand(0), 1790 DAG.getConstant(LHSR->getAPIntValue() ^ 1791 RHSC->getAPIntValue(), 1792 N0.getValueType()), 1793 Cond); 1794 } 1795 1796 // Turn (C1-X) == C2 --> X == C1-C2 1797 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1798 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1799 return 1800 DAG.getSetCC(dl, VT, N0.getOperand(1), 1801 DAG.getConstant(SUBC->getAPIntValue() - 1802 RHSC->getAPIntValue(), 1803 N0.getValueType()), 1804 Cond); 1805 } 1806 } 1807 } 1808 1809 // Simplify (X+Z) == X --> Z == 0 1810 if (N0.getOperand(0) == N1) 1811 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1812 DAG.getConstant(0, N0.getValueType()), Cond); 1813 if (N0.getOperand(1) == N1) { 1814 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1815 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1816 DAG.getConstant(0, N0.getValueType()), Cond); 1817 else if (N0.getNode()->hasOneUse()) { 1818 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1819 // (Z-X) == X --> Z == X<<1 1820 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1821 N1, 1822 DAG.getConstant(1, getShiftAmountTy())); 1823 if (!DCI.isCalledByLegalizer()) 1824 DCI.AddToWorklist(SH.getNode()); 1825 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1826 } 1827 } 1828 } 1829 1830 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1831 N1.getOpcode() == ISD::XOR) { 1832 // Simplify X == (X+Z) --> Z == 0 1833 if (N1.getOperand(0) == N0) { 1834 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1835 DAG.getConstant(0, N1.getValueType()), Cond); 1836 } else if (N1.getOperand(1) == N0) { 1837 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1838 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1839 DAG.getConstant(0, N1.getValueType()), Cond); 1840 } else if (N1.getNode()->hasOneUse()) { 1841 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1842 // X == (Z-X) --> X<<1 == Z 1843 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1844 DAG.getConstant(1, getShiftAmountTy())); 1845 if (!DCI.isCalledByLegalizer()) 1846 DCI.AddToWorklist(SH.getNode()); 1847 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1848 } 1849 } 1850 } 1851 1852 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1853 // Note that where y is variable and is known to have at most 1854 // one bit set (for example, if it is z&1) we cannot do this; 1855 // the expressions are not equivalent when y==0. 1856 if (N0.getOpcode() == ISD::AND) 1857 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1858 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1859 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1860 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1861 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1862 } 1863 } 1864 if (N1.getOpcode() == ISD::AND) 1865 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1866 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1867 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1868 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1869 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1870 } 1871 } 1872 } 1873 1874 // Fold away ALL boolean setcc's. 1875 SDValue Temp; 1876 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1877 switch (Cond) { 1878 default: assert(0 && "Unknown integer setcc!"); 1879 case ISD::SETEQ: // X == Y -> ~(X^Y) 1880 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1881 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1882 if (!DCI.isCalledByLegalizer()) 1883 DCI.AddToWorklist(Temp.getNode()); 1884 break; 1885 case ISD::SETNE: // X != Y --> (X^Y) 1886 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1887 break; 1888 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1889 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1890 Temp = DAG.getNOT(dl, N0, MVT::i1); 1891 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1892 if (!DCI.isCalledByLegalizer()) 1893 DCI.AddToWorklist(Temp.getNode()); 1894 break; 1895 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1896 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1897 Temp = DAG.getNOT(dl, N1, MVT::i1); 1898 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 1899 if (!DCI.isCalledByLegalizer()) 1900 DCI.AddToWorklist(Temp.getNode()); 1901 break; 1902 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1903 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1904 Temp = DAG.getNOT(dl, N0, MVT::i1); 1905 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 1906 if (!DCI.isCalledByLegalizer()) 1907 DCI.AddToWorklist(Temp.getNode()); 1908 break; 1909 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1910 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1911 Temp = DAG.getNOT(dl, N1, MVT::i1); 1912 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 1913 break; 1914 } 1915 if (VT != MVT::i1) { 1916 if (!DCI.isCalledByLegalizer()) 1917 DCI.AddToWorklist(N0.getNode()); 1918 // FIXME: If running after legalize, we probably can't do this. 1919 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 1920 } 1921 return N0; 1922 } 1923 1924 // Could not fold it. 1925 return SDValue(); 1926} 1927 1928/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1929/// node is a GlobalAddress + offset. 1930bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1931 int64_t &Offset) const { 1932 if (isa<GlobalAddressSDNode>(N)) { 1933 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1934 GA = GASD->getGlobal(); 1935 Offset += GASD->getOffset(); 1936 return true; 1937 } 1938 1939 if (N->getOpcode() == ISD::ADD) { 1940 SDValue N1 = N->getOperand(0); 1941 SDValue N2 = N->getOperand(1); 1942 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1943 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1944 if (V) { 1945 Offset += V->getSExtValue(); 1946 return true; 1947 } 1948 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1949 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1950 if (V) { 1951 Offset += V->getSExtValue(); 1952 return true; 1953 } 1954 } 1955 } 1956 return false; 1957} 1958 1959 1960/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1961/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1962/// location that the 'Base' load is loading from. 1963bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1964 unsigned Bytes, int Dist, 1965 const MachineFrameInfo *MFI) const { 1966 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) 1967 return false; 1968 MVT VT = LD->getValueType(0); 1969 if (VT.getSizeInBits() / 8 != Bytes) 1970 return false; 1971 1972 SDValue Loc = LD->getOperand(1); 1973 SDValue BaseLoc = Base->getOperand(1); 1974 if (Loc.getOpcode() == ISD::FrameIndex) { 1975 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1976 return false; 1977 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1978 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1979 int FS = MFI->getObjectSize(FI); 1980 int BFS = MFI->getObjectSize(BFI); 1981 if (FS != BFS || FS != (int)Bytes) return false; 1982 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1983 } 1984 1985 GlobalValue *GV1 = NULL; 1986 GlobalValue *GV2 = NULL; 1987 int64_t Offset1 = 0; 1988 int64_t Offset2 = 0; 1989 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 1990 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 1991 if (isGA1 && isGA2 && GV1 == GV2) 1992 return Offset1 == (Offset2 + Dist*Bytes); 1993 return false; 1994} 1995 1996 1997SDValue TargetLowering:: 1998PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1999 // Default implementation: no optimization. 2000 return SDValue(); 2001} 2002 2003//===----------------------------------------------------------------------===// 2004// Inline Assembler Implementation Methods 2005//===----------------------------------------------------------------------===// 2006 2007 2008TargetLowering::ConstraintType 2009TargetLowering::getConstraintType(const std::string &Constraint) const { 2010 // FIXME: lots more standard ones to handle. 2011 if (Constraint.size() == 1) { 2012 switch (Constraint[0]) { 2013 default: break; 2014 case 'r': return C_RegisterClass; 2015 case 'm': // memory 2016 case 'o': // offsetable 2017 case 'V': // not offsetable 2018 return C_Memory; 2019 case 'i': // Simple Integer or Relocatable Constant 2020 case 'n': // Simple Integer 2021 case 's': // Relocatable Constant 2022 case 'X': // Allow ANY value. 2023 case 'I': // Target registers. 2024 case 'J': 2025 case 'K': 2026 case 'L': 2027 case 'M': 2028 case 'N': 2029 case 'O': 2030 case 'P': 2031 return C_Other; 2032 } 2033 } 2034 2035 if (Constraint.size() > 1 && Constraint[0] == '{' && 2036 Constraint[Constraint.size()-1] == '}') 2037 return C_Register; 2038 return C_Unknown; 2039} 2040 2041/// LowerXConstraint - try to replace an X constraint, which matches anything, 2042/// with another that has more specific requirements based on the type of the 2043/// corresponding operand. 2044const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2045 if (ConstraintVT.isInteger()) 2046 return "r"; 2047 if (ConstraintVT.isFloatingPoint()) 2048 return "f"; // works for many targets 2049 return 0; 2050} 2051 2052/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2053/// vector. If it is invalid, don't add anything to Ops. 2054void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2055 char ConstraintLetter, 2056 bool hasMemory, 2057 std::vector<SDValue> &Ops, 2058 SelectionDAG &DAG) const { 2059 switch (ConstraintLetter) { 2060 default: break; 2061 case 'X': // Allows any operand; labels (basic block) use this. 2062 if (Op.getOpcode() == ISD::BasicBlock) { 2063 Ops.push_back(Op); 2064 return; 2065 } 2066 // fall through 2067 case 'i': // Simple Integer or Relocatable Constant 2068 case 'n': // Simple Integer 2069 case 's': { // Relocatable Constant 2070 // These operands are interested in values of the form (GV+C), where C may 2071 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2072 // is possible and fine if either GV or C are missing. 2073 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2074 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2075 2076 // If we have "(add GV, C)", pull out GV/C 2077 if (Op.getOpcode() == ISD::ADD) { 2078 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2079 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2080 if (C == 0 || GA == 0) { 2081 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2082 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2083 } 2084 if (C == 0 || GA == 0) 2085 C = 0, GA = 0; 2086 } 2087 2088 // If we find a valid operand, map to the TargetXXX version so that the 2089 // value itself doesn't get selected. 2090 if (GA) { // Either &GV or &GV+C 2091 if (ConstraintLetter != 'n') { 2092 int64_t Offs = GA->getOffset(); 2093 if (C) Offs += C->getZExtValue(); 2094 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2095 Op.getValueType(), Offs)); 2096 return; 2097 } 2098 } 2099 if (C) { // just C, no GV. 2100 // Simple constants are not allowed for 's'. 2101 if (ConstraintLetter != 's') { 2102 // gcc prints these as sign extended. Sign extend value to 64 bits 2103 // now; without this it would get ZExt'd later in 2104 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2105 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2106 MVT::i64)); 2107 return; 2108 } 2109 } 2110 break; 2111 } 2112 } 2113} 2114 2115std::vector<unsigned> TargetLowering:: 2116getRegClassForInlineAsmConstraint(const std::string &Constraint, 2117 MVT VT) const { 2118 return std::vector<unsigned>(); 2119} 2120 2121 2122std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2123getRegForInlineAsmConstraint(const std::string &Constraint, 2124 MVT VT) const { 2125 if (Constraint[0] != '{') 2126 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2127 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2128 2129 // Remove the braces from around the name. 2130 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2131 2132 // Figure out which register class contains this reg. 2133 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2134 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2135 E = RI->regclass_end(); RCI != E; ++RCI) { 2136 const TargetRegisterClass *RC = *RCI; 2137 2138 // If none of the the value types for this register class are valid, we 2139 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2140 bool isLegal = false; 2141 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2142 I != E; ++I) { 2143 if (isTypeLegal(*I)) { 2144 isLegal = true; 2145 break; 2146 } 2147 } 2148 2149 if (!isLegal) continue; 2150 2151 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2152 I != E; ++I) { 2153 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2154 return std::make_pair(*I, RC); 2155 } 2156 } 2157 2158 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2159} 2160 2161//===----------------------------------------------------------------------===// 2162// Constraint Selection. 2163 2164/// isMatchingInputConstraint - Return true of this is an input operand that is 2165/// a matching constraint like "4". 2166bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2167 assert(!ConstraintCode.empty() && "No known constraint!"); 2168 return isdigit(ConstraintCode[0]); 2169} 2170 2171/// getMatchedOperand - If this is an input matching constraint, this method 2172/// returns the output operand it matches. 2173unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2174 assert(!ConstraintCode.empty() && "No known constraint!"); 2175 return atoi(ConstraintCode.c_str()); 2176} 2177 2178 2179/// getConstraintGenerality - Return an integer indicating how general CT 2180/// is. 2181static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2182 switch (CT) { 2183 default: assert(0 && "Unknown constraint type!"); 2184 case TargetLowering::C_Other: 2185 case TargetLowering::C_Unknown: 2186 return 0; 2187 case TargetLowering::C_Register: 2188 return 1; 2189 case TargetLowering::C_RegisterClass: 2190 return 2; 2191 case TargetLowering::C_Memory: 2192 return 3; 2193 } 2194} 2195 2196/// ChooseConstraint - If there are multiple different constraints that we 2197/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2198/// This is somewhat tricky: constraints fall into four classes: 2199/// Other -> immediates and magic values 2200/// Register -> one specific register 2201/// RegisterClass -> a group of regs 2202/// Memory -> memory 2203/// Ideally, we would pick the most specific constraint possible: if we have 2204/// something that fits into a register, we would pick it. The problem here 2205/// is that if we have something that could either be in a register or in 2206/// memory that use of the register could cause selection of *other* 2207/// operands to fail: they might only succeed if we pick memory. Because of 2208/// this the heuristic we use is: 2209/// 2210/// 1) If there is an 'other' constraint, and if the operand is valid for 2211/// that constraint, use it. This makes us take advantage of 'i' 2212/// constraints when available. 2213/// 2) Otherwise, pick the most general constraint present. This prefers 2214/// 'm' over 'r', for example. 2215/// 2216static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2217 bool hasMemory, const TargetLowering &TLI, 2218 SDValue Op, SelectionDAG *DAG) { 2219 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2220 unsigned BestIdx = 0; 2221 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2222 int BestGenerality = -1; 2223 2224 // Loop over the options, keeping track of the most general one. 2225 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2226 TargetLowering::ConstraintType CType = 2227 TLI.getConstraintType(OpInfo.Codes[i]); 2228 2229 // If this is an 'other' constraint, see if the operand is valid for it. 2230 // For example, on X86 we might have an 'rI' constraint. If the operand 2231 // is an integer in the range [0..31] we want to use I (saving a load 2232 // of a register), otherwise we must use 'r'. 2233 if (CType == TargetLowering::C_Other && Op.getNode()) { 2234 assert(OpInfo.Codes[i].size() == 1 && 2235 "Unhandled multi-letter 'other' constraint"); 2236 std::vector<SDValue> ResultOps; 2237 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2238 ResultOps, *DAG); 2239 if (!ResultOps.empty()) { 2240 BestType = CType; 2241 BestIdx = i; 2242 break; 2243 } 2244 } 2245 2246 // This constraint letter is more general than the previous one, use it. 2247 int Generality = getConstraintGenerality(CType); 2248 if (Generality > BestGenerality) { 2249 BestType = CType; 2250 BestIdx = i; 2251 BestGenerality = Generality; 2252 } 2253 } 2254 2255 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2256 OpInfo.ConstraintType = BestType; 2257} 2258 2259/// ComputeConstraintToUse - Determines the constraint code and constraint 2260/// type to use for the specific AsmOperandInfo, setting 2261/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2262void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2263 SDValue Op, 2264 bool hasMemory, 2265 SelectionDAG *DAG) const { 2266 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2267 2268 // Single-letter constraints ('r') are very common. 2269 if (OpInfo.Codes.size() == 1) { 2270 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2271 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2272 } else { 2273 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2274 } 2275 2276 // 'X' matches anything. 2277 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2278 // Labels and constants are handled elsewhere ('X' is the only thing 2279 // that matches labels). 2280 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2281 isa<ConstantInt>(OpInfo.CallOperandVal)) 2282 return; 2283 2284 // Otherwise, try to resolve it to something we know about by looking at 2285 // the actual operand type. 2286 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2287 OpInfo.ConstraintCode = Repl; 2288 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2289 } 2290 } 2291} 2292 2293//===----------------------------------------------------------------------===// 2294// Loop Strength Reduction hooks 2295//===----------------------------------------------------------------------===// 2296 2297/// isLegalAddressingMode - Return true if the addressing mode represented 2298/// by AM is legal for this target, for a load/store of the specified type. 2299bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2300 const Type *Ty) const { 2301 // The default implementation of this implements a conservative RISCy, r+r and 2302 // r+i addr mode. 2303 2304 // Allows a sign-extended 16-bit immediate field. 2305 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2306 return false; 2307 2308 // No global is ever allowed as a base. 2309 if (AM.BaseGV) 2310 return false; 2311 2312 // Only support r+r, 2313 switch (AM.Scale) { 2314 case 0: // "r+i" or just "i", depending on HasBaseReg. 2315 break; 2316 case 1: 2317 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2318 return false; 2319 // Otherwise we have r+r or r+i. 2320 break; 2321 case 2: 2322 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2323 return false; 2324 // Allow 2*r as r+r. 2325 break; 2326 } 2327 2328 return true; 2329} 2330 2331struct mu { 2332 APInt m; // magic number 2333 bool a; // add indicator 2334 unsigned s; // shift amount 2335}; 2336 2337/// magicu - calculate the magic numbers required to codegen an integer udiv as 2338/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2339static mu magicu(const APInt& d) { 2340 unsigned p; 2341 APInt nc, delta, q1, r1, q2, r2; 2342 struct mu magu; 2343 magu.a = 0; // initialize "add" indicator 2344 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2345 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2346 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2347 2348 nc = allOnes - (-d).urem(d); 2349 p = d.getBitWidth() - 1; // initialize p 2350 q1 = signedMin.udiv(nc); // initialize q1 = 2p/nc 2351 r1 = signedMin - q1*nc; // initialize r1 = rem(2p,nc) 2352 q2 = signedMax.udiv(d); // initialize q2 = (2p-1)/d 2353 r2 = signedMax - q2*d; // initialize r2 = rem((2p-1),d) 2354 do { 2355 p = p + 1; 2356 if (r1.uge(nc - r1)) { 2357 q1 = q1 + q1 + 1; // update q1 2358 r1 = r1 + r1 - nc; // update r1 2359 } 2360 else { 2361 q1 = q1+q1; // update q1 2362 r1 = r1+r1; // update r1 2363 } 2364 if ((r2 + 1).uge(d - r2)) { 2365 if (q2.uge(signedMax)) magu.a = 1; 2366 q2 = q2+q2 + 1; // update q2 2367 r2 = r2+r2 + 1 - d; // update r2 2368 } 2369 else { 2370 if (q2.uge(signedMin)) magu.a = 1; 2371 q2 = q2+q2; // update q2 2372 r2 = r2+r2 + 1; // update r2 2373 } 2374 delta = d - 1 - r2; 2375 } while (p < d.getBitWidth()*2 && 2376 (q1.ult(delta) || (q1 == delta && r1 == 0))); 2377 magu.m = q2 + 1; // resulting magic number 2378 magu.s = p - d.getBitWidth(); // resulting shift 2379 return magu; 2380} 2381 2382// Magic for divide replacement 2383struct ms { 2384 APInt m; // magic number 2385 unsigned s; // shift amount 2386}; 2387 2388/// magic - calculate the magic numbers required to codegen an integer sdiv as 2389/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2390/// or -1. 2391static ms magic(const APInt& d) { 2392 unsigned p; 2393 APInt ad, anc, delta, q1, r1, q2, r2, t; 2394 APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()); 2395 APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); 2396 APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); 2397 struct ms mag; 2398 2399 ad = d.abs(); 2400 t = signedMin + (d.lshr(d.getBitWidth() - 1)); 2401 anc = t - 1 - t.urem(ad); // absolute value of nc 2402 p = d.getBitWidth() - 1; // initialize p 2403 q1 = signedMin.udiv(anc); // initialize q1 = 2p/abs(nc) 2404 r1 = signedMin - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2405 q2 = signedMin.udiv(ad); // initialize q2 = 2p/abs(d) 2406 r2 = signedMin - q2*ad; // initialize r2 = rem(2p,abs(d)) 2407 do { 2408 p = p + 1; 2409 q1 = q1<<1; // update q1 = 2p/abs(nc) 2410 r1 = r1<<1; // update r1 = rem(2p/abs(nc)) 2411 if (r1.uge(anc)) { // must be unsigned comparison 2412 q1 = q1 + 1; 2413 r1 = r1 - anc; 2414 } 2415 q2 = q2<<1; // update q2 = 2p/abs(d) 2416 r2 = r2<<1; // update r2 = rem(2p/abs(d)) 2417 if (r2.uge(ad)) { // must be unsigned comparison 2418 q2 = q2 + 1; 2419 r2 = r2 - ad; 2420 } 2421 delta = ad - r2; 2422 } while (q1.ule(delta) || (q1 == delta && r1 == 0)); 2423 2424 mag.m = q2 + 1; 2425 if (d.isNegative()) mag.m = -mag.m; // resulting magic number 2426 mag.s = p - d.getBitWidth(); // resulting shift 2427 return mag; 2428} 2429 2430/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2431/// return a DAG expression to select that will generate the same value by 2432/// multiplying by a magic number. See: 2433/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2434SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2435 std::vector<SDNode*>* Created) const { 2436 MVT VT = N->getValueType(0); 2437 DebugLoc dl= N->getDebugLoc(); 2438 2439 // Check to see if we can do this. 2440 // FIXME: We should be more aggressive here. 2441 if (!isTypeLegal(VT)) 2442 return SDValue(); 2443 2444 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2445 ms magics = magic(d); 2446 2447 // Multiply the numerator (operand 0) by the magic value 2448 // FIXME: We should support doing a MUL in a wider type 2449 SDValue Q; 2450 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2451 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2452 DAG.getConstant(magics.m, VT)); 2453 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2454 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2455 N->getOperand(0), 2456 DAG.getConstant(magics.m, VT)).getNode(), 1); 2457 else 2458 return SDValue(); // No mulhs or equvialent 2459 // If d > 0 and m < 0, add the numerator 2460 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2461 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2462 if (Created) 2463 Created->push_back(Q.getNode()); 2464 } 2465 // If d < 0 and m > 0, subtract the numerator. 2466 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2467 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2468 if (Created) 2469 Created->push_back(Q.getNode()); 2470 } 2471 // Shift right algebraic if shift value is nonzero 2472 if (magics.s > 0) { 2473 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2474 DAG.getConstant(magics.s, getShiftAmountTy())); 2475 if (Created) 2476 Created->push_back(Q.getNode()); 2477 } 2478 // Extract the sign bit and add it to the quotient 2479 SDValue T = 2480 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2481 getShiftAmountTy())); 2482 if (Created) 2483 Created->push_back(T.getNode()); 2484 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2485} 2486 2487/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2488/// return a DAG expression to select that will generate the same value by 2489/// multiplying by a magic number. See: 2490/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2491SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2492 std::vector<SDNode*>* Created) const { 2493 MVT VT = N->getValueType(0); 2494 DebugLoc dl = N->getDebugLoc(); 2495 2496 // Check to see if we can do this. 2497 // FIXME: We should be more aggressive here. 2498 if (!isTypeLegal(VT)) 2499 return SDValue(); 2500 2501 // FIXME: We should use a narrower constant when the upper 2502 // bits are known to be zero. 2503 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2504 mu magics = magicu(N1C->getAPIntValue()); 2505 2506 // Multiply the numerator (operand 0) by the magic value 2507 // FIXME: We should support doing a MUL in a wider type 2508 SDValue Q; 2509 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2510 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2511 DAG.getConstant(magics.m, VT)); 2512 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2513 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2514 N->getOperand(0), 2515 DAG.getConstant(magics.m, VT)).getNode(), 1); 2516 else 2517 return SDValue(); // No mulhu or equvialent 2518 if (Created) 2519 Created->push_back(Q.getNode()); 2520 2521 if (magics.a == 0) { 2522 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2523 "We shouldn't generate an undefined shift!"); 2524 return DAG.getNode(ISD::SRL, dl, VT, Q, 2525 DAG.getConstant(magics.s, getShiftAmountTy())); 2526 } else { 2527 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2528 if (Created) 2529 Created->push_back(NPQ.getNode()); 2530 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2531 DAG.getConstant(1, getShiftAmountTy())); 2532 if (Created) 2533 Created->push_back(NPQ.getNode()); 2534 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2535 if (Created) 2536 Created->push_back(NPQ.getNode()); 2537 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2538 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2539 } 2540} 2541