TargetLowering.cpp revision 9a77bb65128afa9cccbdc68d1db076eb0dc52107
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/ADT/StringExtras.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/Support/MathExtras.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_F80] = "__addxf3"; 52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 53 Names[RTLIB::SUB_F32] = "__subsf3"; 54 Names[RTLIB::SUB_F64] = "__subdf3"; 55 Names[RTLIB::SUB_F80] = "__subxf3"; 56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 57 Names[RTLIB::MUL_F32] = "__mulsf3"; 58 Names[RTLIB::MUL_F64] = "__muldf3"; 59 Names[RTLIB::MUL_F80] = "__mulxf3"; 60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 61 Names[RTLIB::DIV_F32] = "__divsf3"; 62 Names[RTLIB::DIV_F64] = "__divdf3"; 63 Names[RTLIB::DIV_F80] = "__divxf3"; 64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 65 Names[RTLIB::REM_F32] = "fmodf"; 66 Names[RTLIB::REM_F64] = "fmod"; 67 Names[RTLIB::REM_F80] = "fmodl"; 68 Names[RTLIB::REM_PPCF128] = "fmodl"; 69 Names[RTLIB::POWI_F32] = "__powisf2"; 70 Names[RTLIB::POWI_F64] = "__powidf2"; 71 Names[RTLIB::POWI_F80] = "__powixf2"; 72 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 73 Names[RTLIB::SQRT_F32] = "sqrtf"; 74 Names[RTLIB::SQRT_F64] = "sqrt"; 75 Names[RTLIB::SQRT_F80] = "sqrtl"; 76 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 77 Names[RTLIB::SIN_F32] = "sinf"; 78 Names[RTLIB::SIN_F64] = "sin"; 79 Names[RTLIB::SIN_F80] = "sinl"; 80 Names[RTLIB::SIN_PPCF128] = "sinl"; 81 Names[RTLIB::COS_F32] = "cosf"; 82 Names[RTLIB::COS_F64] = "cos"; 83 Names[RTLIB::COS_F80] = "cosl"; 84 Names[RTLIB::COS_PPCF128] = "cosl"; 85 Names[RTLIB::POW_F32] = "powf"; 86 Names[RTLIB::POW_F64] = "pow"; 87 Names[RTLIB::POW_F80] = "powl"; 88 Names[RTLIB::POW_PPCF128] = "powl"; 89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 93 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 94 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 95 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 96 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 97 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 98 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 99 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 100 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 101 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 102 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 103 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 104 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 105 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 106 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 107 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 108 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 109 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 110 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 111 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 112 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 113 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 114 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 115 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 116 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 117 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 118 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 119 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 120 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 121 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 122 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 123 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 124 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 125 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 126 Names[RTLIB::OEQ_F32] = "__eqsf2"; 127 Names[RTLIB::OEQ_F64] = "__eqdf2"; 128 Names[RTLIB::UNE_F32] = "__nesf2"; 129 Names[RTLIB::UNE_F64] = "__nedf2"; 130 Names[RTLIB::OGE_F32] = "__gesf2"; 131 Names[RTLIB::OGE_F64] = "__gedf2"; 132 Names[RTLIB::OLT_F32] = "__ltsf2"; 133 Names[RTLIB::OLT_F64] = "__ltdf2"; 134 Names[RTLIB::OLE_F32] = "__lesf2"; 135 Names[RTLIB::OLE_F64] = "__ledf2"; 136 Names[RTLIB::OGT_F32] = "__gtsf2"; 137 Names[RTLIB::OGT_F64] = "__gtdf2"; 138 Names[RTLIB::UO_F32] = "__unordsf2"; 139 Names[RTLIB::UO_F64] = "__unorddf2"; 140 Names[RTLIB::O_F32] = "__unordsf2"; 141 Names[RTLIB::O_F64] = "__unorddf2"; 142} 143 144/// InitCmpLibcallCCs - Set default comparison libcall CC. 145/// 146static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 147 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 148 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 149 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 150 CCs[RTLIB::UNE_F32] = ISD::SETNE; 151 CCs[RTLIB::UNE_F64] = ISD::SETNE; 152 CCs[RTLIB::OGE_F32] = ISD::SETGE; 153 CCs[RTLIB::OGE_F64] = ISD::SETGE; 154 CCs[RTLIB::OLT_F32] = ISD::SETLT; 155 CCs[RTLIB::OLT_F64] = ISD::SETLT; 156 CCs[RTLIB::OLE_F32] = ISD::SETLE; 157 CCs[RTLIB::OLE_F64] = ISD::SETLE; 158 CCs[RTLIB::OGT_F32] = ISD::SETGT; 159 CCs[RTLIB::OGT_F64] = ISD::SETGT; 160 CCs[RTLIB::UO_F32] = ISD::SETNE; 161 CCs[RTLIB::UO_F64] = ISD::SETNE; 162 CCs[RTLIB::O_F32] = ISD::SETEQ; 163 CCs[RTLIB::O_F64] = ISD::SETEQ; 164} 165 166TargetLowering::TargetLowering(TargetMachine &tm) 167 : TM(tm), TD(TM.getTargetData()) { 168 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 169 "Fixed size array in TargetLowering is not large enough!"); 170 // All operations default to being supported. 171 memset(OpActions, 0, sizeof(OpActions)); 172 memset(LoadXActions, 0, sizeof(LoadXActions)); 173 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 174 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 175 memset(ConvertActions, 0, sizeof(ConvertActions)); 176 177 // Set default actions for various operations. 178 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 179 // Default all indexed load / store to expand. 180 for (unsigned IM = (unsigned)ISD::PRE_INC; 181 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 182 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 183 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 184 } 185 186 // These operations default to expand. 187 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); 188 } 189 190 // Most targets ignore the @llvm.prefetch intrinsic. 191 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 192 193 // ConstantFP nodes default to expand. Targets can either change this to 194 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 195 // to optimize expansions for certain constants. 196 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 197 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 198 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 199 200 // Default ISD::TRAP to expand (which turns it into abort). 201 setOperationAction(ISD::TRAP, MVT::Other, Expand); 202 203 IsLittleEndian = TD->isLittleEndian(); 204 UsesGlobalOffsetTable = false; 205 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 206 ShiftAmtHandling = Undefined; 207 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 208 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 209 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 210 allowUnalignedMemoryAccesses = false; 211 UseUnderscoreSetJmp = false; 212 UseUnderscoreLongJmp = false; 213 SelectIsExpensive = false; 214 IntDivIsCheap = false; 215 Pow2DivIsCheap = false; 216 StackPointerRegisterToSaveRestore = 0; 217 ExceptionPointerRegister = 0; 218 ExceptionSelectorRegister = 0; 219 SetCCResultContents = UndefinedSetCCResult; 220 SchedPreferenceInfo = SchedulingForLatency; 221 JumpBufSize = 0; 222 JumpBufAlignment = 0; 223 IfCvtBlockSizeLimit = 2; 224 IfCvtDupBlockSizeLimit = 0; 225 PrefLoopAlignment = 0; 226 227 InitLibcallNames(LibcallRoutineNames); 228 InitCmpLibcallCCs(CmpLibcallCCs); 229 230 // Tell Legalize whether the assembler supports DEBUG_LOC. 231 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 232 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 233} 234 235TargetLowering::~TargetLowering() {} 236 237/// computeRegisterProperties - Once all of the register classes are added, 238/// this allows us to compute derived properties we expose. 239void TargetLowering::computeRegisterProperties() { 240 assert(MVT::LAST_VALUETYPE <= 32 && 241 "Too many value types for ValueTypeActions to hold!"); 242 243 // Everything defaults to needing one register. 244 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 245 NumRegistersForVT[i] = 1; 246 RegisterTypeForVT[i] = TransformToType[i] = i; 247 } 248 // ...except isVoid, which doesn't need any registers. 249 NumRegistersForVT[MVT::isVoid] = 0; 250 251 // Find the largest integer register class. 252 unsigned LargestIntReg = MVT::i128; 253 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 254 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 255 256 // Every integer value type larger than this largest register takes twice as 257 // many registers to represent as the previous ValueType. 258 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 259 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 260 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 261 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 262 TransformToType[ExpandedReg] = ExpandedReg - 1; 263 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 264 } 265 266 // Inspect all of the ValueType's smaller than the largest integer 267 // register to see which ones need promotion. 268 MVT::ValueType LegalIntReg = LargestIntReg; 269 for (MVT::ValueType IntReg = LargestIntReg - 1; 270 IntReg >= MVT::i1; --IntReg) { 271 if (isTypeLegal(IntReg)) { 272 LegalIntReg = IntReg; 273 } else { 274 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 275 ValueTypeActions.setTypeAction(IntReg, Promote); 276 } 277 } 278 279 // ppcf128 type is really two f64's. 280 if (!isTypeLegal(MVT::ppcf128)) { 281 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 282 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 283 TransformToType[MVT::ppcf128] = MVT::f64; 284 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 285 } 286 287 // Decide how to handle f64. If the target does not have native f64 support, 288 // expand it to i64 and we will be generating soft float library calls. 289 if (!isTypeLegal(MVT::f64)) { 290 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 291 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 292 TransformToType[MVT::f64] = MVT::i64; 293 ValueTypeActions.setTypeAction(MVT::f64, Expand); 294 } 295 296 // Decide how to handle f32. If the target does not have native support for 297 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 298 if (!isTypeLegal(MVT::f32)) { 299 if (isTypeLegal(MVT::f64)) { 300 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 301 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 302 TransformToType[MVT::f32] = MVT::f64; 303 ValueTypeActions.setTypeAction(MVT::f32, Promote); 304 } else { 305 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 306 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 307 TransformToType[MVT::f32] = MVT::i32; 308 ValueTypeActions.setTypeAction(MVT::f32, Expand); 309 } 310 } 311 312 // Loop over all of the vector value types to see which need transformations. 313 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 315 if (!isTypeLegal(i)) { 316 MVT::ValueType IntermediateVT, RegisterVT; 317 unsigned NumIntermediates; 318 NumRegistersForVT[i] = 319 getVectorTypeBreakdown(i, 320 IntermediateVT, NumIntermediates, 321 RegisterVT); 322 RegisterTypeForVT[i] = RegisterVT; 323 TransformToType[i] = MVT::Other; // this isn't actually used 324 ValueTypeActions.setTypeAction(i, Expand); 325 } 326 } 327} 328 329const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 330 return NULL; 331} 332 333 334MVT::ValueType 335TargetLowering::getSetCCResultType(const SDOperand &) const { 336 return getValueType(TD->getIntPtrType()); 337} 338 339 340/// getVectorTypeBreakdown - Vector types are broken down into some number of 341/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 342/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 343/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 344/// 345/// This method returns the number of registers needed, and the VT for each 346/// register. It also returns the VT and quantity of the intermediate values 347/// before they are promoted/expanded. 348/// 349unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 350 MVT::ValueType &IntermediateVT, 351 unsigned &NumIntermediates, 352 MVT::ValueType &RegisterVT) const { 353 // Figure out the right, legal destination reg to copy into. 354 unsigned NumElts = MVT::getVectorNumElements(VT); 355 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 356 357 unsigned NumVectorRegs = 1; 358 359 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 360 // could break down into LHS/RHS like LegalizeDAG does. 361 if (!isPowerOf2_32(NumElts)) { 362 NumVectorRegs = NumElts; 363 NumElts = 1; 364 } 365 366 // Divide the input until we get to a supported size. This will always 367 // end with a scalar if the target doesn't support vectors. 368 while (NumElts > 1 && 369 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 370 NumElts >>= 1; 371 NumVectorRegs <<= 1; 372 } 373 374 NumIntermediates = NumVectorRegs; 375 376 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 377 if (!isTypeLegal(NewVT)) 378 NewVT = EltTy; 379 IntermediateVT = NewVT; 380 381 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 382 RegisterVT = DestVT; 383 if (DestVT < NewVT) { 384 // Value is expanded, e.g. i64 -> i16. 385 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 386 } else { 387 // Otherwise, promotion or legal types use the same number of registers as 388 // the vector decimated to the appropriate level. 389 return NumVectorRegs; 390 } 391 392 return 1; 393} 394 395/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 396/// function arguments in the caller parameter area. This is the actual 397/// alignment, not its logarithm. 398unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 399 return TD->getCallFrameTypeAlignment(Ty); 400} 401 402SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 403 SelectionDAG &DAG) const { 404 if (usesGlobalOffsetTable()) 405 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 406 return Table; 407} 408 409//===----------------------------------------------------------------------===// 410// Optimization Methods 411//===----------------------------------------------------------------------===// 412 413/// ShrinkDemandedConstant - Check to see if the specified operand of the 414/// specified instruction is a constant integer. If so, check to see if there 415/// are any bits set in the constant that are not demanded. If so, shrink the 416/// constant and return true. 417bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 418 const APInt &Demanded) { 419 // FIXME: ISD::SELECT, ISD::SELECT_CC 420 switch(Op.getOpcode()) { 421 default: break; 422 case ISD::AND: 423 case ISD::OR: 424 case ISD::XOR: 425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 426 if (C->getAPIntValue().intersects(~Demanded)) { 427 MVT::ValueType VT = Op.getValueType(); 428 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 429 DAG.getConstant(Demanded & 430 C->getAPIntValue(), 431 VT)); 432 return CombineTo(Op, New); 433 } 434 break; 435 } 436 return false; 437} 438 439/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 440/// DemandedMask bits of the result of Op are ever used downstream. If we can 441/// use this information to simplify Op, create a new simplified DAG node and 442/// return true, returning the original and new nodes in Old and New. Otherwise, 443/// analyze the expression and return a mask of KnownOne and KnownZero bits for 444/// the expression (used to simplify the caller). The KnownZero/One bits may 445/// only be accurate for those bits in the DemandedMask. 446bool TargetLowering::SimplifyDemandedBits(SDOperand Op, 447 const APInt &DemandedMask, 448 APInt &KnownZero, 449 APInt &KnownOne, 450 TargetLoweringOpt &TLO, 451 unsigned Depth) const { 452 unsigned BitWidth = DemandedMask.getBitWidth(); 453 assert(Op.getValueSizeInBits() == BitWidth && 454 "Mask size mismatches value type size!"); 455 APInt NewMask = DemandedMask; 456 457 // Don't know anything. 458 KnownZero = KnownOne = APInt(BitWidth, 0); 459 460 // Other users may use these bits. 461 if (!Op.Val->hasOneUse()) { 462 if (Depth != 0) { 463 // If not at the root, Just compute the KnownZero/KnownOne bits to 464 // simplify things downstream. 465 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 466 return false; 467 } 468 // If this is the root being simplified, allow it to have multiple uses, 469 // just set the NewMask to all bits. 470 NewMask = APInt::getAllOnesValue(BitWidth); 471 } else if (DemandedMask == 0) { 472 // Not demanding any bits from Op. 473 if (Op.getOpcode() != ISD::UNDEF) 474 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 475 return false; 476 } else if (Depth == 6) { // Limit search depth. 477 return false; 478 } 479 480 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 481 switch (Op.getOpcode()) { 482 case ISD::Constant: 483 // We know all of the bits for a constant! 484 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 485 KnownZero = ~KnownOne & NewMask; 486 return false; // Don't fall through, will infinitely loop. 487 case ISD::AND: 488 // If the RHS is a constant, check to see if the LHS would be zero without 489 // using the bits from the RHS. Below, we use knowledge about the RHS to 490 // simplify the LHS, here we're using information from the LHS to simplify 491 // the RHS. 492 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 493 APInt LHSZero, LHSOne; 494 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 495 LHSZero, LHSOne, Depth+1); 496 // If the LHS already has zeros where RHSC does, this and is dead. 497 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 498 return TLO.CombineTo(Op, Op.getOperand(0)); 499 // If any of the set bits in the RHS are known zero on the LHS, shrink 500 // the constant. 501 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 502 return true; 503 } 504 505 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 506 KnownOne, TLO, Depth+1)) 507 return true; 508 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 509 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 510 KnownZero2, KnownOne2, TLO, Depth+1)) 511 return true; 512 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 513 514 // If all of the demanded bits are known one on one side, return the other. 515 // These bits cannot contribute to the result of the 'and'. 516 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 517 return TLO.CombineTo(Op, Op.getOperand(0)); 518 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 519 return TLO.CombineTo(Op, Op.getOperand(1)); 520 // If all of the demanded bits in the inputs are known zeros, return zero. 521 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 522 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 523 // If the RHS is a constant, see if we can simplify it. 524 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 525 return true; 526 527 // Output known-1 bits are only known if set in both the LHS & RHS. 528 KnownOne &= KnownOne2; 529 // Output known-0 are known to be clear if zero in either the LHS | RHS. 530 KnownZero |= KnownZero2; 531 break; 532 case ISD::OR: 533 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 534 KnownOne, TLO, Depth+1)) 535 return true; 536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 537 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 538 KnownZero2, KnownOne2, TLO, Depth+1)) 539 return true; 540 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 541 542 // If all of the demanded bits are known zero on one side, return the other. 543 // These bits cannot contribute to the result of the 'or'. 544 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 545 return TLO.CombineTo(Op, Op.getOperand(0)); 546 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 547 return TLO.CombineTo(Op, Op.getOperand(1)); 548 // If all of the potentially set bits on one side are known to be set on 549 // the other side, just use the 'other' side. 550 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 551 return TLO.CombineTo(Op, Op.getOperand(0)); 552 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 553 return TLO.CombineTo(Op, Op.getOperand(1)); 554 // If the RHS is a constant, see if we can simplify it. 555 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 556 return true; 557 558 // Output known-0 bits are only known if clear in both the LHS & RHS. 559 KnownZero &= KnownZero2; 560 // Output known-1 are known to be set if set in either the LHS | RHS. 561 KnownOne |= KnownOne2; 562 break; 563 case ISD::XOR: 564 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 565 KnownOne, TLO, Depth+1)) 566 return true; 567 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 568 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 569 KnownOne2, TLO, Depth+1)) 570 return true; 571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 572 573 // If all of the demanded bits are known zero on one side, return the other. 574 // These bits cannot contribute to the result of the 'xor'. 575 if ((KnownZero & NewMask) == NewMask) 576 return TLO.CombineTo(Op, Op.getOperand(0)); 577 if ((KnownZero2 & NewMask) == NewMask) 578 return TLO.CombineTo(Op, Op.getOperand(1)); 579 580 // If all of the unknown bits are known to be zero on one side or the other 581 // (but not both) turn this into an *inclusive* or. 582 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 583 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 585 Op.getOperand(0), 586 Op.getOperand(1))); 587 588 // Output known-0 bits are known if clear or set in both the LHS & RHS. 589 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 590 // Output known-1 are known to be set if set in only one of the LHS, RHS. 591 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 592 593 // If all of the demanded bits on one side are known, and all of the set 594 // bits on that side are also known to be set on the other side, turn this 595 // into an AND, as we know the bits will be cleared. 596 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 597 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 598 if ((KnownOne & KnownOne2) == KnownOne) { 599 MVT::ValueType VT = Op.getValueType(); 600 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 602 ANDC)); 603 } 604 } 605 606 // If the RHS is a constant, see if we can simplify it. 607 // for XOR, we prefer to force bits to 1 if they will make a -1. 608 // if we can't force bits, try to shrink constant 609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 610 APInt Expanded = C->getAPIntValue() | (~NewMask); 611 // if we can expand it to have all bits set, do it 612 if (Expanded.isAllOnesValue()) { 613 if (Expanded != C->getAPIntValue()) { 614 MVT::ValueType VT = Op.getValueType(); 615 SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 616 TLO.DAG.getConstant(Expanded, VT)); 617 return TLO.CombineTo(Op, New); 618 } 619 // if it already has all the bits set, nothing to change 620 // but don't shrink either! 621 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 622 return true; 623 } 624 } 625 626 KnownZero = KnownZeroOut; 627 KnownOne = KnownOneOut; 628 break; 629 case ISD::SELECT: 630 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 631 KnownOne, TLO, Depth+1)) 632 return true; 633 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 634 KnownOne2, TLO, Depth+1)) 635 return true; 636 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 637 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 638 639 // If the operands are constants, see if we can simplify them. 640 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 641 return true; 642 643 // Only known if known in both the LHS and RHS. 644 KnownOne &= KnownOne2; 645 KnownZero &= KnownZero2; 646 break; 647 case ISD::SELECT_CC: 648 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 649 KnownOne, TLO, Depth+1)) 650 return true; 651 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 652 KnownOne2, TLO, Depth+1)) 653 return true; 654 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 655 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 656 657 // If the operands are constants, see if we can simplify them. 658 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 659 return true; 660 661 // Only known if known in both the LHS and RHS. 662 KnownOne &= KnownOne2; 663 KnownZero &= KnownZero2; 664 break; 665 case ISD::SHL: 666 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 667 unsigned ShAmt = SA->getValue(); 668 SDOperand InOp = Op.getOperand(0); 669 670 // If the shift count is an invalid immediate, don't do anything. 671 if (ShAmt >= BitWidth) 672 break; 673 674 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 675 // single shift. We can do this if the bottom bits (which are shifted 676 // out) are never demanded. 677 if (InOp.getOpcode() == ISD::SRL && 678 isa<ConstantSDNode>(InOp.getOperand(1))) { 679 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 680 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 681 unsigned Opc = ISD::SHL; 682 int Diff = ShAmt-C1; 683 if (Diff < 0) { 684 Diff = -Diff; 685 Opc = ISD::SRL; 686 } 687 688 SDOperand NewSA = 689 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 690 MVT::ValueType VT = Op.getValueType(); 691 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 692 InOp.getOperand(0), NewSA)); 693 } 694 } 695 696 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 697 KnownZero, KnownOne, TLO, Depth+1)) 698 return true; 699 KnownZero <<= SA->getValue(); 700 KnownOne <<= SA->getValue(); 701 // low bits known zero. 702 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue()); 703 } 704 break; 705 case ISD::SRL: 706 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 707 MVT::ValueType VT = Op.getValueType(); 708 unsigned ShAmt = SA->getValue(); 709 unsigned VTSize = MVT::getSizeInBits(VT); 710 SDOperand InOp = Op.getOperand(0); 711 712 // If the shift count is an invalid immediate, don't do anything. 713 if (ShAmt >= BitWidth) 714 break; 715 716 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 717 // single shift. We can do this if the top bits (which are shifted out) 718 // are never demanded. 719 if (InOp.getOpcode() == ISD::SHL && 720 isa<ConstantSDNode>(InOp.getOperand(1))) { 721 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 722 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 723 unsigned Opc = ISD::SRL; 724 int Diff = ShAmt-C1; 725 if (Diff < 0) { 726 Diff = -Diff; 727 Opc = ISD::SHL; 728 } 729 730 SDOperand NewSA = 731 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 732 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 733 InOp.getOperand(0), NewSA)); 734 } 735 } 736 737 // Compute the new bits that are at the top now. 738 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 739 KnownZero, KnownOne, TLO, Depth+1)) 740 return true; 741 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 742 KnownZero = KnownZero.lshr(ShAmt); 743 KnownOne = KnownOne.lshr(ShAmt); 744 745 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 746 KnownZero |= HighBits; // High bits known zero. 747 } 748 break; 749 case ISD::SRA: 750 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 751 MVT::ValueType VT = Op.getValueType(); 752 unsigned ShAmt = SA->getValue(); 753 754 // If the shift count is an invalid immediate, don't do anything. 755 if (ShAmt >= BitWidth) 756 break; 757 758 APInt InDemandedMask = (NewMask << ShAmt); 759 760 // If any of the demanded bits are produced by the sign extension, we also 761 // demand the input sign bit. 762 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 763 if (HighBits.intersects(NewMask)) 764 InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT)); 765 766 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 767 KnownZero, KnownOne, TLO, Depth+1)) 768 return true; 769 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 770 KnownZero = KnownZero.lshr(ShAmt); 771 KnownOne = KnownOne.lshr(ShAmt); 772 773 // Handle the sign bit, adjusted to where it is now in the mask. 774 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 775 776 // If the input sign bit is known to be zero, or if none of the top bits 777 // are demanded, turn this into an unsigned shift right. 778 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 779 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 780 Op.getOperand(1))); 781 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 782 KnownOne |= HighBits; 783 } 784 } 785 break; 786 case ISD::SIGN_EXTEND_INREG: { 787 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 788 789 // Sign extension. Compute the demanded bits in the result that are not 790 // present in the input. 791 APInt NewBits = APInt::getHighBitsSet(BitWidth, 792 BitWidth - MVT::getSizeInBits(EVT)) & 793 NewMask; 794 795 // If none of the extended bits are demanded, eliminate the sextinreg. 796 if (NewBits == 0) 797 return TLO.CombineTo(Op, Op.getOperand(0)); 798 799 APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); 800 InSignBit.zext(BitWidth); 801 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 802 MVT::getSizeInBits(EVT)) & 803 NewMask; 804 805 // Since the sign extended bits are demanded, we know that the sign 806 // bit is demanded. 807 InputDemandedBits |= InSignBit; 808 809 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 810 KnownZero, KnownOne, TLO, Depth+1)) 811 return true; 812 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 813 814 // If the sign bit of the input is known set or clear, then we know the 815 // top bits of the result. 816 817 // If the input sign bit is known zero, convert this into a zero extension. 818 if (KnownZero.intersects(InSignBit)) 819 return TLO.CombineTo(Op, 820 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 821 822 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 823 KnownOne |= NewBits; 824 KnownZero &= ~NewBits; 825 } else { // Input sign bit unknown 826 KnownZero &= ~NewBits; 827 KnownOne &= ~NewBits; 828 } 829 break; 830 } 831 case ISD::ZERO_EXTEND: { 832 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 833 APInt InMask = NewMask; 834 InMask.trunc(OperandBitWidth); 835 836 // If none of the top bits are demanded, convert this into an any_extend. 837 APInt NewBits = 838 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 839 if (!NewBits.intersects(NewMask)) 840 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 841 Op.getValueType(), 842 Op.getOperand(0))); 843 844 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 845 KnownZero, KnownOne, TLO, Depth+1)) 846 return true; 847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 848 KnownZero.zext(BitWidth); 849 KnownOne.zext(BitWidth); 850 KnownZero |= NewBits; 851 break; 852 } 853 case ISD::SIGN_EXTEND: { 854 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 855 unsigned InBits = MVT::getSizeInBits(InVT); 856 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 857 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 858 APInt NewBits = ~InMask & NewMask; 859 860 // If none of the top bits are demanded, convert this into an any_extend. 861 if (NewBits == 0) 862 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 863 Op.getOperand(0))); 864 865 // Since some of the sign extended bits are demanded, we know that the sign 866 // bit is demanded. 867 APInt InDemandedBits = InMask & NewMask; 868 InDemandedBits |= InSignBit; 869 InDemandedBits.trunc(InBits); 870 871 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 872 KnownOne, TLO, Depth+1)) 873 return true; 874 KnownZero.zext(BitWidth); 875 KnownOne.zext(BitWidth); 876 877 // If the sign bit is known zero, convert this to a zero extend. 878 if (KnownZero.intersects(InSignBit)) 879 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 880 Op.getValueType(), 881 Op.getOperand(0))); 882 883 // If the sign bit is known one, the top bits match. 884 if (KnownOne.intersects(InSignBit)) { 885 KnownOne |= NewBits; 886 KnownZero &= ~NewBits; 887 } else { // Otherwise, top bits aren't known. 888 KnownOne &= ~NewBits; 889 KnownZero &= ~NewBits; 890 } 891 break; 892 } 893 case ISD::ANY_EXTEND: { 894 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 895 APInt InMask = NewMask; 896 InMask.trunc(OperandBitWidth); 897 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 898 KnownZero, KnownOne, TLO, Depth+1)) 899 return true; 900 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 901 KnownZero.zext(BitWidth); 902 KnownOne.zext(BitWidth); 903 break; 904 } 905 case ISD::TRUNCATE: { 906 // Simplify the input, using demanded bit information, and compute the known 907 // zero/one bits live out. 908 APInt TruncMask = NewMask; 909 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 910 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 911 KnownZero, KnownOne, TLO, Depth+1)) 912 return true; 913 KnownZero.trunc(BitWidth); 914 KnownOne.trunc(BitWidth); 915 916 // If the input is only used by this truncate, see if we can shrink it based 917 // on the known demanded bits. 918 if (Op.getOperand(0).Val->hasOneUse()) { 919 SDOperand In = Op.getOperand(0); 920 unsigned InBitWidth = In.getValueSizeInBits(); 921 switch (In.getOpcode()) { 922 default: break; 923 case ISD::SRL: 924 // Shrink SRL by a constant if none of the high bits shifted in are 925 // demanded. 926 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 927 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 928 InBitWidth - BitWidth); 929 HighBits = HighBits.lshr(ShAmt->getValue()); 930 HighBits.trunc(BitWidth); 931 932 if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) { 933 // None of the shifted in bits are needed. Add a truncate of the 934 // shift input, then shift it. 935 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 936 Op.getValueType(), 937 In.getOperand(0)); 938 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 939 NewTrunc, In.getOperand(1))); 940 } 941 } 942 break; 943 } 944 } 945 946 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 947 break; 948 } 949 case ISD::AssertZext: { 950 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 951 APInt InMask = APInt::getLowBitsSet(BitWidth, 952 MVT::getSizeInBits(VT)); 953 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 954 KnownZero, KnownOne, TLO, Depth+1)) 955 return true; 956 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 957 KnownZero |= ~InMask & NewMask; 958 break; 959 } 960 case ISD::BIT_CONVERT: 961#if 0 962 // If this is an FP->Int bitcast and if the sign bit is the only thing that 963 // is demanded, turn this into a FGETSIGN. 964 if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) && 965 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 966 !MVT::isVector(Op.getOperand(0).getValueType())) { 967 // Only do this xform if FGETSIGN is valid or if before legalize. 968 if (!TLO.AfterLegalize || 969 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 970 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 971 // place. We expect the SHL to be eliminated by other optimizations. 972 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 973 Op.getOperand(0)); 974 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; 975 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 976 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 977 Sign, ShAmt)); 978 } 979 } 980#endif 981 break; 982 default: 983 // Just use ComputeMaskedBits to compute output bits. 984 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 985 break; 986 } 987 988 // If we know the value of all of the demanded bits, return this as a 989 // constant. 990 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 991 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 992 993 return false; 994} 995 996/// computeMaskedBitsForTargetNode - Determine which of the bits specified 997/// in Mask are known to be either zero or one and return them in the 998/// KnownZero/KnownOne bitsets. 999void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1000 const APInt &Mask, 1001 APInt &KnownZero, 1002 APInt &KnownOne, 1003 const SelectionDAG &DAG, 1004 unsigned Depth) const { 1005 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1006 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1007 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1008 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1009 "Should use MaskedValueIsZero if you don't know whether Op" 1010 " is a target node!"); 1011 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1012} 1013 1014/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1015/// targets that want to expose additional information about sign bits to the 1016/// DAG Combiner. 1017unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1018 unsigned Depth) const { 1019 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1020 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1021 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1022 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1023 "Should use ComputeNumSignBits if you don't know whether Op" 1024 " is a target node!"); 1025 return 1; 1026} 1027 1028 1029/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1030/// and cc. If it is unable to simplify it, return a null SDOperand. 1031SDOperand 1032TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1033 ISD::CondCode Cond, bool foldBooleans, 1034 DAGCombinerInfo &DCI) const { 1035 SelectionDAG &DAG = DCI.DAG; 1036 1037 // These setcc operations always fold. 1038 switch (Cond) { 1039 default: break; 1040 case ISD::SETFALSE: 1041 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1042 case ISD::SETTRUE: 1043 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1044 } 1045 1046 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1047 const APInt &C1 = N1C->getAPIntValue(); 1048 if (isa<ConstantSDNode>(N0.Val)) { 1049 return DAG.FoldSetCC(VT, N0, N1, Cond); 1050 } else { 1051 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1052 // equality comparison, then we're just comparing whether X itself is 1053 // zero. 1054 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1055 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1056 N0.getOperand(1).getOpcode() == ISD::Constant) { 1057 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1058 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1059 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1060 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1061 // (srl (ctlz x), 5) == 0 -> X != 0 1062 // (srl (ctlz x), 5) != 1 -> X != 0 1063 Cond = ISD::SETNE; 1064 } else { 1065 // (srl (ctlz x), 5) != 0 -> X == 0 1066 // (srl (ctlz x), 5) == 1 -> X == 0 1067 Cond = ISD::SETEQ; 1068 } 1069 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1070 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1071 Zero, Cond); 1072 } 1073 } 1074 1075 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1076 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1077 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1078 1079 // If the comparison constant has bits in the upper part, the 1080 // zero-extended value could never match. 1081 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1082 C1.getBitWidth() - InSize))) { 1083 switch (Cond) { 1084 case ISD::SETUGT: 1085 case ISD::SETUGE: 1086 case ISD::SETEQ: return DAG.getConstant(0, VT); 1087 case ISD::SETULT: 1088 case ISD::SETULE: 1089 case ISD::SETNE: return DAG.getConstant(1, VT); 1090 case ISD::SETGT: 1091 case ISD::SETGE: 1092 // True if the sign bit of C1 is set. 1093 return DAG.getConstant(C1.isNegative(), VT); 1094 case ISD::SETLT: 1095 case ISD::SETLE: 1096 // True if the sign bit of C1 isn't set. 1097 return DAG.getConstant(C1.isNonNegative(), VT); 1098 default: 1099 break; 1100 } 1101 } 1102 1103 // Otherwise, we can perform the comparison with the low bits. 1104 switch (Cond) { 1105 case ISD::SETEQ: 1106 case ISD::SETNE: 1107 case ISD::SETUGT: 1108 case ISD::SETUGE: 1109 case ISD::SETULT: 1110 case ISD::SETULE: 1111 return DAG.getSetCC(VT, N0.getOperand(0), 1112 DAG.getConstant(APInt(C1).trunc(InSize), 1113 N0.getOperand(0).getValueType()), 1114 Cond); 1115 default: 1116 break; // todo, be more careful with signed comparisons 1117 } 1118 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1119 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1120 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1121 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1122 MVT::ValueType ExtDstTy = N0.getValueType(); 1123 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1124 1125 // If the extended part has any inconsistent bits, it cannot ever 1126 // compare equal. In other words, they have to be all ones or all 1127 // zeros. 1128 APInt ExtBits = 1129 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1130 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1131 return DAG.getConstant(Cond == ISD::SETNE, VT); 1132 1133 SDOperand ZextOp; 1134 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1135 if (Op0Ty == ExtSrcTy) { 1136 ZextOp = N0.getOperand(0); 1137 } else { 1138 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1139 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1140 DAG.getConstant(Imm, Op0Ty)); 1141 } 1142 if (!DCI.isCalledByLegalizer()) 1143 DCI.AddToWorklist(ZextOp.Val); 1144 // Otherwise, make this a use of a zext. 1145 return DAG.getSetCC(VT, ZextOp, 1146 DAG.getConstant(C1 & APInt::getLowBitsSet( 1147 ExtDstTyBits, 1148 ExtSrcTyBits), 1149 ExtDstTy), 1150 Cond); 1151 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1152 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1153 1154 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1155 if (N0.getOpcode() == ISD::SETCC) { 1156 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1157 if (TrueWhenTrue) 1158 return N0; 1159 1160 // Invert the condition. 1161 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1162 CC = ISD::getSetCCInverse(CC, 1163 MVT::isInteger(N0.getOperand(0).getValueType())); 1164 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1165 } 1166 1167 if ((N0.getOpcode() == ISD::XOR || 1168 (N0.getOpcode() == ISD::AND && 1169 N0.getOperand(0).getOpcode() == ISD::XOR && 1170 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1171 isa<ConstantSDNode>(N0.getOperand(1)) && 1172 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1173 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1174 // can only do this if the top bits are known zero. 1175 unsigned BitWidth = N0.getValueSizeInBits(); 1176 if (DAG.MaskedValueIsZero(N0, 1177 APInt::getHighBitsSet(BitWidth, 1178 BitWidth-1))) { 1179 // Okay, get the un-inverted input value. 1180 SDOperand Val; 1181 if (N0.getOpcode() == ISD::XOR) 1182 Val = N0.getOperand(0); 1183 else { 1184 assert(N0.getOpcode() == ISD::AND && 1185 N0.getOperand(0).getOpcode() == ISD::XOR); 1186 // ((X^1)&1)^1 -> X & 1 1187 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1188 N0.getOperand(0).getOperand(0), 1189 N0.getOperand(1)); 1190 } 1191 return DAG.getSetCC(VT, Val, N1, 1192 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1193 } 1194 } 1195 } 1196 1197 APInt MinVal, MaxVal; 1198 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1199 if (ISD::isSignedIntSetCC(Cond)) { 1200 MinVal = APInt::getSignedMinValue(OperandBitSize); 1201 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1202 } else { 1203 MinVal = APInt::getMinValue(OperandBitSize); 1204 MaxVal = APInt::getMaxValue(OperandBitSize); 1205 } 1206 1207 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1208 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1209 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1210 // X >= C0 --> X > (C0-1) 1211 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1212 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1213 } 1214 1215 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1216 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1217 // X <= C0 --> X < (C0+1) 1218 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1219 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1220 } 1221 1222 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1223 return DAG.getConstant(0, VT); // X < MIN --> false 1224 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1225 return DAG.getConstant(1, VT); // X >= MIN --> true 1226 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1227 return DAG.getConstant(0, VT); // X > MAX --> false 1228 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1229 return DAG.getConstant(1, VT); // X <= MAX --> true 1230 1231 // Canonicalize setgt X, Min --> setne X, Min 1232 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1233 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1234 // Canonicalize setlt X, Max --> setne X, Max 1235 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1236 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1237 1238 // If we have setult X, 1, turn it into seteq X, 0 1239 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1240 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1241 ISD::SETEQ); 1242 // If we have setugt X, Max-1, turn it into seteq X, Max 1243 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1244 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1245 ISD::SETEQ); 1246 1247 // If we have "setcc X, C0", check to see if we can shrink the immediate 1248 // by changing cc. 1249 1250 // SETUGT X, SINTMAX -> SETLT X, 0 1251 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1252 C1 == (~0ULL >> (65-OperandBitSize))) 1253 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1254 ISD::SETLT); 1255 1256 // FIXME: Implement the rest of these. 1257 1258 // Fold bit comparisons when we can. 1259 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1260 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1261 if (ConstantSDNode *AndRHS = 1262 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1263 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1264 // Perform the xform if the AND RHS is a single bit. 1265 if (isPowerOf2_64(AndRHS->getValue())) { 1266 return DAG.getNode(ISD::SRL, VT, N0, 1267 DAG.getConstant(Log2_64(AndRHS->getValue()), 1268 getShiftAmountTy())); 1269 } 1270 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1271 // (X & 8) == 8 --> (X & 8) >> 3 1272 // Perform the xform if C1 is a single bit. 1273 if (C1.isPowerOf2()) { 1274 return DAG.getNode(ISD::SRL, VT, N0, 1275 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1276 } 1277 } 1278 } 1279 } 1280 } else if (isa<ConstantSDNode>(N0.Val)) { 1281 // Ensure that the constant occurs on the RHS. 1282 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1283 } 1284 1285 if (isa<ConstantFPSDNode>(N0.Val)) { 1286 // Constant fold or commute setcc. 1287 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1288 if (O.Val) return O; 1289 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1290 // If the RHS of an FP comparison is a constant, simplify it away in 1291 // some cases. 1292 if (CFP->getValueAPF().isNaN()) { 1293 // If an operand is known to be a nan, we can fold it. 1294 switch (ISD::getUnorderedFlavor(Cond)) { 1295 default: assert(0 && "Unknown flavor!"); 1296 case 0: // Known false. 1297 return DAG.getConstant(0, VT); 1298 case 1: // Known true. 1299 return DAG.getConstant(1, VT); 1300 case 2: // Undefined. 1301 return DAG.getNode(ISD::UNDEF, VT); 1302 } 1303 } 1304 1305 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1306 // constant if knowing that the operand is non-nan is enough. We prefer to 1307 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1308 // materialize 0.0. 1309 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1310 return DAG.getSetCC(VT, N0, N0, Cond); 1311 } 1312 1313 if (N0 == N1) { 1314 // We can always fold X == X for integer setcc's. 1315 if (MVT::isInteger(N0.getValueType())) 1316 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1317 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1318 if (UOF == 2) // FP operators that are undefined on NaNs. 1319 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1320 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1321 return DAG.getConstant(UOF, VT); 1322 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1323 // if it is not already. 1324 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1325 if (NewCond != Cond) 1326 return DAG.getSetCC(VT, N0, N1, NewCond); 1327 } 1328 1329 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1330 MVT::isInteger(N0.getValueType())) { 1331 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1332 N0.getOpcode() == ISD::XOR) { 1333 // Simplify (X+Y) == (X+Z) --> Y == Z 1334 if (N0.getOpcode() == N1.getOpcode()) { 1335 if (N0.getOperand(0) == N1.getOperand(0)) 1336 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1337 if (N0.getOperand(1) == N1.getOperand(1)) 1338 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1339 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1340 // If X op Y == Y op X, try other combinations. 1341 if (N0.getOperand(0) == N1.getOperand(1)) 1342 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1343 if (N0.getOperand(1) == N1.getOperand(0)) 1344 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1345 } 1346 } 1347 1348 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1349 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1350 // Turn (X+C1) == C2 --> X == C2-C1 1351 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1352 return DAG.getSetCC(VT, N0.getOperand(0), 1353 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1354 N0.getValueType()), Cond); 1355 } 1356 1357 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1358 if (N0.getOpcode() == ISD::XOR) 1359 // If we know that all of the inverted bits are zero, don't bother 1360 // performing the inversion. 1361 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1362 return 1363 DAG.getSetCC(VT, N0.getOperand(0), 1364 DAG.getConstant(LHSR->getAPIntValue() ^ 1365 RHSC->getAPIntValue(), 1366 N0.getValueType()), 1367 Cond); 1368 } 1369 1370 // Turn (C1-X) == C2 --> X == C1-C2 1371 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1372 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1373 return 1374 DAG.getSetCC(VT, N0.getOperand(1), 1375 DAG.getConstant(SUBC->getAPIntValue() - 1376 RHSC->getAPIntValue(), 1377 N0.getValueType()), 1378 Cond); 1379 } 1380 } 1381 } 1382 1383 // Simplify (X+Z) == X --> Z == 0 1384 if (N0.getOperand(0) == N1) 1385 return DAG.getSetCC(VT, N0.getOperand(1), 1386 DAG.getConstant(0, N0.getValueType()), Cond); 1387 if (N0.getOperand(1) == N1) { 1388 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1389 return DAG.getSetCC(VT, N0.getOperand(0), 1390 DAG.getConstant(0, N0.getValueType()), Cond); 1391 else if (N0.Val->hasOneUse()) { 1392 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1393 // (Z-X) == X --> Z == X<<1 1394 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1395 N1, 1396 DAG.getConstant(1, getShiftAmountTy())); 1397 if (!DCI.isCalledByLegalizer()) 1398 DCI.AddToWorklist(SH.Val); 1399 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1400 } 1401 } 1402 } 1403 1404 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1405 N1.getOpcode() == ISD::XOR) { 1406 // Simplify X == (X+Z) --> Z == 0 1407 if (N1.getOperand(0) == N0) { 1408 return DAG.getSetCC(VT, N1.getOperand(1), 1409 DAG.getConstant(0, N1.getValueType()), Cond); 1410 } else if (N1.getOperand(1) == N0) { 1411 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1412 return DAG.getSetCC(VT, N1.getOperand(0), 1413 DAG.getConstant(0, N1.getValueType()), Cond); 1414 } else if (N1.Val->hasOneUse()) { 1415 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1416 // X == (Z-X) --> X<<1 == Z 1417 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1418 DAG.getConstant(1, getShiftAmountTy())); 1419 if (!DCI.isCalledByLegalizer()) 1420 DCI.AddToWorklist(SH.Val); 1421 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1422 } 1423 } 1424 } 1425 } 1426 1427 // Fold away ALL boolean setcc's. 1428 SDOperand Temp; 1429 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1430 switch (Cond) { 1431 default: assert(0 && "Unknown integer setcc!"); 1432 case ISD::SETEQ: // X == Y -> (X^Y)^1 1433 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1434 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1435 if (!DCI.isCalledByLegalizer()) 1436 DCI.AddToWorklist(Temp.Val); 1437 break; 1438 case ISD::SETNE: // X != Y --> (X^Y) 1439 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1440 break; 1441 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1442 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1443 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1444 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1445 if (!DCI.isCalledByLegalizer()) 1446 DCI.AddToWorklist(Temp.Val); 1447 break; 1448 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1449 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1450 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1451 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1452 if (!DCI.isCalledByLegalizer()) 1453 DCI.AddToWorklist(Temp.Val); 1454 break; 1455 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1456 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1457 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1458 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1459 if (!DCI.isCalledByLegalizer()) 1460 DCI.AddToWorklist(Temp.Val); 1461 break; 1462 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1463 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1464 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1465 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1466 break; 1467 } 1468 if (VT != MVT::i1) { 1469 if (!DCI.isCalledByLegalizer()) 1470 DCI.AddToWorklist(N0.Val); 1471 // FIXME: If running after legalize, we probably can't do this. 1472 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1473 } 1474 return N0; 1475 } 1476 1477 // Could not fold it. 1478 return SDOperand(); 1479} 1480 1481SDOperand TargetLowering:: 1482PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1483 // Default implementation: no optimization. 1484 return SDOperand(); 1485} 1486 1487//===----------------------------------------------------------------------===// 1488// Inline Assembler Implementation Methods 1489//===----------------------------------------------------------------------===// 1490 1491 1492TargetLowering::ConstraintType 1493TargetLowering::getConstraintType(const std::string &Constraint) const { 1494 // FIXME: lots more standard ones to handle. 1495 if (Constraint.size() == 1) { 1496 switch (Constraint[0]) { 1497 default: break; 1498 case 'r': return C_RegisterClass; 1499 case 'm': // memory 1500 case 'o': // offsetable 1501 case 'V': // not offsetable 1502 return C_Memory; 1503 case 'i': // Simple Integer or Relocatable Constant 1504 case 'n': // Simple Integer 1505 case 's': // Relocatable Constant 1506 case 'X': // Allow ANY value. 1507 case 'I': // Target registers. 1508 case 'J': 1509 case 'K': 1510 case 'L': 1511 case 'M': 1512 case 'N': 1513 case 'O': 1514 case 'P': 1515 return C_Other; 1516 } 1517 } 1518 1519 if (Constraint.size() > 1 && Constraint[0] == '{' && 1520 Constraint[Constraint.size()-1] == '}') 1521 return C_Register; 1522 return C_Unknown; 1523} 1524 1525/// LowerXConstraint - try to replace an X constraint, which matches anything, 1526/// with another that has more specific requirements based on the type of the 1527/// corresponding operand. 1528const char *TargetLowering::LowerXConstraint(MVT::ValueType ConstraintVT) const{ 1529 if (MVT::isInteger(ConstraintVT)) 1530 return "r"; 1531 if (MVT::isFloatingPoint(ConstraintVT)) 1532 return "f"; // works for many targets 1533 return 0; 1534} 1535 1536/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1537/// vector. If it is invalid, don't add anything to Ops. 1538void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1539 char ConstraintLetter, 1540 std::vector<SDOperand> &Ops, 1541 SelectionDAG &DAG) const { 1542 switch (ConstraintLetter) { 1543 default: break; 1544 case 'X': // Allows any operand; labels (basic block) use this. 1545 if (Op.getOpcode() == ISD::BasicBlock) { 1546 Ops.push_back(Op); 1547 return; 1548 } 1549 // fall through 1550 case 'i': // Simple Integer or Relocatable Constant 1551 case 'n': // Simple Integer 1552 case 's': { // Relocatable Constant 1553 // These operands are interested in values of the form (GV+C), where C may 1554 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1555 // is possible and fine if either GV or C are missing. 1556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1557 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1558 1559 // If we have "(add GV, C)", pull out GV/C 1560 if (Op.getOpcode() == ISD::ADD) { 1561 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1562 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1563 if (C == 0 || GA == 0) { 1564 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1565 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1566 } 1567 if (C == 0 || GA == 0) 1568 C = 0, GA = 0; 1569 } 1570 1571 // If we find a valid operand, map to the TargetXXX version so that the 1572 // value itself doesn't get selected. 1573 if (GA) { // Either &GV or &GV+C 1574 if (ConstraintLetter != 'n') { 1575 int64_t Offs = GA->getOffset(); 1576 if (C) Offs += C->getValue(); 1577 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1578 Op.getValueType(), Offs)); 1579 return; 1580 } 1581 } 1582 if (C) { // just C, no GV. 1583 // Simple constants are not allowed for 's'. 1584 if (ConstraintLetter != 's') { 1585 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1586 return; 1587 } 1588 } 1589 break; 1590 } 1591 } 1592} 1593 1594std::vector<unsigned> TargetLowering:: 1595getRegClassForInlineAsmConstraint(const std::string &Constraint, 1596 MVT::ValueType VT) const { 1597 return std::vector<unsigned>(); 1598} 1599 1600 1601std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1602getRegForInlineAsmConstraint(const std::string &Constraint, 1603 MVT::ValueType VT) const { 1604 if (Constraint[0] != '{') 1605 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1606 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1607 1608 // Remove the braces from around the name. 1609 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1610 1611 // Figure out which register class contains this reg. 1612 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1613 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1614 E = RI->regclass_end(); RCI != E; ++RCI) { 1615 const TargetRegisterClass *RC = *RCI; 1616 1617 // If none of the the value types for this register class are valid, we 1618 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1619 bool isLegal = false; 1620 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1621 I != E; ++I) { 1622 if (isTypeLegal(*I)) { 1623 isLegal = true; 1624 break; 1625 } 1626 } 1627 1628 if (!isLegal) continue; 1629 1630 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1631 I != E; ++I) { 1632 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1633 return std::make_pair(*I, RC); 1634 } 1635 } 1636 1637 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1638} 1639 1640//===----------------------------------------------------------------------===// 1641// Constraint Selection. 1642 1643/// getConstraintGenerality - Return an integer indicating how general CT 1644/// is. 1645static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 1646 switch (CT) { 1647 default: assert(0 && "Unknown constraint type!"); 1648 case TargetLowering::C_Other: 1649 case TargetLowering::C_Unknown: 1650 return 0; 1651 case TargetLowering::C_Register: 1652 return 1; 1653 case TargetLowering::C_RegisterClass: 1654 return 2; 1655 case TargetLowering::C_Memory: 1656 return 3; 1657 } 1658} 1659 1660/// ChooseConstraint - If there are multiple different constraints that we 1661/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 1662/// This is somewhat tricky: constraints fall into four classes: 1663/// Other -> immediates and magic values 1664/// Register -> one specific register 1665/// RegisterClass -> a group of regs 1666/// Memory -> memory 1667/// Ideally, we would pick the most specific constraint possible: if we have 1668/// something that fits into a register, we would pick it. The problem here 1669/// is that if we have something that could either be in a register or in 1670/// memory that use of the register could cause selection of *other* 1671/// operands to fail: they might only succeed if we pick memory. Because of 1672/// this the heuristic we use is: 1673/// 1674/// 1) If there is an 'other' constraint, and if the operand is valid for 1675/// that constraint, use it. This makes us take advantage of 'i' 1676/// constraints when available. 1677/// 2) Otherwise, pick the most general constraint present. This prefers 1678/// 'm' over 'r', for example. 1679/// 1680static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 1681 const TargetLowering &TLI, 1682 SDOperand Op, SelectionDAG *DAG) { 1683 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 1684 unsigned BestIdx = 0; 1685 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 1686 int BestGenerality = -1; 1687 1688 // Loop over the options, keeping track of the most general one. 1689 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 1690 TargetLowering::ConstraintType CType = 1691 TLI.getConstraintType(OpInfo.Codes[i]); 1692 1693 // If this is an 'other' constraint, see if the operand is valid for it. 1694 // For example, on X86 we might have an 'rI' constraint. If the operand 1695 // is an integer in the range [0..31] we want to use I (saving a load 1696 // of a register), otherwise we must use 'r'. 1697 if (CType == TargetLowering::C_Other && Op.Val) { 1698 assert(OpInfo.Codes[i].size() == 1 && 1699 "Unhandled multi-letter 'other' constraint"); 1700 std::vector<SDOperand> ResultOps; 1701 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 1702 ResultOps, *DAG); 1703 if (!ResultOps.empty()) { 1704 BestType = CType; 1705 BestIdx = i; 1706 break; 1707 } 1708 } 1709 1710 // This constraint letter is more general than the previous one, use it. 1711 int Generality = getConstraintGenerality(CType); 1712 if (Generality > BestGenerality) { 1713 BestType = CType; 1714 BestIdx = i; 1715 BestGenerality = Generality; 1716 } 1717 } 1718 1719 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 1720 OpInfo.ConstraintType = BestType; 1721} 1722 1723/// ComputeConstraintToUse - Determines the constraint code and constraint 1724/// type to use for the specific AsmOperandInfo, setting 1725/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 1726void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1727 SDOperand Op, 1728 SelectionDAG *DAG) const { 1729 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 1730 1731 // Single-letter constraints ('r') are very common. 1732 if (OpInfo.Codes.size() == 1) { 1733 OpInfo.ConstraintCode = OpInfo.Codes[0]; 1734 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 1735 } else { 1736 ChooseConstraint(OpInfo, *this, Op, DAG); 1737 } 1738 1739 // 'X' matches anything. 1740 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 1741 // Labels and constants are handled elsewhere ('X' is the only thing 1742 // that matches labels). 1743 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 1744 isa<ConstantInt>(OpInfo.CallOperandVal)) 1745 return; 1746 1747 // Otherwise, try to resolve it to something we know about by looking at 1748 // the actual operand type. 1749 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 1750 OpInfo.ConstraintCode = Repl; 1751 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 1752 } 1753 } 1754} 1755 1756//===----------------------------------------------------------------------===// 1757// Loop Strength Reduction hooks 1758//===----------------------------------------------------------------------===// 1759 1760/// isLegalAddressingMode - Return true if the addressing mode represented 1761/// by AM is legal for this target, for a load/store of the specified type. 1762bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1763 const Type *Ty) const { 1764 // The default implementation of this implements a conservative RISCy, r+r and 1765 // r+i addr mode. 1766 1767 // Allows a sign-extended 16-bit immediate field. 1768 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1769 return false; 1770 1771 // No global is ever allowed as a base. 1772 if (AM.BaseGV) 1773 return false; 1774 1775 // Only support r+r, 1776 switch (AM.Scale) { 1777 case 0: // "r+i" or just "i", depending on HasBaseReg. 1778 break; 1779 case 1: 1780 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1781 return false; 1782 // Otherwise we have r+r or r+i. 1783 break; 1784 case 2: 1785 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1786 return false; 1787 // Allow 2*r as r+r. 1788 break; 1789 } 1790 1791 return true; 1792} 1793 1794// Magic for divide replacement 1795 1796struct ms { 1797 int64_t m; // magic number 1798 int64_t s; // shift amount 1799}; 1800 1801struct mu { 1802 uint64_t m; // magic number 1803 int64_t a; // add indicator 1804 int64_t s; // shift amount 1805}; 1806 1807/// magic - calculate the magic numbers required to codegen an integer sdiv as 1808/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1809/// or -1. 1810static ms magic32(int32_t d) { 1811 int32_t p; 1812 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1813 const uint32_t two31 = 0x80000000U; 1814 struct ms mag; 1815 1816 ad = abs(d); 1817 t = two31 + ((uint32_t)d >> 31); 1818 anc = t - 1 - t%ad; // absolute value of nc 1819 p = 31; // initialize p 1820 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1821 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1822 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1823 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1824 do { 1825 p = p + 1; 1826 q1 = 2*q1; // update q1 = 2p/abs(nc) 1827 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1828 if (r1 >= anc) { // must be unsigned comparison 1829 q1 = q1 + 1; 1830 r1 = r1 - anc; 1831 } 1832 q2 = 2*q2; // update q2 = 2p/abs(d) 1833 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1834 if (r2 >= ad) { // must be unsigned comparison 1835 q2 = q2 + 1; 1836 r2 = r2 - ad; 1837 } 1838 delta = ad - r2; 1839 } while (q1 < delta || (q1 == delta && r1 == 0)); 1840 1841 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1842 if (d < 0) mag.m = -mag.m; // resulting magic number 1843 mag.s = p - 32; // resulting shift 1844 return mag; 1845} 1846 1847/// magicu - calculate the magic numbers required to codegen an integer udiv as 1848/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1849static mu magicu32(uint32_t d) { 1850 int32_t p; 1851 uint32_t nc, delta, q1, r1, q2, r2; 1852 struct mu magu; 1853 magu.a = 0; // initialize "add" indicator 1854 nc = - 1 - (-d)%d; 1855 p = 31; // initialize p 1856 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1857 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1858 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1859 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1860 do { 1861 p = p + 1; 1862 if (r1 >= nc - r1 ) { 1863 q1 = 2*q1 + 1; // update q1 1864 r1 = 2*r1 - nc; // update r1 1865 } 1866 else { 1867 q1 = 2*q1; // update q1 1868 r1 = 2*r1; // update r1 1869 } 1870 if (r2 + 1 >= d - r2) { 1871 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1872 q2 = 2*q2 + 1; // update q2 1873 r2 = 2*r2 + 1 - d; // update r2 1874 } 1875 else { 1876 if (q2 >= 0x80000000) magu.a = 1; 1877 q2 = 2*q2; // update q2 1878 r2 = 2*r2 + 1; // update r2 1879 } 1880 delta = d - 1 - r2; 1881 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1882 magu.m = q2 + 1; // resulting magic number 1883 magu.s = p - 32; // resulting shift 1884 return magu; 1885} 1886 1887/// magic - calculate the magic numbers required to codegen an integer sdiv as 1888/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1889/// or -1. 1890static ms magic64(int64_t d) { 1891 int64_t p; 1892 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1893 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1894 struct ms mag; 1895 1896 ad = d >= 0 ? d : -d; 1897 t = two63 + ((uint64_t)d >> 63); 1898 anc = t - 1 - t%ad; // absolute value of nc 1899 p = 63; // initialize p 1900 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1901 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1902 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1903 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1904 do { 1905 p = p + 1; 1906 q1 = 2*q1; // update q1 = 2p/abs(nc) 1907 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1908 if (r1 >= anc) { // must be unsigned comparison 1909 q1 = q1 + 1; 1910 r1 = r1 - anc; 1911 } 1912 q2 = 2*q2; // update q2 = 2p/abs(d) 1913 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1914 if (r2 >= ad) { // must be unsigned comparison 1915 q2 = q2 + 1; 1916 r2 = r2 - ad; 1917 } 1918 delta = ad - r2; 1919 } while (q1 < delta || (q1 == delta && r1 == 0)); 1920 1921 mag.m = q2 + 1; 1922 if (d < 0) mag.m = -mag.m; // resulting magic number 1923 mag.s = p - 64; // resulting shift 1924 return mag; 1925} 1926 1927/// magicu - calculate the magic numbers required to codegen an integer udiv as 1928/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1929static mu magicu64(uint64_t d) 1930{ 1931 int64_t p; 1932 uint64_t nc, delta, q1, r1, q2, r2; 1933 struct mu magu; 1934 magu.a = 0; // initialize "add" indicator 1935 nc = - 1 - (-d)%d; 1936 p = 63; // initialize p 1937 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1938 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1939 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1940 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1941 do { 1942 p = p + 1; 1943 if (r1 >= nc - r1 ) { 1944 q1 = 2*q1 + 1; // update q1 1945 r1 = 2*r1 - nc; // update r1 1946 } 1947 else { 1948 q1 = 2*q1; // update q1 1949 r1 = 2*r1; // update r1 1950 } 1951 if (r2 + 1 >= d - r2) { 1952 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1953 q2 = 2*q2 + 1; // update q2 1954 r2 = 2*r2 + 1 - d; // update r2 1955 } 1956 else { 1957 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1958 q2 = 2*q2; // update q2 1959 r2 = 2*r2 + 1; // update r2 1960 } 1961 delta = d - 1 - r2; 1962 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1963 magu.m = q2 + 1; // resulting magic number 1964 magu.s = p - 64; // resulting shift 1965 return magu; 1966} 1967 1968/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1969/// return a DAG expression to select that will generate the same value by 1970/// multiplying by a magic number. See: 1971/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1972SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1973 std::vector<SDNode*>* Created) const { 1974 MVT::ValueType VT = N->getValueType(0); 1975 1976 // Check to see if we can do this. 1977 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1978 return SDOperand(); // BuildSDIV only operates on i32 or i64 1979 1980 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1981 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1982 1983 // Multiply the numerator (operand 0) by the magic value 1984 SDOperand Q; 1985 if (isOperationLegal(ISD::MULHS, VT)) 1986 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1987 DAG.getConstant(magics.m, VT)); 1988 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1989 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1990 N->getOperand(0), 1991 DAG.getConstant(magics.m, VT)).Val, 1); 1992 else 1993 return SDOperand(); // No mulhs or equvialent 1994 // If d > 0 and m < 0, add the numerator 1995 if (d > 0 && magics.m < 0) { 1996 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1997 if (Created) 1998 Created->push_back(Q.Val); 1999 } 2000 // If d < 0 and m > 0, subtract the numerator. 2001 if (d < 0 && magics.m > 0) { 2002 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2003 if (Created) 2004 Created->push_back(Q.Val); 2005 } 2006 // Shift right algebraic if shift value is nonzero 2007 if (magics.s > 0) { 2008 Q = DAG.getNode(ISD::SRA, VT, Q, 2009 DAG.getConstant(magics.s, getShiftAmountTy())); 2010 if (Created) 2011 Created->push_back(Q.Val); 2012 } 2013 // Extract the sign bit and add it to the quotient 2014 SDOperand T = 2015 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2016 getShiftAmountTy())); 2017 if (Created) 2018 Created->push_back(T.Val); 2019 return DAG.getNode(ISD::ADD, VT, Q, T); 2020} 2021 2022/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2023/// return a DAG expression to select that will generate the same value by 2024/// multiplying by a magic number. See: 2025/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2026SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2027 std::vector<SDNode*>* Created) const { 2028 MVT::ValueType VT = N->getValueType(0); 2029 2030 // Check to see if we can do this. 2031 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2032 return SDOperand(); // BuildUDIV only operates on i32 or i64 2033 2034 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2035 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2036 2037 // Multiply the numerator (operand 0) by the magic value 2038 SDOperand Q; 2039 if (isOperationLegal(ISD::MULHU, VT)) 2040 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2041 DAG.getConstant(magics.m, VT)); 2042 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2043 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2044 N->getOperand(0), 2045 DAG.getConstant(magics.m, VT)).Val, 1); 2046 else 2047 return SDOperand(); // No mulhu or equvialent 2048 if (Created) 2049 Created->push_back(Q.Val); 2050 2051 if (magics.a == 0) { 2052 return DAG.getNode(ISD::SRL, VT, Q, 2053 DAG.getConstant(magics.s, getShiftAmountTy())); 2054 } else { 2055 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2056 if (Created) 2057 Created->push_back(NPQ.Val); 2058 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2059 DAG.getConstant(1, getShiftAmountTy())); 2060 if (Created) 2061 Created->push_back(NPQ.Val); 2062 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2063 if (Created) 2064 Created->push_back(NPQ.Val); 2065 return DAG.getNode(ISD::SRL, VT, NPQ, 2066 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2067 } 2068} 2069