TargetLowering.cpp revision a2e9485e34f1348526ed104dbdc194673e291077
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/CallingConv.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/ADT/StringExtras.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/Support/MathExtras.h" 26using namespace llvm; 27 28/// InitLibcallNames - Set default libcall names. 29/// 30static void InitLibcallNames(const char **Names) { 31 Names[RTLIB::SHL_I32] = "__ashlsi3"; 32 Names[RTLIB::SHL_I64] = "__ashldi3"; 33 Names[RTLIB::SRL_I32] = "__lshrsi3"; 34 Names[RTLIB::SRL_I64] = "__lshrdi3"; 35 Names[RTLIB::SRA_I32] = "__ashrsi3"; 36 Names[RTLIB::SRA_I64] = "__ashrdi3"; 37 Names[RTLIB::MUL_I32] = "__mulsi3"; 38 Names[RTLIB::MUL_I64] = "__muldi3"; 39 Names[RTLIB::SDIV_I32] = "__divsi3"; 40 Names[RTLIB::SDIV_I64] = "__divdi3"; 41 Names[RTLIB::UDIV_I32] = "__udivsi3"; 42 Names[RTLIB::UDIV_I64] = "__udivdi3"; 43 Names[RTLIB::SREM_I32] = "__modsi3"; 44 Names[RTLIB::SREM_I64] = "__moddi3"; 45 Names[RTLIB::UREM_I32] = "__umodsi3"; 46 Names[RTLIB::UREM_I64] = "__umoddi3"; 47 Names[RTLIB::NEG_I32] = "__negsi2"; 48 Names[RTLIB::NEG_I64] = "__negdi2"; 49 Names[RTLIB::ADD_F32] = "__addsf3"; 50 Names[RTLIB::ADD_F64] = "__adddf3"; 51 Names[RTLIB::ADD_F80] = "__addxf3"; 52 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 53 Names[RTLIB::SUB_F32] = "__subsf3"; 54 Names[RTLIB::SUB_F64] = "__subdf3"; 55 Names[RTLIB::SUB_F80] = "__subxf3"; 56 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 57 Names[RTLIB::MUL_F32] = "__mulsf3"; 58 Names[RTLIB::MUL_F64] = "__muldf3"; 59 Names[RTLIB::MUL_F80] = "__mulxf3"; 60 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 61 Names[RTLIB::DIV_F32] = "__divsf3"; 62 Names[RTLIB::DIV_F64] = "__divdf3"; 63 Names[RTLIB::DIV_F80] = "__divxf3"; 64 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 65 Names[RTLIB::REM_F32] = "fmodf"; 66 Names[RTLIB::REM_F64] = "fmod"; 67 Names[RTLIB::REM_F80] = "fmodl"; 68 Names[RTLIB::REM_PPCF128] = "fmodl"; 69 Names[RTLIB::POWI_F32] = "__powisf2"; 70 Names[RTLIB::POWI_F64] = "__powidf2"; 71 Names[RTLIB::POWI_F80] = "__powixf2"; 72 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 73 Names[RTLIB::SQRT_F32] = "sqrtf"; 74 Names[RTLIB::SQRT_F64] = "sqrt"; 75 Names[RTLIB::SQRT_F80] = "sqrtl"; 76 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 77 Names[RTLIB::SIN_F32] = "sinf"; 78 Names[RTLIB::SIN_F64] = "sin"; 79 Names[RTLIB::SIN_F80] = "sinl"; 80 Names[RTLIB::SIN_PPCF128] = "sinl"; 81 Names[RTLIB::COS_F32] = "cosf"; 82 Names[RTLIB::COS_F64] = "cos"; 83 Names[RTLIB::COS_F80] = "cosl"; 84 Names[RTLIB::COS_PPCF128] = "cosl"; 85 Names[RTLIB::POW_F32] = "powf"; 86 Names[RTLIB::POW_F64] = "pow"; 87 Names[RTLIB::POW_F80] = "powl"; 88 Names[RTLIB::POW_PPCF128] = "powl"; 89 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 90 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 91 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 92 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 93 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 94 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 95 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 96 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 97 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 98 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 99 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 100 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 101 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 102 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 103 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 104 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 105 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 106 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 107 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 108 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 109 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 110 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 111 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 112 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 113 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 114 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 115 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 116 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 117 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 118 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 119 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 120 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 121 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 122 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 123 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 124 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 125 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 126 Names[RTLIB::OEQ_F32] = "__eqsf2"; 127 Names[RTLIB::OEQ_F64] = "__eqdf2"; 128 Names[RTLIB::UNE_F32] = "__nesf2"; 129 Names[RTLIB::UNE_F64] = "__nedf2"; 130 Names[RTLIB::OGE_F32] = "__gesf2"; 131 Names[RTLIB::OGE_F64] = "__gedf2"; 132 Names[RTLIB::OLT_F32] = "__ltsf2"; 133 Names[RTLIB::OLT_F64] = "__ltdf2"; 134 Names[RTLIB::OLE_F32] = "__lesf2"; 135 Names[RTLIB::OLE_F64] = "__ledf2"; 136 Names[RTLIB::OGT_F32] = "__gtsf2"; 137 Names[RTLIB::OGT_F64] = "__gtdf2"; 138 Names[RTLIB::UO_F32] = "__unordsf2"; 139 Names[RTLIB::UO_F64] = "__unorddf2"; 140 Names[RTLIB::O_F32] = "__unordsf2"; 141 Names[RTLIB::O_F64] = "__unorddf2"; 142} 143 144/// InitCmpLibcallCCs - Set default comparison libcall CC. 145/// 146static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 147 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 148 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 149 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 150 CCs[RTLIB::UNE_F32] = ISD::SETNE; 151 CCs[RTLIB::UNE_F64] = ISD::SETNE; 152 CCs[RTLIB::OGE_F32] = ISD::SETGE; 153 CCs[RTLIB::OGE_F64] = ISD::SETGE; 154 CCs[RTLIB::OLT_F32] = ISD::SETLT; 155 CCs[RTLIB::OLT_F64] = ISD::SETLT; 156 CCs[RTLIB::OLE_F32] = ISD::SETLE; 157 CCs[RTLIB::OLE_F64] = ISD::SETLE; 158 CCs[RTLIB::OGT_F32] = ISD::SETGT; 159 CCs[RTLIB::OGT_F64] = ISD::SETGT; 160 CCs[RTLIB::UO_F32] = ISD::SETNE; 161 CCs[RTLIB::UO_F64] = ISD::SETNE; 162 CCs[RTLIB::O_F32] = ISD::SETEQ; 163 CCs[RTLIB::O_F64] = ISD::SETEQ; 164} 165 166TargetLowering::TargetLowering(TargetMachine &tm) 167 : TM(tm), TD(TM.getTargetData()) { 168 assert(ISD::BUILTIN_OP_END <= 156 && 169 "Fixed size array in TargetLowering is not large enough!"); 170 // All operations default to being supported. 171 memset(OpActions, 0, sizeof(OpActions)); 172 memset(LoadXActions, 0, sizeof(LoadXActions)); 173 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 174 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 175 memset(ConvertActions, 0, sizeof(ConvertActions)); 176 177 // Set default actions for various operations. 178 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 179 // Default all indexed load / store to expand. 180 for (unsigned IM = (unsigned)ISD::PRE_INC; 181 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 182 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 183 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 184 } 185 186 // These operations default to expand. 187 setOperationAction(ISD::FGETSIGN, (MVT::ValueType)VT, Expand); 188 } 189 190 // Most targets ignore the @llvm.prefetch intrinsic. 191 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 192 193 // ConstantFP nodes default to expand. Targets can either change this to 194 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 195 // to optimize expansions for certain constants. 196 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 197 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 198 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 199 200 // Default ISD::TRAP to expand (which turns it into abort). 201 setOperationAction(ISD::TRAP, MVT::Other, Expand); 202 203 IsLittleEndian = TD->isLittleEndian(); 204 UsesGlobalOffsetTable = false; 205 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 206 ShiftAmtHandling = Undefined; 207 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 208 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 209 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 210 allowUnalignedMemoryAccesses = false; 211 UseUnderscoreSetJmp = false; 212 UseUnderscoreLongJmp = false; 213 SelectIsExpensive = false; 214 IntDivIsCheap = false; 215 Pow2DivIsCheap = false; 216 StackPointerRegisterToSaveRestore = 0; 217 ExceptionPointerRegister = 0; 218 ExceptionSelectorRegister = 0; 219 SetCCResultContents = UndefinedSetCCResult; 220 SchedPreferenceInfo = SchedulingForLatency; 221 JumpBufSize = 0; 222 JumpBufAlignment = 0; 223 IfCvtBlockSizeLimit = 2; 224 IfCvtDupBlockSizeLimit = 0; 225 PrefLoopAlignment = 0; 226 227 InitLibcallNames(LibcallRoutineNames); 228 InitCmpLibcallCCs(CmpLibcallCCs); 229 230 // Tell Legalize whether the assembler supports DEBUG_LOC. 231 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 232 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 233} 234 235TargetLowering::~TargetLowering() {} 236 237 238SDOperand TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 239 assert(getSubtarget() && "Subtarget not defined"); 240 SDOperand ChainOp = Op.getOperand(0); 241 SDOperand DestOp = Op.getOperand(1); 242 SDOperand SourceOp = Op.getOperand(2); 243 SDOperand CountOp = Op.getOperand(3); 244 SDOperand AlignOp = Op.getOperand(4); 245 SDOperand AlwaysInlineOp = Op.getOperand(5); 246 247 bool AlwaysInline = (bool)cast<ConstantSDNode>(AlwaysInlineOp)->getValue(); 248 unsigned Align = (unsigned)cast<ConstantSDNode>(AlignOp)->getValue(); 249 if (Align == 0) Align = 1; 250 251 // If size is unknown, call memcpy. 252 ConstantSDNode *I = dyn_cast<ConstantSDNode>(CountOp); 253 if (!I) { 254 assert(!AlwaysInline && "Cannot inline copy of unknown size"); 255 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 256 } 257 258 // If not DWORD aligned or if size is more than threshold, then call memcpy. 259 // The libc version is likely to be faster for the following cases. It can 260 // use the address value and run time information about the CPU. 261 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster 262 unsigned Size = I->getValue(); 263 if (AlwaysInline || 264 (Size <= getSubtarget()->getMaxInlineSizeThreshold() && 265 (Align & 3) == 0)) 266 return LowerMEMCPYInline(ChainOp, DestOp, SourceOp, Size, Align, DAG); 267 return LowerMEMCPYCall(ChainOp, DestOp, SourceOp, CountOp, DAG); 268} 269 270 271SDOperand TargetLowering::LowerMEMCPYCall(SDOperand Chain, 272 SDOperand Dest, 273 SDOperand Source, 274 SDOperand Count, 275 SelectionDAG &DAG) { 276 MVT::ValueType IntPtr = getPointerTy(); 277 TargetLowering::ArgListTy Args; 278 TargetLowering::ArgListEntry Entry; 279 Entry.Ty = getTargetData()->getIntPtrType(); 280 Entry.Node = Dest; Args.push_back(Entry); 281 Entry.Node = Source; Args.push_back(Entry); 282 Entry.Node = Count; Args.push_back(Entry); 283 std::pair<SDOperand,SDOperand> CallResult = 284 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C, 285 false, DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 286 return CallResult.second; 287} 288 289 290/// computeRegisterProperties - Once all of the register classes are added, 291/// this allows us to compute derived properties we expose. 292void TargetLowering::computeRegisterProperties() { 293 assert(MVT::LAST_VALUETYPE <= 32 && 294 "Too many value types for ValueTypeActions to hold!"); 295 296 // Everything defaults to needing one register. 297 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 298 NumRegistersForVT[i] = 1; 299 RegisterTypeForVT[i] = TransformToType[i] = i; 300 } 301 // ...except isVoid, which doesn't need any registers. 302 NumRegistersForVT[MVT::isVoid] = 0; 303 304 // Find the largest integer register class. 305 unsigned LargestIntReg = MVT::i128; 306 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 307 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 308 309 // Every integer value type larger than this largest register takes twice as 310 // many registers to represent as the previous ValueType. 311 for (MVT::ValueType ExpandedReg = LargestIntReg + 1; 312 MVT::isInteger(ExpandedReg); ++ExpandedReg) { 313 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 314 RegisterTypeForVT[ExpandedReg] = LargestIntReg; 315 TransformToType[ExpandedReg] = ExpandedReg - 1; 316 ValueTypeActions.setTypeAction(ExpandedReg, Expand); 317 } 318 319 // Inspect all of the ValueType's smaller than the largest integer 320 // register to see which ones need promotion. 321 MVT::ValueType LegalIntReg = LargestIntReg; 322 for (MVT::ValueType IntReg = LargestIntReg - 1; 323 IntReg >= MVT::i1; --IntReg) { 324 if (isTypeLegal(IntReg)) { 325 LegalIntReg = IntReg; 326 } else { 327 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg; 328 ValueTypeActions.setTypeAction(IntReg, Promote); 329 } 330 } 331 332 // ppcf128 type is really two f64's. 333 if (!isTypeLegal(MVT::ppcf128)) { 334 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 335 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 336 TransformToType[MVT::ppcf128] = MVT::f64; 337 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 338 } 339 340 // Decide how to handle f64. If the target does not have native f64 support, 341 // expand it to i64 and we will be generating soft float library calls. 342 if (!isTypeLegal(MVT::f64)) { 343 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 344 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 345 TransformToType[MVT::f64] = MVT::i64; 346 ValueTypeActions.setTypeAction(MVT::f64, Expand); 347 } 348 349 // Decide how to handle f32. If the target does not have native support for 350 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 351 if (!isTypeLegal(MVT::f32)) { 352 if (isTypeLegal(MVT::f64)) { 353 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 354 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 355 TransformToType[MVT::f32] = MVT::f64; 356 ValueTypeActions.setTypeAction(MVT::f32, Promote); 357 } else { 358 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 359 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 360 TransformToType[MVT::f32] = MVT::i32; 361 ValueTypeActions.setTypeAction(MVT::f32, Expand); 362 } 363 } 364 365 // Loop over all of the vector value types to see which need transformations. 366 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE; 367 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 368 if (!isTypeLegal(i)) { 369 MVT::ValueType IntermediateVT, RegisterVT; 370 unsigned NumIntermediates; 371 NumRegistersForVT[i] = 372 getVectorTypeBreakdown(i, 373 IntermediateVT, NumIntermediates, 374 RegisterVT); 375 RegisterTypeForVT[i] = RegisterVT; 376 TransformToType[i] = MVT::Other; // this isn't actually used 377 ValueTypeActions.setTypeAction(i, Expand); 378 } 379 } 380} 381 382const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 383 return NULL; 384} 385 386 387MVT::ValueType 388TargetLowering::getSetCCResultType(const SDOperand &) const { 389 return getValueType(TD->getIntPtrType()); 390} 391 392 393/// getVectorTypeBreakdown - Vector types are broken down into some number of 394/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 395/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 396/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 397/// 398/// This method returns the number of registers needed, and the VT for each 399/// register. It also returns the VT and quantity of the intermediate values 400/// before they are promoted/expanded. 401/// 402unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, 403 MVT::ValueType &IntermediateVT, 404 unsigned &NumIntermediates, 405 MVT::ValueType &RegisterVT) const { 406 // Figure out the right, legal destination reg to copy into. 407 unsigned NumElts = MVT::getVectorNumElements(VT); 408 MVT::ValueType EltTy = MVT::getVectorElementType(VT); 409 410 unsigned NumVectorRegs = 1; 411 412 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 413 // could break down into LHS/RHS like LegalizeDAG does. 414 if (!isPowerOf2_32(NumElts)) { 415 NumVectorRegs = NumElts; 416 NumElts = 1; 417 } 418 419 // Divide the input until we get to a supported size. This will always 420 // end with a scalar if the target doesn't support vectors. 421 while (NumElts > 1 && 422 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) { 423 NumElts >>= 1; 424 NumVectorRegs <<= 1; 425 } 426 427 NumIntermediates = NumVectorRegs; 428 429 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts); 430 if (!isTypeLegal(NewVT)) 431 NewVT = EltTy; 432 IntermediateVT = NewVT; 433 434 MVT::ValueType DestVT = getTypeToTransformTo(NewVT); 435 RegisterVT = DestVT; 436 if (DestVT < NewVT) { 437 // Value is expanded, e.g. i64 -> i16. 438 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT)); 439 } else { 440 // Otherwise, promotion or legal types use the same number of registers as 441 // the vector decimated to the appropriate level. 442 return NumVectorRegs; 443 } 444 445 return 1; 446} 447 448/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 449/// function arguments in the caller parameter area. This is the actual 450/// alignment, not its logarithm. 451unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 452 return TD->getCallFrameTypeAlignment(Ty); 453} 454 455SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, 456 SelectionDAG &DAG) const { 457 if (usesGlobalOffsetTable()) 458 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 459 return Table; 460} 461 462//===----------------------------------------------------------------------===// 463// Optimization Methods 464//===----------------------------------------------------------------------===// 465 466/// ShrinkDemandedConstant - Check to see if the specified operand of the 467/// specified instruction is a constant integer. If so, check to see if there 468/// are any bits set in the constant that are not demanded. If so, shrink the 469/// constant and return true. 470bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 471 const APInt &Demanded) { 472 // FIXME: ISD::SELECT, ISD::SELECT_CC 473 switch(Op.getOpcode()) { 474 default: break; 475 case ISD::AND: 476 case ISD::OR: 477 case ISD::XOR: 478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 479 if (C->getAPIntValue().intersects(~Demanded)) { 480 MVT::ValueType VT = Op.getValueType(); 481 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 482 DAG.getConstant(Demanded & 483 C->getAPIntValue(), 484 VT)); 485 return CombineTo(Op, New); 486 } 487 break; 488 } 489 return false; 490} 491 492/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 493/// DemandedMask bits of the result of Op are ever used downstream. If we can 494/// use this information to simplify Op, create a new simplified DAG node and 495/// return true, returning the original and new nodes in Old and New. Otherwise, 496/// analyze the expression and return a mask of KnownOne and KnownZero bits for 497/// the expression (used to simplify the caller). The KnownZero/One bits may 498/// only be accurate for those bits in the DemandedMask. 499bool TargetLowering::SimplifyDemandedBits(SDOperand Op, 500 const APInt &DemandedMask, 501 APInt &KnownZero, 502 APInt &KnownOne, 503 TargetLoweringOpt &TLO, 504 unsigned Depth) const { 505 unsigned BitWidth = DemandedMask.getBitWidth(); 506 assert(Op.getValueSizeInBits() == BitWidth && 507 "Mask size mismatches value type size!"); 508 APInt NewMask = DemandedMask; 509 510 // Don't know anything. 511 KnownZero = KnownOne = APInt(BitWidth, 0); 512 513 // Other users may use these bits. 514 if (!Op.Val->hasOneUse()) { 515 if (Depth != 0) { 516 // If not at the root, Just compute the KnownZero/KnownOne bits to 517 // simplify things downstream. 518 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 519 return false; 520 } 521 // If this is the root being simplified, allow it to have multiple uses, 522 // just set the NewMask to all bits. 523 NewMask = APInt::getAllOnesValue(BitWidth); 524 } else if (DemandedMask == 0) { 525 // Not demanding any bits from Op. 526 if (Op.getOpcode() != ISD::UNDEF) 527 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 528 return false; 529 } else if (Depth == 6) { // Limit search depth. 530 return false; 531 } 532 533 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 534 switch (Op.getOpcode()) { 535 case ISD::Constant: 536 // We know all of the bits for a constant! 537 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 538 KnownZero = ~KnownOne & NewMask; 539 return false; // Don't fall through, will infinitely loop. 540 case ISD::AND: 541 // If the RHS is a constant, check to see if the LHS would be zero without 542 // using the bits from the RHS. Below, we use knowledge about the RHS to 543 // simplify the LHS, here we're using information from the LHS to simplify 544 // the RHS. 545 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 546 APInt LHSZero, LHSOne; 547 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 548 LHSZero, LHSOne, Depth+1); 549 // If the LHS already has zeros where RHSC does, this and is dead. 550 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 551 return TLO.CombineTo(Op, Op.getOperand(0)); 552 // If any of the set bits in the RHS are known zero on the LHS, shrink 553 // the constant. 554 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 555 return true; 556 } 557 558 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 559 KnownOne, TLO, Depth+1)) 560 return true; 561 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 562 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 563 KnownZero2, KnownOne2, TLO, Depth+1)) 564 return true; 565 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 566 567 // If all of the demanded bits are known one on one side, return the other. 568 // These bits cannot contribute to the result of the 'and'. 569 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 570 return TLO.CombineTo(Op, Op.getOperand(0)); 571 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 572 return TLO.CombineTo(Op, Op.getOperand(1)); 573 // If all of the demanded bits in the inputs are known zeros, return zero. 574 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 575 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 576 // If the RHS is a constant, see if we can simplify it. 577 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 578 return true; 579 580 // Output known-1 bits are only known if set in both the LHS & RHS. 581 KnownOne &= KnownOne2; 582 // Output known-0 are known to be clear if zero in either the LHS | RHS. 583 KnownZero |= KnownZero2; 584 break; 585 case ISD::OR: 586 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 587 KnownOne, TLO, Depth+1)) 588 return true; 589 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 590 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 591 KnownZero2, KnownOne2, TLO, Depth+1)) 592 return true; 593 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 594 595 // If all of the demanded bits are known zero on one side, return the other. 596 // These bits cannot contribute to the result of the 'or'. 597 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 598 return TLO.CombineTo(Op, Op.getOperand(0)); 599 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 600 return TLO.CombineTo(Op, Op.getOperand(1)); 601 // If all of the potentially set bits on one side are known to be set on 602 // the other side, just use the 'other' side. 603 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 604 return TLO.CombineTo(Op, Op.getOperand(0)); 605 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 606 return TLO.CombineTo(Op, Op.getOperand(1)); 607 // If the RHS is a constant, see if we can simplify it. 608 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 609 return true; 610 611 // Output known-0 bits are only known if clear in both the LHS & RHS. 612 KnownZero &= KnownZero2; 613 // Output known-1 are known to be set if set in either the LHS | RHS. 614 KnownOne |= KnownOne2; 615 break; 616 case ISD::XOR: 617 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 618 KnownOne, TLO, Depth+1)) 619 return true; 620 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 621 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 622 KnownOne2, TLO, Depth+1)) 623 return true; 624 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 625 626 // If all of the demanded bits are known zero on one side, return the other. 627 // These bits cannot contribute to the result of the 'xor'. 628 if ((KnownZero & NewMask) == NewMask) 629 return TLO.CombineTo(Op, Op.getOperand(0)); 630 if ((KnownZero2 & NewMask) == NewMask) 631 return TLO.CombineTo(Op, Op.getOperand(1)); 632 633 // If all of the unknown bits are known to be zero on one side or the other 634 // (but not both) turn this into an *inclusive* or. 635 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 636 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 637 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 638 Op.getOperand(0), 639 Op.getOperand(1))); 640 641 // Output known-0 bits are known if clear or set in both the LHS & RHS. 642 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 643 // Output known-1 are known to be set if set in only one of the LHS, RHS. 644 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 645 646 // If all of the demanded bits on one side are known, and all of the set 647 // bits on that side are also known to be set on the other side, turn this 648 // into an AND, as we know the bits will be cleared. 649 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 650 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 651 if ((KnownOne & KnownOne2) == KnownOne) { 652 MVT::ValueType VT = Op.getValueType(); 653 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 654 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 655 ANDC)); 656 } 657 } 658 659 // If the RHS is a constant, see if we can simplify it. 660 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 661 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 662 return true; 663 664 KnownZero = KnownZeroOut; 665 KnownOne = KnownOneOut; 666 break; 667 case ISD::SELECT: 668 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 669 KnownOne, TLO, Depth+1)) 670 return true; 671 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 672 KnownOne2, TLO, Depth+1)) 673 return true; 674 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 675 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 676 677 // If the operands are constants, see if we can simplify them. 678 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 679 return true; 680 681 // Only known if known in both the LHS and RHS. 682 KnownOne &= KnownOne2; 683 KnownZero &= KnownZero2; 684 break; 685 case ISD::SELECT_CC: 686 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 687 KnownOne, TLO, Depth+1)) 688 return true; 689 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 690 KnownOne2, TLO, Depth+1)) 691 return true; 692 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 693 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 694 695 // If the operands are constants, see if we can simplify them. 696 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 697 return true; 698 699 // Only known if known in both the LHS and RHS. 700 KnownOne &= KnownOne2; 701 KnownZero &= KnownZero2; 702 break; 703 case ISD::SHL: 704 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 705 unsigned ShAmt = SA->getValue(); 706 SDOperand InOp = Op.getOperand(0); 707 708 // If the shift count is an invalid immediate, don't do anything. 709 if (ShAmt >= BitWidth) 710 break; 711 712 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 713 // single shift. We can do this if the bottom bits (which are shifted 714 // out) are never demanded. 715 if (InOp.getOpcode() == ISD::SRL && 716 isa<ConstantSDNode>(InOp.getOperand(1))) { 717 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 718 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 719 unsigned Opc = ISD::SHL; 720 int Diff = ShAmt-C1; 721 if (Diff < 0) { 722 Diff = -Diff; 723 Opc = ISD::SRL; 724 } 725 726 SDOperand NewSA = 727 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 728 MVT::ValueType VT = Op.getValueType(); 729 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 730 InOp.getOperand(0), NewSA)); 731 } 732 } 733 734 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 735 KnownZero, KnownOne, TLO, Depth+1)) 736 return true; 737 KnownZero <<= SA->getValue(); 738 KnownOne <<= SA->getValue(); 739 // low bits known zero. 740 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue()); 741 } 742 break; 743 case ISD::SRL: 744 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 745 MVT::ValueType VT = Op.getValueType(); 746 unsigned ShAmt = SA->getValue(); 747 unsigned VTSize = MVT::getSizeInBits(VT); 748 SDOperand InOp = Op.getOperand(0); 749 750 // If the shift count is an invalid immediate, don't do anything. 751 if (ShAmt >= BitWidth) 752 break; 753 754 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 755 // single shift. We can do this if the top bits (which are shifted out) 756 // are never demanded. 757 if (InOp.getOpcode() == ISD::SHL && 758 isa<ConstantSDNode>(InOp.getOperand(1))) { 759 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 760 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 761 unsigned Opc = ISD::SRL; 762 int Diff = ShAmt-C1; 763 if (Diff < 0) { 764 Diff = -Diff; 765 Opc = ISD::SHL; 766 } 767 768 SDOperand NewSA = 769 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 770 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 771 InOp.getOperand(0), NewSA)); 772 } 773 } 774 775 // Compute the new bits that are at the top now. 776 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 777 KnownZero, KnownOne, TLO, Depth+1)) 778 return true; 779 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 780 KnownZero = KnownZero.lshr(ShAmt); 781 KnownOne = KnownOne.lshr(ShAmt); 782 783 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 784 KnownZero |= HighBits; // High bits known zero. 785 } 786 break; 787 case ISD::SRA: 788 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 789 MVT::ValueType VT = Op.getValueType(); 790 unsigned ShAmt = SA->getValue(); 791 792 // If the shift count is an invalid immediate, don't do anything. 793 if (ShAmt >= BitWidth) 794 break; 795 796 APInt InDemandedMask = (NewMask << ShAmt); 797 798 // If any of the demanded bits are produced by the sign extension, we also 799 // demand the input sign bit. 800 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 801 if (HighBits.intersects(NewMask)) 802 InDemandedMask |= APInt::getSignBit(MVT::getSizeInBits(VT)); 803 804 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 805 KnownZero, KnownOne, TLO, Depth+1)) 806 return true; 807 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 808 KnownZero = KnownZero.lshr(ShAmt); 809 KnownOne = KnownOne.lshr(ShAmt); 810 811 // Handle the sign bit, adjusted to where it is now in the mask. 812 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 813 814 // If the input sign bit is known to be zero, or if none of the top bits 815 // are demanded, turn this into an unsigned shift right. 816 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 817 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 818 Op.getOperand(1))); 819 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 820 KnownOne |= HighBits; 821 } 822 } 823 break; 824 case ISD::SIGN_EXTEND_INREG: { 825 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 826 827 // Sign extension. Compute the demanded bits in the result that are not 828 // present in the input. 829 APInt NewBits = APInt::getHighBitsSet(BitWidth, 830 BitWidth - MVT::getSizeInBits(EVT)) & 831 NewMask; 832 833 // If none of the extended bits are demanded, eliminate the sextinreg. 834 if (NewBits == 0) 835 return TLO.CombineTo(Op, Op.getOperand(0)); 836 837 APInt InSignBit = APInt::getSignBit(MVT::getSizeInBits(EVT)); 838 InSignBit.zext(BitWidth); 839 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 840 MVT::getSizeInBits(EVT)) & 841 NewMask; 842 843 // Since the sign extended bits are demanded, we know that the sign 844 // bit is demanded. 845 InputDemandedBits |= InSignBit; 846 847 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 848 KnownZero, KnownOne, TLO, Depth+1)) 849 return true; 850 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 851 852 // If the sign bit of the input is known set or clear, then we know the 853 // top bits of the result. 854 855 // If the input sign bit is known zero, convert this into a zero extension. 856 if (KnownZero.intersects(InSignBit)) 857 return TLO.CombineTo(Op, 858 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 859 860 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 861 KnownOne |= NewBits; 862 KnownZero &= ~NewBits; 863 } else { // Input sign bit unknown 864 KnownZero &= ~NewBits; 865 KnownOne &= ~NewBits; 866 } 867 break; 868 } 869 case ISD::ZERO_EXTEND: { 870 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 871 APInt InMask = NewMask; 872 InMask.trunc(OperandBitWidth); 873 874 // If none of the top bits are demanded, convert this into an any_extend. 875 APInt NewBits = 876 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 877 if (!NewBits.intersects(NewMask)) 878 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 879 Op.getValueType(), 880 Op.getOperand(0))); 881 882 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 883 KnownZero, KnownOne, TLO, Depth+1)) 884 return true; 885 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 886 KnownZero.zext(BitWidth); 887 KnownOne.zext(BitWidth); 888 KnownZero |= NewBits; 889 break; 890 } 891 case ISD::SIGN_EXTEND: { 892 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 893 unsigned InBits = MVT::getSizeInBits(InVT); 894 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 895 APInt InSignBit = APInt::getLowBitsSet(BitWidth, InBits); 896 APInt NewBits = ~InMask & NewMask; 897 898 // If none of the top bits are demanded, convert this into an any_extend. 899 if (NewBits == 0) 900 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 901 Op.getOperand(0))); 902 903 // Since some of the sign extended bits are demanded, we know that the sign 904 // bit is demanded. 905 APInt InDemandedBits = InMask & NewMask; 906 InDemandedBits |= InSignBit; 907 InDemandedBits.trunc(InBits); 908 909 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 910 KnownOne, TLO, Depth+1)) 911 return true; 912 KnownZero.zext(BitWidth); 913 KnownOne.zext(BitWidth); 914 915 // If the sign bit is known zero, convert this to a zero extend. 916 if (KnownZero.intersects(InSignBit)) 917 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 918 Op.getValueType(), 919 Op.getOperand(0))); 920 921 // If the sign bit is known one, the top bits match. 922 if (KnownOne.intersects(InSignBit)) { 923 KnownOne |= NewBits; 924 KnownZero &= ~NewBits; 925 } else { // Otherwise, top bits aren't known. 926 KnownOne &= ~NewBits; 927 KnownZero &= ~NewBits; 928 } 929 break; 930 } 931 case ISD::ANY_EXTEND: { 932 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 933 APInt InMask = NewMask; 934 InMask.trunc(OperandBitWidth); 935 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 936 KnownZero, KnownOne, TLO, Depth+1)) 937 return true; 938 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 939 KnownZero.zext(BitWidth); 940 KnownOne.zext(BitWidth); 941 break; 942 } 943 case ISD::TRUNCATE: { 944 // Simplify the input, using demanded bit information, and compute the known 945 // zero/one bits live out. 946 APInt TruncMask = NewMask; 947 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 948 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 949 KnownZero, KnownOne, TLO, Depth+1)) 950 return true; 951 KnownZero.trunc(BitWidth); 952 KnownOne.trunc(BitWidth); 953 954 // If the input is only used by this truncate, see if we can shrink it based 955 // on the known demanded bits. 956 if (Op.getOperand(0).Val->hasOneUse()) { 957 SDOperand In = Op.getOperand(0); 958 unsigned InBitWidth = In.getValueSizeInBits(); 959 switch (In.getOpcode()) { 960 default: break; 961 case ISD::SRL: 962 // Shrink SRL by a constant if none of the high bits shifted in are 963 // demanded. 964 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 965 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 966 InBitWidth - BitWidth); 967 HighBits = HighBits.lshr(ShAmt->getValue()); 968 HighBits.trunc(BitWidth); 969 970 if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) { 971 // None of the shifted in bits are needed. Add a truncate of the 972 // shift input, then shift it. 973 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 974 Op.getValueType(), 975 In.getOperand(0)); 976 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 977 NewTrunc, In.getOperand(1))); 978 } 979 } 980 break; 981 } 982 } 983 984 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 985 break; 986 } 987 case ISD::AssertZext: { 988 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 989 APInt InMask = APInt::getLowBitsSet(BitWidth, 990 MVT::getSizeInBits(VT)); 991 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 992 KnownZero, KnownOne, TLO, Depth+1)) 993 return true; 994 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 995 KnownZero |= ~InMask & NewMask; 996 break; 997 } 998 case ISD::BIT_CONVERT: 999#if 0 1000 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1001 // is demanded, turn this into a FGETSIGN. 1002 if (NewMask == MVT::getIntVTSignBit(Op.getValueType()) && 1003 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1004 !MVT::isVector(Op.getOperand(0).getValueType())) { 1005 // Only do this xform if FGETSIGN is valid or if before legalize. 1006 if (!TLO.AfterLegalize || 1007 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1008 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1009 // place. We expect the SHL to be eliminated by other optimizations. 1010 SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1011 Op.getOperand(0)); 1012 unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1; 1013 SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1014 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1015 Sign, ShAmt)); 1016 } 1017 } 1018#endif 1019 break; 1020 case ISD::ADD: 1021 case ISD::SUB: 1022 case ISD::INTRINSIC_WO_CHAIN: 1023 case ISD::INTRINSIC_W_CHAIN: 1024 case ISD::INTRINSIC_VOID: 1025 case ISD::CTTZ: 1026 case ISD::CTLZ: 1027 case ISD::CTPOP: 1028 case ISD::LOAD: 1029 case ISD::SETCC: 1030 case ISD::FGETSIGN: 1031 // Just use ComputeMaskedBits to compute output bits. 1032 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1033 break; 1034 } 1035 1036 // If we know the value of all of the demanded bits, return this as a 1037 // constant. 1038 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1039 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1040 1041 return false; 1042} 1043 1044/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1045/// in Mask are known to be either zero or one and return them in the 1046/// KnownZero/KnownOne bitsets. 1047void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1048 const APInt &Mask, 1049 APInt &KnownZero, 1050 APInt &KnownOne, 1051 const SelectionDAG &DAG, 1052 unsigned Depth) const { 1053 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1054 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1055 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1056 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1057 "Should use MaskedValueIsZero if you don't know whether Op" 1058 " is a target node!"); 1059 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1060} 1061 1062/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1063/// targets that want to expose additional information about sign bits to the 1064/// DAG Combiner. 1065unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1066 unsigned Depth) const { 1067 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1068 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1069 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1070 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1071 "Should use ComputeNumSignBits if you don't know whether Op" 1072 " is a target node!"); 1073 return 1; 1074} 1075 1076 1077/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1078/// and cc. If it is unable to simplify it, return a null SDOperand. 1079SDOperand 1080TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1081 ISD::CondCode Cond, bool foldBooleans, 1082 DAGCombinerInfo &DCI) const { 1083 SelectionDAG &DAG = DCI.DAG; 1084 1085 // These setcc operations always fold. 1086 switch (Cond) { 1087 default: break; 1088 case ISD::SETFALSE: 1089 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1090 case ISD::SETTRUE: 1091 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1092 } 1093 1094 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1095 const APInt &C1 = N1C->getAPIntValue(); 1096 if (isa<ConstantSDNode>(N0.Val)) { 1097 return DAG.FoldSetCC(VT, N0, N1, Cond); 1098 } else { 1099 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1100 // equality comparison, then we're just comparing whether X itself is 1101 // zero. 1102 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1103 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1104 N0.getOperand(1).getOpcode() == ISD::Constant) { 1105 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1106 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1107 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1108 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1109 // (srl (ctlz x), 5) == 0 -> X != 0 1110 // (srl (ctlz x), 5) != 1 -> X != 0 1111 Cond = ISD::SETNE; 1112 } else { 1113 // (srl (ctlz x), 5) != 0 -> X == 0 1114 // (srl (ctlz x), 5) == 1 -> X == 0 1115 Cond = ISD::SETEQ; 1116 } 1117 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1118 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1119 Zero, Cond); 1120 } 1121 } 1122 1123 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1124 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1125 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1126 1127 // If the comparison constant has bits in the upper part, the 1128 // zero-extended value could never match. 1129 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1130 C1.getBitWidth() - InSize))) { 1131 switch (Cond) { 1132 case ISD::SETUGT: 1133 case ISD::SETUGE: 1134 case ISD::SETEQ: return DAG.getConstant(0, VT); 1135 case ISD::SETULT: 1136 case ISD::SETULE: 1137 case ISD::SETNE: return DAG.getConstant(1, VT); 1138 case ISD::SETGT: 1139 case ISD::SETGE: 1140 // True if the sign bit of C1 is set. 1141 return DAG.getConstant(C1.isNegative(), VT); 1142 case ISD::SETLT: 1143 case ISD::SETLE: 1144 // True if the sign bit of C1 isn't set. 1145 return DAG.getConstant(C1.isNonNegative(), VT); 1146 default: 1147 break; 1148 } 1149 } 1150 1151 // Otherwise, we can perform the comparison with the low bits. 1152 switch (Cond) { 1153 case ISD::SETEQ: 1154 case ISD::SETNE: 1155 case ISD::SETUGT: 1156 case ISD::SETUGE: 1157 case ISD::SETULT: 1158 case ISD::SETULE: 1159 return DAG.getSetCC(VT, N0.getOperand(0), 1160 DAG.getConstant(APInt(C1).trunc(InSize), 1161 N0.getOperand(0).getValueType()), 1162 Cond); 1163 default: 1164 break; // todo, be more careful with signed comparisons 1165 } 1166 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1167 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1168 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1169 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1170 MVT::ValueType ExtDstTy = N0.getValueType(); 1171 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1172 1173 // If the extended part has any inconsistent bits, it cannot ever 1174 // compare equal. In other words, they have to be all ones or all 1175 // zeros. 1176 APInt ExtBits = 1177 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1178 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1179 return DAG.getConstant(Cond == ISD::SETNE, VT); 1180 1181 SDOperand ZextOp; 1182 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1183 if (Op0Ty == ExtSrcTy) { 1184 ZextOp = N0.getOperand(0); 1185 } else { 1186 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1187 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1188 DAG.getConstant(Imm, Op0Ty)); 1189 } 1190 if (!DCI.isCalledByLegalizer()) 1191 DCI.AddToWorklist(ZextOp.Val); 1192 // Otherwise, make this a use of a zext. 1193 return DAG.getSetCC(VT, ZextOp, 1194 DAG.getConstant(C1 & APInt::getLowBitsSet( 1195 ExtDstTyBits, 1196 ExtSrcTyBits), 1197 ExtDstTy), 1198 Cond); 1199 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1200 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1201 1202 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1203 if (N0.getOpcode() == ISD::SETCC) { 1204 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1205 if (TrueWhenTrue) 1206 return N0; 1207 1208 // Invert the condition. 1209 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1210 CC = ISD::getSetCCInverse(CC, 1211 MVT::isInteger(N0.getOperand(0).getValueType())); 1212 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1213 } 1214 1215 if ((N0.getOpcode() == ISD::XOR || 1216 (N0.getOpcode() == ISD::AND && 1217 N0.getOperand(0).getOpcode() == ISD::XOR && 1218 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1219 isa<ConstantSDNode>(N0.getOperand(1)) && 1220 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1221 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1222 // can only do this if the top bits are known zero. 1223 unsigned BitWidth = N0.getValueSizeInBits(); 1224 if (DAG.MaskedValueIsZero(N0, 1225 APInt::getHighBitsSet(BitWidth, 1226 BitWidth-1))) { 1227 // Okay, get the un-inverted input value. 1228 SDOperand Val; 1229 if (N0.getOpcode() == ISD::XOR) 1230 Val = N0.getOperand(0); 1231 else { 1232 assert(N0.getOpcode() == ISD::AND && 1233 N0.getOperand(0).getOpcode() == ISD::XOR); 1234 // ((X^1)&1)^1 -> X & 1 1235 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1236 N0.getOperand(0).getOperand(0), 1237 N0.getOperand(1)); 1238 } 1239 return DAG.getSetCC(VT, Val, N1, 1240 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1241 } 1242 } 1243 } 1244 1245 APInt MinVal, MaxVal; 1246 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1247 if (ISD::isSignedIntSetCC(Cond)) { 1248 MinVal = APInt::getSignedMinValue(OperandBitSize); 1249 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1250 } else { 1251 MinVal = APInt::getMinValue(OperandBitSize); 1252 MaxVal = APInt::getMaxValue(OperandBitSize); 1253 } 1254 1255 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1256 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1257 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1258 // X >= C0 --> X > (C0-1) 1259 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1260 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1261 } 1262 1263 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1264 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1265 // X <= C0 --> X < (C0+1) 1266 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1267 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1268 } 1269 1270 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1271 return DAG.getConstant(0, VT); // X < MIN --> false 1272 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1273 return DAG.getConstant(1, VT); // X >= MIN --> true 1274 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1275 return DAG.getConstant(0, VT); // X > MAX --> false 1276 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1277 return DAG.getConstant(1, VT); // X <= MAX --> true 1278 1279 // Canonicalize setgt X, Min --> setne X, Min 1280 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1281 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1282 // Canonicalize setlt X, Max --> setne X, Max 1283 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1284 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1285 1286 // If we have setult X, 1, turn it into seteq X, 0 1287 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1288 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1289 ISD::SETEQ); 1290 // If we have setugt X, Max-1, turn it into seteq X, Max 1291 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1292 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1293 ISD::SETEQ); 1294 1295 // If we have "setcc X, C0", check to see if we can shrink the immediate 1296 // by changing cc. 1297 1298 // SETUGT X, SINTMAX -> SETLT X, 0 1299 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1300 C1 == (~0ULL >> (65-OperandBitSize))) 1301 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1302 ISD::SETLT); 1303 1304 // FIXME: Implement the rest of these. 1305 1306 // Fold bit comparisons when we can. 1307 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1308 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1309 if (ConstantSDNode *AndRHS = 1310 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1311 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1312 // Perform the xform if the AND RHS is a single bit. 1313 if (isPowerOf2_64(AndRHS->getValue())) { 1314 return DAG.getNode(ISD::SRL, VT, N0, 1315 DAG.getConstant(Log2_64(AndRHS->getValue()), 1316 getShiftAmountTy())); 1317 } 1318 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1319 // (X & 8) == 8 --> (X & 8) >> 3 1320 // Perform the xform if C1 is a single bit. 1321 if (C1.isPowerOf2()) { 1322 return DAG.getNode(ISD::SRL, VT, N0, 1323 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1324 } 1325 } 1326 } 1327 } 1328 } else if (isa<ConstantSDNode>(N0.Val)) { 1329 // Ensure that the constant occurs on the RHS. 1330 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1331 } 1332 1333 if (isa<ConstantFPSDNode>(N0.Val)) { 1334 // Constant fold or commute setcc. 1335 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1336 if (O.Val) return O; 1337 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1338 // If the RHS of an FP comparison is a constant, simplify it away in 1339 // some cases. 1340 if (CFP->getValueAPF().isNaN()) { 1341 // If an operand is known to be a nan, we can fold it. 1342 switch (ISD::getUnorderedFlavor(Cond)) { 1343 default: assert(0 && "Unknown flavor!"); 1344 case 0: // Known false. 1345 return DAG.getConstant(0, VT); 1346 case 1: // Known true. 1347 return DAG.getConstant(1, VT); 1348 case 2: // Undefined. 1349 return DAG.getNode(ISD::UNDEF, VT); 1350 } 1351 } 1352 1353 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1354 // constant if knowing that the operand is non-nan is enough. We prefer to 1355 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1356 // materialize 0.0. 1357 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1358 return DAG.getSetCC(VT, N0, N0, Cond); 1359 } 1360 1361 if (N0 == N1) { 1362 // We can always fold X == X for integer setcc's. 1363 if (MVT::isInteger(N0.getValueType())) 1364 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1365 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1366 if (UOF == 2) // FP operators that are undefined on NaNs. 1367 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1368 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1369 return DAG.getConstant(UOF, VT); 1370 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1371 // if it is not already. 1372 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1373 if (NewCond != Cond) 1374 return DAG.getSetCC(VT, N0, N1, NewCond); 1375 } 1376 1377 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1378 MVT::isInteger(N0.getValueType())) { 1379 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1380 N0.getOpcode() == ISD::XOR) { 1381 // Simplify (X+Y) == (X+Z) --> Y == Z 1382 if (N0.getOpcode() == N1.getOpcode()) { 1383 if (N0.getOperand(0) == N1.getOperand(0)) 1384 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1385 if (N0.getOperand(1) == N1.getOperand(1)) 1386 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1387 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1388 // If X op Y == Y op X, try other combinations. 1389 if (N0.getOperand(0) == N1.getOperand(1)) 1390 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1391 if (N0.getOperand(1) == N1.getOperand(0)) 1392 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1393 } 1394 } 1395 1396 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1397 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1398 // Turn (X+C1) == C2 --> X == C2-C1 1399 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1400 return DAG.getSetCC(VT, N0.getOperand(0), 1401 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1402 N0.getValueType()), Cond); 1403 } 1404 1405 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1406 if (N0.getOpcode() == ISD::XOR) 1407 // If we know that all of the inverted bits are zero, don't bother 1408 // performing the inversion. 1409 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1410 return 1411 DAG.getSetCC(VT, N0.getOperand(0), 1412 DAG.getConstant(LHSR->getAPIntValue() ^ 1413 RHSC->getAPIntValue(), 1414 N0.getValueType()), 1415 Cond); 1416 } 1417 1418 // Turn (C1-X) == C2 --> X == C1-C2 1419 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1420 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1421 return 1422 DAG.getSetCC(VT, N0.getOperand(1), 1423 DAG.getConstant(SUBC->getAPIntValue() - 1424 RHSC->getAPIntValue(), 1425 N0.getValueType()), 1426 Cond); 1427 } 1428 } 1429 } 1430 1431 // Simplify (X+Z) == X --> Z == 0 1432 if (N0.getOperand(0) == N1) 1433 return DAG.getSetCC(VT, N0.getOperand(1), 1434 DAG.getConstant(0, N0.getValueType()), Cond); 1435 if (N0.getOperand(1) == N1) { 1436 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1437 return DAG.getSetCC(VT, N0.getOperand(0), 1438 DAG.getConstant(0, N0.getValueType()), Cond); 1439 else if (N0.Val->hasOneUse()) { 1440 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1441 // (Z-X) == X --> Z == X<<1 1442 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1443 N1, 1444 DAG.getConstant(1, getShiftAmountTy())); 1445 if (!DCI.isCalledByLegalizer()) 1446 DCI.AddToWorklist(SH.Val); 1447 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1448 } 1449 } 1450 } 1451 1452 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1453 N1.getOpcode() == ISD::XOR) { 1454 // Simplify X == (X+Z) --> Z == 0 1455 if (N1.getOperand(0) == N0) { 1456 return DAG.getSetCC(VT, N1.getOperand(1), 1457 DAG.getConstant(0, N1.getValueType()), Cond); 1458 } else if (N1.getOperand(1) == N0) { 1459 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1460 return DAG.getSetCC(VT, N1.getOperand(0), 1461 DAG.getConstant(0, N1.getValueType()), Cond); 1462 } else if (N1.Val->hasOneUse()) { 1463 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1464 // X == (Z-X) --> X<<1 == Z 1465 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1466 DAG.getConstant(1, getShiftAmountTy())); 1467 if (!DCI.isCalledByLegalizer()) 1468 DCI.AddToWorklist(SH.Val); 1469 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1470 } 1471 } 1472 } 1473 } 1474 1475 // Fold away ALL boolean setcc's. 1476 SDOperand Temp; 1477 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1478 switch (Cond) { 1479 default: assert(0 && "Unknown integer setcc!"); 1480 case ISD::SETEQ: // X == Y -> (X^Y)^1 1481 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1482 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1483 if (!DCI.isCalledByLegalizer()) 1484 DCI.AddToWorklist(Temp.Val); 1485 break; 1486 case ISD::SETNE: // X != Y --> (X^Y) 1487 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1488 break; 1489 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1490 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1491 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1492 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1493 if (!DCI.isCalledByLegalizer()) 1494 DCI.AddToWorklist(Temp.Val); 1495 break; 1496 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1497 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1498 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1499 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1500 if (!DCI.isCalledByLegalizer()) 1501 DCI.AddToWorklist(Temp.Val); 1502 break; 1503 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1504 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1505 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1506 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1507 if (!DCI.isCalledByLegalizer()) 1508 DCI.AddToWorklist(Temp.Val); 1509 break; 1510 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1511 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1512 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1513 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1514 break; 1515 } 1516 if (VT != MVT::i1) { 1517 if (!DCI.isCalledByLegalizer()) 1518 DCI.AddToWorklist(N0.Val); 1519 // FIXME: If running after legalize, we probably can't do this. 1520 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1521 } 1522 return N0; 1523 } 1524 1525 // Could not fold it. 1526 return SDOperand(); 1527} 1528 1529SDOperand TargetLowering:: 1530PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1531 // Default implementation: no optimization. 1532 return SDOperand(); 1533} 1534 1535//===----------------------------------------------------------------------===// 1536// Inline Assembler Implementation Methods 1537//===----------------------------------------------------------------------===// 1538 1539TargetLowering::ConstraintType 1540TargetLowering::getConstraintType(const std::string &Constraint) const { 1541 // FIXME: lots more standard ones to handle. 1542 if (Constraint.size() == 1) { 1543 switch (Constraint[0]) { 1544 default: break; 1545 case 'r': return C_RegisterClass; 1546 case 'm': // memory 1547 case 'o': // offsetable 1548 case 'V': // not offsetable 1549 return C_Memory; 1550 case 'i': // Simple Integer or Relocatable Constant 1551 case 'n': // Simple Integer 1552 case 's': // Relocatable Constant 1553 case 'X': // Allow ANY value. 1554 case 'I': // Target registers. 1555 case 'J': 1556 case 'K': 1557 case 'L': 1558 case 'M': 1559 case 'N': 1560 case 'O': 1561 case 'P': 1562 return C_Other; 1563 } 1564 } 1565 1566 if (Constraint.size() > 1 && Constraint[0] == '{' && 1567 Constraint[Constraint.size()-1] == '}') 1568 return C_Register; 1569 return C_Unknown; 1570} 1571 1572/// LowerXConstraint - try to replace an X constraint, which matches anything, 1573/// with another that has more specific requirements based on the type of the 1574/// corresponding operand. 1575void TargetLowering::lowerXConstraint(MVT::ValueType ConstraintVT, 1576 std::string& s) const { 1577 if (MVT::isInteger(ConstraintVT)) 1578 s = "r"; 1579 else if (MVT::isFloatingPoint(ConstraintVT)) 1580 s = "f"; // works for many targets 1581 else 1582 s = ""; 1583} 1584 1585/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1586/// vector. If it is invalid, don't add anything to Ops. 1587void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, 1588 char ConstraintLetter, 1589 std::vector<SDOperand> &Ops, 1590 SelectionDAG &DAG) { 1591 switch (ConstraintLetter) { 1592 default: break; 1593 case 'X': // Allows any operand; labels (basic block) use this. 1594 if (Op.getOpcode() == ISD::BasicBlock) { 1595 Ops.push_back(Op); 1596 return; 1597 } 1598 // fall through 1599 case 'i': // Simple Integer or Relocatable Constant 1600 case 'n': // Simple Integer 1601 case 's': { // Relocatable Constant 1602 // These operands are interested in values of the form (GV+C), where C may 1603 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1604 // is possible and fine if either GV or C are missing. 1605 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1606 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1607 1608 // If we have "(add GV, C)", pull out GV/C 1609 if (Op.getOpcode() == ISD::ADD) { 1610 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1611 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1612 if (C == 0 || GA == 0) { 1613 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1614 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1615 } 1616 if (C == 0 || GA == 0) 1617 C = 0, GA = 0; 1618 } 1619 1620 // If we find a valid operand, map to the TargetXXX version so that the 1621 // value itself doesn't get selected. 1622 if (GA) { // Either &GV or &GV+C 1623 if (ConstraintLetter != 'n') { 1624 int64_t Offs = GA->getOffset(); 1625 if (C) Offs += C->getValue(); 1626 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1627 Op.getValueType(), Offs)); 1628 return; 1629 } 1630 } 1631 if (C) { // just C, no GV. 1632 // Simple constants are not allowed for 's'. 1633 if (ConstraintLetter != 's') { 1634 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1635 return; 1636 } 1637 } 1638 break; 1639 } 1640 } 1641} 1642 1643std::vector<unsigned> TargetLowering:: 1644getRegClassForInlineAsmConstraint(const std::string &Constraint, 1645 MVT::ValueType VT) const { 1646 return std::vector<unsigned>(); 1647} 1648 1649 1650std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1651getRegForInlineAsmConstraint(const std::string &Constraint, 1652 MVT::ValueType VT) const { 1653 if (Constraint[0] != '{') 1654 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1655 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1656 1657 // Remove the braces from around the name. 1658 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1659 1660 // Figure out which register class contains this reg. 1661 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1662 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1663 E = RI->regclass_end(); RCI != E; ++RCI) { 1664 const TargetRegisterClass *RC = *RCI; 1665 1666 // If none of the the value types for this register class are valid, we 1667 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1668 bool isLegal = false; 1669 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1670 I != E; ++I) { 1671 if (isTypeLegal(*I)) { 1672 isLegal = true; 1673 break; 1674 } 1675 } 1676 1677 if (!isLegal) continue; 1678 1679 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1680 I != E; ++I) { 1681 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1682 return std::make_pair(*I, RC); 1683 } 1684 } 1685 1686 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1687} 1688 1689//===----------------------------------------------------------------------===// 1690// Loop Strength Reduction hooks 1691//===----------------------------------------------------------------------===// 1692 1693/// isLegalAddressingMode - Return true if the addressing mode represented 1694/// by AM is legal for this target, for a load/store of the specified type. 1695bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1696 const Type *Ty) const { 1697 // The default implementation of this implements a conservative RISCy, r+r and 1698 // r+i addr mode. 1699 1700 // Allows a sign-extended 16-bit immediate field. 1701 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1702 return false; 1703 1704 // No global is ever allowed as a base. 1705 if (AM.BaseGV) 1706 return false; 1707 1708 // Only support r+r, 1709 switch (AM.Scale) { 1710 case 0: // "r+i" or just "i", depending on HasBaseReg. 1711 break; 1712 case 1: 1713 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1714 return false; 1715 // Otherwise we have r+r or r+i. 1716 break; 1717 case 2: 1718 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1719 return false; 1720 // Allow 2*r as r+r. 1721 break; 1722 } 1723 1724 return true; 1725} 1726 1727// Magic for divide replacement 1728 1729struct ms { 1730 int64_t m; // magic number 1731 int64_t s; // shift amount 1732}; 1733 1734struct mu { 1735 uint64_t m; // magic number 1736 int64_t a; // add indicator 1737 int64_t s; // shift amount 1738}; 1739 1740/// magic - calculate the magic numbers required to codegen an integer sdiv as 1741/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1742/// or -1. 1743static ms magic32(int32_t d) { 1744 int32_t p; 1745 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 1746 const uint32_t two31 = 0x80000000U; 1747 struct ms mag; 1748 1749 ad = abs(d); 1750 t = two31 + ((uint32_t)d >> 31); 1751 anc = t - 1 - t%ad; // absolute value of nc 1752 p = 31; // initialize p 1753 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 1754 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1755 q2 = two31/ad; // initialize q2 = 2p/abs(d) 1756 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1757 do { 1758 p = p + 1; 1759 q1 = 2*q1; // update q1 = 2p/abs(nc) 1760 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1761 if (r1 >= anc) { // must be unsigned comparison 1762 q1 = q1 + 1; 1763 r1 = r1 - anc; 1764 } 1765 q2 = 2*q2; // update q2 = 2p/abs(d) 1766 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1767 if (r2 >= ad) { // must be unsigned comparison 1768 q2 = q2 + 1; 1769 r2 = r2 - ad; 1770 } 1771 delta = ad - r2; 1772 } while (q1 < delta || (q1 == delta && r1 == 0)); 1773 1774 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 1775 if (d < 0) mag.m = -mag.m; // resulting magic number 1776 mag.s = p - 32; // resulting shift 1777 return mag; 1778} 1779 1780/// magicu - calculate the magic numbers required to codegen an integer udiv as 1781/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1782static mu magicu32(uint32_t d) { 1783 int32_t p; 1784 uint32_t nc, delta, q1, r1, q2, r2; 1785 struct mu magu; 1786 magu.a = 0; // initialize "add" indicator 1787 nc = - 1 - (-d)%d; 1788 p = 31; // initialize p 1789 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 1790 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 1791 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 1792 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 1793 do { 1794 p = p + 1; 1795 if (r1 >= nc - r1 ) { 1796 q1 = 2*q1 + 1; // update q1 1797 r1 = 2*r1 - nc; // update r1 1798 } 1799 else { 1800 q1 = 2*q1; // update q1 1801 r1 = 2*r1; // update r1 1802 } 1803 if (r2 + 1 >= d - r2) { 1804 if (q2 >= 0x7FFFFFFF) magu.a = 1; 1805 q2 = 2*q2 + 1; // update q2 1806 r2 = 2*r2 + 1 - d; // update r2 1807 } 1808 else { 1809 if (q2 >= 0x80000000) magu.a = 1; 1810 q2 = 2*q2; // update q2 1811 r2 = 2*r2 + 1; // update r2 1812 } 1813 delta = d - 1 - r2; 1814 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 1815 magu.m = q2 + 1; // resulting magic number 1816 magu.s = p - 32; // resulting shift 1817 return magu; 1818} 1819 1820/// magic - calculate the magic numbers required to codegen an integer sdiv as 1821/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 1822/// or -1. 1823static ms magic64(int64_t d) { 1824 int64_t p; 1825 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 1826 const uint64_t two63 = 9223372036854775808ULL; // 2^63 1827 struct ms mag; 1828 1829 ad = d >= 0 ? d : -d; 1830 t = two63 + ((uint64_t)d >> 63); 1831 anc = t - 1 - t%ad; // absolute value of nc 1832 p = 63; // initialize p 1833 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 1834 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 1835 q2 = two63/ad; // initialize q2 = 2p/abs(d) 1836 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 1837 do { 1838 p = p + 1; 1839 q1 = 2*q1; // update q1 = 2p/abs(nc) 1840 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 1841 if (r1 >= anc) { // must be unsigned comparison 1842 q1 = q1 + 1; 1843 r1 = r1 - anc; 1844 } 1845 q2 = 2*q2; // update q2 = 2p/abs(d) 1846 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 1847 if (r2 >= ad) { // must be unsigned comparison 1848 q2 = q2 + 1; 1849 r2 = r2 - ad; 1850 } 1851 delta = ad - r2; 1852 } while (q1 < delta || (q1 == delta && r1 == 0)); 1853 1854 mag.m = q2 + 1; 1855 if (d < 0) mag.m = -mag.m; // resulting magic number 1856 mag.s = p - 64; // resulting shift 1857 return mag; 1858} 1859 1860/// magicu - calculate the magic numbers required to codegen an integer udiv as 1861/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 1862static mu magicu64(uint64_t d) 1863{ 1864 int64_t p; 1865 uint64_t nc, delta, q1, r1, q2, r2; 1866 struct mu magu; 1867 magu.a = 0; // initialize "add" indicator 1868 nc = - 1 - (-d)%d; 1869 p = 63; // initialize p 1870 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 1871 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 1872 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 1873 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 1874 do { 1875 p = p + 1; 1876 if (r1 >= nc - r1 ) { 1877 q1 = 2*q1 + 1; // update q1 1878 r1 = 2*r1 - nc; // update r1 1879 } 1880 else { 1881 q1 = 2*q1; // update q1 1882 r1 = 2*r1; // update r1 1883 } 1884 if (r2 + 1 >= d - r2) { 1885 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 1886 q2 = 2*q2 + 1; // update q2 1887 r2 = 2*r2 + 1 - d; // update r2 1888 } 1889 else { 1890 if (q2 >= 0x8000000000000000ull) magu.a = 1; 1891 q2 = 2*q2; // update q2 1892 r2 = 2*r2 + 1; // update r2 1893 } 1894 delta = d - 1 - r2; 1895 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 1896 magu.m = q2 + 1; // resulting magic number 1897 magu.s = p - 64; // resulting shift 1898 return magu; 1899} 1900 1901/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 1902/// return a DAG expression to select that will generate the same value by 1903/// multiplying by a magic number. See: 1904/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1905SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 1906 std::vector<SDNode*>* Created) const { 1907 MVT::ValueType VT = N->getValueType(0); 1908 1909 // Check to see if we can do this. 1910 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1911 return SDOperand(); // BuildSDIV only operates on i32 or i64 1912 1913 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 1914 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 1915 1916 // Multiply the numerator (operand 0) by the magic value 1917 SDOperand Q; 1918 if (isOperationLegal(ISD::MULHS, VT)) 1919 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 1920 DAG.getConstant(magics.m, VT)); 1921 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 1922 Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 1923 N->getOperand(0), 1924 DAG.getConstant(magics.m, VT)).Val, 1); 1925 else 1926 return SDOperand(); // No mulhs or equvialent 1927 // If d > 0 and m < 0, add the numerator 1928 if (d > 0 && magics.m < 0) { 1929 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 1930 if (Created) 1931 Created->push_back(Q.Val); 1932 } 1933 // If d < 0 and m > 0, subtract the numerator. 1934 if (d < 0 && magics.m > 0) { 1935 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 1936 if (Created) 1937 Created->push_back(Q.Val); 1938 } 1939 // Shift right algebraic if shift value is nonzero 1940 if (magics.s > 0) { 1941 Q = DAG.getNode(ISD::SRA, VT, Q, 1942 DAG.getConstant(magics.s, getShiftAmountTy())); 1943 if (Created) 1944 Created->push_back(Q.Val); 1945 } 1946 // Extract the sign bit and add it to the quotient 1947 SDOperand T = 1948 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 1949 getShiftAmountTy())); 1950 if (Created) 1951 Created->push_back(T.Val); 1952 return DAG.getNode(ISD::ADD, VT, Q, T); 1953} 1954 1955/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 1956/// return a DAG expression to select that will generate the same value by 1957/// multiplying by a magic number. See: 1958/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 1959SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 1960 std::vector<SDNode*>* Created) const { 1961 MVT::ValueType VT = N->getValueType(0); 1962 1963 // Check to see if we can do this. 1964 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 1965 return SDOperand(); // BuildUDIV only operates on i32 or i64 1966 1967 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1968 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 1969 1970 // Multiply the numerator (operand 0) by the magic value 1971 SDOperand Q; 1972 if (isOperationLegal(ISD::MULHU, VT)) 1973 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 1974 DAG.getConstant(magics.m, VT)); 1975 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 1976 Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 1977 N->getOperand(0), 1978 DAG.getConstant(magics.m, VT)).Val, 1); 1979 else 1980 return SDOperand(); // No mulhu or equvialent 1981 if (Created) 1982 Created->push_back(Q.Val); 1983 1984 if (magics.a == 0) { 1985 return DAG.getNode(ISD::SRL, VT, Q, 1986 DAG.getConstant(magics.s, getShiftAmountTy())); 1987 } else { 1988 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 1989 if (Created) 1990 Created->push_back(NPQ.Val); 1991 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 1992 DAG.getConstant(1, getShiftAmountTy())); 1993 if (Created) 1994 Created->push_back(NPQ.Val); 1995 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 1996 if (Created) 1997 Created->push_back(NPQ.Val); 1998 return DAG.getNode(ISD::SRL, VT, NPQ, 1999 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2000 } 2001} 2002