TargetLowering.cpp revision b6aacae9413adde66d9686cd9e561eb836b3ee34
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31#include <cctype> 32using namespace llvm; 33 34namespace llvm { 35TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 36 bool isLocal = GV->hasLocalLinkage(); 37 bool isDeclaration = GV->isDeclaration(); 38 // FIXME: what should we do for protected and internal visibility? 39 // For variables, is internal different from hidden? 40 bool isHidden = GV->hasHiddenVisibility(); 41 42 if (reloc == Reloc::PIC_) { 43 if (isLocal || isHidden) 44 return TLSModel::LocalDynamic; 45 else 46 return TLSModel::GeneralDynamic; 47 } else { 48 if (!isDeclaration || isHidden) 49 return TLSModel::LocalExec; 50 else 51 return TLSModel::InitialExec; 52 } 53} 54} 55 56/// InitLibcallNames - Set default libcall names. 57/// 58static void InitLibcallNames(const char **Names) { 59 Names[RTLIB::SHL_I16] = "__ashlhi3"; 60 Names[RTLIB::SHL_I32] = "__ashlsi3"; 61 Names[RTLIB::SHL_I64] = "__ashldi3"; 62 Names[RTLIB::SHL_I128] = "__ashlti3"; 63 Names[RTLIB::SRL_I16] = "__lshrhi3"; 64 Names[RTLIB::SRL_I32] = "__lshrsi3"; 65 Names[RTLIB::SRL_I64] = "__lshrdi3"; 66 Names[RTLIB::SRL_I128] = "__lshrti3"; 67 Names[RTLIB::SRA_I16] = "__ashrhi3"; 68 Names[RTLIB::SRA_I32] = "__ashrsi3"; 69 Names[RTLIB::SRA_I64] = "__ashrdi3"; 70 Names[RTLIB::SRA_I128] = "__ashrti3"; 71 Names[RTLIB::MUL_I8] = "__mulqi3"; 72 Names[RTLIB::MUL_I16] = "__mulhi3"; 73 Names[RTLIB::MUL_I32] = "__mulsi3"; 74 Names[RTLIB::MUL_I64] = "__muldi3"; 75 Names[RTLIB::MUL_I128] = "__multi3"; 76 Names[RTLIB::SDIV_I8] = "__divqi3"; 77 Names[RTLIB::SDIV_I16] = "__divhi3"; 78 Names[RTLIB::SDIV_I32] = "__divsi3"; 79 Names[RTLIB::SDIV_I64] = "__divdi3"; 80 Names[RTLIB::SDIV_I128] = "__divti3"; 81 Names[RTLIB::UDIV_I8] = "__udivqi3"; 82 Names[RTLIB::UDIV_I16] = "__udivhi3"; 83 Names[RTLIB::UDIV_I32] = "__udivsi3"; 84 Names[RTLIB::UDIV_I64] = "__udivdi3"; 85 Names[RTLIB::UDIV_I128] = "__udivti3"; 86 Names[RTLIB::SREM_I8] = "__modqi3"; 87 Names[RTLIB::SREM_I16] = "__modhi3"; 88 Names[RTLIB::SREM_I32] = "__modsi3"; 89 Names[RTLIB::SREM_I64] = "__moddi3"; 90 Names[RTLIB::SREM_I128] = "__modti3"; 91 Names[RTLIB::UREM_I8] = "__umodqi3"; 92 Names[RTLIB::UREM_I16] = "__umodhi3"; 93 Names[RTLIB::UREM_I32] = "__umodsi3"; 94 Names[RTLIB::UREM_I64] = "__umoddi3"; 95 Names[RTLIB::UREM_I128] = "__umodti3"; 96 97 // These are generally not available. 98 Names[RTLIB::SDIVREM_I8] = 0; 99 Names[RTLIB::SDIVREM_I16] = 0; 100 Names[RTLIB::SDIVREM_I32] = 0; 101 Names[RTLIB::SDIVREM_I64] = 0; 102 Names[RTLIB::SDIVREM_I128] = 0; 103 Names[RTLIB::UDIVREM_I8] = 0; 104 Names[RTLIB::UDIVREM_I16] = 0; 105 Names[RTLIB::UDIVREM_I32] = 0; 106 Names[RTLIB::UDIVREM_I64] = 0; 107 Names[RTLIB::UDIVREM_I128] = 0; 108 109 Names[RTLIB::NEG_I32] = "__negsi2"; 110 Names[RTLIB::NEG_I64] = "__negdi2"; 111 Names[RTLIB::ADD_F32] = "__addsf3"; 112 Names[RTLIB::ADD_F64] = "__adddf3"; 113 Names[RTLIB::ADD_F80] = "__addxf3"; 114 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 115 Names[RTLIB::SUB_F32] = "__subsf3"; 116 Names[RTLIB::SUB_F64] = "__subdf3"; 117 Names[RTLIB::SUB_F80] = "__subxf3"; 118 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 119 Names[RTLIB::MUL_F32] = "__mulsf3"; 120 Names[RTLIB::MUL_F64] = "__muldf3"; 121 Names[RTLIB::MUL_F80] = "__mulxf3"; 122 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 123 Names[RTLIB::DIV_F32] = "__divsf3"; 124 Names[RTLIB::DIV_F64] = "__divdf3"; 125 Names[RTLIB::DIV_F80] = "__divxf3"; 126 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 127 Names[RTLIB::REM_F32] = "fmodf"; 128 Names[RTLIB::REM_F64] = "fmod"; 129 Names[RTLIB::REM_F80] = "fmodl"; 130 Names[RTLIB::REM_PPCF128] = "fmodl"; 131 Names[RTLIB::POWI_F32] = "__powisf2"; 132 Names[RTLIB::POWI_F64] = "__powidf2"; 133 Names[RTLIB::POWI_F80] = "__powixf2"; 134 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 135 Names[RTLIB::SQRT_F32] = "sqrtf"; 136 Names[RTLIB::SQRT_F64] = "sqrt"; 137 Names[RTLIB::SQRT_F80] = "sqrtl"; 138 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 139 Names[RTLIB::LOG_F32] = "logf"; 140 Names[RTLIB::LOG_F64] = "log"; 141 Names[RTLIB::LOG_F80] = "logl"; 142 Names[RTLIB::LOG_PPCF128] = "logl"; 143 Names[RTLIB::LOG2_F32] = "log2f"; 144 Names[RTLIB::LOG2_F64] = "log2"; 145 Names[RTLIB::LOG2_F80] = "log2l"; 146 Names[RTLIB::LOG2_PPCF128] = "log2l"; 147 Names[RTLIB::LOG10_F32] = "log10f"; 148 Names[RTLIB::LOG10_F64] = "log10"; 149 Names[RTLIB::LOG10_F80] = "log10l"; 150 Names[RTLIB::LOG10_PPCF128] = "log10l"; 151 Names[RTLIB::EXP_F32] = "expf"; 152 Names[RTLIB::EXP_F64] = "exp"; 153 Names[RTLIB::EXP_F80] = "expl"; 154 Names[RTLIB::EXP_PPCF128] = "expl"; 155 Names[RTLIB::EXP2_F32] = "exp2f"; 156 Names[RTLIB::EXP2_F64] = "exp2"; 157 Names[RTLIB::EXP2_F80] = "exp2l"; 158 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 159 Names[RTLIB::SIN_F32] = "sinf"; 160 Names[RTLIB::SIN_F64] = "sin"; 161 Names[RTLIB::SIN_F80] = "sinl"; 162 Names[RTLIB::SIN_PPCF128] = "sinl"; 163 Names[RTLIB::COS_F32] = "cosf"; 164 Names[RTLIB::COS_F64] = "cos"; 165 Names[RTLIB::COS_F80] = "cosl"; 166 Names[RTLIB::COS_PPCF128] = "cosl"; 167 Names[RTLIB::POW_F32] = "powf"; 168 Names[RTLIB::POW_F64] = "pow"; 169 Names[RTLIB::POW_F80] = "powl"; 170 Names[RTLIB::POW_PPCF128] = "powl"; 171 Names[RTLIB::CEIL_F32] = "ceilf"; 172 Names[RTLIB::CEIL_F64] = "ceil"; 173 Names[RTLIB::CEIL_F80] = "ceill"; 174 Names[RTLIB::CEIL_PPCF128] = "ceill"; 175 Names[RTLIB::TRUNC_F32] = "truncf"; 176 Names[RTLIB::TRUNC_F64] = "trunc"; 177 Names[RTLIB::TRUNC_F80] = "truncl"; 178 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 179 Names[RTLIB::RINT_F32] = "rintf"; 180 Names[RTLIB::RINT_F64] = "rint"; 181 Names[RTLIB::RINT_F80] = "rintl"; 182 Names[RTLIB::RINT_PPCF128] = "rintl"; 183 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 184 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 185 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 186 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 187 Names[RTLIB::FLOOR_F32] = "floorf"; 188 Names[RTLIB::FLOOR_F64] = "floor"; 189 Names[RTLIB::FLOOR_F80] = "floorl"; 190 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 191 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 192 Names[RTLIB::COPYSIGN_F64] = "copysign"; 193 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 194 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 195 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 196 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 197 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 198 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 199 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 200 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 201 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 202 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 203 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 204 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 205 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 206 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 207 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 208 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 209 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 210 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 211 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 212 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 213 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 214 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 215 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 216 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 217 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 218 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 219 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 220 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 221 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 222 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 223 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 224 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 225 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 226 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 227 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 228 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 229 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 230 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 231 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 232 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 233 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 234 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 235 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 236 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 237 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 238 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 239 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 240 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 241 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 242 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 243 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 244 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 245 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 246 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 247 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 248 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 249 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 250 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 251 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 252 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 253 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 254 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 255 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 256 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 257 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 258 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 259 Names[RTLIB::OEQ_F32] = "__eqsf2"; 260 Names[RTLIB::OEQ_F64] = "__eqdf2"; 261 Names[RTLIB::UNE_F32] = "__nesf2"; 262 Names[RTLIB::UNE_F64] = "__nedf2"; 263 Names[RTLIB::OGE_F32] = "__gesf2"; 264 Names[RTLIB::OGE_F64] = "__gedf2"; 265 Names[RTLIB::OLT_F32] = "__ltsf2"; 266 Names[RTLIB::OLT_F64] = "__ltdf2"; 267 Names[RTLIB::OLE_F32] = "__lesf2"; 268 Names[RTLIB::OLE_F64] = "__ledf2"; 269 Names[RTLIB::OGT_F32] = "__gtsf2"; 270 Names[RTLIB::OGT_F64] = "__gtdf2"; 271 Names[RTLIB::UO_F32] = "__unordsf2"; 272 Names[RTLIB::UO_F64] = "__unorddf2"; 273 Names[RTLIB::O_F32] = "__unordsf2"; 274 Names[RTLIB::O_F64] = "__unorddf2"; 275 Names[RTLIB::MEMCPY] = "memcpy"; 276 Names[RTLIB::MEMMOVE] = "memmove"; 277 Names[RTLIB::MEMSET] = "memset"; 278 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 279 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 280 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 281 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 282 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 283 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 284 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 285 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 286 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 287 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 288 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 289 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 290 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 291 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 292 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 293 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 294 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 295 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 296 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 297 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 298 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 299 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 300 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 301 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 302 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 303 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 304 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 305 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 306 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 307 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 308 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 309 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 310 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 311} 312 313/// InitLibcallCallingConvs - Set default libcall CallingConvs. 314/// 315static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 316 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 317 CCs[i] = CallingConv::C; 318 } 319} 320 321/// getFPEXT - Return the FPEXT_*_* value for the given types, or 322/// UNKNOWN_LIBCALL if there is none. 323RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 324 if (OpVT == MVT::f32) { 325 if (RetVT == MVT::f64) 326 return FPEXT_F32_F64; 327 } 328 329 return UNKNOWN_LIBCALL; 330} 331 332/// getFPROUND - Return the FPROUND_*_* value for the given types, or 333/// UNKNOWN_LIBCALL if there is none. 334RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 335 if (RetVT == MVT::f32) { 336 if (OpVT == MVT::f64) 337 return FPROUND_F64_F32; 338 if (OpVT == MVT::f80) 339 return FPROUND_F80_F32; 340 if (OpVT == MVT::ppcf128) 341 return FPROUND_PPCF128_F32; 342 } else if (RetVT == MVT::f64) { 343 if (OpVT == MVT::f80) 344 return FPROUND_F80_F64; 345 if (OpVT == MVT::ppcf128) 346 return FPROUND_PPCF128_F64; 347 } 348 349 return UNKNOWN_LIBCALL; 350} 351 352/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 353/// UNKNOWN_LIBCALL if there is none. 354RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 355 if (OpVT == MVT::f32) { 356 if (RetVT == MVT::i8) 357 return FPTOSINT_F32_I8; 358 if (RetVT == MVT::i16) 359 return FPTOSINT_F32_I16; 360 if (RetVT == MVT::i32) 361 return FPTOSINT_F32_I32; 362 if (RetVT == MVT::i64) 363 return FPTOSINT_F32_I64; 364 if (RetVT == MVT::i128) 365 return FPTOSINT_F32_I128; 366 } else if (OpVT == MVT::f64) { 367 if (RetVT == MVT::i8) 368 return FPTOSINT_F64_I8; 369 if (RetVT == MVT::i16) 370 return FPTOSINT_F64_I16; 371 if (RetVT == MVT::i32) 372 return FPTOSINT_F64_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_F64_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_F64_I128; 377 } else if (OpVT == MVT::f80) { 378 if (RetVT == MVT::i32) 379 return FPTOSINT_F80_I32; 380 if (RetVT == MVT::i64) 381 return FPTOSINT_F80_I64; 382 if (RetVT == MVT::i128) 383 return FPTOSINT_F80_I128; 384 } else if (OpVT == MVT::ppcf128) { 385 if (RetVT == MVT::i32) 386 return FPTOSINT_PPCF128_I32; 387 if (RetVT == MVT::i64) 388 return FPTOSINT_PPCF128_I64; 389 if (RetVT == MVT::i128) 390 return FPTOSINT_PPCF128_I128; 391 } 392 return UNKNOWN_LIBCALL; 393} 394 395/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 396/// UNKNOWN_LIBCALL if there is none. 397RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 398 if (OpVT == MVT::f32) { 399 if (RetVT == MVT::i8) 400 return FPTOUINT_F32_I8; 401 if (RetVT == MVT::i16) 402 return FPTOUINT_F32_I16; 403 if (RetVT == MVT::i32) 404 return FPTOUINT_F32_I32; 405 if (RetVT == MVT::i64) 406 return FPTOUINT_F32_I64; 407 if (RetVT == MVT::i128) 408 return FPTOUINT_F32_I128; 409 } else if (OpVT == MVT::f64) { 410 if (RetVT == MVT::i8) 411 return FPTOUINT_F64_I8; 412 if (RetVT == MVT::i16) 413 return FPTOUINT_F64_I16; 414 if (RetVT == MVT::i32) 415 return FPTOUINT_F64_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_F64_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_F64_I128; 420 } else if (OpVT == MVT::f80) { 421 if (RetVT == MVT::i32) 422 return FPTOUINT_F80_I32; 423 if (RetVT == MVT::i64) 424 return FPTOUINT_F80_I64; 425 if (RetVT == MVT::i128) 426 return FPTOUINT_F80_I128; 427 } else if (OpVT == MVT::ppcf128) { 428 if (RetVT == MVT::i32) 429 return FPTOUINT_PPCF128_I32; 430 if (RetVT == MVT::i64) 431 return FPTOUINT_PPCF128_I64; 432 if (RetVT == MVT::i128) 433 return FPTOUINT_PPCF128_I128; 434 } 435 return UNKNOWN_LIBCALL; 436} 437 438/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 439/// UNKNOWN_LIBCALL if there is none. 440RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 441 if (OpVT == MVT::i32) { 442 if (RetVT == MVT::f32) 443 return SINTTOFP_I32_F32; 444 else if (RetVT == MVT::f64) 445 return SINTTOFP_I32_F64; 446 else if (RetVT == MVT::f80) 447 return SINTTOFP_I32_F80; 448 else if (RetVT == MVT::ppcf128) 449 return SINTTOFP_I32_PPCF128; 450 } else if (OpVT == MVT::i64) { 451 if (RetVT == MVT::f32) 452 return SINTTOFP_I64_F32; 453 else if (RetVT == MVT::f64) 454 return SINTTOFP_I64_F64; 455 else if (RetVT == MVT::f80) 456 return SINTTOFP_I64_F80; 457 else if (RetVT == MVT::ppcf128) 458 return SINTTOFP_I64_PPCF128; 459 } else if (OpVT == MVT::i128) { 460 if (RetVT == MVT::f32) 461 return SINTTOFP_I128_F32; 462 else if (RetVT == MVT::f64) 463 return SINTTOFP_I128_F64; 464 else if (RetVT == MVT::f80) 465 return SINTTOFP_I128_F80; 466 else if (RetVT == MVT::ppcf128) 467 return SINTTOFP_I128_PPCF128; 468 } 469 return UNKNOWN_LIBCALL; 470} 471 472/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 473/// UNKNOWN_LIBCALL if there is none. 474RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 475 if (OpVT == MVT::i32) { 476 if (RetVT == MVT::f32) 477 return UINTTOFP_I32_F32; 478 else if (RetVT == MVT::f64) 479 return UINTTOFP_I32_F64; 480 else if (RetVT == MVT::f80) 481 return UINTTOFP_I32_F80; 482 else if (RetVT == MVT::ppcf128) 483 return UINTTOFP_I32_PPCF128; 484 } else if (OpVT == MVT::i64) { 485 if (RetVT == MVT::f32) 486 return UINTTOFP_I64_F32; 487 else if (RetVT == MVT::f64) 488 return UINTTOFP_I64_F64; 489 else if (RetVT == MVT::f80) 490 return UINTTOFP_I64_F80; 491 else if (RetVT == MVT::ppcf128) 492 return UINTTOFP_I64_PPCF128; 493 } else if (OpVT == MVT::i128) { 494 if (RetVT == MVT::f32) 495 return UINTTOFP_I128_F32; 496 else if (RetVT == MVT::f64) 497 return UINTTOFP_I128_F64; 498 else if (RetVT == MVT::f80) 499 return UINTTOFP_I128_F80; 500 else if (RetVT == MVT::ppcf128) 501 return UINTTOFP_I128_PPCF128; 502 } 503 return UNKNOWN_LIBCALL; 504} 505 506/// InitCmpLibcallCCs - Set default comparison libcall CC. 507/// 508static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 509 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 510 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 511 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 512 CCs[RTLIB::UNE_F32] = ISD::SETNE; 513 CCs[RTLIB::UNE_F64] = ISD::SETNE; 514 CCs[RTLIB::OGE_F32] = ISD::SETGE; 515 CCs[RTLIB::OGE_F64] = ISD::SETGE; 516 CCs[RTLIB::OLT_F32] = ISD::SETLT; 517 CCs[RTLIB::OLT_F64] = ISD::SETLT; 518 CCs[RTLIB::OLE_F32] = ISD::SETLE; 519 CCs[RTLIB::OLE_F64] = ISD::SETLE; 520 CCs[RTLIB::OGT_F32] = ISD::SETGT; 521 CCs[RTLIB::OGT_F64] = ISD::SETGT; 522 CCs[RTLIB::UO_F32] = ISD::SETNE; 523 CCs[RTLIB::UO_F64] = ISD::SETNE; 524 CCs[RTLIB::O_F32] = ISD::SETEQ; 525 CCs[RTLIB::O_F64] = ISD::SETEQ; 526} 527 528/// NOTE: The constructor takes ownership of TLOF. 529TargetLowering::TargetLowering(const TargetMachine &tm, 530 const TargetLoweringObjectFile *tlof) 531 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 532 // All operations default to being supported. 533 memset(OpActions, 0, sizeof(OpActions)); 534 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 535 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 536 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 537 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 538 539 // Set default actions for various operations. 540 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 541 // Default all indexed load / store to expand. 542 for (unsigned IM = (unsigned)ISD::PRE_INC; 543 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 544 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 545 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 546 } 547 548 // These operations default to expand. 549 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 550 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 551 } 552 553 // Most targets ignore the @llvm.prefetch intrinsic. 554 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 555 556 // ConstantFP nodes default to expand. Targets can either change this to 557 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 558 // to optimize expansions for certain constants. 559 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 560 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 561 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 562 563 // These library functions default to expand. 564 setOperationAction(ISD::FLOG , MVT::f64, Expand); 565 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 566 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 567 setOperationAction(ISD::FEXP , MVT::f64, Expand); 568 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 569 setOperationAction(ISD::FLOG , MVT::f32, Expand); 570 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 571 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 572 setOperationAction(ISD::FEXP , MVT::f32, Expand); 573 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 574 575 // Default ISD::TRAP to expand (which turns it into abort). 576 setOperationAction(ISD::TRAP, MVT::Other, Expand); 577 578 IsLittleEndian = TD->isLittleEndian(); 579 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 580 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 581 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 582 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 583 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 584 = maxStoresPerMemmoveOptSize = 4; 585 benefitFromCodePlacementOpt = false; 586 UseUnderscoreSetJmp = false; 587 UseUnderscoreLongJmp = false; 588 SelectIsExpensive = false; 589 IntDivIsCheap = false; 590 Pow2DivIsCheap = false; 591 JumpIsExpensive = false; 592 StackPointerRegisterToSaveRestore = 0; 593 ExceptionPointerRegister = 0; 594 ExceptionSelectorRegister = 0; 595 BooleanContents = UndefinedBooleanContent; 596 SchedPreferenceInfo = Sched::Latency; 597 JumpBufSize = 0; 598 JumpBufAlignment = 0; 599 MinFunctionAlignment = 0; 600 PrefFunctionAlignment = 0; 601 PrefLoopAlignment = 0; 602 MinStackArgumentAlignment = 1; 603 ShouldFoldAtomicFences = false; 604 605 InitLibcallNames(LibcallRoutineNames); 606 InitCmpLibcallCCs(CmpLibcallCCs); 607 InitLibcallCallingConvs(LibcallCallingConvs); 608} 609 610TargetLowering::~TargetLowering() { 611 delete &TLOF; 612} 613 614MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 615 return MVT::getIntegerVT(8*TD->getPointerSize()); 616} 617 618/// canOpTrap - Returns true if the operation can trap for the value type. 619/// VT must be a legal type. 620bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 621 assert(isTypeLegal(VT)); 622 switch (Op) { 623 default: 624 return false; 625 case ISD::FDIV: 626 case ISD::FREM: 627 case ISD::SDIV: 628 case ISD::UDIV: 629 case ISD::SREM: 630 case ISD::UREM: 631 return true; 632 } 633} 634 635 636static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 637 unsigned &NumIntermediates, 638 EVT &RegisterVT, 639 TargetLowering *TLI) { 640 // Figure out the right, legal destination reg to copy into. 641 unsigned NumElts = VT.getVectorNumElements(); 642 MVT EltTy = VT.getVectorElementType(); 643 644 unsigned NumVectorRegs = 1; 645 646 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 647 // could break down into LHS/RHS like LegalizeDAG does. 648 if (!isPowerOf2_32(NumElts)) { 649 NumVectorRegs = NumElts; 650 NumElts = 1; 651 } 652 653 // Divide the input until we get to a supported size. This will always 654 // end with a scalar if the target doesn't support vectors. 655 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 656 NumElts >>= 1; 657 NumVectorRegs <<= 1; 658 } 659 660 NumIntermediates = NumVectorRegs; 661 662 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 663 if (!TLI->isTypeLegal(NewVT)) 664 NewVT = EltTy; 665 IntermediateVT = NewVT; 666 667 EVT DestVT = TLI->getRegisterType(NewVT); 668 RegisterVT = DestVT; 669 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 670 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 671 672 // Otherwise, promotion or legal types use the same number of registers as 673 // the vector decimated to the appropriate level. 674 return NumVectorRegs; 675} 676 677/// isLegalRC - Return true if the value types that can be represented by the 678/// specified register class are all legal. 679bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 680 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 681 I != E; ++I) { 682 if (isTypeLegal(*I)) 683 return true; 684 } 685 return false; 686} 687 688/// hasLegalSuperRegRegClasses - Return true if the specified register class 689/// has one or more super-reg register classes that are legal. 690bool 691TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 692 if (*RC->superregclasses_begin() == 0) 693 return false; 694 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 695 E = RC->superregclasses_end(); I != E; ++I) { 696 const TargetRegisterClass *RRC = *I; 697 if (isLegalRC(RRC)) 698 return true; 699 } 700 return false; 701} 702 703/// findRepresentativeClass - Return the largest legal super-reg register class 704/// of the register class for the specified type and its associated "cost". 705std::pair<const TargetRegisterClass*, uint8_t> 706TargetLowering::findRepresentativeClass(EVT VT) const { 707 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 708 if (!RC) 709 return std::make_pair(RC, 0); 710 const TargetRegisterClass *BestRC = RC; 711 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 712 E = RC->superregclasses_end(); I != E; ++I) { 713 const TargetRegisterClass *RRC = *I; 714 if (RRC->isASubClass() || !isLegalRC(RRC)) 715 continue; 716 if (!hasLegalSuperRegRegClasses(RRC)) 717 return std::make_pair(RRC, 1); 718 BestRC = RRC; 719 } 720 return std::make_pair(BestRC, 1); 721} 722 723 724/// computeRegisterProperties - Once all of the register classes are added, 725/// this allows us to compute derived properties we expose. 726void TargetLowering::computeRegisterProperties() { 727 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 728 "Too many value types for ValueTypeActions to hold!"); 729 730 // Everything defaults to needing one register. 731 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 732 NumRegistersForVT[i] = 1; 733 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 734 } 735 // ...except isVoid, which doesn't need any registers. 736 NumRegistersForVT[MVT::isVoid] = 0; 737 738 // Find the largest integer register class. 739 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 740 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 741 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 742 743 // Every integer value type larger than this largest register takes twice as 744 // many registers to represent as the previous ValueType. 745 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 746 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 747 if (!ExpandedVT.isInteger()) 748 break; 749 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 750 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 751 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 752 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 753 } 754 755 // Inspect all of the ValueType's smaller than the largest integer 756 // register to see which ones need promotion. 757 unsigned LegalIntReg = LargestIntReg; 758 for (unsigned IntReg = LargestIntReg - 1; 759 IntReg >= (unsigned)MVT::i1; --IntReg) { 760 EVT IVT = (MVT::SimpleValueType)IntReg; 761 if (isTypeLegal(IVT)) { 762 LegalIntReg = IntReg; 763 } else { 764 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 765 (MVT::SimpleValueType)LegalIntReg; 766 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 767 } 768 } 769 770 // ppcf128 type is really two f64's. 771 if (!isTypeLegal(MVT::ppcf128)) { 772 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 773 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 774 TransformToType[MVT::ppcf128] = MVT::f64; 775 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 776 } 777 778 // Decide how to handle f64. If the target does not have native f64 support, 779 // expand it to i64 and we will be generating soft float library calls. 780 if (!isTypeLegal(MVT::f64)) { 781 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 782 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 783 TransformToType[MVT::f64] = MVT::i64; 784 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 785 } 786 787 // Decide how to handle f32. If the target does not have native support for 788 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 789 if (!isTypeLegal(MVT::f32)) { 790 if (isTypeLegal(MVT::f64)) { 791 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 792 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 793 TransformToType[MVT::f32] = MVT::f64; 794 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 795 } else { 796 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 797 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 798 TransformToType[MVT::f32] = MVT::i32; 799 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 800 } 801 } 802 803 // Loop over all of the vector value types to see which need transformations. 804 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 805 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 806 MVT VT = (MVT::SimpleValueType)i; 807 if (isTypeLegal(VT)) continue; 808 809 // Determine if there is a legal wider type. If so, we should promote to 810 // that wider vector type. 811 EVT EltVT = VT.getVectorElementType(); 812 unsigned NElts = VT.getVectorNumElements(); 813 if (NElts != 1) { 814 bool IsLegalWiderType = false; 815 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 816 EVT SVT = (MVT::SimpleValueType)nVT; 817 if (SVT.getVectorElementType() == EltVT && 818 SVT.getVectorNumElements() > NElts && 819 isTypeLegal(SVT)) { 820 TransformToType[i] = SVT; 821 RegisterTypeForVT[i] = SVT; 822 NumRegistersForVT[i] = 1; 823 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 824 IsLegalWiderType = true; 825 break; 826 } 827 } 828 if (IsLegalWiderType) continue; 829 } 830 831 MVT IntermediateVT; 832 EVT RegisterVT; 833 unsigned NumIntermediates; 834 NumRegistersForVT[i] = 835 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 836 RegisterVT, this); 837 RegisterTypeForVT[i] = RegisterVT; 838 839 EVT NVT = VT.getPow2VectorType(); 840 if (NVT == VT) { 841 // Type is already a power of 2. The default action is to split. 842 TransformToType[i] = MVT::Other; 843 unsigned NumElts = VT.getVectorNumElements(); 844 ValueTypeActions.setTypeAction(VT, 845 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 846 } else { 847 TransformToType[i] = NVT; 848 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 849 } 850 } 851 852 // Determine the 'representative' register class for each value type. 853 // An representative register class is the largest (meaning one which is 854 // not a sub-register class / subreg register class) legal register class for 855 // a group of value types. For example, on i386, i8, i16, and i32 856 // representative would be GR32; while on x86_64 it's GR64. 857 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 858 const TargetRegisterClass* RRC; 859 uint8_t Cost; 860 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 861 RepRegClassForVT[i] = RRC; 862 RepRegClassCostForVT[i] = Cost; 863 } 864} 865 866const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 867 return NULL; 868} 869 870 871MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 872 return PointerTy.SimpleTy; 873} 874 875MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 876 return MVT::i32; // return the default value 877} 878 879/// getVectorTypeBreakdown - Vector types are broken down into some number of 880/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 881/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 882/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 883/// 884/// This method returns the number of registers needed, and the VT for each 885/// register. It also returns the VT and quantity of the intermediate values 886/// before they are promoted/expanded. 887/// 888unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 889 EVT &IntermediateVT, 890 unsigned &NumIntermediates, 891 EVT &RegisterVT) const { 892 unsigned NumElts = VT.getVectorNumElements(); 893 894 // If there is a wider vector type with the same element type as this one, 895 // we should widen to that legal vector type. This handles things like 896 // <2 x float> -> <4 x float>. 897 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 898 RegisterVT = getTypeToTransformTo(Context, VT); 899 if (isTypeLegal(RegisterVT)) { 900 IntermediateVT = RegisterVT; 901 NumIntermediates = 1; 902 return 1; 903 } 904 } 905 906 // Figure out the right, legal destination reg to copy into. 907 EVT EltTy = VT.getVectorElementType(); 908 909 unsigned NumVectorRegs = 1; 910 911 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 912 // could break down into LHS/RHS like LegalizeDAG does. 913 if (!isPowerOf2_32(NumElts)) { 914 NumVectorRegs = NumElts; 915 NumElts = 1; 916 } 917 918 // Divide the input until we get to a supported size. This will always 919 // end with a scalar if the target doesn't support vectors. 920 while (NumElts > 1 && !isTypeLegal( 921 EVT::getVectorVT(Context, EltTy, NumElts))) { 922 NumElts >>= 1; 923 NumVectorRegs <<= 1; 924 } 925 926 NumIntermediates = NumVectorRegs; 927 928 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 929 if (!isTypeLegal(NewVT)) 930 NewVT = EltTy; 931 IntermediateVT = NewVT; 932 933 EVT DestVT = getRegisterType(Context, NewVT); 934 RegisterVT = DestVT; 935 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 936 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 937 938 // Otherwise, promotion or legal types use the same number of registers as 939 // the vector decimated to the appropriate level. 940 return NumVectorRegs; 941} 942 943/// Get the EVTs and ArgFlags collections that represent the legalized return 944/// type of the given function. This does not require a DAG or a return value, 945/// and is suitable for use before any DAGs for the function are constructed. 946/// TODO: Move this out of TargetLowering.cpp. 947void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 948 SmallVectorImpl<ISD::OutputArg> &Outs, 949 const TargetLowering &TLI, 950 SmallVectorImpl<uint64_t> *Offsets) { 951 SmallVector<EVT, 4> ValueVTs; 952 ComputeValueVTs(TLI, ReturnType, ValueVTs); 953 unsigned NumValues = ValueVTs.size(); 954 if (NumValues == 0) return; 955 unsigned Offset = 0; 956 957 for (unsigned j = 0, f = NumValues; j != f; ++j) { 958 EVT VT = ValueVTs[j]; 959 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 960 961 if (attr & Attribute::SExt) 962 ExtendKind = ISD::SIGN_EXTEND; 963 else if (attr & Attribute::ZExt) 964 ExtendKind = ISD::ZERO_EXTEND; 965 966 // FIXME: C calling convention requires the return type to be promoted to 967 // at least 32-bit. But this is not necessary for non-C calling 968 // conventions. The frontend should mark functions whose return values 969 // require promoting with signext or zeroext attributes. 970 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 971 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 972 if (VT.bitsLT(MinVT)) 973 VT = MinVT; 974 } 975 976 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 977 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 978 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 979 PartVT.getTypeForEVT(ReturnType->getContext())); 980 981 // 'inreg' on function refers to return value 982 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 983 if (attr & Attribute::InReg) 984 Flags.setInReg(); 985 986 // Propagate extension type if any 987 if (attr & Attribute::SExt) 988 Flags.setSExt(); 989 else if (attr & Attribute::ZExt) 990 Flags.setZExt(); 991 992 for (unsigned i = 0; i < NumParts; ++i) { 993 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 994 if (Offsets) { 995 Offsets->push_back(Offset); 996 Offset += PartSize; 997 } 998 } 999 } 1000} 1001 1002/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1003/// function arguments in the caller parameter area. This is the actual 1004/// alignment, not its logarithm. 1005unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1006 return TD->getCallFrameTypeAlignment(Ty); 1007} 1008 1009/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1010/// current function. The returned value is a member of the 1011/// MachineJumpTableInfo::JTEntryKind enum. 1012unsigned TargetLowering::getJumpTableEncoding() const { 1013 // In non-pic modes, just use the address of a block. 1014 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1015 return MachineJumpTableInfo::EK_BlockAddress; 1016 1017 // In PIC mode, if the target supports a GPRel32 directive, use it. 1018 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1019 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1020 1021 // Otherwise, use a label difference. 1022 return MachineJumpTableInfo::EK_LabelDifference32; 1023} 1024 1025SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1026 SelectionDAG &DAG) const { 1027 // If our PIC model is GP relative, use the global offset table as the base. 1028 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1029 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1030 return Table; 1031} 1032 1033/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1034/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1035/// MCExpr. 1036const MCExpr * 1037TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1038 unsigned JTI,MCContext &Ctx) const{ 1039 // The normal PIC reloc base is the label at the start of the jump table. 1040 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1041} 1042 1043bool 1044TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1045 // Assume that everything is safe in static mode. 1046 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1047 return true; 1048 1049 // In dynamic-no-pic mode, assume that known defined values are safe. 1050 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1051 GA && 1052 !GA->getGlobal()->isDeclaration() && 1053 !GA->getGlobal()->isWeakForLinker()) 1054 return true; 1055 1056 // Otherwise assume nothing is safe. 1057 return false; 1058} 1059 1060//===----------------------------------------------------------------------===// 1061// Optimization Methods 1062//===----------------------------------------------------------------------===// 1063 1064/// ShrinkDemandedConstant - Check to see if the specified operand of the 1065/// specified instruction is a constant integer. If so, check to see if there 1066/// are any bits set in the constant that are not demanded. If so, shrink the 1067/// constant and return true. 1068bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1069 const APInt &Demanded) { 1070 DebugLoc dl = Op.getDebugLoc(); 1071 1072 // FIXME: ISD::SELECT, ISD::SELECT_CC 1073 switch (Op.getOpcode()) { 1074 default: break; 1075 case ISD::XOR: 1076 case ISD::AND: 1077 case ISD::OR: { 1078 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1079 if (!C) return false; 1080 1081 if (Op.getOpcode() == ISD::XOR && 1082 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1083 return false; 1084 1085 // if we can expand it to have all bits set, do it 1086 if (C->getAPIntValue().intersects(~Demanded)) { 1087 EVT VT = Op.getValueType(); 1088 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1089 DAG.getConstant(Demanded & 1090 C->getAPIntValue(), 1091 VT)); 1092 return CombineTo(Op, New); 1093 } 1094 1095 break; 1096 } 1097 } 1098 1099 return false; 1100} 1101 1102/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1103/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1104/// cast, but it could be generalized for targets with other types of 1105/// implicit widening casts. 1106bool 1107TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1108 unsigned BitWidth, 1109 const APInt &Demanded, 1110 DebugLoc dl) { 1111 assert(Op.getNumOperands() == 2 && 1112 "ShrinkDemandedOp only supports binary operators!"); 1113 assert(Op.getNode()->getNumValues() == 1 && 1114 "ShrinkDemandedOp only supports nodes with one result!"); 1115 1116 // Don't do this if the node has another user, which may require the 1117 // full value. 1118 if (!Op.getNode()->hasOneUse()) 1119 return false; 1120 1121 // Search for the smallest integer type with free casts to and from 1122 // Op's type. For expedience, just check power-of-2 integer types. 1123 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1124 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1125 if (!isPowerOf2_32(SmallVTBits)) 1126 SmallVTBits = NextPowerOf2(SmallVTBits); 1127 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1128 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1129 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1130 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1131 // We found a type with free casts. 1132 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1133 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1134 Op.getNode()->getOperand(0)), 1135 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1136 Op.getNode()->getOperand(1))); 1137 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1138 return CombineTo(Op, Z); 1139 } 1140 } 1141 return false; 1142} 1143 1144/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1145/// DemandedMask bits of the result of Op are ever used downstream. If we can 1146/// use this information to simplify Op, create a new simplified DAG node and 1147/// return true, returning the original and new nodes in Old and New. Otherwise, 1148/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1149/// the expression (used to simplify the caller). The KnownZero/One bits may 1150/// only be accurate for those bits in the DemandedMask. 1151bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1152 const APInt &DemandedMask, 1153 APInt &KnownZero, 1154 APInt &KnownOne, 1155 TargetLoweringOpt &TLO, 1156 unsigned Depth) const { 1157 unsigned BitWidth = DemandedMask.getBitWidth(); 1158 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1159 "Mask size mismatches value type size!"); 1160 APInt NewMask = DemandedMask; 1161 DebugLoc dl = Op.getDebugLoc(); 1162 1163 // Don't know anything. 1164 KnownZero = KnownOne = APInt(BitWidth, 0); 1165 1166 // Other users may use these bits. 1167 if (!Op.getNode()->hasOneUse()) { 1168 if (Depth != 0) { 1169 // If not at the root, Just compute the KnownZero/KnownOne bits to 1170 // simplify things downstream. 1171 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1172 return false; 1173 } 1174 // If this is the root being simplified, allow it to have multiple uses, 1175 // just set the NewMask to all bits. 1176 NewMask = APInt::getAllOnesValue(BitWidth); 1177 } else if (DemandedMask == 0) { 1178 // Not demanding any bits from Op. 1179 if (Op.getOpcode() != ISD::UNDEF) 1180 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1181 return false; 1182 } else if (Depth == 6) { // Limit search depth. 1183 return false; 1184 } 1185 1186 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1187 switch (Op.getOpcode()) { 1188 case ISD::Constant: 1189 // We know all of the bits for a constant! 1190 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1191 KnownZero = ~KnownOne & NewMask; 1192 return false; // Don't fall through, will infinitely loop. 1193 case ISD::AND: 1194 // If the RHS is a constant, check to see if the LHS would be zero without 1195 // using the bits from the RHS. Below, we use knowledge about the RHS to 1196 // simplify the LHS, here we're using information from the LHS to simplify 1197 // the RHS. 1198 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1199 APInt LHSZero, LHSOne; 1200 // Do not increment Depth here; that can cause an infinite loop. 1201 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1202 LHSZero, LHSOne, Depth); 1203 // If the LHS already has zeros where RHSC does, this and is dead. 1204 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1205 return TLO.CombineTo(Op, Op.getOperand(0)); 1206 // If any of the set bits in the RHS are known zero on the LHS, shrink 1207 // the constant. 1208 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1209 return true; 1210 } 1211 1212 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1213 KnownOne, TLO, Depth+1)) 1214 return true; 1215 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1216 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1217 KnownZero2, KnownOne2, TLO, Depth+1)) 1218 return true; 1219 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1220 1221 // If all of the demanded bits are known one on one side, return the other. 1222 // These bits cannot contribute to the result of the 'and'. 1223 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1224 return TLO.CombineTo(Op, Op.getOperand(0)); 1225 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1226 return TLO.CombineTo(Op, Op.getOperand(1)); 1227 // If all of the demanded bits in the inputs are known zeros, return zero. 1228 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1229 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1230 // If the RHS is a constant, see if we can simplify it. 1231 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1232 return true; 1233 // If the operation can be done in a smaller type, do so. 1234 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1235 return true; 1236 1237 // Output known-1 bits are only known if set in both the LHS & RHS. 1238 KnownOne &= KnownOne2; 1239 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1240 KnownZero |= KnownZero2; 1241 break; 1242 case ISD::OR: 1243 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1244 KnownOne, TLO, Depth+1)) 1245 return true; 1246 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1247 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1248 KnownZero2, KnownOne2, TLO, Depth+1)) 1249 return true; 1250 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1251 1252 // If all of the demanded bits are known zero on one side, return the other. 1253 // These bits cannot contribute to the result of the 'or'. 1254 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1255 return TLO.CombineTo(Op, Op.getOperand(0)); 1256 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1257 return TLO.CombineTo(Op, Op.getOperand(1)); 1258 // If all of the potentially set bits on one side are known to be set on 1259 // the other side, just use the 'other' side. 1260 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1261 return TLO.CombineTo(Op, Op.getOperand(0)); 1262 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1263 return TLO.CombineTo(Op, Op.getOperand(1)); 1264 // If the RHS is a constant, see if we can simplify it. 1265 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1266 return true; 1267 // If the operation can be done in a smaller type, do so. 1268 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1269 return true; 1270 1271 // Output known-0 bits are only known if clear in both the LHS & RHS. 1272 KnownZero &= KnownZero2; 1273 // Output known-1 are known to be set if set in either the LHS | RHS. 1274 KnownOne |= KnownOne2; 1275 break; 1276 case ISD::XOR: 1277 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1278 KnownOne, TLO, Depth+1)) 1279 return true; 1280 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1281 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1282 KnownOne2, TLO, Depth+1)) 1283 return true; 1284 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1285 1286 // If all of the demanded bits are known zero on one side, return the other. 1287 // These bits cannot contribute to the result of the 'xor'. 1288 if ((KnownZero & NewMask) == NewMask) 1289 return TLO.CombineTo(Op, Op.getOperand(0)); 1290 if ((KnownZero2 & NewMask) == NewMask) 1291 return TLO.CombineTo(Op, Op.getOperand(1)); 1292 // If the operation can be done in a smaller type, do so. 1293 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1294 return true; 1295 1296 // If all of the unknown bits are known to be zero on one side or the other 1297 // (but not both) turn this into an *inclusive* or. 1298 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1299 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1300 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1301 Op.getOperand(0), 1302 Op.getOperand(1))); 1303 1304 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1305 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1306 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1307 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1308 1309 // If all of the demanded bits on one side are known, and all of the set 1310 // bits on that side are also known to be set on the other side, turn this 1311 // into an AND, as we know the bits will be cleared. 1312 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1313 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1314 if ((KnownOne & KnownOne2) == KnownOne) { 1315 EVT VT = Op.getValueType(); 1316 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1317 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1318 Op.getOperand(0), ANDC)); 1319 } 1320 } 1321 1322 // If the RHS is a constant, see if we can simplify it. 1323 // for XOR, we prefer to force bits to 1 if they will make a -1. 1324 // if we can't force bits, try to shrink constant 1325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1326 APInt Expanded = C->getAPIntValue() | (~NewMask); 1327 // if we can expand it to have all bits set, do it 1328 if (Expanded.isAllOnesValue()) { 1329 if (Expanded != C->getAPIntValue()) { 1330 EVT VT = Op.getValueType(); 1331 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1332 TLO.DAG.getConstant(Expanded, VT)); 1333 return TLO.CombineTo(Op, New); 1334 } 1335 // if it already has all the bits set, nothing to change 1336 // but don't shrink either! 1337 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1338 return true; 1339 } 1340 } 1341 1342 KnownZero = KnownZeroOut; 1343 KnownOne = KnownOneOut; 1344 break; 1345 case ISD::SELECT: 1346 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1347 KnownOne, TLO, Depth+1)) 1348 return true; 1349 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1350 KnownOne2, TLO, Depth+1)) 1351 return true; 1352 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1353 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1354 1355 // If the operands are constants, see if we can simplify them. 1356 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1357 return true; 1358 1359 // Only known if known in both the LHS and RHS. 1360 KnownOne &= KnownOne2; 1361 KnownZero &= KnownZero2; 1362 break; 1363 case ISD::SELECT_CC: 1364 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1365 KnownOne, TLO, Depth+1)) 1366 return true; 1367 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1368 KnownOne2, TLO, Depth+1)) 1369 return true; 1370 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1371 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1372 1373 // If the operands are constants, see if we can simplify them. 1374 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1375 return true; 1376 1377 // Only known if known in both the LHS and RHS. 1378 KnownOne &= KnownOne2; 1379 KnownZero &= KnownZero2; 1380 break; 1381 case ISD::SHL: 1382 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1383 unsigned ShAmt = SA->getZExtValue(); 1384 SDValue InOp = Op.getOperand(0); 1385 1386 // If the shift count is an invalid immediate, don't do anything. 1387 if (ShAmt >= BitWidth) 1388 break; 1389 1390 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1391 // single shift. We can do this if the bottom bits (which are shifted 1392 // out) are never demanded. 1393 if (InOp.getOpcode() == ISD::SRL && 1394 isa<ConstantSDNode>(InOp.getOperand(1))) { 1395 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1396 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1397 unsigned Opc = ISD::SHL; 1398 int Diff = ShAmt-C1; 1399 if (Diff < 0) { 1400 Diff = -Diff; 1401 Opc = ISD::SRL; 1402 } 1403 1404 SDValue NewSA = 1405 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1406 EVT VT = Op.getValueType(); 1407 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1408 InOp.getOperand(0), NewSA)); 1409 } 1410 } 1411 1412 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1413 KnownZero, KnownOne, TLO, Depth+1)) 1414 return true; 1415 1416 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1417 // are not demanded. This will likely allow the anyext to be folded away. 1418 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1419 SDValue InnerOp = InOp.getNode()->getOperand(0); 1420 EVT InnerVT = InnerOp.getValueType(); 1421 if ((APInt::getHighBitsSet(BitWidth, 1422 BitWidth - InnerVT.getSizeInBits()) & 1423 DemandedMask) == 0 && 1424 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1425 EVT ShTy = getShiftAmountTy(InnerVT); 1426 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1427 ShTy = InnerVT; 1428 SDValue NarrowShl = 1429 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1430 TLO.DAG.getConstant(ShAmt, ShTy)); 1431 return 1432 TLO.CombineTo(Op, 1433 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1434 NarrowShl)); 1435 } 1436 } 1437 1438 KnownZero <<= SA->getZExtValue(); 1439 KnownOne <<= SA->getZExtValue(); 1440 // low bits known zero. 1441 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1442 } 1443 break; 1444 case ISD::SRL: 1445 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1446 EVT VT = Op.getValueType(); 1447 unsigned ShAmt = SA->getZExtValue(); 1448 unsigned VTSize = VT.getSizeInBits(); 1449 SDValue InOp = Op.getOperand(0); 1450 1451 // If the shift count is an invalid immediate, don't do anything. 1452 if (ShAmt >= BitWidth) 1453 break; 1454 1455 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1456 // single shift. We can do this if the top bits (which are shifted out) 1457 // are never demanded. 1458 if (InOp.getOpcode() == ISD::SHL && 1459 isa<ConstantSDNode>(InOp.getOperand(1))) { 1460 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1461 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1462 unsigned Opc = ISD::SRL; 1463 int Diff = ShAmt-C1; 1464 if (Diff < 0) { 1465 Diff = -Diff; 1466 Opc = ISD::SHL; 1467 } 1468 1469 SDValue NewSA = 1470 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1471 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1472 InOp.getOperand(0), NewSA)); 1473 } 1474 } 1475 1476 // Compute the new bits that are at the top now. 1477 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1478 KnownZero, KnownOne, TLO, Depth+1)) 1479 return true; 1480 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1481 KnownZero = KnownZero.lshr(ShAmt); 1482 KnownOne = KnownOne.lshr(ShAmt); 1483 1484 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1485 KnownZero |= HighBits; // High bits known zero. 1486 } 1487 break; 1488 case ISD::SRA: 1489 // If this is an arithmetic shift right and only the low-bit is set, we can 1490 // always convert this into a logical shr, even if the shift amount is 1491 // variable. The low bit of the shift cannot be an input sign bit unless 1492 // the shift amount is >= the size of the datatype, which is undefined. 1493 if (DemandedMask == 1) 1494 return TLO.CombineTo(Op, 1495 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1496 Op.getOperand(0), Op.getOperand(1))); 1497 1498 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1499 EVT VT = Op.getValueType(); 1500 unsigned ShAmt = SA->getZExtValue(); 1501 1502 // If the shift count is an invalid immediate, don't do anything. 1503 if (ShAmt >= BitWidth) 1504 break; 1505 1506 APInt InDemandedMask = (NewMask << ShAmt); 1507 1508 // If any of the demanded bits are produced by the sign extension, we also 1509 // demand the input sign bit. 1510 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1511 if (HighBits.intersects(NewMask)) 1512 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1513 1514 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1515 KnownZero, KnownOne, TLO, Depth+1)) 1516 return true; 1517 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1518 KnownZero = KnownZero.lshr(ShAmt); 1519 KnownOne = KnownOne.lshr(ShAmt); 1520 1521 // Handle the sign bit, adjusted to where it is now in the mask. 1522 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1523 1524 // If the input sign bit is known to be zero, or if none of the top bits 1525 // are demanded, turn this into an unsigned shift right. 1526 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1527 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1528 Op.getOperand(0), 1529 Op.getOperand(1))); 1530 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1531 KnownOne |= HighBits; 1532 } 1533 } 1534 break; 1535 case ISD::SIGN_EXTEND_INREG: { 1536 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1537 1538 // Sign extension. Compute the demanded bits in the result that are not 1539 // present in the input. 1540 APInt NewBits = 1541 APInt::getHighBitsSet(BitWidth, 1542 BitWidth - EVT.getScalarType().getSizeInBits()); 1543 1544 // If none of the extended bits are demanded, eliminate the sextinreg. 1545 if ((NewBits & NewMask) == 0) 1546 return TLO.CombineTo(Op, Op.getOperand(0)); 1547 1548 APInt InSignBit = 1549 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1550 APInt InputDemandedBits = 1551 APInt::getLowBitsSet(BitWidth, 1552 EVT.getScalarType().getSizeInBits()) & 1553 NewMask; 1554 1555 // Since the sign extended bits are demanded, we know that the sign 1556 // bit is demanded. 1557 InputDemandedBits |= InSignBit; 1558 1559 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1560 KnownZero, KnownOne, TLO, Depth+1)) 1561 return true; 1562 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1563 1564 // If the sign bit of the input is known set or clear, then we know the 1565 // top bits of the result. 1566 1567 // If the input sign bit is known zero, convert this into a zero extension. 1568 if (KnownZero.intersects(InSignBit)) 1569 return TLO.CombineTo(Op, 1570 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1571 1572 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1573 KnownOne |= NewBits; 1574 KnownZero &= ~NewBits; 1575 } else { // Input sign bit unknown 1576 KnownZero &= ~NewBits; 1577 KnownOne &= ~NewBits; 1578 } 1579 break; 1580 } 1581 case ISD::ZERO_EXTEND: { 1582 unsigned OperandBitWidth = 1583 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1584 APInt InMask = NewMask.trunc(OperandBitWidth); 1585 1586 // If none of the top bits are demanded, convert this into an any_extend. 1587 APInt NewBits = 1588 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1589 if (!NewBits.intersects(NewMask)) 1590 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1591 Op.getValueType(), 1592 Op.getOperand(0))); 1593 1594 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1595 KnownZero, KnownOne, TLO, Depth+1)) 1596 return true; 1597 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1598 KnownZero = KnownZero.zext(BitWidth); 1599 KnownOne = KnownOne.zext(BitWidth); 1600 KnownZero |= NewBits; 1601 break; 1602 } 1603 case ISD::SIGN_EXTEND: { 1604 EVT InVT = Op.getOperand(0).getValueType(); 1605 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1606 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1607 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1608 APInt NewBits = ~InMask & NewMask; 1609 1610 // If none of the top bits are demanded, convert this into an any_extend. 1611 if (NewBits == 0) 1612 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1613 Op.getValueType(), 1614 Op.getOperand(0))); 1615 1616 // Since some of the sign extended bits are demanded, we know that the sign 1617 // bit is demanded. 1618 APInt InDemandedBits = InMask & NewMask; 1619 InDemandedBits |= InSignBit; 1620 InDemandedBits = InDemandedBits.trunc(InBits); 1621 1622 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1623 KnownOne, TLO, Depth+1)) 1624 return true; 1625 KnownZero = KnownZero.zext(BitWidth); 1626 KnownOne = KnownOne.zext(BitWidth); 1627 1628 // If the sign bit is known zero, convert this to a zero extend. 1629 if (KnownZero.intersects(InSignBit)) 1630 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1631 Op.getValueType(), 1632 Op.getOperand(0))); 1633 1634 // If the sign bit is known one, the top bits match. 1635 if (KnownOne.intersects(InSignBit)) { 1636 KnownOne |= NewBits; 1637 KnownZero &= ~NewBits; 1638 } else { // Otherwise, top bits aren't known. 1639 KnownOne &= ~NewBits; 1640 KnownZero &= ~NewBits; 1641 } 1642 break; 1643 } 1644 case ISD::ANY_EXTEND: { 1645 unsigned OperandBitWidth = 1646 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1647 APInt InMask = NewMask.trunc(OperandBitWidth); 1648 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1649 KnownZero, KnownOne, TLO, Depth+1)) 1650 return true; 1651 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1652 KnownZero = KnownZero.zext(BitWidth); 1653 KnownOne = KnownOne.zext(BitWidth); 1654 break; 1655 } 1656 case ISD::TRUNCATE: { 1657 // Simplify the input, using demanded bit information, and compute the known 1658 // zero/one bits live out. 1659 unsigned OperandBitWidth = 1660 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1661 APInt TruncMask = NewMask.zext(OperandBitWidth); 1662 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1663 KnownZero, KnownOne, TLO, Depth+1)) 1664 return true; 1665 KnownZero = KnownZero.trunc(BitWidth); 1666 KnownOne = KnownOne.trunc(BitWidth); 1667 1668 // If the input is only used by this truncate, see if we can shrink it based 1669 // on the known demanded bits. 1670 if (Op.getOperand(0).getNode()->hasOneUse()) { 1671 SDValue In = Op.getOperand(0); 1672 switch (In.getOpcode()) { 1673 default: break; 1674 case ISD::SRL: 1675 // Shrink SRL by a constant if none of the high bits shifted in are 1676 // demanded. 1677 if (TLO.LegalTypes() && 1678 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1679 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1680 // undesirable. 1681 break; 1682 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1683 if (!ShAmt) 1684 break; 1685 SDValue Shift = In.getOperand(1); 1686 if (TLO.LegalTypes()) { 1687 uint64_t ShVal = ShAmt->getZExtValue(); 1688 Shift = 1689 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1690 } 1691 1692 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1693 OperandBitWidth - BitWidth); 1694 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1695 1696 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1697 // None of the shifted in bits are needed. Add a truncate of the 1698 // shift input, then shift it. 1699 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1700 Op.getValueType(), 1701 In.getOperand(0)); 1702 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1703 Op.getValueType(), 1704 NewTrunc, 1705 Shift)); 1706 } 1707 break; 1708 } 1709 } 1710 1711 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1712 break; 1713 } 1714 case ISD::AssertZext: { 1715 // Demand all the bits of the input that are demanded in the output. 1716 // The low bits are obvious; the high bits are demanded because we're 1717 // asserting that they're zero here. 1718 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1719 KnownZero, KnownOne, TLO, Depth+1)) 1720 return true; 1721 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1722 1723 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1724 APInt InMask = APInt::getLowBitsSet(BitWidth, 1725 VT.getSizeInBits()); 1726 KnownZero |= ~InMask & NewMask; 1727 break; 1728 } 1729 case ISD::BITCAST: 1730#if 0 1731 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1732 // is demanded, turn this into a FGETSIGN. 1733 if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1734 Op.getOperand(0).getValueType().isFloatingPoint() && 1735 !Op.getOperand(0).getValueType().isVector()) { 1736 // Only do this xform if FGETSIGN is valid or if before legalize. 1737 if (TLO.isBeforeLegalize() || 1738 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1739 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1740 // place. We expect the SHL to be eliminated by other optimizations. 1741 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), 1742 Op.getOperand(0)); 1743 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1744 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1745 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1746 Op.getValueType(), 1747 Sign, ShAmt)); 1748 } 1749 } 1750#endif 1751 break; 1752 case ISD::ADD: 1753 case ISD::MUL: 1754 case ISD::SUB: { 1755 // Add, Sub, and Mul don't demand any bits in positions beyond that 1756 // of the highest bit demanded of them. 1757 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1758 BitWidth - NewMask.countLeadingZeros()); 1759 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1760 KnownOne2, TLO, Depth+1)) 1761 return true; 1762 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1763 KnownOne2, TLO, Depth+1)) 1764 return true; 1765 // See if the operation should be performed at a smaller bit width. 1766 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1767 return true; 1768 } 1769 // FALL THROUGH 1770 default: 1771 // Just use ComputeMaskedBits to compute output bits. 1772 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1773 break; 1774 } 1775 1776 // If we know the value of all of the demanded bits, return this as a 1777 // constant. 1778 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1779 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1780 1781 return false; 1782} 1783 1784/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1785/// in Mask are known to be either zero or one and return them in the 1786/// KnownZero/KnownOne bitsets. 1787void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1788 const APInt &Mask, 1789 APInt &KnownZero, 1790 APInt &KnownOne, 1791 const SelectionDAG &DAG, 1792 unsigned Depth) const { 1793 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1794 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1795 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1796 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1797 "Should use MaskedValueIsZero if you don't know whether Op" 1798 " is a target node!"); 1799 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1800} 1801 1802/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1803/// targets that want to expose additional information about sign bits to the 1804/// DAG Combiner. 1805unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1806 unsigned Depth) const { 1807 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1808 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1809 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1810 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1811 "Should use ComputeNumSignBits if you don't know whether Op" 1812 " is a target node!"); 1813 return 1; 1814} 1815 1816/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1817/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1818/// determine which bit is set. 1819/// 1820static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1821 // A left-shift of a constant one will have exactly one bit set, because 1822 // shifting the bit off the end is undefined. 1823 if (Val.getOpcode() == ISD::SHL) 1824 if (ConstantSDNode *C = 1825 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1826 if (C->getAPIntValue() == 1) 1827 return true; 1828 1829 // Similarly, a right-shift of a constant sign-bit will have exactly 1830 // one bit set. 1831 if (Val.getOpcode() == ISD::SRL) 1832 if (ConstantSDNode *C = 1833 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1834 if (C->getAPIntValue().isSignBit()) 1835 return true; 1836 1837 // More could be done here, though the above checks are enough 1838 // to handle some common cases. 1839 1840 // Fall back to ComputeMaskedBits to catch other known cases. 1841 EVT OpVT = Val.getValueType(); 1842 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1843 APInt Mask = APInt::getAllOnesValue(BitWidth); 1844 APInt KnownZero, KnownOne; 1845 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1846 return (KnownZero.countPopulation() == BitWidth - 1) && 1847 (KnownOne.countPopulation() == 1); 1848} 1849 1850/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1851/// and cc. If it is unable to simplify it, return a null SDValue. 1852SDValue 1853TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1854 ISD::CondCode Cond, bool foldBooleans, 1855 DAGCombinerInfo &DCI, DebugLoc dl) const { 1856 SelectionDAG &DAG = DCI.DAG; 1857 1858 // These setcc operations always fold. 1859 switch (Cond) { 1860 default: break; 1861 case ISD::SETFALSE: 1862 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1863 case ISD::SETTRUE: 1864 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1865 } 1866 1867 // Ensure that the constant occurs on the RHS, and fold constant 1868 // comparisons. 1869 if (isa<ConstantSDNode>(N0.getNode())) 1870 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1871 1872 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1873 const APInt &C1 = N1C->getAPIntValue(); 1874 1875 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1876 // equality comparison, then we're just comparing whether X itself is 1877 // zero. 1878 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1879 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1880 N0.getOperand(1).getOpcode() == ISD::Constant) { 1881 const APInt &ShAmt 1882 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1883 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1884 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1885 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1886 // (srl (ctlz x), 5) == 0 -> X != 0 1887 // (srl (ctlz x), 5) != 1 -> X != 0 1888 Cond = ISD::SETNE; 1889 } else { 1890 // (srl (ctlz x), 5) != 0 -> X == 0 1891 // (srl (ctlz x), 5) == 1 -> X == 0 1892 Cond = ISD::SETEQ; 1893 } 1894 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1895 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1896 Zero, Cond); 1897 } 1898 } 1899 1900 SDValue CTPOP = N0; 1901 // Look through truncs that don't change the value of a ctpop. 1902 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1903 CTPOP = N0.getOperand(0); 1904 1905 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1906 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1907 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1908 EVT CTVT = CTPOP.getValueType(); 1909 SDValue CTOp = CTPOP.getOperand(0); 1910 1911 // (ctpop x) u< 2 -> (x & x-1) == 0 1912 // (ctpop x) u> 1 -> (x & x-1) != 0 1913 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1914 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1915 DAG.getConstant(1, CTVT)); 1916 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1917 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1918 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1919 } 1920 1921 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1922 } 1923 1924 // (zext x) == C --> x == (trunc C) 1925 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1926 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1927 unsigned MinBits = N0.getValueSizeInBits(); 1928 SDValue PreZExt; 1929 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1930 // ZExt 1931 MinBits = N0->getOperand(0).getValueSizeInBits(); 1932 PreZExt = N0->getOperand(0); 1933 } else if (N0->getOpcode() == ISD::AND) { 1934 // DAGCombine turns costly ZExts into ANDs 1935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1936 if ((C->getAPIntValue()+1).isPowerOf2()) { 1937 MinBits = C->getAPIntValue().countTrailingOnes(); 1938 PreZExt = N0->getOperand(0); 1939 } 1940 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1941 // ZEXTLOAD 1942 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1943 MinBits = LN0->getMemoryVT().getSizeInBits(); 1944 PreZExt = N0; 1945 } 1946 } 1947 1948 // Make sure we're not loosing bits from the constant. 1949 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 1950 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1951 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1952 // Will get folded away. 1953 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1954 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1955 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1956 } 1957 } 1958 } 1959 1960 // If the LHS is '(and load, const)', the RHS is 0, 1961 // the test is for equality or unsigned, and all 1 bits of the const are 1962 // in the same partial word, see if we can shorten the load. 1963 if (DCI.isBeforeLegalize() && 1964 N0.getOpcode() == ISD::AND && C1 == 0 && 1965 N0.getNode()->hasOneUse() && 1966 isa<LoadSDNode>(N0.getOperand(0)) && 1967 N0.getOperand(0).getNode()->hasOneUse() && 1968 isa<ConstantSDNode>(N0.getOperand(1))) { 1969 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1970 APInt bestMask; 1971 unsigned bestWidth = 0, bestOffset = 0; 1972 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1973 unsigned origWidth = N0.getValueType().getSizeInBits(); 1974 unsigned maskWidth = origWidth; 1975 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1976 // 8 bits, but have to be careful... 1977 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1978 origWidth = Lod->getMemoryVT().getSizeInBits(); 1979 const APInt &Mask = 1980 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1981 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1982 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1983 for (unsigned offset=0; offset<origWidth/width; offset++) { 1984 if ((newMask & Mask) == Mask) { 1985 if (!TD->isLittleEndian()) 1986 bestOffset = (origWidth/width - offset - 1) * (width/8); 1987 else 1988 bestOffset = (uint64_t)offset * (width/8); 1989 bestMask = Mask.lshr(offset * (width/8) * 8); 1990 bestWidth = width; 1991 break; 1992 } 1993 newMask = newMask << width; 1994 } 1995 } 1996 } 1997 if (bestWidth) { 1998 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 1999 if (newVT.isRound()) { 2000 EVT PtrType = Lod->getOperand(1).getValueType(); 2001 SDValue Ptr = Lod->getBasePtr(); 2002 if (bestOffset != 0) 2003 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2004 DAG.getConstant(bestOffset, PtrType)); 2005 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2006 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2007 Lod->getPointerInfo().getWithOffset(bestOffset), 2008 false, false, NewAlign); 2009 return DAG.getSetCC(dl, VT, 2010 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2011 DAG.getConstant(bestMask.trunc(bestWidth), 2012 newVT)), 2013 DAG.getConstant(0LL, newVT), Cond); 2014 } 2015 } 2016 } 2017 2018 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2019 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2020 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2021 2022 // If the comparison constant has bits in the upper part, the 2023 // zero-extended value could never match. 2024 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2025 C1.getBitWidth() - InSize))) { 2026 switch (Cond) { 2027 case ISD::SETUGT: 2028 case ISD::SETUGE: 2029 case ISD::SETEQ: return DAG.getConstant(0, VT); 2030 case ISD::SETULT: 2031 case ISD::SETULE: 2032 case ISD::SETNE: return DAG.getConstant(1, VT); 2033 case ISD::SETGT: 2034 case ISD::SETGE: 2035 // True if the sign bit of C1 is set. 2036 return DAG.getConstant(C1.isNegative(), VT); 2037 case ISD::SETLT: 2038 case ISD::SETLE: 2039 // True if the sign bit of C1 isn't set. 2040 return DAG.getConstant(C1.isNonNegative(), VT); 2041 default: 2042 break; 2043 } 2044 } 2045 2046 // Otherwise, we can perform the comparison with the low bits. 2047 switch (Cond) { 2048 case ISD::SETEQ: 2049 case ISD::SETNE: 2050 case ISD::SETUGT: 2051 case ISD::SETUGE: 2052 case ISD::SETULT: 2053 case ISD::SETULE: { 2054 EVT newVT = N0.getOperand(0).getValueType(); 2055 if (DCI.isBeforeLegalizeOps() || 2056 (isOperationLegal(ISD::SETCC, newVT) && 2057 getCondCodeAction(Cond, newVT)==Legal)) 2058 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2059 DAG.getConstant(C1.trunc(InSize), newVT), 2060 Cond); 2061 break; 2062 } 2063 default: 2064 break; // todo, be more careful with signed comparisons 2065 } 2066 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2067 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2068 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2069 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2070 EVT ExtDstTy = N0.getValueType(); 2071 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2072 2073 // If the constant doesn't fit into the number of bits for the source of 2074 // the sign extension, it is impossible for both sides to be equal. 2075 if (C1.getMinSignedBits() > ExtSrcTyBits) 2076 return DAG.getConstant(Cond == ISD::SETNE, VT); 2077 2078 SDValue ZextOp; 2079 EVT Op0Ty = N0.getOperand(0).getValueType(); 2080 if (Op0Ty == ExtSrcTy) { 2081 ZextOp = N0.getOperand(0); 2082 } else { 2083 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2084 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2085 DAG.getConstant(Imm, Op0Ty)); 2086 } 2087 if (!DCI.isCalledByLegalizer()) 2088 DCI.AddToWorklist(ZextOp.getNode()); 2089 // Otherwise, make this a use of a zext. 2090 return DAG.getSetCC(dl, VT, ZextOp, 2091 DAG.getConstant(C1 & APInt::getLowBitsSet( 2092 ExtDstTyBits, 2093 ExtSrcTyBits), 2094 ExtDstTy), 2095 Cond); 2096 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2097 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2098 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2099 if (N0.getOpcode() == ISD::SETCC && 2100 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2101 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2102 if (TrueWhenTrue) 2103 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2104 // Invert the condition. 2105 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2106 CC = ISD::getSetCCInverse(CC, 2107 N0.getOperand(0).getValueType().isInteger()); 2108 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2109 } 2110 2111 if ((N0.getOpcode() == ISD::XOR || 2112 (N0.getOpcode() == ISD::AND && 2113 N0.getOperand(0).getOpcode() == ISD::XOR && 2114 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2115 isa<ConstantSDNode>(N0.getOperand(1)) && 2116 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2117 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2118 // can only do this if the top bits are known zero. 2119 unsigned BitWidth = N0.getValueSizeInBits(); 2120 if (DAG.MaskedValueIsZero(N0, 2121 APInt::getHighBitsSet(BitWidth, 2122 BitWidth-1))) { 2123 // Okay, get the un-inverted input value. 2124 SDValue Val; 2125 if (N0.getOpcode() == ISD::XOR) 2126 Val = N0.getOperand(0); 2127 else { 2128 assert(N0.getOpcode() == ISD::AND && 2129 N0.getOperand(0).getOpcode() == ISD::XOR); 2130 // ((X^1)&1)^1 -> X & 1 2131 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2132 N0.getOperand(0).getOperand(0), 2133 N0.getOperand(1)); 2134 } 2135 2136 return DAG.getSetCC(dl, VT, Val, N1, 2137 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2138 } 2139 } else if (N1C->getAPIntValue() == 1 && 2140 (VT == MVT::i1 || 2141 getBooleanContents() == ZeroOrOneBooleanContent)) { 2142 SDValue Op0 = N0; 2143 if (Op0.getOpcode() == ISD::TRUNCATE) 2144 Op0 = Op0.getOperand(0); 2145 2146 if ((Op0.getOpcode() == ISD::XOR) && 2147 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2148 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2149 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2150 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2151 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2152 Cond); 2153 } else if (Op0.getOpcode() == ISD::AND && 2154 isa<ConstantSDNode>(Op0.getOperand(1)) && 2155 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2156 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2157 if (Op0.getValueType().bitsGT(VT)) 2158 Op0 = DAG.getNode(ISD::AND, dl, VT, 2159 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2160 DAG.getConstant(1, VT)); 2161 else if (Op0.getValueType().bitsLT(VT)) 2162 Op0 = DAG.getNode(ISD::AND, dl, VT, 2163 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2164 DAG.getConstant(1, VT)); 2165 2166 return DAG.getSetCC(dl, VT, Op0, 2167 DAG.getConstant(0, Op0.getValueType()), 2168 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2169 } 2170 } 2171 } 2172 2173 APInt MinVal, MaxVal; 2174 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2175 if (ISD::isSignedIntSetCC(Cond)) { 2176 MinVal = APInt::getSignedMinValue(OperandBitSize); 2177 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2178 } else { 2179 MinVal = APInt::getMinValue(OperandBitSize); 2180 MaxVal = APInt::getMaxValue(OperandBitSize); 2181 } 2182 2183 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2184 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2185 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2186 // X >= C0 --> X > (C0-1) 2187 return DAG.getSetCC(dl, VT, N0, 2188 DAG.getConstant(C1-1, N1.getValueType()), 2189 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2190 } 2191 2192 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2193 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2194 // X <= C0 --> X < (C0+1) 2195 return DAG.getSetCC(dl, VT, N0, 2196 DAG.getConstant(C1+1, N1.getValueType()), 2197 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2198 } 2199 2200 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2201 return DAG.getConstant(0, VT); // X < MIN --> false 2202 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2203 return DAG.getConstant(1, VT); // X >= MIN --> true 2204 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2205 return DAG.getConstant(0, VT); // X > MAX --> false 2206 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2207 return DAG.getConstant(1, VT); // X <= MAX --> true 2208 2209 // Canonicalize setgt X, Min --> setne X, Min 2210 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2211 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2212 // Canonicalize setlt X, Max --> setne X, Max 2213 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2214 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2215 2216 // If we have setult X, 1, turn it into seteq X, 0 2217 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2218 return DAG.getSetCC(dl, VT, N0, 2219 DAG.getConstant(MinVal, N0.getValueType()), 2220 ISD::SETEQ); 2221 // If we have setugt X, Max-1, turn it into seteq X, Max 2222 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2223 return DAG.getSetCC(dl, VT, N0, 2224 DAG.getConstant(MaxVal, N0.getValueType()), 2225 ISD::SETEQ); 2226 2227 // If we have "setcc X, C0", check to see if we can shrink the immediate 2228 // by changing cc. 2229 2230 // SETUGT X, SINTMAX -> SETLT X, 0 2231 if (Cond == ISD::SETUGT && 2232 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2233 return DAG.getSetCC(dl, VT, N0, 2234 DAG.getConstant(0, N1.getValueType()), 2235 ISD::SETLT); 2236 2237 // SETULT X, SINTMIN -> SETGT X, -1 2238 if (Cond == ISD::SETULT && 2239 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2240 SDValue ConstMinusOne = 2241 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2242 N1.getValueType()); 2243 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2244 } 2245 2246 // Fold bit comparisons when we can. 2247 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2248 (VT == N0.getValueType() || 2249 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2250 N0.getOpcode() == ISD::AND) 2251 if (ConstantSDNode *AndRHS = 2252 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2253 EVT ShiftTy = DCI.isBeforeLegalize() ? 2254 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2255 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2256 // Perform the xform if the AND RHS is a single bit. 2257 if (AndRHS->getAPIntValue().isPowerOf2()) { 2258 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2259 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2260 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2261 } 2262 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2263 // (X & 8) == 8 --> (X & 8) >> 3 2264 // Perform the xform if C1 is a single bit. 2265 if (C1.isPowerOf2()) { 2266 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2267 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2268 DAG.getConstant(C1.logBase2(), ShiftTy))); 2269 } 2270 } 2271 } 2272 } 2273 2274 if (isa<ConstantFPSDNode>(N0.getNode())) { 2275 // Constant fold or commute setcc. 2276 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2277 if (O.getNode()) return O; 2278 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2279 // If the RHS of an FP comparison is a constant, simplify it away in 2280 // some cases. 2281 if (CFP->getValueAPF().isNaN()) { 2282 // If an operand is known to be a nan, we can fold it. 2283 switch (ISD::getUnorderedFlavor(Cond)) { 2284 default: llvm_unreachable("Unknown flavor!"); 2285 case 0: // Known false. 2286 return DAG.getConstant(0, VT); 2287 case 1: // Known true. 2288 return DAG.getConstant(1, VT); 2289 case 2: // Undefined. 2290 return DAG.getUNDEF(VT); 2291 } 2292 } 2293 2294 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2295 // constant if knowing that the operand is non-nan is enough. We prefer to 2296 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2297 // materialize 0.0. 2298 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2299 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2300 2301 // If the condition is not legal, see if we can find an equivalent one 2302 // which is legal. 2303 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2304 // If the comparison was an awkward floating-point == or != and one of 2305 // the comparison operands is infinity or negative infinity, convert the 2306 // condition to a less-awkward <= or >=. 2307 if (CFP->getValueAPF().isInfinity()) { 2308 if (CFP->getValueAPF().isNegative()) { 2309 if (Cond == ISD::SETOEQ && 2310 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2311 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2312 if (Cond == ISD::SETUEQ && 2313 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2314 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2315 if (Cond == ISD::SETUNE && 2316 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2317 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2318 if (Cond == ISD::SETONE && 2319 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2320 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2321 } else { 2322 if (Cond == ISD::SETOEQ && 2323 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2324 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2325 if (Cond == ISD::SETUEQ && 2326 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2327 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2328 if (Cond == ISD::SETUNE && 2329 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2330 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2331 if (Cond == ISD::SETONE && 2332 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2333 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2334 } 2335 } 2336 } 2337 } 2338 2339 if (N0 == N1) { 2340 // We can always fold X == X for integer setcc's. 2341 if (N0.getValueType().isInteger()) 2342 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2343 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2344 if (UOF == 2) // FP operators that are undefined on NaNs. 2345 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2346 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2347 return DAG.getConstant(UOF, VT); 2348 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2349 // if it is not already. 2350 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2351 if (NewCond != Cond) 2352 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2353 } 2354 2355 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2356 N0.getValueType().isInteger()) { 2357 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2358 N0.getOpcode() == ISD::XOR) { 2359 // Simplify (X+Y) == (X+Z) --> Y == Z 2360 if (N0.getOpcode() == N1.getOpcode()) { 2361 if (N0.getOperand(0) == N1.getOperand(0)) 2362 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2363 if (N0.getOperand(1) == N1.getOperand(1)) 2364 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2365 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2366 // If X op Y == Y op X, try other combinations. 2367 if (N0.getOperand(0) == N1.getOperand(1)) 2368 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2369 Cond); 2370 if (N0.getOperand(1) == N1.getOperand(0)) 2371 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2372 Cond); 2373 } 2374 } 2375 2376 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2377 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2378 // Turn (X+C1) == C2 --> X == C2-C1 2379 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2380 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2381 DAG.getConstant(RHSC->getAPIntValue()- 2382 LHSR->getAPIntValue(), 2383 N0.getValueType()), Cond); 2384 } 2385 2386 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2387 if (N0.getOpcode() == ISD::XOR) 2388 // If we know that all of the inverted bits are zero, don't bother 2389 // performing the inversion. 2390 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2391 return 2392 DAG.getSetCC(dl, VT, N0.getOperand(0), 2393 DAG.getConstant(LHSR->getAPIntValue() ^ 2394 RHSC->getAPIntValue(), 2395 N0.getValueType()), 2396 Cond); 2397 } 2398 2399 // Turn (C1-X) == C2 --> X == C1-C2 2400 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2401 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2402 return 2403 DAG.getSetCC(dl, VT, N0.getOperand(1), 2404 DAG.getConstant(SUBC->getAPIntValue() - 2405 RHSC->getAPIntValue(), 2406 N0.getValueType()), 2407 Cond); 2408 } 2409 } 2410 } 2411 2412 // Simplify (X+Z) == X --> Z == 0 2413 if (N0.getOperand(0) == N1) 2414 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2415 DAG.getConstant(0, N0.getValueType()), Cond); 2416 if (N0.getOperand(1) == N1) { 2417 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2418 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2419 DAG.getConstant(0, N0.getValueType()), Cond); 2420 else if (N0.getNode()->hasOneUse()) { 2421 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2422 // (Z-X) == X --> Z == X<<1 2423 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2424 N1, 2425 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2426 if (!DCI.isCalledByLegalizer()) 2427 DCI.AddToWorklist(SH.getNode()); 2428 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2429 } 2430 } 2431 } 2432 2433 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2434 N1.getOpcode() == ISD::XOR) { 2435 // Simplify X == (X+Z) --> Z == 0 2436 if (N1.getOperand(0) == N0) { 2437 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2438 DAG.getConstant(0, N1.getValueType()), Cond); 2439 } else if (N1.getOperand(1) == N0) { 2440 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2441 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2442 DAG.getConstant(0, N1.getValueType()), Cond); 2443 } else if (N1.getNode()->hasOneUse()) { 2444 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2445 // X == (Z-X) --> X<<1 == Z 2446 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2447 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2448 if (!DCI.isCalledByLegalizer()) 2449 DCI.AddToWorklist(SH.getNode()); 2450 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2451 } 2452 } 2453 } 2454 2455 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2456 // Note that where y is variable and is known to have at most 2457 // one bit set (for example, if it is z&1) we cannot do this; 2458 // the expressions are not equivalent when y==0. 2459 if (N0.getOpcode() == ISD::AND) 2460 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2461 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2462 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2463 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2464 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2465 } 2466 } 2467 if (N1.getOpcode() == ISD::AND) 2468 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2469 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2470 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2471 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2472 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2473 } 2474 } 2475 } 2476 2477 // Fold away ALL boolean setcc's. 2478 SDValue Temp; 2479 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2480 switch (Cond) { 2481 default: llvm_unreachable("Unknown integer setcc!"); 2482 case ISD::SETEQ: // X == Y -> ~(X^Y) 2483 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2484 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2485 if (!DCI.isCalledByLegalizer()) 2486 DCI.AddToWorklist(Temp.getNode()); 2487 break; 2488 case ISD::SETNE: // X != Y --> (X^Y) 2489 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2490 break; 2491 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2492 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2493 Temp = DAG.getNOT(dl, N0, MVT::i1); 2494 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2495 if (!DCI.isCalledByLegalizer()) 2496 DCI.AddToWorklist(Temp.getNode()); 2497 break; 2498 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2499 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2500 Temp = DAG.getNOT(dl, N1, MVT::i1); 2501 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2502 if (!DCI.isCalledByLegalizer()) 2503 DCI.AddToWorklist(Temp.getNode()); 2504 break; 2505 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2506 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2507 Temp = DAG.getNOT(dl, N0, MVT::i1); 2508 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2509 if (!DCI.isCalledByLegalizer()) 2510 DCI.AddToWorklist(Temp.getNode()); 2511 break; 2512 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2513 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2514 Temp = DAG.getNOT(dl, N1, MVT::i1); 2515 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2516 break; 2517 } 2518 if (VT != MVT::i1) { 2519 if (!DCI.isCalledByLegalizer()) 2520 DCI.AddToWorklist(N0.getNode()); 2521 // FIXME: If running after legalize, we probably can't do this. 2522 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2523 } 2524 return N0; 2525 } 2526 2527 // Could not fold it. 2528 return SDValue(); 2529} 2530 2531/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2532/// node is a GlobalAddress + offset. 2533bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2534 int64_t &Offset) const { 2535 if (isa<GlobalAddressSDNode>(N)) { 2536 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2537 GA = GASD->getGlobal(); 2538 Offset += GASD->getOffset(); 2539 return true; 2540 } 2541 2542 if (N->getOpcode() == ISD::ADD) { 2543 SDValue N1 = N->getOperand(0); 2544 SDValue N2 = N->getOperand(1); 2545 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2546 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2547 if (V) { 2548 Offset += V->getSExtValue(); 2549 return true; 2550 } 2551 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2552 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2553 if (V) { 2554 Offset += V->getSExtValue(); 2555 return true; 2556 } 2557 } 2558 } 2559 2560 return false; 2561} 2562 2563 2564SDValue TargetLowering:: 2565PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2566 // Default implementation: no optimization. 2567 return SDValue(); 2568} 2569 2570//===----------------------------------------------------------------------===// 2571// Inline Assembler Implementation Methods 2572//===----------------------------------------------------------------------===// 2573 2574 2575TargetLowering::ConstraintType 2576TargetLowering::getConstraintType(const std::string &Constraint) const { 2577 // FIXME: lots more standard ones to handle. 2578 if (Constraint.size() == 1) { 2579 switch (Constraint[0]) { 2580 default: break; 2581 case 'r': return C_RegisterClass; 2582 case 'm': // memory 2583 case 'o': // offsetable 2584 case 'V': // not offsetable 2585 return C_Memory; 2586 case 'i': // Simple Integer or Relocatable Constant 2587 case 'n': // Simple Integer 2588 case 'E': // Floating Point Constant 2589 case 'F': // Floating Point Constant 2590 case 's': // Relocatable Constant 2591 case 'p': // Address. 2592 case 'X': // Allow ANY value. 2593 case 'I': // Target registers. 2594 case 'J': 2595 case 'K': 2596 case 'L': 2597 case 'M': 2598 case 'N': 2599 case 'O': 2600 case 'P': 2601 case '<': 2602 case '>': 2603 return C_Other; 2604 } 2605 } 2606 2607 if (Constraint.size() > 1 && Constraint[0] == '{' && 2608 Constraint[Constraint.size()-1] == '}') 2609 return C_Register; 2610 return C_Unknown; 2611} 2612 2613/// LowerXConstraint - try to replace an X constraint, which matches anything, 2614/// with another that has more specific requirements based on the type of the 2615/// corresponding operand. 2616const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2617 if (ConstraintVT.isInteger()) 2618 return "r"; 2619 if (ConstraintVT.isFloatingPoint()) 2620 return "f"; // works for many targets 2621 return 0; 2622} 2623 2624/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2625/// vector. If it is invalid, don't add anything to Ops. 2626void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2627 char ConstraintLetter, 2628 std::vector<SDValue> &Ops, 2629 SelectionDAG &DAG) const { 2630 switch (ConstraintLetter) { 2631 default: break; 2632 case 'X': // Allows any operand; labels (basic block) use this. 2633 if (Op.getOpcode() == ISD::BasicBlock) { 2634 Ops.push_back(Op); 2635 return; 2636 } 2637 // fall through 2638 case 'i': // Simple Integer or Relocatable Constant 2639 case 'n': // Simple Integer 2640 case 's': { // Relocatable Constant 2641 // These operands are interested in values of the form (GV+C), where C may 2642 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2643 // is possible and fine if either GV or C are missing. 2644 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2645 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2646 2647 // If we have "(add GV, C)", pull out GV/C 2648 if (Op.getOpcode() == ISD::ADD) { 2649 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2650 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2651 if (C == 0 || GA == 0) { 2652 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2653 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2654 } 2655 if (C == 0 || GA == 0) 2656 C = 0, GA = 0; 2657 } 2658 2659 // If we find a valid operand, map to the TargetXXX version so that the 2660 // value itself doesn't get selected. 2661 if (GA) { // Either &GV or &GV+C 2662 if (ConstraintLetter != 'n') { 2663 int64_t Offs = GA->getOffset(); 2664 if (C) Offs += C->getZExtValue(); 2665 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2666 C ? C->getDebugLoc() : DebugLoc(), 2667 Op.getValueType(), Offs)); 2668 return; 2669 } 2670 } 2671 if (C) { // just C, no GV. 2672 // Simple constants are not allowed for 's'. 2673 if (ConstraintLetter != 's') { 2674 // gcc prints these as sign extended. Sign extend value to 64 bits 2675 // now; without this it would get ZExt'd later in 2676 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2677 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2678 MVT::i64)); 2679 return; 2680 } 2681 } 2682 break; 2683 } 2684 } 2685} 2686 2687std::vector<unsigned> TargetLowering:: 2688getRegClassForInlineAsmConstraint(const std::string &Constraint, 2689 EVT VT) const { 2690 return std::vector<unsigned>(); 2691} 2692 2693 2694std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2695getRegForInlineAsmConstraint(const std::string &Constraint, 2696 EVT VT) const { 2697 if (Constraint[0] != '{') 2698 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2699 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2700 2701 // Remove the braces from around the name. 2702 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2703 2704 // Figure out which register class contains this reg. 2705 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2706 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2707 E = RI->regclass_end(); RCI != E; ++RCI) { 2708 const TargetRegisterClass *RC = *RCI; 2709 2710 // If none of the value types for this register class are valid, we 2711 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2712 bool isLegal = false; 2713 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2714 I != E; ++I) { 2715 if (isTypeLegal(*I)) { 2716 isLegal = true; 2717 break; 2718 } 2719 } 2720 2721 if (!isLegal) continue; 2722 2723 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2724 I != E; ++I) { 2725 if (RegName.equals_lower(RI->getName(*I))) 2726 return std::make_pair(*I, RC); 2727 } 2728 } 2729 2730 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2731} 2732 2733//===----------------------------------------------------------------------===// 2734// Constraint Selection. 2735 2736/// isMatchingInputConstraint - Return true of this is an input operand that is 2737/// a matching constraint like "4". 2738bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2739 assert(!ConstraintCode.empty() && "No known constraint!"); 2740 return isdigit(ConstraintCode[0]); 2741} 2742 2743/// getMatchedOperand - If this is an input matching constraint, this method 2744/// returns the output operand it matches. 2745unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2746 assert(!ConstraintCode.empty() && "No known constraint!"); 2747 return atoi(ConstraintCode.c_str()); 2748} 2749 2750 2751/// ParseConstraints - Split up the constraint string from the inline 2752/// assembly value into the specific constraints and their prefixes, 2753/// and also tie in the associated operand values. 2754/// If this returns an empty vector, and if the constraint string itself 2755/// isn't empty, there was an error parsing. 2756TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2757 ImmutableCallSite CS) const { 2758 /// ConstraintOperands - Information about all of the constraints. 2759 AsmOperandInfoVector ConstraintOperands; 2760 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2761 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2762 2763 // Do a prepass over the constraints, canonicalizing them, and building up the 2764 // ConstraintOperands list. 2765 InlineAsm::ConstraintInfoVector 2766 ConstraintInfos = IA->ParseConstraints(); 2767 2768 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2769 unsigned ResNo = 0; // ResNo - The result number of the next output. 2770 2771 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2772 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2773 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2774 2775 // Update multiple alternative constraint count. 2776 if (OpInfo.multipleAlternatives.size() > maCount) 2777 maCount = OpInfo.multipleAlternatives.size(); 2778 2779 OpInfo.ConstraintVT = MVT::Other; 2780 2781 // Compute the value type for each operand. 2782 switch (OpInfo.Type) { 2783 case InlineAsm::isOutput: 2784 // Indirect outputs just consume an argument. 2785 if (OpInfo.isIndirect) { 2786 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2787 break; 2788 } 2789 2790 // The return value of the call is this value. As such, there is no 2791 // corresponding argument. 2792 assert(!CS.getType()->isVoidTy() && 2793 "Bad inline asm!"); 2794 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2795 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2796 } else { 2797 assert(ResNo == 0 && "Asm only has one result!"); 2798 OpInfo.ConstraintVT = getValueType(CS.getType()); 2799 } 2800 ++ResNo; 2801 break; 2802 case InlineAsm::isInput: 2803 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2804 break; 2805 case InlineAsm::isClobber: 2806 // Nothing to do. 2807 break; 2808 } 2809 2810 if (OpInfo.CallOperandVal) { 2811 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2812 if (OpInfo.isIndirect) { 2813 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2814 if (!PtrTy) 2815 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2816 OpTy = PtrTy->getElementType(); 2817 } 2818 2819 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2820 if (const StructType *STy = dyn_cast<StructType>(OpTy)) 2821 if (STy->getNumElements() == 1) 2822 OpTy = STy->getElementType(0); 2823 2824 // If OpTy is not a single value, it may be a struct/union that we 2825 // can tile with integers. 2826 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2827 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2828 switch (BitSize) { 2829 default: break; 2830 case 1: 2831 case 8: 2832 case 16: 2833 case 32: 2834 case 64: 2835 case 128: 2836 OpInfo.ConstraintVT = 2837 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2838 break; 2839 } 2840 } else if (dyn_cast<PointerType>(OpTy)) { 2841 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2842 } else { 2843 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2844 } 2845 } 2846 } 2847 2848 // If we have multiple alternative constraints, select the best alternative. 2849 if (ConstraintInfos.size()) { 2850 if (maCount) { 2851 unsigned bestMAIndex = 0; 2852 int bestWeight = -1; 2853 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2854 int weight = -1; 2855 unsigned maIndex; 2856 // Compute the sums of the weights for each alternative, keeping track 2857 // of the best (highest weight) one so far. 2858 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2859 int weightSum = 0; 2860 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2861 cIndex != eIndex; ++cIndex) { 2862 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2863 if (OpInfo.Type == InlineAsm::isClobber) 2864 continue; 2865 2866 // If this is an output operand with a matching input operand, 2867 // look up the matching input. If their types mismatch, e.g. one 2868 // is an integer, the other is floating point, or their sizes are 2869 // different, flag it as an maCantMatch. 2870 if (OpInfo.hasMatchingInput()) { 2871 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2872 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2873 if ((OpInfo.ConstraintVT.isInteger() != 2874 Input.ConstraintVT.isInteger()) || 2875 (OpInfo.ConstraintVT.getSizeInBits() != 2876 Input.ConstraintVT.getSizeInBits())) { 2877 weightSum = -1; // Can't match. 2878 break; 2879 } 2880 } 2881 } 2882 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2883 if (weight == -1) { 2884 weightSum = -1; 2885 break; 2886 } 2887 weightSum += weight; 2888 } 2889 // Update best. 2890 if (weightSum > bestWeight) { 2891 bestWeight = weightSum; 2892 bestMAIndex = maIndex; 2893 } 2894 } 2895 2896 // Now select chosen alternative in each constraint. 2897 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2898 cIndex != eIndex; ++cIndex) { 2899 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2900 if (cInfo.Type == InlineAsm::isClobber) 2901 continue; 2902 cInfo.selectAlternative(bestMAIndex); 2903 } 2904 } 2905 } 2906 2907 // Check and hook up tied operands, choose constraint code to use. 2908 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2909 cIndex != eIndex; ++cIndex) { 2910 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2911 2912 // If this is an output operand with a matching input operand, look up the 2913 // matching input. If their types mismatch, e.g. one is an integer, the 2914 // other is floating point, or their sizes are different, flag it as an 2915 // error. 2916 if (OpInfo.hasMatchingInput()) { 2917 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2918 2919 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2920 if ((OpInfo.ConstraintVT.isInteger() != 2921 Input.ConstraintVT.isInteger()) || 2922 (OpInfo.ConstraintVT.getSizeInBits() != 2923 Input.ConstraintVT.getSizeInBits())) { 2924 report_fatal_error("Unsupported asm: input constraint" 2925 " with a matching output constraint of" 2926 " incompatible type!"); 2927 } 2928 } 2929 2930 } 2931 } 2932 2933 return ConstraintOperands; 2934} 2935 2936 2937/// getConstraintGenerality - Return an integer indicating how general CT 2938/// is. 2939static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2940 switch (CT) { 2941 default: llvm_unreachable("Unknown constraint type!"); 2942 case TargetLowering::C_Other: 2943 case TargetLowering::C_Unknown: 2944 return 0; 2945 case TargetLowering::C_Register: 2946 return 1; 2947 case TargetLowering::C_RegisterClass: 2948 return 2; 2949 case TargetLowering::C_Memory: 2950 return 3; 2951 } 2952} 2953 2954/// Examine constraint type and operand type and determine a weight value. 2955/// This object must already have been set up with the operand type 2956/// and the current alternative constraint selected. 2957TargetLowering::ConstraintWeight 2958 TargetLowering::getMultipleConstraintMatchWeight( 2959 AsmOperandInfo &info, int maIndex) const { 2960 InlineAsm::ConstraintCodeVector *rCodes; 2961 if (maIndex >= (int)info.multipleAlternatives.size()) 2962 rCodes = &info.Codes; 2963 else 2964 rCodes = &info.multipleAlternatives[maIndex].Codes; 2965 ConstraintWeight BestWeight = CW_Invalid; 2966 2967 // Loop over the options, keeping track of the most general one. 2968 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2969 ConstraintWeight weight = 2970 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2971 if (weight > BestWeight) 2972 BestWeight = weight; 2973 } 2974 2975 return BestWeight; 2976} 2977 2978/// Examine constraint type and operand type and determine a weight value. 2979/// This object must already have been set up with the operand type 2980/// and the current alternative constraint selected. 2981TargetLowering::ConstraintWeight 2982 TargetLowering::getSingleConstraintMatchWeight( 2983 AsmOperandInfo &info, const char *constraint) const { 2984 ConstraintWeight weight = CW_Invalid; 2985 Value *CallOperandVal = info.CallOperandVal; 2986 // If we don't have a value, we can't do a match, 2987 // but allow it at the lowest weight. 2988 if (CallOperandVal == NULL) 2989 return CW_Default; 2990 // Look at the constraint type. 2991 switch (*constraint) { 2992 case 'i': // immediate integer. 2993 case 'n': // immediate integer with a known value. 2994 if (isa<ConstantInt>(CallOperandVal)) 2995 weight = CW_Constant; 2996 break; 2997 case 's': // non-explicit intregal immediate. 2998 if (isa<GlobalValue>(CallOperandVal)) 2999 weight = CW_Constant; 3000 break; 3001 case 'E': // immediate float if host format. 3002 case 'F': // immediate float. 3003 if (isa<ConstantFP>(CallOperandVal)) 3004 weight = CW_Constant; 3005 break; 3006 case '<': // memory operand with autodecrement. 3007 case '>': // memory operand with autoincrement. 3008 case 'm': // memory operand. 3009 case 'o': // offsettable memory operand 3010 case 'V': // non-offsettable memory operand 3011 weight = CW_Memory; 3012 break; 3013 case 'r': // general register. 3014 case 'g': // general register, memory operand or immediate integer. 3015 // note: Clang converts "g" to "imr". 3016 if (CallOperandVal->getType()->isIntegerTy()) 3017 weight = CW_Register; 3018 break; 3019 case 'X': // any operand. 3020 default: 3021 weight = CW_Default; 3022 break; 3023 } 3024 return weight; 3025} 3026 3027/// ChooseConstraint - If there are multiple different constraints that we 3028/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3029/// This is somewhat tricky: constraints fall into four classes: 3030/// Other -> immediates and magic values 3031/// Register -> one specific register 3032/// RegisterClass -> a group of regs 3033/// Memory -> memory 3034/// Ideally, we would pick the most specific constraint possible: if we have 3035/// something that fits into a register, we would pick it. The problem here 3036/// is that if we have something that could either be in a register or in 3037/// memory that use of the register could cause selection of *other* 3038/// operands to fail: they might only succeed if we pick memory. Because of 3039/// this the heuristic we use is: 3040/// 3041/// 1) If there is an 'other' constraint, and if the operand is valid for 3042/// that constraint, use it. This makes us take advantage of 'i' 3043/// constraints when available. 3044/// 2) Otherwise, pick the most general constraint present. This prefers 3045/// 'm' over 'r', for example. 3046/// 3047static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3048 const TargetLowering &TLI, 3049 SDValue Op, SelectionDAG *DAG) { 3050 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3051 unsigned BestIdx = 0; 3052 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3053 int BestGenerality = -1; 3054 3055 // Loop over the options, keeping track of the most general one. 3056 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3057 TargetLowering::ConstraintType CType = 3058 TLI.getConstraintType(OpInfo.Codes[i]); 3059 3060 // If this is an 'other' constraint, see if the operand is valid for it. 3061 // For example, on X86 we might have an 'rI' constraint. If the operand 3062 // is an integer in the range [0..31] we want to use I (saving a load 3063 // of a register), otherwise we must use 'r'. 3064 if (CType == TargetLowering::C_Other && Op.getNode()) { 3065 assert(OpInfo.Codes[i].size() == 1 && 3066 "Unhandled multi-letter 'other' constraint"); 3067 std::vector<SDValue> ResultOps; 3068 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 3069 ResultOps, *DAG); 3070 if (!ResultOps.empty()) { 3071 BestType = CType; 3072 BestIdx = i; 3073 break; 3074 } 3075 } 3076 3077 // Things with matching constraints can only be registers, per gcc 3078 // documentation. This mainly affects "g" constraints. 3079 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3080 continue; 3081 3082 // This constraint letter is more general than the previous one, use it. 3083 int Generality = getConstraintGenerality(CType); 3084 if (Generality > BestGenerality) { 3085 BestType = CType; 3086 BestIdx = i; 3087 BestGenerality = Generality; 3088 } 3089 } 3090 3091 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3092 OpInfo.ConstraintType = BestType; 3093} 3094 3095/// ComputeConstraintToUse - Determines the constraint code and constraint 3096/// type to use for the specific AsmOperandInfo, setting 3097/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3098void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3099 SDValue Op, 3100 SelectionDAG *DAG) const { 3101 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3102 3103 // Single-letter constraints ('r') are very common. 3104 if (OpInfo.Codes.size() == 1) { 3105 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3106 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3107 } else { 3108 ChooseConstraint(OpInfo, *this, Op, DAG); 3109 } 3110 3111 // 'X' matches anything. 3112 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3113 // Labels and constants are handled elsewhere ('X' is the only thing 3114 // that matches labels). For Functions, the type here is the type of 3115 // the result, which is not what we want to look at; leave them alone. 3116 Value *v = OpInfo.CallOperandVal; 3117 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3118 OpInfo.CallOperandVal = v; 3119 return; 3120 } 3121 3122 // Otherwise, try to resolve it to something we know about by looking at 3123 // the actual operand type. 3124 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3125 OpInfo.ConstraintCode = Repl; 3126 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3127 } 3128 } 3129} 3130 3131//===----------------------------------------------------------------------===// 3132// Loop Strength Reduction hooks 3133//===----------------------------------------------------------------------===// 3134 3135/// isLegalAddressingMode - Return true if the addressing mode represented 3136/// by AM is legal for this target, for a load/store of the specified type. 3137bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3138 const Type *Ty) const { 3139 // The default implementation of this implements a conservative RISCy, r+r and 3140 // r+i addr mode. 3141 3142 // Allows a sign-extended 16-bit immediate field. 3143 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3144 return false; 3145 3146 // No global is ever allowed as a base. 3147 if (AM.BaseGV) 3148 return false; 3149 3150 // Only support r+r, 3151 switch (AM.Scale) { 3152 case 0: // "r+i" or just "i", depending on HasBaseReg. 3153 break; 3154 case 1: 3155 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3156 return false; 3157 // Otherwise we have r+r or r+i. 3158 break; 3159 case 2: 3160 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3161 return false; 3162 // Allow 2*r as r+r. 3163 break; 3164 } 3165 3166 return true; 3167} 3168 3169/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3170/// return a DAG expression to select that will generate the same value by 3171/// multiplying by a magic number. See: 3172/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3173SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3174 std::vector<SDNode*>* Created) const { 3175 EVT VT = N->getValueType(0); 3176 DebugLoc dl= N->getDebugLoc(); 3177 3178 // Check to see if we can do this. 3179 // FIXME: We should be more aggressive here. 3180 if (!isTypeLegal(VT)) 3181 return SDValue(); 3182 3183 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3184 APInt::ms magics = d.magic(); 3185 3186 // Multiply the numerator (operand 0) by the magic value 3187 // FIXME: We should support doing a MUL in a wider type 3188 SDValue Q; 3189 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3190 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3191 DAG.getConstant(magics.m, VT)); 3192 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3193 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3194 N->getOperand(0), 3195 DAG.getConstant(magics.m, VT)).getNode(), 1); 3196 else 3197 return SDValue(); // No mulhs or equvialent 3198 // If d > 0 and m < 0, add the numerator 3199 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3200 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3201 if (Created) 3202 Created->push_back(Q.getNode()); 3203 } 3204 // If d < 0 and m > 0, subtract the numerator. 3205 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3206 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3207 if (Created) 3208 Created->push_back(Q.getNode()); 3209 } 3210 // Shift right algebraic if shift value is nonzero 3211 if (magics.s > 0) { 3212 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3213 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3214 if (Created) 3215 Created->push_back(Q.getNode()); 3216 } 3217 // Extract the sign bit and add it to the quotient 3218 SDValue T = 3219 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3220 getShiftAmountTy(Q.getValueType()))); 3221 if (Created) 3222 Created->push_back(T.getNode()); 3223 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3224} 3225 3226/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3227/// return a DAG expression to select that will generate the same value by 3228/// multiplying by a magic number. See: 3229/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3230SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3231 std::vector<SDNode*>* Created) const { 3232 EVT VT = N->getValueType(0); 3233 DebugLoc dl = N->getDebugLoc(); 3234 3235 // Check to see if we can do this. 3236 // FIXME: We should be more aggressive here. 3237 if (!isTypeLegal(VT)) 3238 return SDValue(); 3239 3240 // FIXME: We should use a narrower constant when the upper 3241 // bits are known to be zero. 3242 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3243 APInt::mu magics = N1C.magicu(); 3244 3245 SDValue Q = N->getOperand(0); 3246 3247 // If the divisor is even, we can avoid using the expensive fixup by shifting 3248 // the divided value upfront. 3249 if (magics.a != 0 && !N1C[0]) { 3250 unsigned Shift = N1C.countTrailingZeros(); 3251 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3252 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3253 if (Created) 3254 Created->push_back(Q.getNode()); 3255 3256 // Get magic number for the shifted divisor. 3257 magics = N1C.lshr(Shift).magicu(Shift); 3258 assert(magics.a == 0 && "Should use cheap fixup now"); 3259 } 3260 3261 // Multiply the numerator (operand 0) by the magic value 3262 // FIXME: We should support doing a MUL in a wider type 3263 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3264 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3265 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3266 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3267 DAG.getConstant(magics.m, VT)).getNode(), 1); 3268 else 3269 return SDValue(); // No mulhu or equvialent 3270 if (Created) 3271 Created->push_back(Q.getNode()); 3272 3273 if (magics.a == 0) { 3274 assert(magics.s < N1C.getBitWidth() && 3275 "We shouldn't generate an undefined shift!"); 3276 return DAG.getNode(ISD::SRL, dl, VT, Q, 3277 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3278 } else { 3279 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3280 if (Created) 3281 Created->push_back(NPQ.getNode()); 3282 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3283 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3284 if (Created) 3285 Created->push_back(NPQ.getNode()); 3286 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3287 if (Created) 3288 Created->push_back(NPQ.getNode()); 3289 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3290 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3291 } 3292} 3293