TargetLowering.cpp revision c25e7581b9b8088910da31702d4ca21c4734c6d7
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28using namespace llvm; 29 30namespace llvm { 31TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 32 bool isLocal = GV->hasLocalLinkage(); 33 bool isDeclaration = GV->isDeclaration(); 34 // FIXME: what should we do for protected and internal visibility? 35 // For variables, is internal different from hidden? 36 bool isHidden = GV->hasHiddenVisibility(); 37 38 if (reloc == Reloc::PIC_) { 39 if (isLocal || isHidden) 40 return TLSModel::LocalDynamic; 41 else 42 return TLSModel::GeneralDynamic; 43 } else { 44 if (!isDeclaration || isHidden) 45 return TLSModel::LocalExec; 46 else 47 return TLSModel::InitialExec; 48 } 49} 50} 51 52/// InitLibcallNames - Set default libcall names. 53/// 54static void InitLibcallNames(const char **Names) { 55 Names[RTLIB::SHL_I16] = "__ashlhi3"; 56 Names[RTLIB::SHL_I32] = "__ashlsi3"; 57 Names[RTLIB::SHL_I64] = "__ashldi3"; 58 Names[RTLIB::SHL_I128] = "__ashlti3"; 59 Names[RTLIB::SRL_I16] = "__lshrhi3"; 60 Names[RTLIB::SRL_I32] = "__lshrsi3"; 61 Names[RTLIB::SRL_I64] = "__lshrdi3"; 62 Names[RTLIB::SRL_I128] = "__lshrti3"; 63 Names[RTLIB::SRA_I16] = "__ashrhi3"; 64 Names[RTLIB::SRA_I32] = "__ashrsi3"; 65 Names[RTLIB::SRA_I64] = "__ashrdi3"; 66 Names[RTLIB::SRA_I128] = "__ashrti3"; 67 Names[RTLIB::MUL_I16] = "__mulhi3"; 68 Names[RTLIB::MUL_I32] = "__mulsi3"; 69 Names[RTLIB::MUL_I64] = "__muldi3"; 70 Names[RTLIB::MUL_I128] = "__multi3"; 71 Names[RTLIB::SDIV_I16] = "__divhi3"; 72 Names[RTLIB::SDIV_I32] = "__divsi3"; 73 Names[RTLIB::SDIV_I64] = "__divdi3"; 74 Names[RTLIB::SDIV_I128] = "__divti3"; 75 Names[RTLIB::UDIV_I16] = "__udivhi3"; 76 Names[RTLIB::UDIV_I32] = "__udivsi3"; 77 Names[RTLIB::UDIV_I64] = "__udivdi3"; 78 Names[RTLIB::UDIV_I128] = "__udivti3"; 79 Names[RTLIB::SREM_I16] = "__modhi3"; 80 Names[RTLIB::SREM_I32] = "__modsi3"; 81 Names[RTLIB::SREM_I64] = "__moddi3"; 82 Names[RTLIB::SREM_I128] = "__modti3"; 83 Names[RTLIB::UREM_I16] = "__umodhi3"; 84 Names[RTLIB::UREM_I32] = "__umodsi3"; 85 Names[RTLIB::UREM_I64] = "__umoddi3"; 86 Names[RTLIB::UREM_I128] = "__umodti3"; 87 Names[RTLIB::NEG_I32] = "__negsi2"; 88 Names[RTLIB::NEG_I64] = "__negdi2"; 89 Names[RTLIB::ADD_F32] = "__addsf3"; 90 Names[RTLIB::ADD_F64] = "__adddf3"; 91 Names[RTLIB::ADD_F80] = "__addxf3"; 92 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 93 Names[RTLIB::SUB_F32] = "__subsf3"; 94 Names[RTLIB::SUB_F64] = "__subdf3"; 95 Names[RTLIB::SUB_F80] = "__subxf3"; 96 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 97 Names[RTLIB::MUL_F32] = "__mulsf3"; 98 Names[RTLIB::MUL_F64] = "__muldf3"; 99 Names[RTLIB::MUL_F80] = "__mulxf3"; 100 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 101 Names[RTLIB::DIV_F32] = "__divsf3"; 102 Names[RTLIB::DIV_F64] = "__divdf3"; 103 Names[RTLIB::DIV_F80] = "__divxf3"; 104 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 105 Names[RTLIB::REM_F32] = "fmodf"; 106 Names[RTLIB::REM_F64] = "fmod"; 107 Names[RTLIB::REM_F80] = "fmodl"; 108 Names[RTLIB::REM_PPCF128] = "fmodl"; 109 Names[RTLIB::POWI_F32] = "__powisf2"; 110 Names[RTLIB::POWI_F64] = "__powidf2"; 111 Names[RTLIB::POWI_F80] = "__powixf2"; 112 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 113 Names[RTLIB::SQRT_F32] = "sqrtf"; 114 Names[RTLIB::SQRT_F64] = "sqrt"; 115 Names[RTLIB::SQRT_F80] = "sqrtl"; 116 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 117 Names[RTLIB::LOG_F32] = "logf"; 118 Names[RTLIB::LOG_F64] = "log"; 119 Names[RTLIB::LOG_F80] = "logl"; 120 Names[RTLIB::LOG_PPCF128] = "logl"; 121 Names[RTLIB::LOG2_F32] = "log2f"; 122 Names[RTLIB::LOG2_F64] = "log2"; 123 Names[RTLIB::LOG2_F80] = "log2l"; 124 Names[RTLIB::LOG2_PPCF128] = "log2l"; 125 Names[RTLIB::LOG10_F32] = "log10f"; 126 Names[RTLIB::LOG10_F64] = "log10"; 127 Names[RTLIB::LOG10_F80] = "log10l"; 128 Names[RTLIB::LOG10_PPCF128] = "log10l"; 129 Names[RTLIB::EXP_F32] = "expf"; 130 Names[RTLIB::EXP_F64] = "exp"; 131 Names[RTLIB::EXP_F80] = "expl"; 132 Names[RTLIB::EXP_PPCF128] = "expl"; 133 Names[RTLIB::EXP2_F32] = "exp2f"; 134 Names[RTLIB::EXP2_F64] = "exp2"; 135 Names[RTLIB::EXP2_F80] = "exp2l"; 136 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 137 Names[RTLIB::SIN_F32] = "sinf"; 138 Names[RTLIB::SIN_F64] = "sin"; 139 Names[RTLIB::SIN_F80] = "sinl"; 140 Names[RTLIB::SIN_PPCF128] = "sinl"; 141 Names[RTLIB::COS_F32] = "cosf"; 142 Names[RTLIB::COS_F64] = "cos"; 143 Names[RTLIB::COS_F80] = "cosl"; 144 Names[RTLIB::COS_PPCF128] = "cosl"; 145 Names[RTLIB::POW_F32] = "powf"; 146 Names[RTLIB::POW_F64] = "pow"; 147 Names[RTLIB::POW_F80] = "powl"; 148 Names[RTLIB::POW_PPCF128] = "powl"; 149 Names[RTLIB::CEIL_F32] = "ceilf"; 150 Names[RTLIB::CEIL_F64] = "ceil"; 151 Names[RTLIB::CEIL_F80] = "ceill"; 152 Names[RTLIB::CEIL_PPCF128] = "ceill"; 153 Names[RTLIB::TRUNC_F32] = "truncf"; 154 Names[RTLIB::TRUNC_F64] = "trunc"; 155 Names[RTLIB::TRUNC_F80] = "truncl"; 156 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 157 Names[RTLIB::RINT_F32] = "rintf"; 158 Names[RTLIB::RINT_F64] = "rint"; 159 Names[RTLIB::RINT_F80] = "rintl"; 160 Names[RTLIB::RINT_PPCF128] = "rintl"; 161 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 162 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 163 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 164 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 165 Names[RTLIB::FLOOR_F32] = "floorf"; 166 Names[RTLIB::FLOOR_F64] = "floor"; 167 Names[RTLIB::FLOOR_F80] = "floorl"; 168 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 169 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 170 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 171 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 172 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 173 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 174 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 175 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 176 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 177 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 178 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 179 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 180 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 181 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 182 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 183 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 184 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 185 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 186 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 187 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 188 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 189 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 190 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 191 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 192 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 193 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 194 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 195 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 196 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 197 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 198 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 199 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 200 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 201 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 202 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 203 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 204 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 205 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 206 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 207 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 208 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 209 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 210 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 211 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 212 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 213 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 214 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 215 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 216 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 217 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 218 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 219 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 220 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 221 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 222 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 223 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 224 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 225 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 226 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 227 Names[RTLIB::OEQ_F32] = "__eqsf2"; 228 Names[RTLIB::OEQ_F64] = "__eqdf2"; 229 Names[RTLIB::UNE_F32] = "__nesf2"; 230 Names[RTLIB::UNE_F64] = "__nedf2"; 231 Names[RTLIB::OGE_F32] = "__gesf2"; 232 Names[RTLIB::OGE_F64] = "__gedf2"; 233 Names[RTLIB::OLT_F32] = "__ltsf2"; 234 Names[RTLIB::OLT_F64] = "__ltdf2"; 235 Names[RTLIB::OLE_F32] = "__lesf2"; 236 Names[RTLIB::OLE_F64] = "__ledf2"; 237 Names[RTLIB::OGT_F32] = "__gtsf2"; 238 Names[RTLIB::OGT_F64] = "__gtdf2"; 239 Names[RTLIB::UO_F32] = "__unordsf2"; 240 Names[RTLIB::UO_F64] = "__unorddf2"; 241 Names[RTLIB::O_F32] = "__unordsf2"; 242 Names[RTLIB::O_F64] = "__unorddf2"; 243 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 244} 245 246/// getFPEXT - Return the FPEXT_*_* value for the given types, or 247/// UNKNOWN_LIBCALL if there is none. 248RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 249 if (OpVT == MVT::f32) { 250 if (RetVT == MVT::f64) 251 return FPEXT_F32_F64; 252 } 253 return UNKNOWN_LIBCALL; 254} 255 256/// getFPROUND - Return the FPROUND_*_* value for the given types, or 257/// UNKNOWN_LIBCALL if there is none. 258RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 259 if (RetVT == MVT::f32) { 260 if (OpVT == MVT::f64) 261 return FPROUND_F64_F32; 262 if (OpVT == MVT::f80) 263 return FPROUND_F80_F32; 264 if (OpVT == MVT::ppcf128) 265 return FPROUND_PPCF128_F32; 266 } else if (RetVT == MVT::f64) { 267 if (OpVT == MVT::f80) 268 return FPROUND_F80_F64; 269 if (OpVT == MVT::ppcf128) 270 return FPROUND_PPCF128_F64; 271 } 272 return UNKNOWN_LIBCALL; 273} 274 275/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 276/// UNKNOWN_LIBCALL if there is none. 277RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 278 if (OpVT == MVT::f32) { 279 if (RetVT == MVT::i8) 280 return FPTOSINT_F32_I8; 281 if (RetVT == MVT::i16) 282 return FPTOSINT_F32_I16; 283 if (RetVT == MVT::i32) 284 return FPTOSINT_F32_I32; 285 if (RetVT == MVT::i64) 286 return FPTOSINT_F32_I64; 287 if (RetVT == MVT::i128) 288 return FPTOSINT_F32_I128; 289 } else if (OpVT == MVT::f64) { 290 if (RetVT == MVT::i32) 291 return FPTOSINT_F64_I32; 292 if (RetVT == MVT::i64) 293 return FPTOSINT_F64_I64; 294 if (RetVT == MVT::i128) 295 return FPTOSINT_F64_I128; 296 } else if (OpVT == MVT::f80) { 297 if (RetVT == MVT::i32) 298 return FPTOSINT_F80_I32; 299 if (RetVT == MVT::i64) 300 return FPTOSINT_F80_I64; 301 if (RetVT == MVT::i128) 302 return FPTOSINT_F80_I128; 303 } else if (OpVT == MVT::ppcf128) { 304 if (RetVT == MVT::i32) 305 return FPTOSINT_PPCF128_I32; 306 if (RetVT == MVT::i64) 307 return FPTOSINT_PPCF128_I64; 308 if (RetVT == MVT::i128) 309 return FPTOSINT_PPCF128_I128; 310 } 311 return UNKNOWN_LIBCALL; 312} 313 314/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 315/// UNKNOWN_LIBCALL if there is none. 316RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 317 if (OpVT == MVT::f32) { 318 if (RetVT == MVT::i8) 319 return FPTOUINT_F32_I8; 320 if (RetVT == MVT::i16) 321 return FPTOUINT_F32_I16; 322 if (RetVT == MVT::i32) 323 return FPTOUINT_F32_I32; 324 if (RetVT == MVT::i64) 325 return FPTOUINT_F32_I64; 326 if (RetVT == MVT::i128) 327 return FPTOUINT_F32_I128; 328 } else if (OpVT == MVT::f64) { 329 if (RetVT == MVT::i32) 330 return FPTOUINT_F64_I32; 331 if (RetVT == MVT::i64) 332 return FPTOUINT_F64_I64; 333 if (RetVT == MVT::i128) 334 return FPTOUINT_F64_I128; 335 } else if (OpVT == MVT::f80) { 336 if (RetVT == MVT::i32) 337 return FPTOUINT_F80_I32; 338 if (RetVT == MVT::i64) 339 return FPTOUINT_F80_I64; 340 if (RetVT == MVT::i128) 341 return FPTOUINT_F80_I128; 342 } else if (OpVT == MVT::ppcf128) { 343 if (RetVT == MVT::i32) 344 return FPTOUINT_PPCF128_I32; 345 if (RetVT == MVT::i64) 346 return FPTOUINT_PPCF128_I64; 347 if (RetVT == MVT::i128) 348 return FPTOUINT_PPCF128_I128; 349 } 350 return UNKNOWN_LIBCALL; 351} 352 353/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 354/// UNKNOWN_LIBCALL if there is none. 355RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 356 if (OpVT == MVT::i32) { 357 if (RetVT == MVT::f32) 358 return SINTTOFP_I32_F32; 359 else if (RetVT == MVT::f64) 360 return SINTTOFP_I32_F64; 361 else if (RetVT == MVT::f80) 362 return SINTTOFP_I32_F80; 363 else if (RetVT == MVT::ppcf128) 364 return SINTTOFP_I32_PPCF128; 365 } else if (OpVT == MVT::i64) { 366 if (RetVT == MVT::f32) 367 return SINTTOFP_I64_F32; 368 else if (RetVT == MVT::f64) 369 return SINTTOFP_I64_F64; 370 else if (RetVT == MVT::f80) 371 return SINTTOFP_I64_F80; 372 else if (RetVT == MVT::ppcf128) 373 return SINTTOFP_I64_PPCF128; 374 } else if (OpVT == MVT::i128) { 375 if (RetVT == MVT::f32) 376 return SINTTOFP_I128_F32; 377 else if (RetVT == MVT::f64) 378 return SINTTOFP_I128_F64; 379 else if (RetVT == MVT::f80) 380 return SINTTOFP_I128_F80; 381 else if (RetVT == MVT::ppcf128) 382 return SINTTOFP_I128_PPCF128; 383 } 384 return UNKNOWN_LIBCALL; 385} 386 387/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 388/// UNKNOWN_LIBCALL if there is none. 389RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 390 if (OpVT == MVT::i32) { 391 if (RetVT == MVT::f32) 392 return UINTTOFP_I32_F32; 393 else if (RetVT == MVT::f64) 394 return UINTTOFP_I32_F64; 395 else if (RetVT == MVT::f80) 396 return UINTTOFP_I32_F80; 397 else if (RetVT == MVT::ppcf128) 398 return UINTTOFP_I32_PPCF128; 399 } else if (OpVT == MVT::i64) { 400 if (RetVT == MVT::f32) 401 return UINTTOFP_I64_F32; 402 else if (RetVT == MVT::f64) 403 return UINTTOFP_I64_F64; 404 else if (RetVT == MVT::f80) 405 return UINTTOFP_I64_F80; 406 else if (RetVT == MVT::ppcf128) 407 return UINTTOFP_I64_PPCF128; 408 } else if (OpVT == MVT::i128) { 409 if (RetVT == MVT::f32) 410 return UINTTOFP_I128_F32; 411 else if (RetVT == MVT::f64) 412 return UINTTOFP_I128_F64; 413 else if (RetVT == MVT::f80) 414 return UINTTOFP_I128_F80; 415 else if (RetVT == MVT::ppcf128) 416 return UINTTOFP_I128_PPCF128; 417 } 418 return UNKNOWN_LIBCALL; 419} 420 421/// InitCmpLibcallCCs - Set default comparison libcall CC. 422/// 423static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 424 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 425 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 426 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 427 CCs[RTLIB::UNE_F32] = ISD::SETNE; 428 CCs[RTLIB::UNE_F64] = ISD::SETNE; 429 CCs[RTLIB::OGE_F32] = ISD::SETGE; 430 CCs[RTLIB::OGE_F64] = ISD::SETGE; 431 CCs[RTLIB::OLT_F32] = ISD::SETLT; 432 CCs[RTLIB::OLT_F64] = ISD::SETLT; 433 CCs[RTLIB::OLE_F32] = ISD::SETLE; 434 CCs[RTLIB::OLE_F64] = ISD::SETLE; 435 CCs[RTLIB::OGT_F32] = ISD::SETGT; 436 CCs[RTLIB::OGT_F64] = ISD::SETGT; 437 CCs[RTLIB::UO_F32] = ISD::SETNE; 438 CCs[RTLIB::UO_F64] = ISD::SETNE; 439 CCs[RTLIB::O_F32] = ISD::SETEQ; 440 CCs[RTLIB::O_F64] = ISD::SETEQ; 441} 442 443TargetLowering::TargetLowering(TargetMachine &tm) 444 : TM(tm), TD(TM.getTargetData()) { 445 // All operations default to being supported. 446 memset(OpActions, 0, sizeof(OpActions)); 447 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 448 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 449 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 450 memset(ConvertActions, 0, sizeof(ConvertActions)); 451 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 452 453 // Set default actions for various operations. 454 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 455 // Default all indexed load / store to expand. 456 for (unsigned IM = (unsigned)ISD::PRE_INC; 457 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 458 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 459 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 460 } 461 462 // These operations default to expand. 463 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 464 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 465 } 466 467 // Most targets ignore the @llvm.prefetch intrinsic. 468 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 469 470 // ConstantFP nodes default to expand. Targets can either change this to 471 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 472 // to optimize expansions for certain constants. 473 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 474 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 475 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 476 477 // These library functions default to expand. 478 setOperationAction(ISD::FLOG , MVT::f64, Expand); 479 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 480 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 481 setOperationAction(ISD::FEXP , MVT::f64, Expand); 482 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 483 setOperationAction(ISD::FLOG , MVT::f32, Expand); 484 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 485 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 486 setOperationAction(ISD::FEXP , MVT::f32, Expand); 487 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 488 489 // Default ISD::TRAP to expand (which turns it into abort). 490 setOperationAction(ISD::TRAP, MVT::Other, Expand); 491 492 IsLittleEndian = TD->isLittleEndian(); 493 UsesGlobalOffsetTable = false; 494 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 495 ShiftAmtHandling = Undefined; 496 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 497 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 498 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 499 allowUnalignedMemoryAccesses = false; 500 benefitFromCodePlacementOpt = false; 501 UseUnderscoreSetJmp = false; 502 UseUnderscoreLongJmp = false; 503 SelectIsExpensive = false; 504 IntDivIsCheap = false; 505 Pow2DivIsCheap = false; 506 StackPointerRegisterToSaveRestore = 0; 507 ExceptionPointerRegister = 0; 508 ExceptionSelectorRegister = 0; 509 BooleanContents = UndefinedBooleanContent; 510 SchedPreferenceInfo = SchedulingForLatency; 511 JumpBufSize = 0; 512 JumpBufAlignment = 0; 513 IfCvtBlockSizeLimit = 2; 514 IfCvtDupBlockSizeLimit = 0; 515 PrefLoopAlignment = 0; 516 517 InitLibcallNames(LibcallRoutineNames); 518 InitCmpLibcallCCs(CmpLibcallCCs); 519 520 // Tell Legalize whether the assembler supports DEBUG_LOC. 521 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 522 if (!TASM || !TASM->hasDotLocAndDotFile()) 523 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 524} 525 526TargetLowering::~TargetLowering() {} 527 528/// computeRegisterProperties - Once all of the register classes are added, 529/// this allows us to compute derived properties we expose. 530void TargetLowering::computeRegisterProperties() { 531 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 532 "Too many value types for ValueTypeActions to hold!"); 533 534 // Everything defaults to needing one register. 535 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 536 NumRegistersForVT[i] = 1; 537 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 538 } 539 // ...except isVoid, which doesn't need any registers. 540 NumRegistersForVT[MVT::isVoid] = 0; 541 542 // Find the largest integer register class. 543 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 544 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 545 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 546 547 // Every integer value type larger than this largest register takes twice as 548 // many registers to represent as the previous ValueType. 549 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 550 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 551 if (!EVT.isInteger()) 552 break; 553 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 554 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 555 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 556 ValueTypeActions.setTypeAction(EVT, Expand); 557 } 558 559 // Inspect all of the ValueType's smaller than the largest integer 560 // register to see which ones need promotion. 561 unsigned LegalIntReg = LargestIntReg; 562 for (unsigned IntReg = LargestIntReg - 1; 563 IntReg >= (unsigned)MVT::i1; --IntReg) { 564 MVT IVT = (MVT::SimpleValueType)IntReg; 565 if (isTypeLegal(IVT)) { 566 LegalIntReg = IntReg; 567 } else { 568 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 569 (MVT::SimpleValueType)LegalIntReg; 570 ValueTypeActions.setTypeAction(IVT, Promote); 571 } 572 } 573 574 // ppcf128 type is really two f64's. 575 if (!isTypeLegal(MVT::ppcf128)) { 576 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 577 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 578 TransformToType[MVT::ppcf128] = MVT::f64; 579 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 580 } 581 582 // Decide how to handle f64. If the target does not have native f64 support, 583 // expand it to i64 and we will be generating soft float library calls. 584 if (!isTypeLegal(MVT::f64)) { 585 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 586 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 587 TransformToType[MVT::f64] = MVT::i64; 588 ValueTypeActions.setTypeAction(MVT::f64, Expand); 589 } 590 591 // Decide how to handle f32. If the target does not have native support for 592 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 593 if (!isTypeLegal(MVT::f32)) { 594 if (isTypeLegal(MVT::f64)) { 595 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 596 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 597 TransformToType[MVT::f32] = MVT::f64; 598 ValueTypeActions.setTypeAction(MVT::f32, Promote); 599 } else { 600 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 601 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 602 TransformToType[MVT::f32] = MVT::i32; 603 ValueTypeActions.setTypeAction(MVT::f32, Expand); 604 } 605 } 606 607 // Loop over all of the vector value types to see which need transformations. 608 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 609 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 610 MVT VT = (MVT::SimpleValueType)i; 611 if (!isTypeLegal(VT)) { 612 MVT IntermediateVT, RegisterVT; 613 unsigned NumIntermediates; 614 NumRegistersForVT[i] = 615 getVectorTypeBreakdown(VT, 616 IntermediateVT, NumIntermediates, 617 RegisterVT); 618 RegisterTypeForVT[i] = RegisterVT; 619 620 // Determine if there is a legal wider type. 621 bool IsLegalWiderType = false; 622 MVT EltVT = VT.getVectorElementType(); 623 unsigned NElts = VT.getVectorNumElements(); 624 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 625 MVT SVT = (MVT::SimpleValueType)nVT; 626 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 627 SVT.getVectorNumElements() > NElts) { 628 TransformToType[i] = SVT; 629 ValueTypeActions.setTypeAction(VT, Promote); 630 IsLegalWiderType = true; 631 break; 632 } 633 } 634 if (!IsLegalWiderType) { 635 MVT NVT = VT.getPow2VectorType(); 636 if (NVT == VT) { 637 // Type is already a power of 2. The default action is to split. 638 TransformToType[i] = MVT::Other; 639 ValueTypeActions.setTypeAction(VT, Expand); 640 } else { 641 TransformToType[i] = NVT; 642 ValueTypeActions.setTypeAction(VT, Promote); 643 } 644 } 645 } 646 } 647} 648 649const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 650 return NULL; 651} 652 653 654MVT TargetLowering::getSetCCResultType(MVT VT) const { 655 return getValueType(TD->getIntPtrType()); 656} 657 658 659/// getVectorTypeBreakdown - Vector types are broken down into some number of 660/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 661/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 662/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 663/// 664/// This method returns the number of registers needed, and the VT for each 665/// register. It also returns the VT and quantity of the intermediate values 666/// before they are promoted/expanded. 667/// 668unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 669 MVT &IntermediateVT, 670 unsigned &NumIntermediates, 671 MVT &RegisterVT) const { 672 // Figure out the right, legal destination reg to copy into. 673 unsigned NumElts = VT.getVectorNumElements(); 674 MVT EltTy = VT.getVectorElementType(); 675 676 unsigned NumVectorRegs = 1; 677 678 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 679 // could break down into LHS/RHS like LegalizeDAG does. 680 if (!isPowerOf2_32(NumElts)) { 681 NumVectorRegs = NumElts; 682 NumElts = 1; 683 } 684 685 // Divide the input until we get to a supported size. This will always 686 // end with a scalar if the target doesn't support vectors. 687 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 688 NumElts >>= 1; 689 NumVectorRegs <<= 1; 690 } 691 692 NumIntermediates = NumVectorRegs; 693 694 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 695 if (!isTypeLegal(NewVT)) 696 NewVT = EltTy; 697 IntermediateVT = NewVT; 698 699 MVT DestVT = getRegisterType(NewVT); 700 RegisterVT = DestVT; 701 if (DestVT.bitsLT(NewVT)) { 702 // Value is expanded, e.g. i64 -> i16. 703 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 704 } else { 705 // Otherwise, promotion or legal types use the same number of registers as 706 // the vector decimated to the appropriate level. 707 return NumVectorRegs; 708 } 709 710 return 1; 711} 712 713/// getWidenVectorType: given a vector type, returns the type to widen to 714/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 715/// If there is no vector type that we want to widen to, returns MVT::Other 716/// When and where to widen is target dependent based on the cost of 717/// scalarizing vs using the wider vector type. 718MVT TargetLowering::getWidenVectorType(MVT VT) const { 719 assert(VT.isVector()); 720 if (isTypeLegal(VT)) 721 return VT; 722 723 // Default is not to widen until moved to LegalizeTypes 724 return MVT::Other; 725} 726 727/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 728/// function arguments in the caller parameter area. This is the actual 729/// alignment, not its logarithm. 730unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 731 return TD->getCallFrameTypeAlignment(Ty); 732} 733 734SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 735 SelectionDAG &DAG) const { 736 if (usesGlobalOffsetTable()) 737 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 738 return Table; 739} 740 741bool 742TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 743 // Assume that everything is safe in static mode. 744 if (getTargetMachine().getRelocationModel() == Reloc::Static) 745 return true; 746 747 // In dynamic-no-pic mode, assume that known defined values are safe. 748 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 749 GA && 750 !GA->getGlobal()->isDeclaration() && 751 !GA->getGlobal()->isWeakForLinker()) 752 return true; 753 754 // Otherwise assume nothing is safe. 755 return false; 756} 757 758//===----------------------------------------------------------------------===// 759// Optimization Methods 760//===----------------------------------------------------------------------===// 761 762/// ShrinkDemandedConstant - Check to see if the specified operand of the 763/// specified instruction is a constant integer. If so, check to see if there 764/// are any bits set in the constant that are not demanded. If so, shrink the 765/// constant and return true. 766bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 767 const APInt &Demanded) { 768 DebugLoc dl = Op.getDebugLoc(); 769 770 // FIXME: ISD::SELECT, ISD::SELECT_CC 771 switch (Op.getOpcode()) { 772 default: break; 773 case ISD::XOR: 774 case ISD::AND: 775 case ISD::OR: { 776 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 777 if (!C) return false; 778 779 if (Op.getOpcode() == ISD::XOR && 780 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 781 return false; 782 783 // if we can expand it to have all bits set, do it 784 if (C->getAPIntValue().intersects(~Demanded)) { 785 MVT VT = Op.getValueType(); 786 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 787 DAG.getConstant(Demanded & 788 C->getAPIntValue(), 789 VT)); 790 return CombineTo(Op, New); 791 } 792 793 break; 794 } 795 } 796 797 return false; 798} 799 800/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 801/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 802/// cast, but it could be generalized for targets with other types of 803/// implicit widening casts. 804bool 805TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 806 unsigned BitWidth, 807 const APInt &Demanded, 808 DebugLoc dl) { 809 assert(Op.getNumOperands() == 2 && 810 "ShrinkDemandedOp only supports binary operators!"); 811 assert(Op.getNode()->getNumValues() == 1 && 812 "ShrinkDemandedOp only supports nodes with one result!"); 813 814 // Don't do this if the node has another user, which may require the 815 // full value. 816 if (!Op.getNode()->hasOneUse()) 817 return false; 818 819 // Search for the smallest integer type with free casts to and from 820 // Op's type. For expedience, just check power-of-2 integer types. 821 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 822 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 823 if (!isPowerOf2_32(SmallVTBits)) 824 SmallVTBits = NextPowerOf2(SmallVTBits); 825 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 826 MVT SmallVT = MVT::getIntegerVT(SmallVTBits); 827 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 828 TLI.isZExtFree(SmallVT, Op.getValueType())) { 829 // We found a type with free casts. 830 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 831 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 832 Op.getNode()->getOperand(0)), 833 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 834 Op.getNode()->getOperand(1))); 835 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 836 return CombineTo(Op, Z); 837 } 838 } 839 return false; 840} 841 842/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 843/// DemandedMask bits of the result of Op are ever used downstream. If we can 844/// use this information to simplify Op, create a new simplified DAG node and 845/// return true, returning the original and new nodes in Old and New. Otherwise, 846/// analyze the expression and return a mask of KnownOne and KnownZero bits for 847/// the expression (used to simplify the caller). The KnownZero/One bits may 848/// only be accurate for those bits in the DemandedMask. 849bool TargetLowering::SimplifyDemandedBits(SDValue Op, 850 const APInt &DemandedMask, 851 APInt &KnownZero, 852 APInt &KnownOne, 853 TargetLoweringOpt &TLO, 854 unsigned Depth) const { 855 unsigned BitWidth = DemandedMask.getBitWidth(); 856 assert(Op.getValueSizeInBits() == BitWidth && 857 "Mask size mismatches value type size!"); 858 APInt NewMask = DemandedMask; 859 DebugLoc dl = Op.getDebugLoc(); 860 861 // Don't know anything. 862 KnownZero = KnownOne = APInt(BitWidth, 0); 863 864 // Other users may use these bits. 865 if (!Op.getNode()->hasOneUse()) { 866 if (Depth != 0) { 867 // If not at the root, Just compute the KnownZero/KnownOne bits to 868 // simplify things downstream. 869 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 870 return false; 871 } 872 // If this is the root being simplified, allow it to have multiple uses, 873 // just set the NewMask to all bits. 874 NewMask = APInt::getAllOnesValue(BitWidth); 875 } else if (DemandedMask == 0) { 876 // Not demanding any bits from Op. 877 if (Op.getOpcode() != ISD::UNDEF) 878 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 879 return false; 880 } else if (Depth == 6) { // Limit search depth. 881 return false; 882 } 883 884 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 885 switch (Op.getOpcode()) { 886 case ISD::Constant: 887 // We know all of the bits for a constant! 888 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 889 KnownZero = ~KnownOne & NewMask; 890 return false; // Don't fall through, will infinitely loop. 891 case ISD::AND: 892 // If the RHS is a constant, check to see if the LHS would be zero without 893 // using the bits from the RHS. Below, we use knowledge about the RHS to 894 // simplify the LHS, here we're using information from the LHS to simplify 895 // the RHS. 896 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 897 APInt LHSZero, LHSOne; 898 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 899 LHSZero, LHSOne, Depth+1); 900 // If the LHS already has zeros where RHSC does, this and is dead. 901 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 902 return TLO.CombineTo(Op, Op.getOperand(0)); 903 // If any of the set bits in the RHS are known zero on the LHS, shrink 904 // the constant. 905 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 906 return true; 907 } 908 909 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 910 KnownOne, TLO, Depth+1)) 911 return true; 912 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 913 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 914 KnownZero2, KnownOne2, TLO, Depth+1)) 915 return true; 916 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 917 918 // If all of the demanded bits are known one on one side, return the other. 919 // These bits cannot contribute to the result of the 'and'. 920 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 921 return TLO.CombineTo(Op, Op.getOperand(0)); 922 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 923 return TLO.CombineTo(Op, Op.getOperand(1)); 924 // If all of the demanded bits in the inputs are known zeros, return zero. 925 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 926 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 927 // If the RHS is a constant, see if we can simplify it. 928 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 929 return true; 930 // If the operation can be done in a smaller type, do so. 931 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 932 return true; 933 934 // Output known-1 bits are only known if set in both the LHS & RHS. 935 KnownOne &= KnownOne2; 936 // Output known-0 are known to be clear if zero in either the LHS | RHS. 937 KnownZero |= KnownZero2; 938 break; 939 case ISD::OR: 940 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 941 KnownOne, TLO, Depth+1)) 942 return true; 943 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 944 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 945 KnownZero2, KnownOne2, TLO, Depth+1)) 946 return true; 947 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 948 949 // If all of the demanded bits are known zero on one side, return the other. 950 // These bits cannot contribute to the result of the 'or'. 951 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 952 return TLO.CombineTo(Op, Op.getOperand(0)); 953 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 954 return TLO.CombineTo(Op, Op.getOperand(1)); 955 // If all of the potentially set bits on one side are known to be set on 956 // the other side, just use the 'other' side. 957 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 958 return TLO.CombineTo(Op, Op.getOperand(0)); 959 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 960 return TLO.CombineTo(Op, Op.getOperand(1)); 961 // If the RHS is a constant, see if we can simplify it. 962 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 963 return true; 964 // If the operation can be done in a smaller type, do so. 965 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 966 return true; 967 968 // Output known-0 bits are only known if clear in both the LHS & RHS. 969 KnownZero &= KnownZero2; 970 // Output known-1 are known to be set if set in either the LHS | RHS. 971 KnownOne |= KnownOne2; 972 break; 973 case ISD::XOR: 974 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 975 KnownOne, TLO, Depth+1)) 976 return true; 977 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 978 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 979 KnownOne2, TLO, Depth+1)) 980 return true; 981 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 982 983 // If all of the demanded bits are known zero on one side, return the other. 984 // These bits cannot contribute to the result of the 'xor'. 985 if ((KnownZero & NewMask) == NewMask) 986 return TLO.CombineTo(Op, Op.getOperand(0)); 987 if ((KnownZero2 & NewMask) == NewMask) 988 return TLO.CombineTo(Op, Op.getOperand(1)); 989 // If the operation can be done in a smaller type, do so. 990 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 991 return true; 992 993 // If all of the unknown bits are known to be zero on one side or the other 994 // (but not both) turn this into an *inclusive* or. 995 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 996 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 997 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 998 Op.getOperand(0), 999 Op.getOperand(1))); 1000 1001 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1002 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1003 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1004 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1005 1006 // If all of the demanded bits on one side are known, and all of the set 1007 // bits on that side are also known to be set on the other side, turn this 1008 // into an AND, as we know the bits will be cleared. 1009 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1010 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1011 if ((KnownOne & KnownOne2) == KnownOne) { 1012 MVT VT = Op.getValueType(); 1013 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1014 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1015 Op.getOperand(0), ANDC)); 1016 } 1017 } 1018 1019 // If the RHS is a constant, see if we can simplify it. 1020 // for XOR, we prefer to force bits to 1 if they will make a -1. 1021 // if we can't force bits, try to shrink constant 1022 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1023 APInt Expanded = C->getAPIntValue() | (~NewMask); 1024 // if we can expand it to have all bits set, do it 1025 if (Expanded.isAllOnesValue()) { 1026 if (Expanded != C->getAPIntValue()) { 1027 MVT VT = Op.getValueType(); 1028 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1029 TLO.DAG.getConstant(Expanded, VT)); 1030 return TLO.CombineTo(Op, New); 1031 } 1032 // if it already has all the bits set, nothing to change 1033 // but don't shrink either! 1034 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1035 return true; 1036 } 1037 } 1038 1039 KnownZero = KnownZeroOut; 1040 KnownOne = KnownOneOut; 1041 break; 1042 case ISD::SELECT: 1043 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1044 KnownOne, TLO, Depth+1)) 1045 return true; 1046 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1047 KnownOne2, TLO, Depth+1)) 1048 return true; 1049 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1050 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1051 1052 // If the operands are constants, see if we can simplify them. 1053 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1054 return true; 1055 1056 // Only known if known in both the LHS and RHS. 1057 KnownOne &= KnownOne2; 1058 KnownZero &= KnownZero2; 1059 break; 1060 case ISD::SELECT_CC: 1061 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1062 KnownOne, TLO, Depth+1)) 1063 return true; 1064 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1065 KnownOne2, TLO, Depth+1)) 1066 return true; 1067 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1068 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1069 1070 // If the operands are constants, see if we can simplify them. 1071 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1072 return true; 1073 1074 // Only known if known in both the LHS and RHS. 1075 KnownOne &= KnownOne2; 1076 KnownZero &= KnownZero2; 1077 break; 1078 case ISD::SHL: 1079 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1080 unsigned ShAmt = SA->getZExtValue(); 1081 SDValue InOp = Op.getOperand(0); 1082 1083 // If the shift count is an invalid immediate, don't do anything. 1084 if (ShAmt >= BitWidth) 1085 break; 1086 1087 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1088 // single shift. We can do this if the bottom bits (which are shifted 1089 // out) are never demanded. 1090 if (InOp.getOpcode() == ISD::SRL && 1091 isa<ConstantSDNode>(InOp.getOperand(1))) { 1092 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1093 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1094 unsigned Opc = ISD::SHL; 1095 int Diff = ShAmt-C1; 1096 if (Diff < 0) { 1097 Diff = -Diff; 1098 Opc = ISD::SRL; 1099 } 1100 1101 SDValue NewSA = 1102 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1103 MVT VT = Op.getValueType(); 1104 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1105 InOp.getOperand(0), NewSA)); 1106 } 1107 } 1108 1109 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1110 KnownZero, KnownOne, TLO, Depth+1)) 1111 return true; 1112 KnownZero <<= SA->getZExtValue(); 1113 KnownOne <<= SA->getZExtValue(); 1114 // low bits known zero. 1115 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1116 } 1117 break; 1118 case ISD::SRL: 1119 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1120 MVT VT = Op.getValueType(); 1121 unsigned ShAmt = SA->getZExtValue(); 1122 unsigned VTSize = VT.getSizeInBits(); 1123 SDValue InOp = Op.getOperand(0); 1124 1125 // If the shift count is an invalid immediate, don't do anything. 1126 if (ShAmt >= BitWidth) 1127 break; 1128 1129 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1130 // single shift. We can do this if the top bits (which are shifted out) 1131 // are never demanded. 1132 if (InOp.getOpcode() == ISD::SHL && 1133 isa<ConstantSDNode>(InOp.getOperand(1))) { 1134 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1135 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1136 unsigned Opc = ISD::SRL; 1137 int Diff = ShAmt-C1; 1138 if (Diff < 0) { 1139 Diff = -Diff; 1140 Opc = ISD::SHL; 1141 } 1142 1143 SDValue NewSA = 1144 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1145 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1146 InOp.getOperand(0), NewSA)); 1147 } 1148 } 1149 1150 // Compute the new bits that are at the top now. 1151 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1152 KnownZero, KnownOne, TLO, Depth+1)) 1153 return true; 1154 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1155 KnownZero = KnownZero.lshr(ShAmt); 1156 KnownOne = KnownOne.lshr(ShAmt); 1157 1158 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1159 KnownZero |= HighBits; // High bits known zero. 1160 } 1161 break; 1162 case ISD::SRA: 1163 // If this is an arithmetic shift right and only the low-bit is set, we can 1164 // always convert this into a logical shr, even if the shift amount is 1165 // variable. The low bit of the shift cannot be an input sign bit unless 1166 // the shift amount is >= the size of the datatype, which is undefined. 1167 if (DemandedMask == 1) 1168 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1169 Op.getOperand(0), Op.getOperand(1))); 1170 1171 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1172 MVT VT = Op.getValueType(); 1173 unsigned ShAmt = SA->getZExtValue(); 1174 1175 // If the shift count is an invalid immediate, don't do anything. 1176 if (ShAmt >= BitWidth) 1177 break; 1178 1179 APInt InDemandedMask = (NewMask << ShAmt); 1180 1181 // If any of the demanded bits are produced by the sign extension, we also 1182 // demand the input sign bit. 1183 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1184 if (HighBits.intersects(NewMask)) 1185 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1186 1187 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1188 KnownZero, KnownOne, TLO, Depth+1)) 1189 return true; 1190 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1191 KnownZero = KnownZero.lshr(ShAmt); 1192 KnownOne = KnownOne.lshr(ShAmt); 1193 1194 // Handle the sign bit, adjusted to where it is now in the mask. 1195 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1196 1197 // If the input sign bit is known to be zero, or if none of the top bits 1198 // are demanded, turn this into an unsigned shift right. 1199 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1200 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1201 Op.getOperand(0), 1202 Op.getOperand(1))); 1203 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1204 KnownOne |= HighBits; 1205 } 1206 } 1207 break; 1208 case ISD::SIGN_EXTEND_INREG: { 1209 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1210 1211 // Sign extension. Compute the demanded bits in the result that are not 1212 // present in the input. 1213 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1214 BitWidth - EVT.getSizeInBits()) & 1215 NewMask; 1216 1217 // If none of the extended bits are demanded, eliminate the sextinreg. 1218 if (NewBits == 0) 1219 return TLO.CombineTo(Op, Op.getOperand(0)); 1220 1221 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1222 InSignBit.zext(BitWidth); 1223 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1224 EVT.getSizeInBits()) & 1225 NewMask; 1226 1227 // Since the sign extended bits are demanded, we know that the sign 1228 // bit is demanded. 1229 InputDemandedBits |= InSignBit; 1230 1231 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1232 KnownZero, KnownOne, TLO, Depth+1)) 1233 return true; 1234 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1235 1236 // If the sign bit of the input is known set or clear, then we know the 1237 // top bits of the result. 1238 1239 // If the input sign bit is known zero, convert this into a zero extension. 1240 if (KnownZero.intersects(InSignBit)) 1241 return TLO.CombineTo(Op, 1242 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1243 1244 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1245 KnownOne |= NewBits; 1246 KnownZero &= ~NewBits; 1247 } else { // Input sign bit unknown 1248 KnownZero &= ~NewBits; 1249 KnownOne &= ~NewBits; 1250 } 1251 break; 1252 } 1253 case ISD::ZERO_EXTEND: { 1254 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1255 APInt InMask = NewMask; 1256 InMask.trunc(OperandBitWidth); 1257 1258 // If none of the top bits are demanded, convert this into an any_extend. 1259 APInt NewBits = 1260 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1261 if (!NewBits.intersects(NewMask)) 1262 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1263 Op.getValueType(), 1264 Op.getOperand(0))); 1265 1266 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1267 KnownZero, KnownOne, TLO, Depth+1)) 1268 return true; 1269 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1270 KnownZero.zext(BitWidth); 1271 KnownOne.zext(BitWidth); 1272 KnownZero |= NewBits; 1273 break; 1274 } 1275 case ISD::SIGN_EXTEND: { 1276 MVT InVT = Op.getOperand(0).getValueType(); 1277 unsigned InBits = InVT.getSizeInBits(); 1278 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1279 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1280 APInt NewBits = ~InMask & NewMask; 1281 1282 // If none of the top bits are demanded, convert this into an any_extend. 1283 if (NewBits == 0) 1284 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1285 Op.getValueType(), 1286 Op.getOperand(0))); 1287 1288 // Since some of the sign extended bits are demanded, we know that the sign 1289 // bit is demanded. 1290 APInt InDemandedBits = InMask & NewMask; 1291 InDemandedBits |= InSignBit; 1292 InDemandedBits.trunc(InBits); 1293 1294 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1295 KnownOne, TLO, Depth+1)) 1296 return true; 1297 KnownZero.zext(BitWidth); 1298 KnownOne.zext(BitWidth); 1299 1300 // If the sign bit is known zero, convert this to a zero extend. 1301 if (KnownZero.intersects(InSignBit)) 1302 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1303 Op.getValueType(), 1304 Op.getOperand(0))); 1305 1306 // If the sign bit is known one, the top bits match. 1307 if (KnownOne.intersects(InSignBit)) { 1308 KnownOne |= NewBits; 1309 KnownZero &= ~NewBits; 1310 } else { // Otherwise, top bits aren't known. 1311 KnownOne &= ~NewBits; 1312 KnownZero &= ~NewBits; 1313 } 1314 break; 1315 } 1316 case ISD::ANY_EXTEND: { 1317 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1318 APInt InMask = NewMask; 1319 InMask.trunc(OperandBitWidth); 1320 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1321 KnownZero, KnownOne, TLO, Depth+1)) 1322 return true; 1323 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1324 KnownZero.zext(BitWidth); 1325 KnownOne.zext(BitWidth); 1326 break; 1327 } 1328 case ISD::TRUNCATE: { 1329 // Simplify the input, using demanded bit information, and compute the known 1330 // zero/one bits live out. 1331 APInt TruncMask = NewMask; 1332 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1333 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1334 KnownZero, KnownOne, TLO, Depth+1)) 1335 return true; 1336 KnownZero.trunc(BitWidth); 1337 KnownOne.trunc(BitWidth); 1338 1339 // If the input is only used by this truncate, see if we can shrink it based 1340 // on the known demanded bits. 1341 if (Op.getOperand(0).getNode()->hasOneUse()) { 1342 SDValue In = Op.getOperand(0); 1343 unsigned InBitWidth = In.getValueSizeInBits(); 1344 switch (In.getOpcode()) { 1345 default: break; 1346 case ISD::SRL: 1347 // Shrink SRL by a constant if none of the high bits shifted in are 1348 // demanded. 1349 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1350 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1351 InBitWidth - BitWidth); 1352 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1353 HighBits.trunc(BitWidth); 1354 1355 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1356 // None of the shifted in bits are needed. Add a truncate of the 1357 // shift input, then shift it. 1358 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1359 Op.getValueType(), 1360 In.getOperand(0)); 1361 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1362 Op.getValueType(), 1363 NewTrunc, 1364 In.getOperand(1))); 1365 } 1366 } 1367 break; 1368 } 1369 } 1370 1371 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1372 break; 1373 } 1374 case ISD::AssertZext: { 1375 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1376 APInt InMask = APInt::getLowBitsSet(BitWidth, 1377 VT.getSizeInBits()); 1378 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1379 KnownZero, KnownOne, TLO, Depth+1)) 1380 return true; 1381 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1382 KnownZero |= ~InMask & NewMask; 1383 break; 1384 } 1385 case ISD::BIT_CONVERT: 1386#if 0 1387 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1388 // is demanded, turn this into a FGETSIGN. 1389 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1390 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1391 !MVT::isVector(Op.getOperand(0).getValueType())) { 1392 // Only do this xform if FGETSIGN is valid or if before legalize. 1393 if (!TLO.AfterLegalize || 1394 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1395 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1396 // place. We expect the SHL to be eliminated by other optimizations. 1397 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1398 Op.getOperand(0)); 1399 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1400 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1401 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1402 Sign, ShAmt)); 1403 } 1404 } 1405#endif 1406 break; 1407 case ISD::ADD: 1408 case ISD::MUL: 1409 case ISD::SUB: { 1410 // Add, Sub, and Mul don't demand any bits in positions beyond that 1411 // of the highest bit demanded of them. 1412 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1413 BitWidth - NewMask.countLeadingZeros()); 1414 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1415 KnownOne2, TLO, Depth+1)) 1416 return true; 1417 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1418 KnownOne2, TLO, Depth+1)) 1419 return true; 1420 // See if the operation should be performed at a smaller bit width. 1421 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1422 return true; 1423 } 1424 // FALL THROUGH 1425 default: 1426 // Just use ComputeMaskedBits to compute output bits. 1427 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1428 break; 1429 } 1430 1431 // If we know the value of all of the demanded bits, return this as a 1432 // constant. 1433 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1434 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1435 1436 return false; 1437} 1438 1439/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1440/// in Mask are known to be either zero or one and return them in the 1441/// KnownZero/KnownOne bitsets. 1442void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1443 const APInt &Mask, 1444 APInt &KnownZero, 1445 APInt &KnownOne, 1446 const SelectionDAG &DAG, 1447 unsigned Depth) const { 1448 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1449 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1450 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1451 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1452 "Should use MaskedValueIsZero if you don't know whether Op" 1453 " is a target node!"); 1454 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1455} 1456 1457/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1458/// targets that want to expose additional information about sign bits to the 1459/// DAG Combiner. 1460unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1461 unsigned Depth) const { 1462 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1463 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1464 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1465 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1466 "Should use ComputeNumSignBits if you don't know whether Op" 1467 " is a target node!"); 1468 return 1; 1469} 1470 1471/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1472/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1473/// determine which bit is set. 1474/// 1475static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1476 // A left-shift of a constant one will have exactly one bit set, because 1477 // shifting the bit off the end is undefined. 1478 if (Val.getOpcode() == ISD::SHL) 1479 if (ConstantSDNode *C = 1480 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1481 if (C->getAPIntValue() == 1) 1482 return true; 1483 1484 // Similarly, a right-shift of a constant sign-bit will have exactly 1485 // one bit set. 1486 if (Val.getOpcode() == ISD::SRL) 1487 if (ConstantSDNode *C = 1488 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1489 if (C->getAPIntValue().isSignBit()) 1490 return true; 1491 1492 // More could be done here, though the above checks are enough 1493 // to handle some common cases. 1494 1495 // Fall back to ComputeMaskedBits to catch other known cases. 1496 MVT OpVT = Val.getValueType(); 1497 unsigned BitWidth = OpVT.getSizeInBits(); 1498 APInt Mask = APInt::getAllOnesValue(BitWidth); 1499 APInt KnownZero, KnownOne; 1500 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1501 return (KnownZero.countPopulation() == BitWidth - 1) && 1502 (KnownOne.countPopulation() == 1); 1503} 1504 1505/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1506/// and cc. If it is unable to simplify it, return a null SDValue. 1507SDValue 1508TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1509 ISD::CondCode Cond, bool foldBooleans, 1510 DAGCombinerInfo &DCI, DebugLoc dl) const { 1511 SelectionDAG &DAG = DCI.DAG; 1512 1513 // These setcc operations always fold. 1514 switch (Cond) { 1515 default: break; 1516 case ISD::SETFALSE: 1517 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1518 case ISD::SETTRUE: 1519 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1520 } 1521 1522 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1523 const APInt &C1 = N1C->getAPIntValue(); 1524 if (isa<ConstantSDNode>(N0.getNode())) { 1525 return DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1526 } else { 1527 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1528 // equality comparison, then we're just comparing whether X itself is 1529 // zero. 1530 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1531 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1532 N0.getOperand(1).getOpcode() == ISD::Constant) { 1533 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1534 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1535 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1536 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1537 // (srl (ctlz x), 5) == 0 -> X != 0 1538 // (srl (ctlz x), 5) != 1 -> X != 0 1539 Cond = ISD::SETNE; 1540 } else { 1541 // (srl (ctlz x), 5) != 0 -> X == 0 1542 // (srl (ctlz x), 5) == 1 -> X == 0 1543 Cond = ISD::SETEQ; 1544 } 1545 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1546 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1547 Zero, Cond); 1548 } 1549 } 1550 1551 // If the LHS is '(and load, const)', the RHS is 0, 1552 // the test is for equality or unsigned, and all 1 bits of the const are 1553 // in the same partial word, see if we can shorten the load. 1554 if (DCI.isBeforeLegalize() && 1555 N0.getOpcode() == ISD::AND && C1 == 0 && 1556 N0.getNode()->hasOneUse() && 1557 isa<LoadSDNode>(N0.getOperand(0)) && 1558 N0.getOperand(0).getNode()->hasOneUse() && 1559 isa<ConstantSDNode>(N0.getOperand(1))) { 1560 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1561 uint64_t bestMask = 0; 1562 unsigned bestWidth = 0, bestOffset = 0; 1563 if (!Lod->isVolatile() && Lod->isUnindexed() && 1564 // FIXME: This uses getZExtValue() below so it only works on i64 and 1565 // below. 1566 N0.getValueType().getSizeInBits() <= 64) { 1567 unsigned origWidth = N0.getValueType().getSizeInBits(); 1568 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1569 // 8 bits, but have to be careful... 1570 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1571 origWidth = Lod->getMemoryVT().getSizeInBits(); 1572 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1573 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1574 uint64_t newMask = (1ULL << width) - 1; 1575 for (unsigned offset=0; offset<origWidth/width; offset++) { 1576 if ((newMask & Mask) == Mask) { 1577 if (!TD->isLittleEndian()) 1578 bestOffset = (origWidth/width - offset - 1) * (width/8); 1579 else 1580 bestOffset = (uint64_t)offset * (width/8); 1581 bestMask = Mask >> (offset * (width/8) * 8); 1582 bestWidth = width; 1583 break; 1584 } 1585 newMask = newMask << width; 1586 } 1587 } 1588 } 1589 if (bestWidth) { 1590 MVT newVT = MVT::getIntegerVT(bestWidth); 1591 if (newVT.isRound()) { 1592 MVT PtrType = Lod->getOperand(1).getValueType(); 1593 SDValue Ptr = Lod->getBasePtr(); 1594 if (bestOffset != 0) 1595 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1596 DAG.getConstant(bestOffset, PtrType)); 1597 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1598 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1599 Lod->getSrcValue(), 1600 Lod->getSrcValueOffset() + bestOffset, 1601 false, NewAlign); 1602 return DAG.getSetCC(dl, VT, 1603 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1604 DAG.getConstant(bestMask, newVT)), 1605 DAG.getConstant(0LL, newVT), Cond); 1606 } 1607 } 1608 } 1609 1610 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1611 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1612 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1613 1614 // If the comparison constant has bits in the upper part, the 1615 // zero-extended value could never match. 1616 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1617 C1.getBitWidth() - InSize))) { 1618 switch (Cond) { 1619 case ISD::SETUGT: 1620 case ISD::SETUGE: 1621 case ISD::SETEQ: return DAG.getConstant(0, VT); 1622 case ISD::SETULT: 1623 case ISD::SETULE: 1624 case ISD::SETNE: return DAG.getConstant(1, VT); 1625 case ISD::SETGT: 1626 case ISD::SETGE: 1627 // True if the sign bit of C1 is set. 1628 return DAG.getConstant(C1.isNegative(), VT); 1629 case ISD::SETLT: 1630 case ISD::SETLE: 1631 // True if the sign bit of C1 isn't set. 1632 return DAG.getConstant(C1.isNonNegative(), VT); 1633 default: 1634 break; 1635 } 1636 } 1637 1638 // Otherwise, we can perform the comparison with the low bits. 1639 switch (Cond) { 1640 case ISD::SETEQ: 1641 case ISD::SETNE: 1642 case ISD::SETUGT: 1643 case ISD::SETUGE: 1644 case ISD::SETULT: 1645 case ISD::SETULE: 1646 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1647 DAG.getConstant(APInt(C1).trunc(InSize), 1648 N0.getOperand(0).getValueType()), 1649 Cond); 1650 default: 1651 break; // todo, be more careful with signed comparisons 1652 } 1653 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1654 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1655 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1656 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1657 MVT ExtDstTy = N0.getValueType(); 1658 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1659 1660 // If the extended part has any inconsistent bits, it cannot ever 1661 // compare equal. In other words, they have to be all ones or all 1662 // zeros. 1663 APInt ExtBits = 1664 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1665 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1666 return DAG.getConstant(Cond == ISD::SETNE, VT); 1667 1668 SDValue ZextOp; 1669 MVT Op0Ty = N0.getOperand(0).getValueType(); 1670 if (Op0Ty == ExtSrcTy) { 1671 ZextOp = N0.getOperand(0); 1672 } else { 1673 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1674 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1675 DAG.getConstant(Imm, Op0Ty)); 1676 } 1677 if (!DCI.isCalledByLegalizer()) 1678 DCI.AddToWorklist(ZextOp.getNode()); 1679 // Otherwise, make this a use of a zext. 1680 return DAG.getSetCC(dl, VT, ZextOp, 1681 DAG.getConstant(C1 & APInt::getLowBitsSet( 1682 ExtDstTyBits, 1683 ExtSrcTyBits), 1684 ExtDstTy), 1685 Cond); 1686 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1687 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1688 1689 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1690 if (N0.getOpcode() == ISD::SETCC) { 1691 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1692 if (TrueWhenTrue) 1693 return N0; 1694 1695 // Invert the condition. 1696 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1697 CC = ISD::getSetCCInverse(CC, 1698 N0.getOperand(0).getValueType().isInteger()); 1699 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1700 } 1701 1702 if ((N0.getOpcode() == ISD::XOR || 1703 (N0.getOpcode() == ISD::AND && 1704 N0.getOperand(0).getOpcode() == ISD::XOR && 1705 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1706 isa<ConstantSDNode>(N0.getOperand(1)) && 1707 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1708 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1709 // can only do this if the top bits are known zero. 1710 unsigned BitWidth = N0.getValueSizeInBits(); 1711 if (DAG.MaskedValueIsZero(N0, 1712 APInt::getHighBitsSet(BitWidth, 1713 BitWidth-1))) { 1714 // Okay, get the un-inverted input value. 1715 SDValue Val; 1716 if (N0.getOpcode() == ISD::XOR) 1717 Val = N0.getOperand(0); 1718 else { 1719 assert(N0.getOpcode() == ISD::AND && 1720 N0.getOperand(0).getOpcode() == ISD::XOR); 1721 // ((X^1)&1)^1 -> X & 1 1722 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1723 N0.getOperand(0).getOperand(0), 1724 N0.getOperand(1)); 1725 } 1726 return DAG.getSetCC(dl, VT, Val, N1, 1727 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1728 } 1729 } 1730 } 1731 1732 APInt MinVal, MaxVal; 1733 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1734 if (ISD::isSignedIntSetCC(Cond)) { 1735 MinVal = APInt::getSignedMinValue(OperandBitSize); 1736 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1737 } else { 1738 MinVal = APInt::getMinValue(OperandBitSize); 1739 MaxVal = APInt::getMaxValue(OperandBitSize); 1740 } 1741 1742 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1743 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1744 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1745 // X >= C0 --> X > (C0-1) 1746 return DAG.getSetCC(dl, VT, N0, 1747 DAG.getConstant(C1-1, N1.getValueType()), 1748 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1749 } 1750 1751 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1752 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1753 // X <= C0 --> X < (C0+1) 1754 return DAG.getSetCC(dl, VT, N0, 1755 DAG.getConstant(C1+1, N1.getValueType()), 1756 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1757 } 1758 1759 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1760 return DAG.getConstant(0, VT); // X < MIN --> false 1761 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1762 return DAG.getConstant(1, VT); // X >= MIN --> true 1763 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1764 return DAG.getConstant(0, VT); // X > MAX --> false 1765 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1766 return DAG.getConstant(1, VT); // X <= MAX --> true 1767 1768 // Canonicalize setgt X, Min --> setne X, Min 1769 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1770 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1771 // Canonicalize setlt X, Max --> setne X, Max 1772 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1773 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1774 1775 // If we have setult X, 1, turn it into seteq X, 0 1776 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1777 return DAG.getSetCC(dl, VT, N0, 1778 DAG.getConstant(MinVal, N0.getValueType()), 1779 ISD::SETEQ); 1780 // If we have setugt X, Max-1, turn it into seteq X, Max 1781 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1782 return DAG.getSetCC(dl, VT, N0, 1783 DAG.getConstant(MaxVal, N0.getValueType()), 1784 ISD::SETEQ); 1785 1786 // If we have "setcc X, C0", check to see if we can shrink the immediate 1787 // by changing cc. 1788 1789 // SETUGT X, SINTMAX -> SETLT X, 0 1790 if (Cond == ISD::SETUGT && 1791 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1792 return DAG.getSetCC(dl, VT, N0, 1793 DAG.getConstant(0, N1.getValueType()), 1794 ISD::SETLT); 1795 1796 // SETULT X, SINTMIN -> SETGT X, -1 1797 if (Cond == ISD::SETULT && 1798 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1799 SDValue ConstMinusOne = 1800 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1801 N1.getValueType()); 1802 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1803 } 1804 1805 // Fold bit comparisons when we can. 1806 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1807 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1808 if (ConstantSDNode *AndRHS = 1809 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1810 MVT ShiftTy = DCI.isBeforeLegalize() ? 1811 getPointerTy() : getShiftAmountTy(); 1812 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1813 // Perform the xform if the AND RHS is a single bit. 1814 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1815 return DAG.getNode(ISD::SRL, dl, VT, N0, 1816 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1817 ShiftTy)); 1818 } 1819 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1820 // (X & 8) == 8 --> (X & 8) >> 3 1821 // Perform the xform if C1 is a single bit. 1822 if (C1.isPowerOf2()) { 1823 return DAG.getNode(ISD::SRL, dl, VT, N0, 1824 DAG.getConstant(C1.logBase2(), ShiftTy)); 1825 } 1826 } 1827 } 1828 } 1829 } else if (isa<ConstantSDNode>(N0.getNode())) { 1830 // Ensure that the constant occurs on the RHS. 1831 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1832 } 1833 1834 if (isa<ConstantFPSDNode>(N0.getNode())) { 1835 // Constant fold or commute setcc. 1836 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1837 if (O.getNode()) return O; 1838 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1839 // If the RHS of an FP comparison is a constant, simplify it away in 1840 // some cases. 1841 if (CFP->getValueAPF().isNaN()) { 1842 // If an operand is known to be a nan, we can fold it. 1843 switch (ISD::getUnorderedFlavor(Cond)) { 1844 default: LLVM_UNREACHABLE("Unknown flavor!"); 1845 case 0: // Known false. 1846 return DAG.getConstant(0, VT); 1847 case 1: // Known true. 1848 return DAG.getConstant(1, VT); 1849 case 2: // Undefined. 1850 return DAG.getUNDEF(VT); 1851 } 1852 } 1853 1854 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1855 // constant if knowing that the operand is non-nan is enough. We prefer to 1856 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1857 // materialize 0.0. 1858 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1859 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1860 } 1861 1862 if (N0 == N1) { 1863 // We can always fold X == X for integer setcc's. 1864 if (N0.getValueType().isInteger()) 1865 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1866 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1867 if (UOF == 2) // FP operators that are undefined on NaNs. 1868 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1869 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1870 return DAG.getConstant(UOF, VT); 1871 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1872 // if it is not already. 1873 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1874 if (NewCond != Cond) 1875 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1876 } 1877 1878 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1879 N0.getValueType().isInteger()) { 1880 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1881 N0.getOpcode() == ISD::XOR) { 1882 // Simplify (X+Y) == (X+Z) --> Y == Z 1883 if (N0.getOpcode() == N1.getOpcode()) { 1884 if (N0.getOperand(0) == N1.getOperand(0)) 1885 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1886 if (N0.getOperand(1) == N1.getOperand(1)) 1887 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1888 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1889 // If X op Y == Y op X, try other combinations. 1890 if (N0.getOperand(0) == N1.getOperand(1)) 1891 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1892 Cond); 1893 if (N0.getOperand(1) == N1.getOperand(0)) 1894 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1895 Cond); 1896 } 1897 } 1898 1899 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1900 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1901 // Turn (X+C1) == C2 --> X == C2-C1 1902 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1903 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1904 DAG.getConstant(RHSC->getAPIntValue()- 1905 LHSR->getAPIntValue(), 1906 N0.getValueType()), Cond); 1907 } 1908 1909 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1910 if (N0.getOpcode() == ISD::XOR) 1911 // If we know that all of the inverted bits are zero, don't bother 1912 // performing the inversion. 1913 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1914 return 1915 DAG.getSetCC(dl, VT, N0.getOperand(0), 1916 DAG.getConstant(LHSR->getAPIntValue() ^ 1917 RHSC->getAPIntValue(), 1918 N0.getValueType()), 1919 Cond); 1920 } 1921 1922 // Turn (C1-X) == C2 --> X == C1-C2 1923 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1924 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1925 return 1926 DAG.getSetCC(dl, VT, N0.getOperand(1), 1927 DAG.getConstant(SUBC->getAPIntValue() - 1928 RHSC->getAPIntValue(), 1929 N0.getValueType()), 1930 Cond); 1931 } 1932 } 1933 } 1934 1935 // Simplify (X+Z) == X --> Z == 0 1936 if (N0.getOperand(0) == N1) 1937 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1938 DAG.getConstant(0, N0.getValueType()), Cond); 1939 if (N0.getOperand(1) == N1) { 1940 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1941 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1942 DAG.getConstant(0, N0.getValueType()), Cond); 1943 else if (N0.getNode()->hasOneUse()) { 1944 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1945 // (Z-X) == X --> Z == X<<1 1946 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1947 N1, 1948 DAG.getConstant(1, getShiftAmountTy())); 1949 if (!DCI.isCalledByLegalizer()) 1950 DCI.AddToWorklist(SH.getNode()); 1951 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1952 } 1953 } 1954 } 1955 1956 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1957 N1.getOpcode() == ISD::XOR) { 1958 // Simplify X == (X+Z) --> Z == 0 1959 if (N1.getOperand(0) == N0) { 1960 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1961 DAG.getConstant(0, N1.getValueType()), Cond); 1962 } else if (N1.getOperand(1) == N0) { 1963 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1964 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1965 DAG.getConstant(0, N1.getValueType()), Cond); 1966 } else if (N1.getNode()->hasOneUse()) { 1967 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1968 // X == (Z-X) --> X<<1 == Z 1969 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1970 DAG.getConstant(1, getShiftAmountTy())); 1971 if (!DCI.isCalledByLegalizer()) 1972 DCI.AddToWorklist(SH.getNode()); 1973 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1974 } 1975 } 1976 } 1977 1978 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1979 // Note that where y is variable and is known to have at most 1980 // one bit set (for example, if it is z&1) we cannot do this; 1981 // the expressions are not equivalent when y==0. 1982 if (N0.getOpcode() == ISD::AND) 1983 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1984 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1985 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1986 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1987 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1988 } 1989 } 1990 if (N1.getOpcode() == ISD::AND) 1991 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1992 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1993 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1994 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1995 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1996 } 1997 } 1998 } 1999 2000 // Fold away ALL boolean setcc's. 2001 SDValue Temp; 2002 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2003 switch (Cond) { 2004 default: LLVM_UNREACHABLE("Unknown integer setcc!"); 2005 case ISD::SETEQ: // X == Y -> ~(X^Y) 2006 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2007 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2008 if (!DCI.isCalledByLegalizer()) 2009 DCI.AddToWorklist(Temp.getNode()); 2010 break; 2011 case ISD::SETNE: // X != Y --> (X^Y) 2012 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2013 break; 2014 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2015 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2016 Temp = DAG.getNOT(dl, N0, MVT::i1); 2017 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2018 if (!DCI.isCalledByLegalizer()) 2019 DCI.AddToWorklist(Temp.getNode()); 2020 break; 2021 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2022 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2023 Temp = DAG.getNOT(dl, N1, MVT::i1); 2024 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2025 if (!DCI.isCalledByLegalizer()) 2026 DCI.AddToWorklist(Temp.getNode()); 2027 break; 2028 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2029 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2030 Temp = DAG.getNOT(dl, N0, MVT::i1); 2031 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2032 if (!DCI.isCalledByLegalizer()) 2033 DCI.AddToWorklist(Temp.getNode()); 2034 break; 2035 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2036 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2037 Temp = DAG.getNOT(dl, N1, MVT::i1); 2038 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2039 break; 2040 } 2041 if (VT != MVT::i1) { 2042 if (!DCI.isCalledByLegalizer()) 2043 DCI.AddToWorklist(N0.getNode()); 2044 // FIXME: If running after legalize, we probably can't do this. 2045 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2046 } 2047 return N0; 2048 } 2049 2050 // Could not fold it. 2051 return SDValue(); 2052} 2053 2054/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2055/// node is a GlobalAddress + offset. 2056bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2057 int64_t &Offset) const { 2058 if (isa<GlobalAddressSDNode>(N)) { 2059 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2060 GA = GASD->getGlobal(); 2061 Offset += GASD->getOffset(); 2062 return true; 2063 } 2064 2065 if (N->getOpcode() == ISD::ADD) { 2066 SDValue N1 = N->getOperand(0); 2067 SDValue N2 = N->getOperand(1); 2068 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2069 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2070 if (V) { 2071 Offset += V->getSExtValue(); 2072 return true; 2073 } 2074 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2075 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2076 if (V) { 2077 Offset += V->getSExtValue(); 2078 return true; 2079 } 2080 } 2081 } 2082 return false; 2083} 2084 2085 2086/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 2087/// location that is 'Dist' units away from the location that the 'Base' load 2088/// is loading from. 2089bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, 2090 unsigned Bytes, int Dist, 2091 const MachineFrameInfo *MFI) const { 2092 if (LD->getChain() != Base->getChain()) 2093 return false; 2094 MVT VT = LD->getValueType(0); 2095 if (VT.getSizeInBits() / 8 != Bytes) 2096 return false; 2097 2098 SDValue Loc = LD->getOperand(1); 2099 SDValue BaseLoc = Base->getOperand(1); 2100 if (Loc.getOpcode() == ISD::FrameIndex) { 2101 if (BaseLoc.getOpcode() != ISD::FrameIndex) 2102 return false; 2103 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 2104 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 2105 int FS = MFI->getObjectSize(FI); 2106 int BFS = MFI->getObjectSize(BFI); 2107 if (FS != BFS || FS != (int)Bytes) return false; 2108 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 2109 } 2110 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) { 2111 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1)); 2112 if (V && (V->getSExtValue() == Dist*Bytes)) 2113 return true; 2114 } 2115 2116 GlobalValue *GV1 = NULL; 2117 GlobalValue *GV2 = NULL; 2118 int64_t Offset1 = 0; 2119 int64_t Offset2 = 0; 2120 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 2121 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 2122 if (isGA1 && isGA2 && GV1 == GV2) 2123 return Offset1 == (Offset2 + Dist*Bytes); 2124 return false; 2125} 2126 2127 2128SDValue TargetLowering:: 2129PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2130 // Default implementation: no optimization. 2131 return SDValue(); 2132} 2133 2134//===----------------------------------------------------------------------===// 2135// Inline Assembler Implementation Methods 2136//===----------------------------------------------------------------------===// 2137 2138 2139TargetLowering::ConstraintType 2140TargetLowering::getConstraintType(const std::string &Constraint) const { 2141 // FIXME: lots more standard ones to handle. 2142 if (Constraint.size() == 1) { 2143 switch (Constraint[0]) { 2144 default: break; 2145 case 'r': return C_RegisterClass; 2146 case 'm': // memory 2147 case 'o': // offsetable 2148 case 'V': // not offsetable 2149 return C_Memory; 2150 case 'i': // Simple Integer or Relocatable Constant 2151 case 'n': // Simple Integer 2152 case 's': // Relocatable Constant 2153 case 'X': // Allow ANY value. 2154 case 'I': // Target registers. 2155 case 'J': 2156 case 'K': 2157 case 'L': 2158 case 'M': 2159 case 'N': 2160 case 'O': 2161 case 'P': 2162 return C_Other; 2163 } 2164 } 2165 2166 if (Constraint.size() > 1 && Constraint[0] == '{' && 2167 Constraint[Constraint.size()-1] == '}') 2168 return C_Register; 2169 return C_Unknown; 2170} 2171 2172/// LowerXConstraint - try to replace an X constraint, which matches anything, 2173/// with another that has more specific requirements based on the type of the 2174/// corresponding operand. 2175const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2176 if (ConstraintVT.isInteger()) 2177 return "r"; 2178 if (ConstraintVT.isFloatingPoint()) 2179 return "f"; // works for many targets 2180 return 0; 2181} 2182 2183/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2184/// vector. If it is invalid, don't add anything to Ops. 2185void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2186 char ConstraintLetter, 2187 bool hasMemory, 2188 std::vector<SDValue> &Ops, 2189 SelectionDAG &DAG) const { 2190 switch (ConstraintLetter) { 2191 default: break; 2192 case 'X': // Allows any operand; labels (basic block) use this. 2193 if (Op.getOpcode() == ISD::BasicBlock) { 2194 Ops.push_back(Op); 2195 return; 2196 } 2197 // fall through 2198 case 'i': // Simple Integer or Relocatable Constant 2199 case 'n': // Simple Integer 2200 case 's': { // Relocatable Constant 2201 // These operands are interested in values of the form (GV+C), where C may 2202 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2203 // is possible and fine if either GV or C are missing. 2204 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2205 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2206 2207 // If we have "(add GV, C)", pull out GV/C 2208 if (Op.getOpcode() == ISD::ADD) { 2209 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2210 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2211 if (C == 0 || GA == 0) { 2212 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2213 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2214 } 2215 if (C == 0 || GA == 0) 2216 C = 0, GA = 0; 2217 } 2218 2219 // If we find a valid operand, map to the TargetXXX version so that the 2220 // value itself doesn't get selected. 2221 if (GA) { // Either &GV or &GV+C 2222 if (ConstraintLetter != 'n') { 2223 int64_t Offs = GA->getOffset(); 2224 if (C) Offs += C->getZExtValue(); 2225 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2226 Op.getValueType(), Offs)); 2227 return; 2228 } 2229 } 2230 if (C) { // just C, no GV. 2231 // Simple constants are not allowed for 's'. 2232 if (ConstraintLetter != 's') { 2233 // gcc prints these as sign extended. Sign extend value to 64 bits 2234 // now; without this it would get ZExt'd later in 2235 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2236 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2237 MVT::i64)); 2238 return; 2239 } 2240 } 2241 break; 2242 } 2243 } 2244} 2245 2246std::vector<unsigned> TargetLowering:: 2247getRegClassForInlineAsmConstraint(const std::string &Constraint, 2248 MVT VT) const { 2249 return std::vector<unsigned>(); 2250} 2251 2252 2253std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2254getRegForInlineAsmConstraint(const std::string &Constraint, 2255 MVT VT) const { 2256 if (Constraint[0] != '{') 2257 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2258 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2259 2260 // Remove the braces from around the name. 2261 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2262 2263 // Figure out which register class contains this reg. 2264 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2265 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2266 E = RI->regclass_end(); RCI != E; ++RCI) { 2267 const TargetRegisterClass *RC = *RCI; 2268 2269 // If none of the the value types for this register class are valid, we 2270 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2271 bool isLegal = false; 2272 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2273 I != E; ++I) { 2274 if (isTypeLegal(*I)) { 2275 isLegal = true; 2276 break; 2277 } 2278 } 2279 2280 if (!isLegal) continue; 2281 2282 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2283 I != E; ++I) { 2284 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2285 return std::make_pair(*I, RC); 2286 } 2287 } 2288 2289 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2290} 2291 2292//===----------------------------------------------------------------------===// 2293// Constraint Selection. 2294 2295/// isMatchingInputConstraint - Return true of this is an input operand that is 2296/// a matching constraint like "4". 2297bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2298 assert(!ConstraintCode.empty() && "No known constraint!"); 2299 return isdigit(ConstraintCode[0]); 2300} 2301 2302/// getMatchedOperand - If this is an input matching constraint, this method 2303/// returns the output operand it matches. 2304unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2305 assert(!ConstraintCode.empty() && "No known constraint!"); 2306 return atoi(ConstraintCode.c_str()); 2307} 2308 2309 2310/// getConstraintGenerality - Return an integer indicating how general CT 2311/// is. 2312static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2313 switch (CT) { 2314 default: LLVM_UNREACHABLE("Unknown constraint type!"); 2315 case TargetLowering::C_Other: 2316 case TargetLowering::C_Unknown: 2317 return 0; 2318 case TargetLowering::C_Register: 2319 return 1; 2320 case TargetLowering::C_RegisterClass: 2321 return 2; 2322 case TargetLowering::C_Memory: 2323 return 3; 2324 } 2325} 2326 2327/// ChooseConstraint - If there are multiple different constraints that we 2328/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2329/// This is somewhat tricky: constraints fall into four classes: 2330/// Other -> immediates and magic values 2331/// Register -> one specific register 2332/// RegisterClass -> a group of regs 2333/// Memory -> memory 2334/// Ideally, we would pick the most specific constraint possible: if we have 2335/// something that fits into a register, we would pick it. The problem here 2336/// is that if we have something that could either be in a register or in 2337/// memory that use of the register could cause selection of *other* 2338/// operands to fail: they might only succeed if we pick memory. Because of 2339/// this the heuristic we use is: 2340/// 2341/// 1) If there is an 'other' constraint, and if the operand is valid for 2342/// that constraint, use it. This makes us take advantage of 'i' 2343/// constraints when available. 2344/// 2) Otherwise, pick the most general constraint present. This prefers 2345/// 'm' over 'r', for example. 2346/// 2347static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2348 bool hasMemory, const TargetLowering &TLI, 2349 SDValue Op, SelectionDAG *DAG) { 2350 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2351 unsigned BestIdx = 0; 2352 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2353 int BestGenerality = -1; 2354 2355 // Loop over the options, keeping track of the most general one. 2356 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2357 TargetLowering::ConstraintType CType = 2358 TLI.getConstraintType(OpInfo.Codes[i]); 2359 2360 // If this is an 'other' constraint, see if the operand is valid for it. 2361 // For example, on X86 we might have an 'rI' constraint. If the operand 2362 // is an integer in the range [0..31] we want to use I (saving a load 2363 // of a register), otherwise we must use 'r'. 2364 if (CType == TargetLowering::C_Other && Op.getNode()) { 2365 assert(OpInfo.Codes[i].size() == 1 && 2366 "Unhandled multi-letter 'other' constraint"); 2367 std::vector<SDValue> ResultOps; 2368 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2369 ResultOps, *DAG); 2370 if (!ResultOps.empty()) { 2371 BestType = CType; 2372 BestIdx = i; 2373 break; 2374 } 2375 } 2376 2377 // This constraint letter is more general than the previous one, use it. 2378 int Generality = getConstraintGenerality(CType); 2379 if (Generality > BestGenerality) { 2380 BestType = CType; 2381 BestIdx = i; 2382 BestGenerality = Generality; 2383 } 2384 } 2385 2386 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2387 OpInfo.ConstraintType = BestType; 2388} 2389 2390/// ComputeConstraintToUse - Determines the constraint code and constraint 2391/// type to use for the specific AsmOperandInfo, setting 2392/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2393void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2394 SDValue Op, 2395 bool hasMemory, 2396 SelectionDAG *DAG) const { 2397 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2398 2399 // Single-letter constraints ('r') are very common. 2400 if (OpInfo.Codes.size() == 1) { 2401 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2402 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2403 } else { 2404 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2405 } 2406 2407 // 'X' matches anything. 2408 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2409 // Look through bitcasts over functions. In the context of an asm 2410 // argument we don't care about bitcasting function types; the parameters 2411 // to the function, if any, will have been handled elsewhere. 2412 Value *v = OpInfo.CallOperandVal; 2413 ConstantExpr *CE = NULL; 2414 while ((CE = dyn_cast<ConstantExpr>(v)) && 2415 CE->getOpcode()==Instruction::BitCast) 2416 v = CE->getOperand(0); 2417 if (!isa<Function>(v)) 2418 v = OpInfo.CallOperandVal; 2419 // Labels and constants are handled elsewhere ('X' is the only thing 2420 // that matches labels). For Functions, the type here is the type of 2421 // the result, which is not what we want to look at; leave them alone 2422 // (minus any bitcasts). 2423 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2424 OpInfo.CallOperandVal = v; 2425 return; 2426 } 2427 2428 // Otherwise, try to resolve it to something we know about by looking at 2429 // the actual operand type. 2430 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2431 OpInfo.ConstraintCode = Repl; 2432 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2433 } 2434 } 2435} 2436 2437//===----------------------------------------------------------------------===// 2438// Loop Strength Reduction hooks 2439//===----------------------------------------------------------------------===// 2440 2441/// isLegalAddressingMode - Return true if the addressing mode represented 2442/// by AM is legal for this target, for a load/store of the specified type. 2443bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2444 const Type *Ty) const { 2445 // The default implementation of this implements a conservative RISCy, r+r and 2446 // r+i addr mode. 2447 2448 // Allows a sign-extended 16-bit immediate field. 2449 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2450 return false; 2451 2452 // No global is ever allowed as a base. 2453 if (AM.BaseGV) 2454 return false; 2455 2456 // Only support r+r, 2457 switch (AM.Scale) { 2458 case 0: // "r+i" or just "i", depending on HasBaseReg. 2459 break; 2460 case 1: 2461 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2462 return false; 2463 // Otherwise we have r+r or r+i. 2464 break; 2465 case 2: 2466 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2467 return false; 2468 // Allow 2*r as r+r. 2469 break; 2470 } 2471 2472 return true; 2473} 2474 2475/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2476/// return a DAG expression to select that will generate the same value by 2477/// multiplying by a magic number. See: 2478/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2479SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2480 std::vector<SDNode*>* Created) const { 2481 MVT VT = N->getValueType(0); 2482 DebugLoc dl= N->getDebugLoc(); 2483 2484 // Check to see if we can do this. 2485 // FIXME: We should be more aggressive here. 2486 if (!isTypeLegal(VT)) 2487 return SDValue(); 2488 2489 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2490 APInt::ms magics = d.magic(); 2491 2492 // Multiply the numerator (operand 0) by the magic value 2493 // FIXME: We should support doing a MUL in a wider type 2494 SDValue Q; 2495 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2496 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2497 DAG.getConstant(magics.m, VT)); 2498 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2499 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2500 N->getOperand(0), 2501 DAG.getConstant(magics.m, VT)).getNode(), 1); 2502 else 2503 return SDValue(); // No mulhs or equvialent 2504 // If d > 0 and m < 0, add the numerator 2505 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2506 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2507 if (Created) 2508 Created->push_back(Q.getNode()); 2509 } 2510 // If d < 0 and m > 0, subtract the numerator. 2511 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2512 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2513 if (Created) 2514 Created->push_back(Q.getNode()); 2515 } 2516 // Shift right algebraic if shift value is nonzero 2517 if (magics.s > 0) { 2518 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2519 DAG.getConstant(magics.s, getShiftAmountTy())); 2520 if (Created) 2521 Created->push_back(Q.getNode()); 2522 } 2523 // Extract the sign bit and add it to the quotient 2524 SDValue T = 2525 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2526 getShiftAmountTy())); 2527 if (Created) 2528 Created->push_back(T.getNode()); 2529 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2530} 2531 2532/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2533/// return a DAG expression to select that will generate the same value by 2534/// multiplying by a magic number. See: 2535/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2536SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2537 std::vector<SDNode*>* Created) const { 2538 MVT VT = N->getValueType(0); 2539 DebugLoc dl = N->getDebugLoc(); 2540 2541 // Check to see if we can do this. 2542 // FIXME: We should be more aggressive here. 2543 if (!isTypeLegal(VT)) 2544 return SDValue(); 2545 2546 // FIXME: We should use a narrower constant when the upper 2547 // bits are known to be zero. 2548 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2549 APInt::mu magics = N1C->getAPIntValue().magicu(); 2550 2551 // Multiply the numerator (operand 0) by the magic value 2552 // FIXME: We should support doing a MUL in a wider type 2553 SDValue Q; 2554 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2555 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2556 DAG.getConstant(magics.m, VT)); 2557 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2558 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2559 N->getOperand(0), 2560 DAG.getConstant(magics.m, VT)).getNode(), 1); 2561 else 2562 return SDValue(); // No mulhu or equvialent 2563 if (Created) 2564 Created->push_back(Q.getNode()); 2565 2566 if (magics.a == 0) { 2567 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2568 "We shouldn't generate an undefined shift!"); 2569 return DAG.getNode(ISD::SRL, dl, VT, Q, 2570 DAG.getConstant(magics.s, getShiftAmountTy())); 2571 } else { 2572 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2573 if (Created) 2574 Created->push_back(NPQ.getNode()); 2575 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2576 DAG.getConstant(1, getShiftAmountTy())); 2577 if (Created) 2578 Created->push_back(NPQ.getNode()); 2579 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2580 if (Created) 2581 Created->push_back(NPQ.getNode()); 2582 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2583 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2584 } 2585} 2586 2587/// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET 2588/// node that don't prevent tail call optimization. 2589static SDValue IgnoreHarmlessInstructions(SDValue node) { 2590 // Found call return. 2591 if (node.getOpcode() == ISD::CALL) return node; 2592 // Ignore MERGE_VALUES. Will have at least one operand. 2593 if (node.getOpcode() == ISD::MERGE_VALUES) 2594 return IgnoreHarmlessInstructions(node.getOperand(0)); 2595 // Ignore ANY_EXTEND node. 2596 if (node.getOpcode() == ISD::ANY_EXTEND) 2597 return IgnoreHarmlessInstructions(node.getOperand(0)); 2598 if (node.getOpcode() == ISD::TRUNCATE) 2599 return IgnoreHarmlessInstructions(node.getOperand(0)); 2600 // Any other node type. 2601 return node; 2602} 2603 2604bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall, 2605 SDValue Ret) { 2606 unsigned NumOps = Ret.getNumOperands(); 2607 // ISD::CALL results:(value0, ..., valuen, chain) 2608 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn) 2609 // Value return: 2610 // Check that operand of the RET node sources from the CALL node. The RET node 2611 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the 2612 // value. 2613 // Also we need to check that there is no code in between the call and the 2614 // return. Hence we also check that the incomming chain to the return sources 2615 // from the outgoing chain of the call. 2616 if (NumOps > 1 && 2617 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0) && 2618 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2619 return true; 2620 // void return: The RET node has the chain result value of the CALL node as 2621 // input. 2622 if (NumOps == 1 && 2623 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2624 return true; 2625 2626 return false; 2627} 2628