TargetLowering.cpp revision d2f340b746e54fca27b654fd6740973fdf6b85f1
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetData.h" 16#include "llvm/Target/TargetMachine.h" 17#include "llvm/Target/MRegisterInfo.h" 18#include "llvm/DerivedTypes.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/Support/MathExtras.h" 22using namespace llvm; 23 24/// InitLibcallNames - Set default libcall names. 25/// 26static void InitLibcallNames(const char **Names) { 27 Names[RTLIB::SHL_I32] = "__ashlsi3"; 28 Names[RTLIB::SHL_I64] = "__ashldi3"; 29 Names[RTLIB::SRL_I32] = "__lshrsi3"; 30 Names[RTLIB::SRL_I64] = "__lshrdi3"; 31 Names[RTLIB::SRA_I32] = "__ashrsi3"; 32 Names[RTLIB::SRA_I64] = "__ashrdi3"; 33 Names[RTLIB::MUL_I32] = "__mulsi3"; 34 Names[RTLIB::MUL_I64] = "__muldi3"; 35 Names[RTLIB::SDIV_I32] = "__divsi3"; 36 Names[RTLIB::SDIV_I64] = "__divdi3"; 37 Names[RTLIB::UDIV_I32] = "__udivsi3"; 38 Names[RTLIB::UDIV_I64] = "__udivdi3"; 39 Names[RTLIB::SREM_I32] = "__modsi3"; 40 Names[RTLIB::SREM_I64] = "__moddi3"; 41 Names[RTLIB::UREM_I32] = "__umodsi3"; 42 Names[RTLIB::UREM_I64] = "__umoddi3"; 43 Names[RTLIB::NEG_I32] = "__negsi2"; 44 Names[RTLIB::NEG_I64] = "__negdi2"; 45 Names[RTLIB::ADD_F32] = "__addsf3"; 46 Names[RTLIB::ADD_F64] = "__adddf3"; 47 Names[RTLIB::SUB_F32] = "__subsf3"; 48 Names[RTLIB::SUB_F64] = "__subdf3"; 49 Names[RTLIB::MUL_F32] = "__mulsf3"; 50 Names[RTLIB::MUL_F64] = "__muldf3"; 51 Names[RTLIB::DIV_F32] = "__divsf3"; 52 Names[RTLIB::DIV_F64] = "__divdf3"; 53 Names[RTLIB::REM_F32] = "fmodf"; 54 Names[RTLIB::REM_F64] = "fmod"; 55 Names[RTLIB::NEG_F32] = "__negsf2"; 56 Names[RTLIB::NEG_F64] = "__negdf2"; 57 Names[RTLIB::POWI_F32] = "__powisf2"; 58 Names[RTLIB::POWI_F64] = "__powidf2"; 59 Names[RTLIB::SQRT_F32] = "sqrtf"; 60 Names[RTLIB::SQRT_F64] = "sqrt"; 61 Names[RTLIB::SIN_F32] = "sinf"; 62 Names[RTLIB::SIN_F64] = "sin"; 63 Names[RTLIB::COS_F32] = "cosf"; 64 Names[RTLIB::COS_F64] = "cos"; 65 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 66 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 67 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 68 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 69 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 70 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 71 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 72 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 73 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 74 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 75 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 76 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 77 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 78 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 79 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 80 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 81 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 82 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 83 Names[RTLIB::OEQ_F32] = "__eqsf2"; 84 Names[RTLIB::OEQ_F64] = "__eqdf2"; 85 Names[RTLIB::UNE_F32] = "__nesf2"; 86 Names[RTLIB::UNE_F64] = "__nedf2"; 87 Names[RTLIB::OGE_F32] = "__gesf2"; 88 Names[RTLIB::OGE_F64] = "__gedf2"; 89 Names[RTLIB::OLT_F32] = "__ltsf2"; 90 Names[RTLIB::OLT_F64] = "__ltdf2"; 91 Names[RTLIB::OLE_F32] = "__lesf2"; 92 Names[RTLIB::OLE_F64] = "__ledf2"; 93 Names[RTLIB::OGT_F32] = "__gtsf2"; 94 Names[RTLIB::OGT_F64] = "__gtdf2"; 95 Names[RTLIB::UO_F32] = "__unordsf2"; 96 Names[RTLIB::UO_F64] = "__unorddf2"; 97 Names[RTLIB::O_F32] = "__unordsf2"; 98 Names[RTLIB::O_F64] = "__unorddf2"; 99} 100 101/// InitCmpLibcallCCs - Set default comparison libcall CC. 102/// 103static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 104 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 105 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 106 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 107 CCs[RTLIB::UNE_F32] = ISD::SETNE; 108 CCs[RTLIB::UNE_F64] = ISD::SETNE; 109 CCs[RTLIB::OGE_F32] = ISD::SETGE; 110 CCs[RTLIB::OGE_F64] = ISD::SETGE; 111 CCs[RTLIB::OLT_F32] = ISD::SETLT; 112 CCs[RTLIB::OLT_F64] = ISD::SETLT; 113 CCs[RTLIB::OLE_F32] = ISD::SETLE; 114 CCs[RTLIB::OLE_F64] = ISD::SETLE; 115 CCs[RTLIB::OGT_F32] = ISD::SETGT; 116 CCs[RTLIB::OGT_F64] = ISD::SETGT; 117 CCs[RTLIB::UO_F32] = ISD::SETNE; 118 CCs[RTLIB::UO_F64] = ISD::SETNE; 119 CCs[RTLIB::O_F32] = ISD::SETEQ; 120 CCs[RTLIB::O_F64] = ISD::SETEQ; 121} 122 123TargetLowering::TargetLowering(TargetMachine &tm) 124 : TM(tm), TD(TM.getTargetData()) { 125 assert(ISD::BUILTIN_OP_END <= 156 && 126 "Fixed size array in TargetLowering is not large enough!"); 127 // All operations default to being supported. 128 memset(OpActions, 0, sizeof(OpActions)); 129 memset(LoadXActions, 0, sizeof(LoadXActions)); 130 memset(&StoreXActions, 0, sizeof(StoreXActions)); 131 // Initialize all indexed load / store to expand. 132 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 133 for (unsigned IM = (unsigned)ISD::PRE_INC; 134 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 135 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand); 136 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand); 137 } 138 } 139 140 IsLittleEndian = TD->isLittleEndian(); 141 UsesGlobalOffsetTable = false; 142 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType()); 143 ShiftAmtHandling = Undefined; 144 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 145 memset(TargetDAGCombineArray, 0, 146 sizeof(TargetDAGCombineArray)/sizeof(TargetDAGCombineArray[0])); 147 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 148 allowUnalignedMemoryAccesses = false; 149 UseUnderscoreSetJmp = false; 150 UseUnderscoreLongJmp = false; 151 SelectIsExpensive = false; 152 IntDivIsCheap = false; 153 Pow2DivIsCheap = false; 154 StackPointerRegisterToSaveRestore = 0; 155 ExceptionPointerRegister = 0; 156 ExceptionSelectorRegister = 0; 157 SchedPreferenceInfo = SchedulingForLatency; 158 JumpBufSize = 0; 159 JumpBufAlignment = 0; 160 161 InitLibcallNames(LibcallRoutineNames); 162 InitCmpLibcallCCs(CmpLibcallCCs); 163} 164 165TargetLowering::~TargetLowering() {} 166 167/// setValueTypeAction - Set the action for a particular value type. This 168/// assumes an action has not already been set for this value type. 169static void SetValueTypeAction(MVT::ValueType VT, 170 TargetLowering::LegalizeAction Action, 171 TargetLowering &TLI, 172 MVT::ValueType *TransformToType, 173 TargetLowering::ValueTypeActionImpl &ValueTypeActions) { 174 ValueTypeActions.setTypeAction(VT, Action); 175 if (Action == TargetLowering::Promote) { 176 MVT::ValueType PromoteTo; 177 if (VT == MVT::f32) 178 PromoteTo = MVT::f64; 179 else { 180 unsigned LargerReg = VT+1; 181 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) { 182 ++LargerReg; 183 assert(MVT::isInteger((MVT::ValueType)LargerReg) && 184 "Nothing to promote to??"); 185 } 186 PromoteTo = (MVT::ValueType)LargerReg; 187 } 188 189 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) && 190 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) && 191 "Can only promote from int->int or fp->fp!"); 192 assert(VT < PromoteTo && "Must promote to a larger type!"); 193 TransformToType[VT] = PromoteTo; 194 } else if (Action == TargetLowering::Expand) { 195 // f32 and f64 is each expanded to corresponding integer type of same size. 196 if (VT == MVT::f32) 197 TransformToType[VT] = MVT::i32; 198 else if (VT == MVT::f64) 199 TransformToType[VT] = MVT::i64; 200 else { 201 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 && 202 "Cannot expand this type: target must support SOME integer reg!"); 203 // Expand to the next smaller integer type! 204 TransformToType[VT] = (MVT::ValueType)(VT-1); 205 } 206 } 207} 208 209 210/// computeRegisterProperties - Once all of the register classes are added, 211/// this allows us to compute derived properties we expose. 212void TargetLowering::computeRegisterProperties() { 213 assert(MVT::LAST_VALUETYPE <= 32 && 214 "Too many value types for ValueTypeActions to hold!"); 215 216 // Everything defaults to one. 217 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) 218 NumElementsForVT[i] = 1; 219 220 // Find the largest integer register class. 221 unsigned LargestIntReg = MVT::i128; 222 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 223 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 224 225 // Every integer value type larger than this largest register takes twice as 226 // many registers to represent as the previous ValueType. 227 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg; 228 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg) 229 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1]; 230 231 // Inspect all of the ValueType's possible, deciding how to process them. 232 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg) 233 // If we are expanding this type, expand it! 234 if (getNumElements((MVT::ValueType)IntReg) != 1) 235 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType, 236 ValueTypeActions); 237 else if (!isTypeLegal((MVT::ValueType)IntReg)) 238 // Otherwise, if we don't have native support, we must promote to a 239 // larger type. 240 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this, 241 TransformToType, ValueTypeActions); 242 else 243 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg; 244 245 // If the target does not have native F64 support, expand it to I64. We will 246 // be generating soft float library calls. If the target does not have native 247 // support for F32, promote it to F64 if it is legal. Otherwise, expand it to 248 // I32. 249 if (isTypeLegal(MVT::f64)) 250 TransformToType[MVT::f64] = MVT::f64; 251 else { 252 NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64]; 253 SetValueTypeAction(MVT::f64, Expand, *this, TransformToType, 254 ValueTypeActions); 255 } 256 if (isTypeLegal(MVT::f32)) 257 TransformToType[MVT::f32] = MVT::f32; 258 else if (isTypeLegal(MVT::f64)) 259 SetValueTypeAction(MVT::f32, Promote, *this, TransformToType, 260 ValueTypeActions); 261 else { 262 NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32]; 263 SetValueTypeAction(MVT::f32, Expand, *this, TransformToType, 264 ValueTypeActions); 265 } 266 267 // Set MVT::Vector to always be Expanded 268 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType, 269 ValueTypeActions); 270 271 // Loop over all of the legal vector value types, specifying an identity type 272 // transformation. 273 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 274 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) { 275 if (isTypeLegal((MVT::ValueType)i)) 276 TransformToType[i] = (MVT::ValueType)i; 277 } 278} 279 280const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 281 return NULL; 282} 283 284/// getVectorTypeBreakdown - Packed types are broken down into some number of 285/// legal first class types. For example, <8 x float> maps to 2 MVT::v4f32 286/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 287/// 288/// This method returns the number and type of the resultant breakdown. 289/// 290unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy, 291 MVT::ValueType &PTyElementVT, 292 MVT::ValueType &PTyLegalElementVT) const { 293 // Figure out the right, legal destination reg to copy into. 294 unsigned NumElts = PTy->getNumElements(); 295 MVT::ValueType EltTy = getValueType(PTy->getElementType()); 296 297 unsigned NumVectorRegs = 1; 298 299 // Divide the input until we get to a supported size. This will always 300 // end with a scalar if the target doesn't support vectors. 301 while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) { 302 NumElts >>= 1; 303 NumVectorRegs <<= 1; 304 } 305 306 MVT::ValueType VT; 307 if (NumElts == 1) { 308 VT = EltTy; 309 } else { 310 VT = getVectorType(EltTy, NumElts); 311 } 312 PTyElementVT = VT; 313 314 MVT::ValueType DestVT = getTypeToTransformTo(VT); 315 PTyLegalElementVT = DestVT; 316 if (DestVT < VT) { 317 // Value is expanded, e.g. i64 -> i16. 318 return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT)); 319 } else { 320 // Otherwise, promotion or legal types use the same number of registers as 321 // the vector decimated to the appropriate level. 322 return NumVectorRegs; 323 } 324 325 return 1; 326} 327 328//===----------------------------------------------------------------------===// 329// Optimization Methods 330//===----------------------------------------------------------------------===// 331 332/// ShrinkDemandedConstant - Check to see if the specified operand of the 333/// specified instruction is a constant integer. If so, check to see if there 334/// are any bits set in the constant that are not demanded. If so, shrink the 335/// constant and return true. 336bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, 337 uint64_t Demanded) { 338 // FIXME: ISD::SELECT, ISD::SELECT_CC 339 switch(Op.getOpcode()) { 340 default: break; 341 case ISD::AND: 342 case ISD::OR: 343 case ISD::XOR: 344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 345 if ((~Demanded & C->getValue()) != 0) { 346 MVT::ValueType VT = Op.getValueType(); 347 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 348 DAG.getConstant(Demanded & C->getValue(), 349 VT)); 350 return CombineTo(Op, New); 351 } 352 break; 353 } 354 return false; 355} 356 357/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 358/// DemandedMask bits of the result of Op are ever used downstream. If we can 359/// use this information to simplify Op, create a new simplified DAG node and 360/// return true, returning the original and new nodes in Old and New. Otherwise, 361/// analyze the expression and return a mask of KnownOne and KnownZero bits for 362/// the expression (used to simplify the caller). The KnownZero/One bits may 363/// only be accurate for those bits in the DemandedMask. 364bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, 365 uint64_t &KnownZero, 366 uint64_t &KnownOne, 367 TargetLoweringOpt &TLO, 368 unsigned Depth) const { 369 KnownZero = KnownOne = 0; // Don't know anything. 370 // Other users may use these bits. 371 if (!Op.Val->hasOneUse()) { 372 if (Depth != 0) { 373 // If not at the root, Just compute the KnownZero/KnownOne bits to 374 // simplify things downstream. 375 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 376 return false; 377 } 378 // If this is the root being simplified, allow it to have multiple uses, 379 // just set the DemandedMask to all bits. 380 DemandedMask = MVT::getIntVTBitMask(Op.getValueType()); 381 } else if (DemandedMask == 0) { 382 // Not demanding any bits from Op. 383 if (Op.getOpcode() != ISD::UNDEF) 384 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 385 return false; 386 } else if (Depth == 6) { // Limit search depth. 387 return false; 388 } 389 390 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 391 switch (Op.getOpcode()) { 392 case ISD::Constant: 393 // We know all of the bits for a constant! 394 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask; 395 KnownZero = ~KnownOne & DemandedMask; 396 return false; // Don't fall through, will infinitely loop. 397 case ISD::AND: 398 // If the RHS is a constant, check to see if the LHS would be zero without 399 // using the bits from the RHS. Below, we use knowledge about the RHS to 400 // simplify the LHS, here we're using information from the LHS to simplify 401 // the RHS. 402 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 403 uint64_t LHSZero, LHSOne; 404 ComputeMaskedBits(Op.getOperand(0), DemandedMask, 405 LHSZero, LHSOne, Depth+1); 406 // If the LHS already has zeros where RHSC does, this and is dead. 407 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask)) 408 return TLO.CombineTo(Op, Op.getOperand(0)); 409 // If any of the set bits in the RHS are known zero on the LHS, shrink 410 // the constant. 411 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask)) 412 return true; 413 } 414 415 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 416 KnownOne, TLO, Depth+1)) 417 return true; 418 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 419 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero, 420 KnownZero2, KnownOne2, TLO, Depth+1)) 421 return true; 422 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 423 424 // If all of the demanded bits are known one on one side, return the other. 425 // These bits cannot contribute to the result of the 'and'. 426 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2)) 427 return TLO.CombineTo(Op, Op.getOperand(0)); 428 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero)) 429 return TLO.CombineTo(Op, Op.getOperand(1)); 430 // If all of the demanded bits in the inputs are known zeros, return zero. 431 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask) 432 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 433 // If the RHS is a constant, see if we can simplify it. 434 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2)) 435 return true; 436 437 // Output known-1 bits are only known if set in both the LHS & RHS. 438 KnownOne &= KnownOne2; 439 // Output known-0 are known to be clear if zero in either the LHS | RHS. 440 KnownZero |= KnownZero2; 441 break; 442 case ISD::OR: 443 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 444 KnownOne, TLO, Depth+1)) 445 return true; 446 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 447 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne, 448 KnownZero2, KnownOne2, TLO, Depth+1)) 449 return true; 450 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 451 452 // If all of the demanded bits are known zero on one side, return the other. 453 // These bits cannot contribute to the result of the 'or'. 454 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2)) 455 return TLO.CombineTo(Op, Op.getOperand(0)); 456 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne)) 457 return TLO.CombineTo(Op, Op.getOperand(1)); 458 // If all of the potentially set bits on one side are known to be set on 459 // the other side, just use the 'other' side. 460 if ((DemandedMask & (~KnownZero) & KnownOne2) == 461 (DemandedMask & (~KnownZero))) 462 return TLO.CombineTo(Op, Op.getOperand(0)); 463 if ((DemandedMask & (~KnownZero2) & KnownOne) == 464 (DemandedMask & (~KnownZero2))) 465 return TLO.CombineTo(Op, Op.getOperand(1)); 466 // If the RHS is a constant, see if we can simplify it. 467 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 468 return true; 469 470 // Output known-0 bits are only known if clear in both the LHS & RHS. 471 KnownZero &= KnownZero2; 472 // Output known-1 are known to be set if set in either the LHS | RHS. 473 KnownOne |= KnownOne2; 474 break; 475 case ISD::XOR: 476 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero, 477 KnownOne, TLO, Depth+1)) 478 return true; 479 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 480 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2, 481 KnownOne2, TLO, Depth+1)) 482 return true; 483 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 484 485 // If all of the demanded bits are known zero on one side, return the other. 486 // These bits cannot contribute to the result of the 'xor'. 487 if ((DemandedMask & KnownZero) == DemandedMask) 488 return TLO.CombineTo(Op, Op.getOperand(0)); 489 if ((DemandedMask & KnownZero2) == DemandedMask) 490 return TLO.CombineTo(Op, Op.getOperand(1)); 491 492 // If all of the unknown bits are known to be zero on one side or the other 493 // (but not both) turn this into an *inclusive* or. 494 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 495 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) 496 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 497 Op.getOperand(0), 498 Op.getOperand(1))); 499 500 // Output known-0 bits are known if clear or set in both the LHS & RHS. 501 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 502 // Output known-1 are known to be set if set in only one of the LHS, RHS. 503 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 504 505 // If all of the demanded bits on one side are known, and all of the set 506 // bits on that side are also known to be set on the other side, turn this 507 // into an AND, as we know the bits will be cleared. 508 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 509 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known 510 if ((KnownOne & KnownOne2) == KnownOne) { 511 MVT::ValueType VT = Op.getValueType(); 512 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT); 513 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 514 ANDC)); 515 } 516 } 517 518 // If the RHS is a constant, see if we can simplify it. 519 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 520 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 521 return true; 522 523 KnownZero = KnownZeroOut; 524 KnownOne = KnownOneOut; 525 break; 526 case ISD::SETCC: 527 // If we know the result of a setcc has the top bits zero, use this info. 528 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 529 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 530 break; 531 case ISD::SELECT: 532 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero, 533 KnownOne, TLO, Depth+1)) 534 return true; 535 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2, 536 KnownOne2, TLO, Depth+1)) 537 return true; 538 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 539 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 540 541 // If the operands are constants, see if we can simplify them. 542 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 543 return true; 544 545 // Only known if known in both the LHS and RHS. 546 KnownOne &= KnownOne2; 547 KnownZero &= KnownZero2; 548 break; 549 case ISD::SELECT_CC: 550 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero, 551 KnownOne, TLO, Depth+1)) 552 return true; 553 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2, 554 KnownOne2, TLO, Depth+1)) 555 return true; 556 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 557 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 558 559 // If the operands are constants, see if we can simplify them. 560 if (TLO.ShrinkDemandedConstant(Op, DemandedMask)) 561 return true; 562 563 // Only known if known in both the LHS and RHS. 564 KnownOne &= KnownOne2; 565 KnownZero &= KnownZero2; 566 break; 567 case ISD::SHL: 568 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 569 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(), 570 KnownZero, KnownOne, TLO, Depth+1)) 571 return true; 572 KnownZero <<= SA->getValue(); 573 KnownOne <<= SA->getValue(); 574 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 575 } 576 break; 577 case ISD::SRL: 578 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 579 MVT::ValueType VT = Op.getValueType(); 580 unsigned ShAmt = SA->getValue(); 581 582 // Compute the new bits that are at the top now. 583 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 584 if (SimplifyDemandedBits(Op.getOperand(0), 585 (DemandedMask << ShAmt) & TypeMask, 586 KnownZero, KnownOne, TLO, Depth+1)) 587 return true; 588 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 589 KnownZero &= TypeMask; 590 KnownOne &= TypeMask; 591 KnownZero >>= ShAmt; 592 KnownOne >>= ShAmt; 593 594 uint64_t HighBits = (1ULL << ShAmt)-1; 595 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 596 KnownZero |= HighBits; // High bits known zero. 597 } 598 break; 599 case ISD::SRA: 600 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 601 MVT::ValueType VT = Op.getValueType(); 602 unsigned ShAmt = SA->getValue(); 603 604 // Compute the new bits that are at the top now. 605 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 606 607 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask; 608 609 // If any of the demanded bits are produced by the sign extension, we also 610 // demand the input sign bit. 611 uint64_t HighBits = (1ULL << ShAmt)-1; 612 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 613 if (HighBits & DemandedMask) 614 InDemandedMask |= MVT::getIntVTSignBit(VT); 615 616 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 617 KnownZero, KnownOne, TLO, Depth+1)) 618 return true; 619 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 620 KnownZero &= TypeMask; 621 KnownOne &= TypeMask; 622 KnownZero >>= ShAmt; 623 KnownOne >>= ShAmt; 624 625 // Handle the sign bits. 626 uint64_t SignBit = MVT::getIntVTSignBit(VT); 627 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 628 629 // If the input sign bit is known to be zero, or if none of the top bits 630 // are demanded, turn this into an unsigned shift right. 631 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) { 632 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 633 Op.getOperand(1))); 634 } else if (KnownOne & SignBit) { // New bits are known one. 635 KnownOne |= HighBits; 636 } 637 } 638 break; 639 case ISD::SIGN_EXTEND_INREG: { 640 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 641 642 // Sign extension. Compute the demanded bits in the result that are not 643 // present in the input. 644 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask; 645 646 // If none of the extended bits are demanded, eliminate the sextinreg. 647 if (NewBits == 0) 648 return TLO.CombineTo(Op, Op.getOperand(0)); 649 650 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 651 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT); 652 653 // Since the sign extended bits are demanded, we know that the sign 654 // bit is demanded. 655 InputDemandedBits |= InSignBit; 656 657 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 658 KnownZero, KnownOne, TLO, Depth+1)) 659 return true; 660 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 661 662 // If the sign bit of the input is known set or clear, then we know the 663 // top bits of the result. 664 665 // If the input sign bit is known zero, convert this into a zero extension. 666 if (KnownZero & InSignBit) 667 return TLO.CombineTo(Op, 668 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 669 670 if (KnownOne & InSignBit) { // Input sign bit known set 671 KnownOne |= NewBits; 672 KnownZero &= ~NewBits; 673 } else { // Input sign bit unknown 674 KnownZero &= ~NewBits; 675 KnownOne &= ~NewBits; 676 } 677 break; 678 } 679 case ISD::CTTZ: 680 case ISD::CTLZ: 681 case ISD::CTPOP: { 682 MVT::ValueType VT = Op.getValueType(); 683 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 684 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 685 KnownOne = 0; 686 break; 687 } 688 case ISD::LOAD: { 689 if (ISD::isZEXTLoad(Op.Val)) { 690 LoadSDNode *LD = cast<LoadSDNode>(Op); 691 MVT::ValueType VT = LD->getLoadedVT(); 692 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; 693 } 694 break; 695 } 696 case ISD::ZERO_EXTEND: { 697 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 698 699 // If none of the top bits are demanded, convert this into an any_extend. 700 uint64_t NewBits = (~InMask) & DemandedMask; 701 if (NewBits == 0) 702 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 703 Op.getValueType(), 704 Op.getOperand(0))); 705 706 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 707 KnownZero, KnownOne, TLO, Depth+1)) 708 return true; 709 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 710 KnownZero |= NewBits; 711 break; 712 } 713 case ISD::SIGN_EXTEND: { 714 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 715 uint64_t InMask = MVT::getIntVTBitMask(InVT); 716 uint64_t InSignBit = MVT::getIntVTSignBit(InVT); 717 uint64_t NewBits = (~InMask) & DemandedMask; 718 719 // If none of the top bits are demanded, convert this into an any_extend. 720 if (NewBits == 0) 721 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 722 Op.getOperand(0))); 723 724 // Since some of the sign extended bits are demanded, we know that the sign 725 // bit is demanded. 726 uint64_t InDemandedBits = DemandedMask & InMask; 727 InDemandedBits |= InSignBit; 728 729 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 730 KnownOne, TLO, Depth+1)) 731 return true; 732 733 // If the sign bit is known zero, convert this to a zero extend. 734 if (KnownZero & InSignBit) 735 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 736 Op.getValueType(), 737 Op.getOperand(0))); 738 739 // If the sign bit is known one, the top bits match. 740 if (KnownOne & InSignBit) { 741 KnownOne |= NewBits; 742 KnownZero &= ~NewBits; 743 } else { // Otherwise, top bits aren't known. 744 KnownOne &= ~NewBits; 745 KnownZero &= ~NewBits; 746 } 747 break; 748 } 749 case ISD::ANY_EXTEND: { 750 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 751 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 752 KnownZero, KnownOne, TLO, Depth+1)) 753 return true; 754 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 755 break; 756 } 757 case ISD::TRUNCATE: { 758 // Simplify the input, using demanded bit information, and compute the known 759 // zero/one bits live out. 760 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, 761 KnownZero, KnownOne, TLO, Depth+1)) 762 return true; 763 764 // If the input is only used by this truncate, see if we can shrink it based 765 // on the known demanded bits. 766 if (Op.getOperand(0).Val->hasOneUse()) { 767 SDOperand In = Op.getOperand(0); 768 switch (In.getOpcode()) { 769 default: break; 770 case ISD::SRL: 771 // Shrink SRL by a constant if none of the high bits shifted in are 772 // demanded. 773 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 774 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType()); 775 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType()); 776 HighBits >>= ShAmt->getValue(); 777 778 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) && 779 (DemandedMask & HighBits) == 0) { 780 // None of the shifted in bits are needed. Add a truncate of the 781 // shift input, then shift it. 782 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 783 Op.getValueType(), 784 In.getOperand(0)); 785 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 786 NewTrunc, In.getOperand(1))); 787 } 788 } 789 break; 790 } 791 } 792 793 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 794 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 795 KnownZero &= OutMask; 796 KnownOne &= OutMask; 797 break; 798 } 799 case ISD::AssertZext: { 800 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 801 uint64_t InMask = MVT::getIntVTBitMask(VT); 802 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask, 803 KnownZero, KnownOne, TLO, Depth+1)) 804 return true; 805 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 806 KnownZero |= ~InMask & DemandedMask; 807 break; 808 } 809 case ISD::ADD: 810 case ISD::SUB: 811 case ISD::INTRINSIC_WO_CHAIN: 812 case ISD::INTRINSIC_W_CHAIN: 813 case ISD::INTRINSIC_VOID: 814 // Just use ComputeMaskedBits to compute output bits. 815 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 816 break; 817 } 818 819 // If we know the value of all of the demanded bits, return this as a 820 // constant. 821 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) 822 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 823 824 return false; 825} 826 827/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 828/// this predicate to simplify operations downstream. Mask is known to be zero 829/// for bits that V cannot have. 830bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask, 831 unsigned Depth) const { 832 uint64_t KnownZero, KnownOne; 833 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 834 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 835 return (KnownZero & Mask) == Mask; 836} 837 838/// ComputeMaskedBits - Determine which of the bits specified in Mask are 839/// known to be either zero or one and return them in the KnownZero/KnownOne 840/// bitsets. This code only analyzes bits in Mask, in order to short-circuit 841/// processing. 842void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, 843 uint64_t &KnownZero, uint64_t &KnownOne, 844 unsigned Depth) const { 845 KnownZero = KnownOne = 0; // Don't know anything. 846 if (Depth == 6 || Mask == 0) 847 return; // Limit search depth. 848 849 uint64_t KnownZero2, KnownOne2; 850 851 switch (Op.getOpcode()) { 852 case ISD::Constant: 853 // We know all of the bits for a constant! 854 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask; 855 KnownZero = ~KnownOne & Mask; 856 return; 857 case ISD::AND: 858 // If either the LHS or the RHS are Zero, the result is zero. 859 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 860 Mask &= ~KnownZero; 861 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 862 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 863 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 864 865 // Output known-1 bits are only known if set in both the LHS & RHS. 866 KnownOne &= KnownOne2; 867 // Output known-0 are known to be clear if zero in either the LHS | RHS. 868 KnownZero |= KnownZero2; 869 return; 870 case ISD::OR: 871 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 872 Mask &= ~KnownOne; 873 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 874 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 875 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 876 877 // Output known-0 bits are only known if clear in both the LHS & RHS. 878 KnownZero &= KnownZero2; 879 // Output known-1 are known to be set if set in either the LHS | RHS. 880 KnownOne |= KnownOne2; 881 return; 882 case ISD::XOR: { 883 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 884 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 885 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 886 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 887 888 // Output known-0 bits are known if clear or set in both the LHS & RHS. 889 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 890 // Output known-1 are known to be set if set in only one of the LHS, RHS. 891 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 892 KnownZero = KnownZeroOut; 893 return; 894 } 895 case ISD::SELECT: 896 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1); 897 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1); 898 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 899 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 900 901 // Only known if known in both the LHS and RHS. 902 KnownOne &= KnownOne2; 903 KnownZero &= KnownZero2; 904 return; 905 case ISD::SELECT_CC: 906 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1); 907 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1); 908 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 909 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 910 911 // Only known if known in both the LHS and RHS. 912 KnownOne &= KnownOne2; 913 KnownZero &= KnownZero2; 914 return; 915 case ISD::SETCC: 916 // If we know the result of a setcc has the top bits zero, use this info. 917 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) 918 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL); 919 return; 920 case ISD::SHL: 921 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 922 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 923 ComputeMaskedBits(Op.getOperand(0), Mask >> SA->getValue(), 924 KnownZero, KnownOne, Depth+1); 925 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 926 KnownZero <<= SA->getValue(); 927 KnownOne <<= SA->getValue(); 928 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero. 929 } 930 return; 931 case ISD::SRL: 932 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0 933 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 934 MVT::ValueType VT = Op.getValueType(); 935 unsigned ShAmt = SA->getValue(); 936 937 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 938 ComputeMaskedBits(Op.getOperand(0), (Mask << ShAmt) & TypeMask, 939 KnownZero, KnownOne, Depth+1); 940 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 941 KnownZero &= TypeMask; 942 KnownOne &= TypeMask; 943 KnownZero >>= ShAmt; 944 KnownOne >>= ShAmt; 945 946 uint64_t HighBits = (1ULL << ShAmt)-1; 947 HighBits <<= MVT::getSizeInBits(VT)-ShAmt; 948 KnownZero |= HighBits; // High bits known zero. 949 } 950 return; 951 case ISD::SRA: 952 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 953 MVT::ValueType VT = Op.getValueType(); 954 unsigned ShAmt = SA->getValue(); 955 956 // Compute the new bits that are at the top now. 957 uint64_t TypeMask = MVT::getIntVTBitMask(VT); 958 959 uint64_t InDemandedMask = (Mask << ShAmt) & TypeMask; 960 // If any of the demanded bits are produced by the sign extension, we also 961 // demand the input sign bit. 962 uint64_t HighBits = (1ULL << ShAmt)-1; 963 HighBits <<= MVT::getSizeInBits(VT) - ShAmt; 964 if (HighBits & Mask) 965 InDemandedMask |= MVT::getIntVTSignBit(VT); 966 967 ComputeMaskedBits(Op.getOperand(0), InDemandedMask, KnownZero, KnownOne, 968 Depth+1); 969 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 970 KnownZero &= TypeMask; 971 KnownOne &= TypeMask; 972 KnownZero >>= ShAmt; 973 KnownOne >>= ShAmt; 974 975 // Handle the sign bits. 976 uint64_t SignBit = MVT::getIntVTSignBit(VT); 977 SignBit >>= ShAmt; // Adjust to where it is now in the mask. 978 979 if (KnownZero & SignBit) { 980 KnownZero |= HighBits; // New bits are known zero. 981 } else if (KnownOne & SignBit) { 982 KnownOne |= HighBits; // New bits are known one. 983 } 984 } 985 return; 986 case ISD::SIGN_EXTEND_INREG: { 987 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 988 989 // Sign extension. Compute the demanded bits in the result that are not 990 // present in the input. 991 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & Mask; 992 993 uint64_t InSignBit = MVT::getIntVTSignBit(EVT); 994 int64_t InputDemandedBits = Mask & MVT::getIntVTBitMask(EVT); 995 996 // If the sign extended bits are demanded, we know that the sign 997 // bit is demanded. 998 if (NewBits) 999 InputDemandedBits |= InSignBit; 1000 1001 ComputeMaskedBits(Op.getOperand(0), InputDemandedBits, 1002 KnownZero, KnownOne, Depth+1); 1003 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1004 1005 // If the sign bit of the input is known set or clear, then we know the 1006 // top bits of the result. 1007 if (KnownZero & InSignBit) { // Input sign bit known clear 1008 KnownZero |= NewBits; 1009 KnownOne &= ~NewBits; 1010 } else if (KnownOne & InSignBit) { // Input sign bit known set 1011 KnownOne |= NewBits; 1012 KnownZero &= ~NewBits; 1013 } else { // Input sign bit unknown 1014 KnownZero &= ~NewBits; 1015 KnownOne &= ~NewBits; 1016 } 1017 return; 1018 } 1019 case ISD::CTTZ: 1020 case ISD::CTLZ: 1021 case ISD::CTPOP: { 1022 MVT::ValueType VT = Op.getValueType(); 1023 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1; 1024 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT); 1025 KnownOne = 0; 1026 return; 1027 } 1028 case ISD::LOAD: { 1029 if (ISD::isZEXTLoad(Op.Val)) { 1030 LoadSDNode *LD = cast<LoadSDNode>(Op); 1031 MVT::ValueType VT = LD->getLoadedVT(); 1032 KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; 1033 } 1034 return; 1035 } 1036 case ISD::ZERO_EXTEND: { 1037 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType()); 1038 uint64_t NewBits = (~InMask) & Mask; 1039 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1040 KnownOne, Depth+1); 1041 KnownZero |= NewBits & Mask; 1042 KnownOne &= ~NewBits; 1043 return; 1044 } 1045 case ISD::SIGN_EXTEND: { 1046 MVT::ValueType InVT = Op.getOperand(0).getValueType(); 1047 unsigned InBits = MVT::getSizeInBits(InVT); 1048 uint64_t InMask = MVT::getIntVTBitMask(InVT); 1049 uint64_t InSignBit = 1ULL << (InBits-1); 1050 uint64_t NewBits = (~InMask) & Mask; 1051 uint64_t InDemandedBits = Mask & InMask; 1052 1053 // If any of the sign extended bits are demanded, we know that the sign 1054 // bit is demanded. 1055 if (NewBits & Mask) 1056 InDemandedBits |= InSignBit; 1057 1058 ComputeMaskedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1059 KnownOne, Depth+1); 1060 // If the sign bit is known zero or one, the top bits match. 1061 if (KnownZero & InSignBit) { 1062 KnownZero |= NewBits; 1063 KnownOne &= ~NewBits; 1064 } else if (KnownOne & InSignBit) { 1065 KnownOne |= NewBits; 1066 KnownZero &= ~NewBits; 1067 } else { // Otherwise, top bits aren't known. 1068 KnownOne &= ~NewBits; 1069 KnownZero &= ~NewBits; 1070 } 1071 return; 1072 } 1073 case ISD::ANY_EXTEND: { 1074 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1075 ComputeMaskedBits(Op.getOperand(0), Mask & MVT::getIntVTBitMask(VT), 1076 KnownZero, KnownOne, Depth+1); 1077 return; 1078 } 1079 case ISD::TRUNCATE: { 1080 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1081 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1082 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType()); 1083 KnownZero &= OutMask; 1084 KnownOne &= OutMask; 1085 break; 1086 } 1087 case ISD::AssertZext: { 1088 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1089 uint64_t InMask = MVT::getIntVTBitMask(VT); 1090 ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, 1091 KnownOne, Depth+1); 1092 KnownZero |= (~InMask) & Mask; 1093 return; 1094 } 1095 case ISD::ADD: { 1096 // If either the LHS or the RHS are Zero, the result is zero. 1097 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1098 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 1099 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1100 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1101 1102 // Output known-0 bits are known if clear or set in both the low clear bits 1103 // common to both LHS & RHS. For example, 8+(X<<3) is known to have the 1104 // low 3 bits clear. 1105 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero), 1106 CountTrailingZeros_64(~KnownZero2)); 1107 1108 KnownZero = (1ULL << KnownZeroOut) - 1; 1109 KnownOne = 0; 1110 return; 1111 } 1112 case ISD::SUB: { 1113 ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1114 if (!CLHS) return; 1115 1116 // We know that the top bits of C-X are clear if X contains less bits 1117 // than C (i.e. no wrap-around can happen). For example, 20-X is 1118 // positive if we can prove that X is >= 0 and < 16. 1119 MVT::ValueType VT = CLHS->getValueType(0); 1120 if ((CLHS->getValue() & MVT::getIntVTSignBit(VT)) == 0) { // sign bit clear 1121 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 1122 uint64_t MaskV = (1ULL << (63-NLZ))-1; // NLZ can't be 64 with no sign bit 1123 MaskV = ~MaskV & MVT::getIntVTBitMask(VT); 1124 ComputeMaskedBits(Op.getOperand(1), MaskV, KnownZero, KnownOne, Depth+1); 1125 1126 // If all of the MaskV bits are known to be zero, then we know the output 1127 // top bits are zero, because we now know that the output is from [0-C]. 1128 if ((KnownZero & MaskV) == MaskV) { 1129 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 1130 KnownZero = ~((1ULL << (64-NLZ2))-1) & Mask; // Top bits known zero. 1131 KnownOne = 0; // No one bits known. 1132 } else { 1133 KnownZero = KnownOne = 0; // Otherwise, nothing known. 1134 } 1135 } 1136 return; 1137 } 1138 default: 1139 // Allow the target to implement this method for its nodes. 1140 if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { 1141 case ISD::INTRINSIC_WO_CHAIN: 1142 case ISD::INTRINSIC_W_CHAIN: 1143 case ISD::INTRINSIC_VOID: 1144 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne); 1145 } 1146 return; 1147 } 1148} 1149 1150/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1151/// in Mask are known to be either zero or one and return them in the 1152/// KnownZero/KnownOne bitsets. 1153void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1154 uint64_t Mask, 1155 uint64_t &KnownZero, 1156 uint64_t &KnownOne, 1157 unsigned Depth) const { 1158 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1159 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1160 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1161 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1162 "Should use MaskedValueIsZero if you don't know whether Op" 1163 " is a target node!"); 1164 KnownZero = 0; 1165 KnownOne = 0; 1166} 1167 1168/// ComputeNumSignBits - Return the number of times the sign bit of the 1169/// register is replicated into the other bits. We know that at least 1 bit 1170/// is always equal to the sign bit (itself), but other cases can give us 1171/// information. For example, immediately after an "SRA X, 2", we know that 1172/// the top 3 bits are all equal to each other, so we return 3. 1173unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ 1174 MVT::ValueType VT = Op.getValueType(); 1175 assert(MVT::isInteger(VT) && "Invalid VT!"); 1176 unsigned VTBits = MVT::getSizeInBits(VT); 1177 unsigned Tmp, Tmp2; 1178 1179 if (Depth == 6) 1180 return 1; // Limit search depth. 1181 1182 switch (Op.getOpcode()) { 1183 default: break; 1184 case ISD::AssertSext: 1185 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1186 return VTBits-Tmp+1; 1187 case ISD::AssertZext: 1188 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1189 return VTBits-Tmp; 1190 1191 case ISD::Constant: { 1192 uint64_t Val = cast<ConstantSDNode>(Op)->getValue(); 1193 // If negative, invert the bits, then look at it. 1194 if (Val & MVT::getIntVTSignBit(VT)) 1195 Val = ~Val; 1196 1197 // Shift the bits so they are the leading bits in the int64_t. 1198 Val <<= 64-VTBits; 1199 1200 // Return # leading zeros. We use 'min' here in case Val was zero before 1201 // shifting. We don't want to return '64' as for an i32 "0". 1202 return std::min(VTBits, CountLeadingZeros_64(Val)); 1203 } 1204 1205 case ISD::SIGN_EXTEND: 1206 Tmp = VTBits-MVT::getSizeInBits(Op.getOperand(0).getValueType()); 1207 return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp; 1208 1209 case ISD::SIGN_EXTEND_INREG: 1210 // Max of the input and what this extends. 1211 Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 1212 Tmp = VTBits-Tmp+1; 1213 1214 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1215 return std::max(Tmp, Tmp2); 1216 1217 case ISD::SRA: 1218 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1219 // SRA X, C -> adds C sign bits. 1220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1221 Tmp += C->getValue(); 1222 if (Tmp > VTBits) Tmp = VTBits; 1223 } 1224 return Tmp; 1225 case ISD::SHL: 1226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1227 // shl destroys sign bits. 1228 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1229 if (C->getValue() >= VTBits || // Bad shift. 1230 C->getValue() >= Tmp) break; // Shifted all sign bits out. 1231 return Tmp - C->getValue(); 1232 } 1233 break; 1234 case ISD::AND: 1235 case ISD::OR: 1236 case ISD::XOR: // NOT is handled here. 1237 // Logical binary ops preserve the number of sign bits. 1238 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1239 if (Tmp == 1) return 1; // Early out. 1240 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1241 return std::min(Tmp, Tmp2); 1242 1243 case ISD::SELECT: 1244 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1245 if (Tmp == 1) return 1; // Early out. 1246 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1247 return std::min(Tmp, Tmp2); 1248 1249 case ISD::SETCC: 1250 // If setcc returns 0/-1, all bits are sign bits. 1251 if (getSetCCResultContents() == ZeroOrNegativeOneSetCCResult) 1252 return VTBits; 1253 break; 1254 case ISD::ROTL: 1255 case ISD::ROTR: 1256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1257 unsigned RotAmt = C->getValue() & (VTBits-1); 1258 1259 // Handle rotate right by N like a rotate left by 32-N. 1260 if (Op.getOpcode() == ISD::ROTR) 1261 RotAmt = (VTBits-RotAmt) & (VTBits-1); 1262 1263 // If we aren't rotating out all of the known-in sign bits, return the 1264 // number that are left. This handles rotl(sext(x), 1) for example. 1265 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1266 if (Tmp > RotAmt+1) return Tmp-RotAmt; 1267 } 1268 break; 1269 case ISD::ADD: 1270 // Add can have at most one carry bit. Thus we know that the output 1271 // is, at worst, one more bit than the inputs. 1272 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1273 if (Tmp == 1) return 1; // Early out. 1274 1275 // Special case decrementing a value (ADD X, -1): 1276 if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1277 if (CRHS->isAllOnesValue()) { 1278 uint64_t KnownZero, KnownOne; 1279 uint64_t Mask = MVT::getIntVTBitMask(VT); 1280 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1281 1282 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1283 // sign bits set. 1284 if ((KnownZero|1) == Mask) 1285 return VTBits; 1286 1287 // If we are subtracting one from a positive number, there is no carry 1288 // out of the result. 1289 if (KnownZero & MVT::getIntVTSignBit(VT)) 1290 return Tmp; 1291 } 1292 1293 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1294 if (Tmp2 == 1) return 1; 1295 return std::min(Tmp, Tmp2)-1; 1296 break; 1297 1298 case ISD::SUB: 1299 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 1300 if (Tmp2 == 1) return 1; 1301 1302 // Handle NEG. 1303 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) 1304 if (CLHS->getValue() == 0) { 1305 uint64_t KnownZero, KnownOne; 1306 uint64_t Mask = MVT::getIntVTBitMask(VT); 1307 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 1308 // If the input is known to be 0 or 1, the output is 0/-1, which is all 1309 // sign bits set. 1310 if ((KnownZero|1) == Mask) 1311 return VTBits; 1312 1313 // If the input is known to be positive (the sign bit is known clear), 1314 // the output of the NEG has the same number of sign bits as the input. 1315 if (KnownZero & MVT::getIntVTSignBit(VT)) 1316 return Tmp2; 1317 1318 // Otherwise, we treat this like a SUB. 1319 } 1320 1321 // Sub can have at most one carry bit. Thus we know that the output 1322 // is, at worst, one more bit than the inputs. 1323 Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1); 1324 if (Tmp == 1) return 1; // Early out. 1325 return std::min(Tmp, Tmp2)-1; 1326 break; 1327 case ISD::TRUNCATE: 1328 // FIXME: it's tricky to do anything useful for this, but it is an important 1329 // case for targets like X86. 1330 break; 1331 } 1332 1333 // Handle LOADX separately here. EXTLOAD case will fallthrough. 1334 if (Op.getOpcode() == ISD::LOAD) { 1335 LoadSDNode *LD = cast<LoadSDNode>(Op); 1336 unsigned ExtType = LD->getExtensionType(); 1337 switch (ExtType) { 1338 default: break; 1339 case ISD::SEXTLOAD: // '17' bits known 1340 Tmp = MVT::getSizeInBits(LD->getLoadedVT()); 1341 return VTBits-Tmp+1; 1342 case ISD::ZEXTLOAD: // '16' bits known 1343 Tmp = MVT::getSizeInBits(LD->getLoadedVT()); 1344 return VTBits-Tmp; 1345 } 1346 } 1347 1348 // Allow the target to implement this method for its nodes. 1349 if (Op.getOpcode() >= ISD::BUILTIN_OP_END || 1350 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1351 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1352 Op.getOpcode() == ISD::INTRINSIC_VOID) { 1353 unsigned NumBits = ComputeNumSignBitsForTargetNode(Op, Depth); 1354 if (NumBits > 1) return NumBits; 1355 } 1356 1357 // Finally, if we can prove that the top bits of the result are 0's or 1's, 1358 // use this information. 1359 uint64_t KnownZero, KnownOne; 1360 uint64_t Mask = MVT::getIntVTBitMask(VT); 1361 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth); 1362 1363 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1364 if (KnownZero & SignBit) { // SignBit is 0 1365 Mask = KnownZero; 1366 } else if (KnownOne & SignBit) { // SignBit is 1; 1367 Mask = KnownOne; 1368 } else { 1369 // Nothing known. 1370 return 1; 1371 } 1372 1373 // Okay, we know that the sign bit in Mask is set. Use CLZ to determine 1374 // the number of identical bits in the top of the input value. 1375 Mask ^= ~0ULL; 1376 Mask <<= 64-VTBits; 1377 // Return # leading zeros. We use 'min' here in case Val was zero before 1378 // shifting. We don't want to return '64' as for an i32 "0". 1379 return std::min(VTBits, CountLeadingZeros_64(Mask)); 1380} 1381 1382 1383 1384/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1385/// targets that want to expose additional information about sign bits to the 1386/// DAG Combiner. 1387unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, 1388 unsigned Depth) const { 1389 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1390 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1391 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1392 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1393 "Should use ComputeNumSignBits if you don't know whether Op" 1394 " is a target node!"); 1395 return 1; 1396} 1397 1398 1399/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1400/// and cc. If it is unable to simplify it, return a null SDOperand. 1401SDOperand 1402TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 1403 ISD::CondCode Cond, bool foldBooleans, 1404 DAGCombinerInfo &DCI) const { 1405 SelectionDAG &DAG = DCI.DAG; 1406 1407 // These setcc operations always fold. 1408 switch (Cond) { 1409 default: break; 1410 case ISD::SETFALSE: 1411 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1412 case ISD::SETTRUE: 1413 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1414 } 1415 1416 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1417 uint64_t C1 = N1C->getValue(); 1418 if (isa<ConstantSDNode>(N0.Val)) { 1419 return DAG.FoldSetCC(VT, N0, N1, Cond); 1420 } else { 1421 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1422 // equality comparison, then we're just comparing whether X itself is 1423 // zero. 1424 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1425 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1426 N0.getOperand(1).getOpcode() == ISD::Constant) { 1427 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1428 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1429 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) { 1430 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1431 // (srl (ctlz x), 5) == 0 -> X != 0 1432 // (srl (ctlz x), 5) != 1 -> X != 0 1433 Cond = ISD::SETNE; 1434 } else { 1435 // (srl (ctlz x), 5) != 0 -> X == 0 1436 // (srl (ctlz x), 5) == 1 -> X == 0 1437 Cond = ISD::SETEQ; 1438 } 1439 SDOperand Zero = DAG.getConstant(0, N0.getValueType()); 1440 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1441 Zero, Cond); 1442 } 1443 } 1444 1445 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1446 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1447 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1448 1449 // If the comparison constant has bits in the upper part, the 1450 // zero-extended value could never match. 1451 if (C1 & (~0ULL << InSize)) { 1452 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1453 switch (Cond) { 1454 case ISD::SETUGT: 1455 case ISD::SETUGE: 1456 case ISD::SETEQ: return DAG.getConstant(0, VT); 1457 case ISD::SETULT: 1458 case ISD::SETULE: 1459 case ISD::SETNE: return DAG.getConstant(1, VT); 1460 case ISD::SETGT: 1461 case ISD::SETGE: 1462 // True if the sign bit of C1 is set. 1463 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT); 1464 case ISD::SETLT: 1465 case ISD::SETLE: 1466 // True if the sign bit of C1 isn't set. 1467 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT); 1468 default: 1469 break; 1470 } 1471 } 1472 1473 // Otherwise, we can perform the comparison with the low bits. 1474 switch (Cond) { 1475 case ISD::SETEQ: 1476 case ISD::SETNE: 1477 case ISD::SETUGT: 1478 case ISD::SETUGE: 1479 case ISD::SETULT: 1480 case ISD::SETULE: 1481 return DAG.getSetCC(VT, N0.getOperand(0), 1482 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1483 Cond); 1484 default: 1485 break; // todo, be more careful with signed comparisons 1486 } 1487 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1488 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1489 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1490 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1491 MVT::ValueType ExtDstTy = N0.getValueType(); 1492 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1493 1494 // If the extended part has any inconsistent bits, it cannot ever 1495 // compare equal. In other words, they have to be all ones or all 1496 // zeros. 1497 uint64_t ExtBits = 1498 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1499 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1500 return DAG.getConstant(Cond == ISD::SETNE, VT); 1501 1502 SDOperand ZextOp; 1503 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1504 if (Op0Ty == ExtSrcTy) { 1505 ZextOp = N0.getOperand(0); 1506 } else { 1507 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1508 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1509 DAG.getConstant(Imm, Op0Ty)); 1510 } 1511 if (!DCI.isCalledByLegalizer()) 1512 DCI.AddToWorklist(ZextOp.Val); 1513 // Otherwise, make this a use of a zext. 1514 return DAG.getSetCC(VT, ZextOp, 1515 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1516 ExtDstTy), 1517 Cond); 1518 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 1519 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1520 1521 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1522 if (N0.getOpcode() == ISD::SETCC) { 1523 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1524 if (TrueWhenTrue) 1525 return N0; 1526 1527 // Invert the condition. 1528 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1529 CC = ISD::getSetCCInverse(CC, 1530 MVT::isInteger(N0.getOperand(0).getValueType())); 1531 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1532 } 1533 1534 if ((N0.getOpcode() == ISD::XOR || 1535 (N0.getOpcode() == ISD::AND && 1536 N0.getOperand(0).getOpcode() == ISD::XOR && 1537 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1538 isa<ConstantSDNode>(N0.getOperand(1)) && 1539 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 1540 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1541 // can only do this if the top bits are known zero. 1542 if (MaskedValueIsZero(N0, MVT::getIntVTBitMask(N0.getValueType())-1)){ 1543 // Okay, get the un-inverted input value. 1544 SDOperand Val; 1545 if (N0.getOpcode() == ISD::XOR) 1546 Val = N0.getOperand(0); 1547 else { 1548 assert(N0.getOpcode() == ISD::AND && 1549 N0.getOperand(0).getOpcode() == ISD::XOR); 1550 // ((X^1)&1)^1 -> X & 1 1551 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1552 N0.getOperand(0).getOperand(0), 1553 N0.getOperand(1)); 1554 } 1555 return DAG.getSetCC(VT, Val, N1, 1556 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1557 } 1558 } 1559 } 1560 1561 uint64_t MinVal, MaxVal; 1562 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1563 if (ISD::isSignedIntSetCC(Cond)) { 1564 MinVal = 1ULL << (OperandBitSize-1); 1565 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1566 MaxVal = ~0ULL >> (65-OperandBitSize); 1567 else 1568 MaxVal = 0; 1569 } else { 1570 MinVal = 0; 1571 MaxVal = ~0ULL >> (64-OperandBitSize); 1572 } 1573 1574 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1575 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1576 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1577 --C1; // X >= C0 --> X > (C0-1) 1578 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1579 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1580 } 1581 1582 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1583 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1584 ++C1; // X <= C0 --> X < (C0+1) 1585 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1586 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1587 } 1588 1589 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1590 return DAG.getConstant(0, VT); // X < MIN --> false 1591 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1592 return DAG.getConstant(1, VT); // X >= MIN --> true 1593 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1594 return DAG.getConstant(0, VT); // X > MAX --> false 1595 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1596 return DAG.getConstant(1, VT); // X <= MAX --> true 1597 1598 // Canonicalize setgt X, Min --> setne X, Min 1599 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1600 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1601 // Canonicalize setlt X, Max --> setne X, Max 1602 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1603 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1604 1605 // If we have setult X, 1, turn it into seteq X, 0 1606 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1607 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1608 ISD::SETEQ); 1609 // If we have setugt X, Max-1, turn it into seteq X, Max 1610 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1611 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1612 ISD::SETEQ); 1613 1614 // If we have "setcc X, C0", check to see if we can shrink the immediate 1615 // by changing cc. 1616 1617 // SETUGT X, SINTMAX -> SETLT X, 0 1618 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1619 C1 == (~0ULL >> (65-OperandBitSize))) 1620 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1621 ISD::SETLT); 1622 1623 // FIXME: Implement the rest of these. 1624 1625 // Fold bit comparisons when we can. 1626 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1627 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1628 if (ConstantSDNode *AndRHS = 1629 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1630 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1631 // Perform the xform if the AND RHS is a single bit. 1632 if (isPowerOf2_64(AndRHS->getValue())) { 1633 return DAG.getNode(ISD::SRL, VT, N0, 1634 DAG.getConstant(Log2_64(AndRHS->getValue()), 1635 getShiftAmountTy())); 1636 } 1637 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1638 // (X & 8) == 8 --> (X & 8) >> 3 1639 // Perform the xform if C1 is a single bit. 1640 if (isPowerOf2_64(C1)) { 1641 return DAG.getNode(ISD::SRL, VT, N0, 1642 DAG.getConstant(Log2_64(C1), getShiftAmountTy())); 1643 } 1644 } 1645 } 1646 } 1647 } else if (isa<ConstantSDNode>(N0.Val)) { 1648 // Ensure that the constant occurs on the RHS. 1649 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1650 } 1651 1652 if (isa<ConstantFPSDNode>(N0.Val)) { 1653 // Constant fold or commute setcc. 1654 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); 1655 if (O.Val) return O; 1656 } 1657 1658 if (N0 == N1) { 1659 // We can always fold X == X for integer setcc's. 1660 if (MVT::isInteger(N0.getValueType())) 1661 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1662 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1663 if (UOF == 2) // FP operators that are undefined on NaNs. 1664 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1665 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1666 return DAG.getConstant(UOF, VT); 1667 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1668 // if it is not already. 1669 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1670 if (NewCond != Cond) 1671 return DAG.getSetCC(VT, N0, N1, NewCond); 1672 } 1673 1674 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1675 MVT::isInteger(N0.getValueType())) { 1676 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1677 N0.getOpcode() == ISD::XOR) { 1678 // Simplify (X+Y) == (X+Z) --> Y == Z 1679 if (N0.getOpcode() == N1.getOpcode()) { 1680 if (N0.getOperand(0) == N1.getOperand(0)) 1681 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1682 if (N0.getOperand(1) == N1.getOperand(1)) 1683 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1684 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1685 // If X op Y == Y op X, try other combinations. 1686 if (N0.getOperand(0) == N1.getOperand(1)) 1687 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1688 if (N0.getOperand(1) == N1.getOperand(0)) 1689 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1690 } 1691 } 1692 1693 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1694 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1695 // Turn (X+C1) == C2 --> X == C2-C1 1696 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1697 return DAG.getSetCC(VT, N0.getOperand(0), 1698 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1699 N0.getValueType()), Cond); 1700 } 1701 1702 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1703 if (N0.getOpcode() == ISD::XOR) 1704 // If we know that all of the inverted bits are zero, don't bother 1705 // performing the inversion. 1706 if (MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 1707 return DAG.getSetCC(VT, N0.getOperand(0), 1708 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 1709 N0.getValueType()), Cond); 1710 } 1711 1712 // Turn (C1-X) == C2 --> X == C1-C2 1713 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1714 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1715 return DAG.getSetCC(VT, N0.getOperand(1), 1716 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 1717 N0.getValueType()), Cond); 1718 } 1719 } 1720 } 1721 1722 // Simplify (X+Z) == X --> Z == 0 1723 if (N0.getOperand(0) == N1) 1724 return DAG.getSetCC(VT, N0.getOperand(1), 1725 DAG.getConstant(0, N0.getValueType()), Cond); 1726 if (N0.getOperand(1) == N1) { 1727 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1728 return DAG.getSetCC(VT, N0.getOperand(0), 1729 DAG.getConstant(0, N0.getValueType()), Cond); 1730 else { 1731 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1732 // (Z-X) == X --> Z == X<<1 1733 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1734 N1, 1735 DAG.getConstant(1, getShiftAmountTy())); 1736 if (!DCI.isCalledByLegalizer()) 1737 DCI.AddToWorklist(SH.Val); 1738 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1739 } 1740 } 1741 } 1742 1743 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1744 N1.getOpcode() == ISD::XOR) { 1745 // Simplify X == (X+Z) --> Z == 0 1746 if (N1.getOperand(0) == N0) { 1747 return DAG.getSetCC(VT, N1.getOperand(1), 1748 DAG.getConstant(0, N1.getValueType()), Cond); 1749 } else if (N1.getOperand(1) == N0) { 1750 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1751 return DAG.getSetCC(VT, N1.getOperand(0), 1752 DAG.getConstant(0, N1.getValueType()), Cond); 1753 } else { 1754 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1755 // X == (Z-X) --> X<<1 == Z 1756 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1757 DAG.getConstant(1, getShiftAmountTy())); 1758 if (!DCI.isCalledByLegalizer()) 1759 DCI.AddToWorklist(SH.Val); 1760 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1761 } 1762 } 1763 } 1764 } 1765 1766 // Fold away ALL boolean setcc's. 1767 SDOperand Temp; 1768 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1769 switch (Cond) { 1770 default: assert(0 && "Unknown integer setcc!"); 1771 case ISD::SETEQ: // X == Y -> (X^Y)^1 1772 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1773 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1774 if (!DCI.isCalledByLegalizer()) 1775 DCI.AddToWorklist(Temp.Val); 1776 break; 1777 case ISD::SETNE: // X != Y --> (X^Y) 1778 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1779 break; 1780 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1781 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1782 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1783 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1784 if (!DCI.isCalledByLegalizer()) 1785 DCI.AddToWorklist(Temp.Val); 1786 break; 1787 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1788 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1789 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1790 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1791 if (!DCI.isCalledByLegalizer()) 1792 DCI.AddToWorklist(Temp.Val); 1793 break; 1794 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1795 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1796 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1797 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1798 if (!DCI.isCalledByLegalizer()) 1799 DCI.AddToWorklist(Temp.Val); 1800 break; 1801 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1802 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1803 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1804 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1805 break; 1806 } 1807 if (VT != MVT::i1) { 1808 if (!DCI.isCalledByLegalizer()) 1809 DCI.AddToWorklist(N0.Val); 1810 // FIXME: If running after legalize, we probably can't do this. 1811 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1812 } 1813 return N0; 1814 } 1815 1816 // Could not fold it. 1817 return SDOperand(); 1818} 1819 1820SDOperand TargetLowering:: 1821PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1822 // Default implementation: no optimization. 1823 return SDOperand(); 1824} 1825 1826//===----------------------------------------------------------------------===// 1827// Inline Assembler Implementation Methods 1828//===----------------------------------------------------------------------===// 1829 1830TargetLowering::ConstraintType 1831TargetLowering::getConstraintType(const std::string &Constraint) const { 1832 // FIXME: lots more standard ones to handle. 1833 if (Constraint.size() == 1) { 1834 switch (Constraint[0]) { 1835 default: break; 1836 case 'r': return C_RegisterClass; 1837 case 'm': // memory 1838 case 'o': // offsetable 1839 case 'V': // not offsetable 1840 return C_Memory; 1841 case 'i': // Simple Integer or Relocatable Constant 1842 case 'n': // Simple Integer 1843 case 's': // Relocatable Constant 1844 case 'X': // Allow ANY value. 1845 case 'I': // Target registers. 1846 case 'J': 1847 case 'K': 1848 case 'L': 1849 case 'M': 1850 case 'N': 1851 case 'O': 1852 case 'P': 1853 return C_Other; 1854 } 1855 } 1856 1857 if (Constraint.size() > 1 && Constraint[0] == '{' && 1858 Constraint[Constraint.size()-1] == '}') 1859 return C_Register; 1860 return C_Unknown; 1861} 1862 1863/// isOperandValidForConstraint - Return the specified operand (possibly 1864/// modified) if the specified SDOperand is valid for the specified target 1865/// constraint letter, otherwise return null. 1866SDOperand TargetLowering::isOperandValidForConstraint(SDOperand Op, 1867 char ConstraintLetter, 1868 SelectionDAG &DAG) { 1869 switch (ConstraintLetter) { 1870 default: break; 1871 case 'i': // Simple Integer or Relocatable Constant 1872 case 'n': // Simple Integer 1873 case 's': // Relocatable Constant 1874 case 'X': // Allows any operand. 1875 // These are okay if the operand is either a global variable address or a 1876 // simple immediate value. If we have one of these, map to the TargetXXX 1877 // version so that the value itself doesn't get selected. 1878 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 1879 // Simple constants are not allowed for 's'. 1880 if (ConstraintLetter != 's') 1881 return DAG.getTargetConstant(C->getValue(), Op.getValueType()); 1882 } 1883 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { 1884 if (ConstraintLetter != 'n') 1885 return DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(), 1886 GA->getOffset()); 1887 } 1888 break; 1889 } 1890 return SDOperand(0,0); 1891} 1892 1893std::vector<unsigned> TargetLowering:: 1894getRegClassForInlineAsmConstraint(const std::string &Constraint, 1895 MVT::ValueType VT) const { 1896 return std::vector<unsigned>(); 1897} 1898 1899 1900std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1901getRegForInlineAsmConstraint(const std::string &Constraint, 1902 MVT::ValueType VT) const { 1903 if (Constraint[0] != '{') 1904 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1905 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1906 1907 // Remove the braces from around the name. 1908 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1909 1910 // Figure out which register class contains this reg. 1911 const MRegisterInfo *RI = TM.getRegisterInfo(); 1912 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1913 E = RI->regclass_end(); RCI != E; ++RCI) { 1914 const TargetRegisterClass *RC = *RCI; 1915 1916 // If none of the the value types for this register class are valid, we 1917 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1918 bool isLegal = false; 1919 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1920 I != E; ++I) { 1921 if (isTypeLegal(*I)) { 1922 isLegal = true; 1923 break; 1924 } 1925 } 1926 1927 if (!isLegal) continue; 1928 1929 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1930 I != E; ++I) { 1931 if (StringsEqualNoCase(RegName, RI->get(*I).Name)) 1932 return std::make_pair(*I, RC); 1933 } 1934 } 1935 1936 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1937} 1938 1939//===----------------------------------------------------------------------===// 1940// Loop Strength Reduction hooks 1941//===----------------------------------------------------------------------===// 1942 1943/// isLegalAddressingMode - Return true if the addressing mode represented 1944/// by AM is legal for this target, for a load/store of the specified type. 1945bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 1946 const Type *Ty) const { 1947 // The default implementation of this implements a conservative RISCy, r+r and 1948 // r+i addr mode. 1949 1950 // Allows a sign-extended 16-bit immediate field. 1951 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1952 return false; 1953 1954 // No global is ever allowed as a base. 1955 if (AM.BaseGV) 1956 return false; 1957 1958 // Only support r+r, 1959 switch (AM.Scale) { 1960 case 0: // "r+i" or just "i", depending on HasBaseReg. 1961 break; 1962 case 1: 1963 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1964 return false; 1965 // Otherwise we have r+r or r+i. 1966 break; 1967 case 2: 1968 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1969 return false; 1970 // Allow 2*r as r+r. 1971 break; 1972 } 1973 1974 return true; 1975} 1976 1977/// isLegalAddressImmediate - Return true if the integer value can be used as 1978/// the offset of the target addressing mode for load / store of the given 1979/// type. 1980bool TargetLowering::isLegalAddressImmediate(int64_t V, const Type *Ty) const { 1981 return false; 1982} 1983 1984/// isLegalAddressImmediate - Return true if the GlobalValue can be used as 1985/// the offset of the target addressing mode. 1986bool TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { 1987 return false; 1988} 1989 1990/// isLegalAddressScale - Return true if the integer value can be used as the 1991/// scale of the target addressing mode for load / store of the given type. 1992bool TargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const { 1993 return false; 1994} 1995 1996/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale 1997/// and V works for isLegalAddressImmediate _and_ both can be applied 1998/// simultaneously to the same instruction. 1999bool TargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V, 2000 const Type* Ty) const { 2001 return false; 2002} 2003 2004/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale 2005/// and GV works for isLegalAddressImmediate _and_ both can be applied 2006/// simultaneously to the same instruction. 2007bool TargetLowering::isLegalAddressScaleAndImm(int64_t S, GlobalValue *GV, 2008 const Type* Ty) const { 2009 2010 return false; 2011} 2012 2013// Magic for divide replacement 2014 2015struct ms { 2016 int64_t m; // magic number 2017 int64_t s; // shift amount 2018}; 2019 2020struct mu { 2021 uint64_t m; // magic number 2022 int64_t a; // add indicator 2023 int64_t s; // shift amount 2024}; 2025 2026/// magic - calculate the magic numbers required to codegen an integer sdiv as 2027/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2028/// or -1. 2029static ms magic32(int32_t d) { 2030 int32_t p; 2031 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2032 const uint32_t two31 = 0x80000000U; 2033 struct ms mag; 2034 2035 ad = abs(d); 2036 t = two31 + ((uint32_t)d >> 31); 2037 anc = t - 1 - t%ad; // absolute value of nc 2038 p = 31; // initialize p 2039 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2040 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2041 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2042 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2043 do { 2044 p = p + 1; 2045 q1 = 2*q1; // update q1 = 2p/abs(nc) 2046 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2047 if (r1 >= anc) { // must be unsigned comparison 2048 q1 = q1 + 1; 2049 r1 = r1 - anc; 2050 } 2051 q2 = 2*q2; // update q2 = 2p/abs(d) 2052 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2053 if (r2 >= ad) { // must be unsigned comparison 2054 q2 = q2 + 1; 2055 r2 = r2 - ad; 2056 } 2057 delta = ad - r2; 2058 } while (q1 < delta || (q1 == delta && r1 == 0)); 2059 2060 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2061 if (d < 0) mag.m = -mag.m; // resulting magic number 2062 mag.s = p - 32; // resulting shift 2063 return mag; 2064} 2065 2066/// magicu - calculate the magic numbers required to codegen an integer udiv as 2067/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2068static mu magicu32(uint32_t d) { 2069 int32_t p; 2070 uint32_t nc, delta, q1, r1, q2, r2; 2071 struct mu magu; 2072 magu.a = 0; // initialize "add" indicator 2073 nc = - 1 - (-d)%d; 2074 p = 31; // initialize p 2075 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2076 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2077 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2078 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2079 do { 2080 p = p + 1; 2081 if (r1 >= nc - r1 ) { 2082 q1 = 2*q1 + 1; // update q1 2083 r1 = 2*r1 - nc; // update r1 2084 } 2085 else { 2086 q1 = 2*q1; // update q1 2087 r1 = 2*r1; // update r1 2088 } 2089 if (r2 + 1 >= d - r2) { 2090 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2091 q2 = 2*q2 + 1; // update q2 2092 r2 = 2*r2 + 1 - d; // update r2 2093 } 2094 else { 2095 if (q2 >= 0x80000000) magu.a = 1; 2096 q2 = 2*q2; // update q2 2097 r2 = 2*r2 + 1; // update r2 2098 } 2099 delta = d - 1 - r2; 2100 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2101 magu.m = q2 + 1; // resulting magic number 2102 magu.s = p - 32; // resulting shift 2103 return magu; 2104} 2105 2106/// magic - calculate the magic numbers required to codegen an integer sdiv as 2107/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2108/// or -1. 2109static ms magic64(int64_t d) { 2110 int64_t p; 2111 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2112 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2113 struct ms mag; 2114 2115 ad = d >= 0 ? d : -d; 2116 t = two63 + ((uint64_t)d >> 63); 2117 anc = t - 1 - t%ad; // absolute value of nc 2118 p = 63; // initialize p 2119 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2120 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2121 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2122 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2123 do { 2124 p = p + 1; 2125 q1 = 2*q1; // update q1 = 2p/abs(nc) 2126 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2127 if (r1 >= anc) { // must be unsigned comparison 2128 q1 = q1 + 1; 2129 r1 = r1 - anc; 2130 } 2131 q2 = 2*q2; // update q2 = 2p/abs(d) 2132 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2133 if (r2 >= ad) { // must be unsigned comparison 2134 q2 = q2 + 1; 2135 r2 = r2 - ad; 2136 } 2137 delta = ad - r2; 2138 } while (q1 < delta || (q1 == delta && r1 == 0)); 2139 2140 mag.m = q2 + 1; 2141 if (d < 0) mag.m = -mag.m; // resulting magic number 2142 mag.s = p - 64; // resulting shift 2143 return mag; 2144} 2145 2146/// magicu - calculate the magic numbers required to codegen an integer udiv as 2147/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2148static mu magicu64(uint64_t d) 2149{ 2150 int64_t p; 2151 uint64_t nc, delta, q1, r1, q2, r2; 2152 struct mu magu; 2153 magu.a = 0; // initialize "add" indicator 2154 nc = - 1 - (-d)%d; 2155 p = 63; // initialize p 2156 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2157 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2158 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2159 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2160 do { 2161 p = p + 1; 2162 if (r1 >= nc - r1 ) { 2163 q1 = 2*q1 + 1; // update q1 2164 r1 = 2*r1 - nc; // update r1 2165 } 2166 else { 2167 q1 = 2*q1; // update q1 2168 r1 = 2*r1; // update r1 2169 } 2170 if (r2 + 1 >= d - r2) { 2171 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2172 q2 = 2*q2 + 1; // update q2 2173 r2 = 2*r2 + 1 - d; // update r2 2174 } 2175 else { 2176 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2177 q2 = 2*q2; // update q2 2178 r2 = 2*r2 + 1; // update r2 2179 } 2180 delta = d - 1 - r2; 2181 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2182 magu.m = q2 + 1; // resulting magic number 2183 magu.s = p - 64; // resulting shift 2184 return magu; 2185} 2186 2187/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2188/// return a DAG expression to select that will generate the same value by 2189/// multiplying by a magic number. See: 2190/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2191SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2192 std::vector<SDNode*>* Created) const { 2193 MVT::ValueType VT = N->getValueType(0); 2194 2195 // Check to see if we can do this. 2196 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2197 return SDOperand(); // BuildSDIV only operates on i32 or i64 2198 if (!isOperationLegal(ISD::MULHS, VT)) 2199 return SDOperand(); // Make sure the target supports MULHS. 2200 2201 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2202 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2203 2204 // Multiply the numerator (operand 0) by the magic value 2205 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2206 DAG.getConstant(magics.m, VT)); 2207 // If d > 0 and m < 0, add the numerator 2208 if (d > 0 && magics.m < 0) { 2209 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2210 if (Created) 2211 Created->push_back(Q.Val); 2212 } 2213 // If d < 0 and m > 0, subtract the numerator. 2214 if (d < 0 && magics.m > 0) { 2215 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2216 if (Created) 2217 Created->push_back(Q.Val); 2218 } 2219 // Shift right algebraic if shift value is nonzero 2220 if (magics.s > 0) { 2221 Q = DAG.getNode(ISD::SRA, VT, Q, 2222 DAG.getConstant(magics.s, getShiftAmountTy())); 2223 if (Created) 2224 Created->push_back(Q.Val); 2225 } 2226 // Extract the sign bit and add it to the quotient 2227 SDOperand T = 2228 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2229 getShiftAmountTy())); 2230 if (Created) 2231 Created->push_back(T.Val); 2232 return DAG.getNode(ISD::ADD, VT, Q, T); 2233} 2234 2235/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2236/// return a DAG expression to select that will generate the same value by 2237/// multiplying by a magic number. See: 2238/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2239SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2240 std::vector<SDNode*>* Created) const { 2241 MVT::ValueType VT = N->getValueType(0); 2242 2243 // Check to see if we can do this. 2244 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2245 return SDOperand(); // BuildUDIV only operates on i32 or i64 2246 if (!isOperationLegal(ISD::MULHU, VT)) 2247 return SDOperand(); // Make sure the target supports MULHU. 2248 2249 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2250 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2251 2252 // Multiply the numerator (operand 0) by the magic value 2253 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2254 DAG.getConstant(magics.m, VT)); 2255 if (Created) 2256 Created->push_back(Q.Val); 2257 2258 if (magics.a == 0) { 2259 return DAG.getNode(ISD::SRL, VT, Q, 2260 DAG.getConstant(magics.s, getShiftAmountTy())); 2261 } else { 2262 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2263 if (Created) 2264 Created->push_back(NPQ.Val); 2265 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2266 DAG.getConstant(1, getShiftAmountTy())); 2267 if (Created) 2268 Created->push_back(NPQ.Val); 2269 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2270 if (Created) 2271 Created->push_back(NPQ.Val); 2272 return DAG.getNode(ISD::SRL, VT, NPQ, 2273 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2274 } 2275} 2276