TargetLowering.cpp revision dd67159ea024c078f6c9f3c41bc400b1f3f2f6e1
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/ADT/STLExtras.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30using namespace llvm; 31 32namespace llvm { 33TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 34 bool isLocal = GV->hasLocalLinkage(); 35 bool isDeclaration = GV->isDeclaration(); 36 // FIXME: what should we do for protected and internal visibility? 37 // For variables, is internal different from hidden? 38 bool isHidden = GV->hasHiddenVisibility(); 39 40 if (reloc == Reloc::PIC_) { 41 if (isLocal || isHidden) 42 return TLSModel::LocalDynamic; 43 else 44 return TLSModel::GeneralDynamic; 45 } else { 46 if (!isDeclaration || isHidden) 47 return TLSModel::LocalExec; 48 else 49 return TLSModel::InitialExec; 50 } 51} 52} 53 54/// InitLibcallNames - Set default libcall names. 55/// 56static void InitLibcallNames(const char **Names) { 57 Names[RTLIB::SHL_I16] = "__ashlhi3"; 58 Names[RTLIB::SHL_I32] = "__ashlsi3"; 59 Names[RTLIB::SHL_I64] = "__ashldi3"; 60 Names[RTLIB::SHL_I128] = "__ashlti3"; 61 Names[RTLIB::SRL_I16] = "__lshrhi3"; 62 Names[RTLIB::SRL_I32] = "__lshrsi3"; 63 Names[RTLIB::SRL_I64] = "__lshrdi3"; 64 Names[RTLIB::SRL_I128] = "__lshrti3"; 65 Names[RTLIB::SRA_I16] = "__ashrhi3"; 66 Names[RTLIB::SRA_I32] = "__ashrsi3"; 67 Names[RTLIB::SRA_I64] = "__ashrdi3"; 68 Names[RTLIB::SRA_I128] = "__ashrti3"; 69 Names[RTLIB::MUL_I8] = "__mulqi3"; 70 Names[RTLIB::MUL_I16] = "__mulhi3"; 71 Names[RTLIB::MUL_I32] = "__mulsi3"; 72 Names[RTLIB::MUL_I64] = "__muldi3"; 73 Names[RTLIB::MUL_I128] = "__multi3"; 74 Names[RTLIB::SDIV_I8] = "__divqi3"; 75 Names[RTLIB::SDIV_I16] = "__divhi3"; 76 Names[RTLIB::SDIV_I32] = "__divsi3"; 77 Names[RTLIB::SDIV_I64] = "__divdi3"; 78 Names[RTLIB::SDIV_I128] = "__divti3"; 79 Names[RTLIB::UDIV_I8] = "__udivqi3"; 80 Names[RTLIB::UDIV_I16] = "__udivhi3"; 81 Names[RTLIB::UDIV_I32] = "__udivsi3"; 82 Names[RTLIB::UDIV_I64] = "__udivdi3"; 83 Names[RTLIB::UDIV_I128] = "__udivti3"; 84 Names[RTLIB::SREM_I8] = "__modqi3"; 85 Names[RTLIB::SREM_I16] = "__modhi3"; 86 Names[RTLIB::SREM_I32] = "__modsi3"; 87 Names[RTLIB::SREM_I64] = "__moddi3"; 88 Names[RTLIB::SREM_I128] = "__modti3"; 89 Names[RTLIB::UREM_I8] = "__umodqi3"; 90 Names[RTLIB::UREM_I16] = "__umodhi3"; 91 Names[RTLIB::UREM_I32] = "__umodsi3"; 92 Names[RTLIB::UREM_I64] = "__umoddi3"; 93 Names[RTLIB::UREM_I128] = "__umodti3"; 94 Names[RTLIB::NEG_I32] = "__negsi2"; 95 Names[RTLIB::NEG_I64] = "__negdi2"; 96 Names[RTLIB::ADD_F32] = "__addsf3"; 97 Names[RTLIB::ADD_F64] = "__adddf3"; 98 Names[RTLIB::ADD_F80] = "__addxf3"; 99 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 100 Names[RTLIB::SUB_F32] = "__subsf3"; 101 Names[RTLIB::SUB_F64] = "__subdf3"; 102 Names[RTLIB::SUB_F80] = "__subxf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 108 Names[RTLIB::DIV_F32] = "__divsf3"; 109 Names[RTLIB::DIV_F64] = "__divdf3"; 110 Names[RTLIB::DIV_F80] = "__divxf3"; 111 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 112 Names[RTLIB::REM_F32] = "fmodf"; 113 Names[RTLIB::REM_F64] = "fmod"; 114 Names[RTLIB::REM_F80] = "fmodl"; 115 Names[RTLIB::REM_PPCF128] = "fmodl"; 116 Names[RTLIB::POWI_F32] = "__powisf2"; 117 Names[RTLIB::POWI_F64] = "__powidf2"; 118 Names[RTLIB::POWI_F80] = "__powixf2"; 119 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 120 Names[RTLIB::SQRT_F32] = "sqrtf"; 121 Names[RTLIB::SQRT_F64] = "sqrt"; 122 Names[RTLIB::SQRT_F80] = "sqrtl"; 123 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 124 Names[RTLIB::LOG_F32] = "logf"; 125 Names[RTLIB::LOG_F64] = "log"; 126 Names[RTLIB::LOG_F80] = "logl"; 127 Names[RTLIB::LOG_PPCF128] = "logl"; 128 Names[RTLIB::LOG2_F32] = "log2f"; 129 Names[RTLIB::LOG2_F64] = "log2"; 130 Names[RTLIB::LOG2_F80] = "log2l"; 131 Names[RTLIB::LOG2_PPCF128] = "log2l"; 132 Names[RTLIB::LOG10_F32] = "log10f"; 133 Names[RTLIB::LOG10_F64] = "log10"; 134 Names[RTLIB::LOG10_F80] = "log10l"; 135 Names[RTLIB::LOG10_PPCF128] = "log10l"; 136 Names[RTLIB::EXP_F32] = "expf"; 137 Names[RTLIB::EXP_F64] = "exp"; 138 Names[RTLIB::EXP_F80] = "expl"; 139 Names[RTLIB::EXP_PPCF128] = "expl"; 140 Names[RTLIB::EXP2_F32] = "exp2f"; 141 Names[RTLIB::EXP2_F64] = "exp2"; 142 Names[RTLIB::EXP2_F80] = "exp2l"; 143 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 144 Names[RTLIB::SIN_F32] = "sinf"; 145 Names[RTLIB::SIN_F64] = "sin"; 146 Names[RTLIB::SIN_F80] = "sinl"; 147 Names[RTLIB::SIN_PPCF128] = "sinl"; 148 Names[RTLIB::COS_F32] = "cosf"; 149 Names[RTLIB::COS_F64] = "cos"; 150 Names[RTLIB::COS_F80] = "cosl"; 151 Names[RTLIB::COS_PPCF128] = "cosl"; 152 Names[RTLIB::POW_F32] = "powf"; 153 Names[RTLIB::POW_F64] = "pow"; 154 Names[RTLIB::POW_F80] = "powl"; 155 Names[RTLIB::POW_PPCF128] = "powl"; 156 Names[RTLIB::CEIL_F32] = "ceilf"; 157 Names[RTLIB::CEIL_F64] = "ceil"; 158 Names[RTLIB::CEIL_F80] = "ceill"; 159 Names[RTLIB::CEIL_PPCF128] = "ceill"; 160 Names[RTLIB::TRUNC_F32] = "truncf"; 161 Names[RTLIB::TRUNC_F64] = "trunc"; 162 Names[RTLIB::TRUNC_F80] = "truncl"; 163 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 164 Names[RTLIB::RINT_F32] = "rintf"; 165 Names[RTLIB::RINT_F64] = "rint"; 166 Names[RTLIB::RINT_F80] = "rintl"; 167 Names[RTLIB::RINT_PPCF128] = "rintl"; 168 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 169 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 170 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 171 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 172 Names[RTLIB::FLOOR_F32] = "floorf"; 173 Names[RTLIB::FLOOR_F64] = "floor"; 174 Names[RTLIB::FLOOR_F80] = "floorl"; 175 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 176 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 177 Names[RTLIB::COPYSIGN_F64] = "copysign"; 178 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 179 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 180 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 181 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 182 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 183 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 184 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 185 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 186 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 187 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 188 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 189 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 190 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 191 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 192 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 193 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 194 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 195 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 196 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 197 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 198 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 199 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 200 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 201 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 202 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 204 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 205 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 206 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 207 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 208 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 209 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 210 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 211 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 212 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 213 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 214 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 215 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 216 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 217 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 218 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 220 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 221 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 222 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 223 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 224 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 225 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 226 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 227 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 228 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 229 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 230 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 231 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 232 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 233 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 234 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 235 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 236 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 237 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 238 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 239 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 240 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 241 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 242 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 243 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 244 Names[RTLIB::OEQ_F32] = "__eqsf2"; 245 Names[RTLIB::OEQ_F64] = "__eqdf2"; 246 Names[RTLIB::UNE_F32] = "__nesf2"; 247 Names[RTLIB::UNE_F64] = "__nedf2"; 248 Names[RTLIB::OGE_F32] = "__gesf2"; 249 Names[RTLIB::OGE_F64] = "__gedf2"; 250 Names[RTLIB::OLT_F32] = "__ltsf2"; 251 Names[RTLIB::OLT_F64] = "__ltdf2"; 252 Names[RTLIB::OLE_F32] = "__lesf2"; 253 Names[RTLIB::OLE_F64] = "__ledf2"; 254 Names[RTLIB::OGT_F32] = "__gtsf2"; 255 Names[RTLIB::OGT_F64] = "__gtdf2"; 256 Names[RTLIB::UO_F32] = "__unordsf2"; 257 Names[RTLIB::UO_F64] = "__unorddf2"; 258 Names[RTLIB::O_F32] = "__unordsf2"; 259 Names[RTLIB::O_F64] = "__unorddf2"; 260 Names[RTLIB::MEMCPY] = "memcpy"; 261 Names[RTLIB::MEMMOVE] = "memmove"; 262 Names[RTLIB::MEMSET] = "memset"; 263 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 264 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 268 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 272 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 276 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 280 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 284 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 288 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 292 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 296} 297 298/// InitLibcallCallingConvs - Set default libcall CallingConvs. 299/// 300static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 301 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 302 CCs[i] = CallingConv::C; 303 } 304} 305 306/// getFPEXT - Return the FPEXT_*_* value for the given types, or 307/// UNKNOWN_LIBCALL if there is none. 308RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 309 if (OpVT == MVT::f32) { 310 if (RetVT == MVT::f64) 311 return FPEXT_F32_F64; 312 } 313 314 return UNKNOWN_LIBCALL; 315} 316 317/// getFPROUND - Return the FPROUND_*_* value for the given types, or 318/// UNKNOWN_LIBCALL if there is none. 319RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 320 if (RetVT == MVT::f32) { 321 if (OpVT == MVT::f64) 322 return FPROUND_F64_F32; 323 if (OpVT == MVT::f80) 324 return FPROUND_F80_F32; 325 if (OpVT == MVT::ppcf128) 326 return FPROUND_PPCF128_F32; 327 } else if (RetVT == MVT::f64) { 328 if (OpVT == MVT::f80) 329 return FPROUND_F80_F64; 330 if (OpVT == MVT::ppcf128) 331 return FPROUND_PPCF128_F64; 332 } 333 334 return UNKNOWN_LIBCALL; 335} 336 337/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 338/// UNKNOWN_LIBCALL if there is none. 339RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 340 if (OpVT == MVT::f32) { 341 if (RetVT == MVT::i8) 342 return FPTOSINT_F32_I8; 343 if (RetVT == MVT::i16) 344 return FPTOSINT_F32_I16; 345 if (RetVT == MVT::i32) 346 return FPTOSINT_F32_I32; 347 if (RetVT == MVT::i64) 348 return FPTOSINT_F32_I64; 349 if (RetVT == MVT::i128) 350 return FPTOSINT_F32_I128; 351 } else if (OpVT == MVT::f64) { 352 if (RetVT == MVT::i8) 353 return FPTOSINT_F64_I8; 354 if (RetVT == MVT::i16) 355 return FPTOSINT_F64_I16; 356 if (RetVT == MVT::i32) 357 return FPTOSINT_F64_I32; 358 if (RetVT == MVT::i64) 359 return FPTOSINT_F64_I64; 360 if (RetVT == MVT::i128) 361 return FPTOSINT_F64_I128; 362 } else if (OpVT == MVT::f80) { 363 if (RetVT == MVT::i32) 364 return FPTOSINT_F80_I32; 365 if (RetVT == MVT::i64) 366 return FPTOSINT_F80_I64; 367 if (RetVT == MVT::i128) 368 return FPTOSINT_F80_I128; 369 } else if (OpVT == MVT::ppcf128) { 370 if (RetVT == MVT::i32) 371 return FPTOSINT_PPCF128_I32; 372 if (RetVT == MVT::i64) 373 return FPTOSINT_PPCF128_I64; 374 if (RetVT == MVT::i128) 375 return FPTOSINT_PPCF128_I128; 376 } 377 return UNKNOWN_LIBCALL; 378} 379 380/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 381/// UNKNOWN_LIBCALL if there is none. 382RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 383 if (OpVT == MVT::f32) { 384 if (RetVT == MVT::i8) 385 return FPTOUINT_F32_I8; 386 if (RetVT == MVT::i16) 387 return FPTOUINT_F32_I16; 388 if (RetVT == MVT::i32) 389 return FPTOUINT_F32_I32; 390 if (RetVT == MVT::i64) 391 return FPTOUINT_F32_I64; 392 if (RetVT == MVT::i128) 393 return FPTOUINT_F32_I128; 394 } else if (OpVT == MVT::f64) { 395 if (RetVT == MVT::i8) 396 return FPTOUINT_F64_I8; 397 if (RetVT == MVT::i16) 398 return FPTOUINT_F64_I16; 399 if (RetVT == MVT::i32) 400 return FPTOUINT_F64_I32; 401 if (RetVT == MVT::i64) 402 return FPTOUINT_F64_I64; 403 if (RetVT == MVT::i128) 404 return FPTOUINT_F64_I128; 405 } else if (OpVT == MVT::f80) { 406 if (RetVT == MVT::i32) 407 return FPTOUINT_F80_I32; 408 if (RetVT == MVT::i64) 409 return FPTOUINT_F80_I64; 410 if (RetVT == MVT::i128) 411 return FPTOUINT_F80_I128; 412 } else if (OpVT == MVT::ppcf128) { 413 if (RetVT == MVT::i32) 414 return FPTOUINT_PPCF128_I32; 415 if (RetVT == MVT::i64) 416 return FPTOUINT_PPCF128_I64; 417 if (RetVT == MVT::i128) 418 return FPTOUINT_PPCF128_I128; 419 } 420 return UNKNOWN_LIBCALL; 421} 422 423/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 424/// UNKNOWN_LIBCALL if there is none. 425RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 426 if (OpVT == MVT::i32) { 427 if (RetVT == MVT::f32) 428 return SINTTOFP_I32_F32; 429 else if (RetVT == MVT::f64) 430 return SINTTOFP_I32_F64; 431 else if (RetVT == MVT::f80) 432 return SINTTOFP_I32_F80; 433 else if (RetVT == MVT::ppcf128) 434 return SINTTOFP_I32_PPCF128; 435 } else if (OpVT == MVT::i64) { 436 if (RetVT == MVT::f32) 437 return SINTTOFP_I64_F32; 438 else if (RetVT == MVT::f64) 439 return SINTTOFP_I64_F64; 440 else if (RetVT == MVT::f80) 441 return SINTTOFP_I64_F80; 442 else if (RetVT == MVT::ppcf128) 443 return SINTTOFP_I64_PPCF128; 444 } else if (OpVT == MVT::i128) { 445 if (RetVT == MVT::f32) 446 return SINTTOFP_I128_F32; 447 else if (RetVT == MVT::f64) 448 return SINTTOFP_I128_F64; 449 else if (RetVT == MVT::f80) 450 return SINTTOFP_I128_F80; 451 else if (RetVT == MVT::ppcf128) 452 return SINTTOFP_I128_PPCF128; 453 } 454 return UNKNOWN_LIBCALL; 455} 456 457/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 458/// UNKNOWN_LIBCALL if there is none. 459RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 460 if (OpVT == MVT::i32) { 461 if (RetVT == MVT::f32) 462 return UINTTOFP_I32_F32; 463 else if (RetVT == MVT::f64) 464 return UINTTOFP_I32_F64; 465 else if (RetVT == MVT::f80) 466 return UINTTOFP_I32_F80; 467 else if (RetVT == MVT::ppcf128) 468 return UINTTOFP_I32_PPCF128; 469 } else if (OpVT == MVT::i64) { 470 if (RetVT == MVT::f32) 471 return UINTTOFP_I64_F32; 472 else if (RetVT == MVT::f64) 473 return UINTTOFP_I64_F64; 474 else if (RetVT == MVT::f80) 475 return UINTTOFP_I64_F80; 476 else if (RetVT == MVT::ppcf128) 477 return UINTTOFP_I64_PPCF128; 478 } else if (OpVT == MVT::i128) { 479 if (RetVT == MVT::f32) 480 return UINTTOFP_I128_F32; 481 else if (RetVT == MVT::f64) 482 return UINTTOFP_I128_F64; 483 else if (RetVT == MVT::f80) 484 return UINTTOFP_I128_F80; 485 else if (RetVT == MVT::ppcf128) 486 return UINTTOFP_I128_PPCF128; 487 } 488 return UNKNOWN_LIBCALL; 489} 490 491/// InitCmpLibcallCCs - Set default comparison libcall CC. 492/// 493static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 494 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 495 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 496 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 497 CCs[RTLIB::UNE_F32] = ISD::SETNE; 498 CCs[RTLIB::UNE_F64] = ISD::SETNE; 499 CCs[RTLIB::OGE_F32] = ISD::SETGE; 500 CCs[RTLIB::OGE_F64] = ISD::SETGE; 501 CCs[RTLIB::OLT_F32] = ISD::SETLT; 502 CCs[RTLIB::OLT_F64] = ISD::SETLT; 503 CCs[RTLIB::OLE_F32] = ISD::SETLE; 504 CCs[RTLIB::OLE_F64] = ISD::SETLE; 505 CCs[RTLIB::OGT_F32] = ISD::SETGT; 506 CCs[RTLIB::OGT_F64] = ISD::SETGT; 507 CCs[RTLIB::UO_F32] = ISD::SETNE; 508 CCs[RTLIB::UO_F64] = ISD::SETNE; 509 CCs[RTLIB::O_F32] = ISD::SETEQ; 510 CCs[RTLIB::O_F64] = ISD::SETEQ; 511} 512 513/// NOTE: The constructor takes ownership of TLOF. 514TargetLowering::TargetLowering(const TargetMachine &tm, 515 const TargetLoweringObjectFile *tlof) 516 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 517 // All operations default to being supported. 518 memset(OpActions, 0, sizeof(OpActions)); 519 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 520 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 521 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 522 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 523 524 // Set default actions for various operations. 525 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 526 // Default all indexed load / store to expand. 527 for (unsigned IM = (unsigned)ISD::PRE_INC; 528 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 529 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 530 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 531 } 532 533 // These operations default to expand. 534 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 535 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 536 } 537 538 // Most targets ignore the @llvm.prefetch intrinsic. 539 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 540 541 // ConstantFP nodes default to expand. Targets can either change this to 542 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 543 // to optimize expansions for certain constants. 544 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 545 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 547 548 // These library functions default to expand. 549 setOperationAction(ISD::FLOG , MVT::f64, Expand); 550 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 551 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 552 setOperationAction(ISD::FEXP , MVT::f64, Expand); 553 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 554 setOperationAction(ISD::FLOG , MVT::f32, Expand); 555 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 556 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 557 setOperationAction(ISD::FEXP , MVT::f32, Expand); 558 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 559 560 // Default ISD::TRAP to expand (which turns it into abort). 561 setOperationAction(ISD::TRAP, MVT::Other, Expand); 562 563 IsLittleEndian = TD->isLittleEndian(); 564 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 565 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 566 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 567 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 568 benefitFromCodePlacementOpt = false; 569 UseUnderscoreSetJmp = false; 570 UseUnderscoreLongJmp = false; 571 SelectIsExpensive = false; 572 IntDivIsCheap = false; 573 Pow2DivIsCheap = false; 574 StackPointerRegisterToSaveRestore = 0; 575 ExceptionPointerRegister = 0; 576 ExceptionSelectorRegister = 0; 577 BooleanContents = UndefinedBooleanContent; 578 SchedPreferenceInfo = Sched::Latency; 579 JumpBufSize = 0; 580 JumpBufAlignment = 0; 581 IfCvtBlockSizeLimit = 2; 582 IfCvtDupBlockSizeLimit = 0; 583 PrefLoopAlignment = 0; 584 585 InitLibcallNames(LibcallRoutineNames); 586 InitCmpLibcallCCs(CmpLibcallCCs); 587 InitLibcallCallingConvs(LibcallCallingConvs); 588} 589 590TargetLowering::~TargetLowering() { 591 delete &TLOF; 592} 593 594/// canOpTrap - Returns true if the operation can trap for the value type. 595/// VT must be a legal type. 596bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 597 assert(isTypeLegal(VT)); 598 switch (Op) { 599 default: 600 return false; 601 case ISD::FDIV: 602 case ISD::FREM: 603 case ISD::SDIV: 604 case ISD::UDIV: 605 case ISD::SREM: 606 case ISD::UREM: 607 return true; 608 } 609} 610 611 612static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 613 unsigned &NumIntermediates, 614 EVT &RegisterVT, 615 TargetLowering* TLI) { 616 // Figure out the right, legal destination reg to copy into. 617 unsigned NumElts = VT.getVectorNumElements(); 618 MVT EltTy = VT.getVectorElementType(); 619 620 unsigned NumVectorRegs = 1; 621 622 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 623 // could break down into LHS/RHS like LegalizeDAG does. 624 if (!isPowerOf2_32(NumElts)) { 625 NumVectorRegs = NumElts; 626 NumElts = 1; 627 } 628 629 // Divide the input until we get to a supported size. This will always 630 // end with a scalar if the target doesn't support vectors. 631 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 632 NumElts >>= 1; 633 NumVectorRegs <<= 1; 634 } 635 636 NumIntermediates = NumVectorRegs; 637 638 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 639 if (!TLI->isTypeLegal(NewVT)) 640 NewVT = EltTy; 641 IntermediateVT = NewVT; 642 643 EVT DestVT = TLI->getRegisterType(NewVT); 644 RegisterVT = DestVT; 645 if (EVT(DestVT).bitsLT(NewVT)) { 646 // Value is expanded, e.g. i64 -> i16. 647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 648 } else { 649 // Otherwise, promotion or legal types use the same number of registers as 650 // the vector decimated to the appropriate level. 651 return NumVectorRegs; 652 } 653 654 return 1; 655} 656 657/// computeRegisterProperties - Once all of the register classes are added, 658/// this allows us to compute derived properties we expose. 659void TargetLowering::computeRegisterProperties() { 660 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 661 "Too many value types for ValueTypeActions to hold!"); 662 663 // Everything defaults to needing one register. 664 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 665 NumRegistersForVT[i] = 1; 666 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 667 } 668 // ...except isVoid, which doesn't need any registers. 669 NumRegistersForVT[MVT::isVoid] = 0; 670 671 // Find the largest integer register class. 672 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 673 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 674 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 675 676 // Every integer value type larger than this largest register takes twice as 677 // many registers to represent as the previous ValueType. 678 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 679 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 680 if (!ExpandedVT.isInteger()) 681 break; 682 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 683 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 684 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 685 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 686 } 687 688 // Inspect all of the ValueType's smaller than the largest integer 689 // register to see which ones need promotion. 690 unsigned LegalIntReg = LargestIntReg; 691 for (unsigned IntReg = LargestIntReg - 1; 692 IntReg >= (unsigned)MVT::i1; --IntReg) { 693 EVT IVT = (MVT::SimpleValueType)IntReg; 694 if (isTypeLegal(IVT)) { 695 LegalIntReg = IntReg; 696 } else { 697 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 698 (MVT::SimpleValueType)LegalIntReg; 699 ValueTypeActions.setTypeAction(IVT, Promote); 700 } 701 } 702 703 // ppcf128 type is really two f64's. 704 if (!isTypeLegal(MVT::ppcf128)) { 705 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 706 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 707 TransformToType[MVT::ppcf128] = MVT::f64; 708 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 709 } 710 711 // Decide how to handle f64. If the target does not have native f64 support, 712 // expand it to i64 and we will be generating soft float library calls. 713 if (!isTypeLegal(MVT::f64)) { 714 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 715 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 716 TransformToType[MVT::f64] = MVT::i64; 717 ValueTypeActions.setTypeAction(MVT::f64, Expand); 718 } 719 720 // Decide how to handle f32. If the target does not have native support for 721 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 722 if (!isTypeLegal(MVT::f32)) { 723 if (isTypeLegal(MVT::f64)) { 724 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 725 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 726 TransformToType[MVT::f32] = MVT::f64; 727 ValueTypeActions.setTypeAction(MVT::f32, Promote); 728 } else { 729 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 730 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 731 TransformToType[MVT::f32] = MVT::i32; 732 ValueTypeActions.setTypeAction(MVT::f32, Expand); 733 } 734 } 735 736 // Loop over all of the vector value types to see which need transformations. 737 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 738 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 739 MVT VT = (MVT::SimpleValueType)i; 740 if (!isTypeLegal(VT)) { 741 MVT IntermediateVT; 742 EVT RegisterVT; 743 unsigned NumIntermediates; 744 NumRegistersForVT[i] = 745 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 746 RegisterVT, this); 747 RegisterTypeForVT[i] = RegisterVT; 748 749 // Determine if there is a legal wider type. 750 bool IsLegalWiderType = false; 751 EVT EltVT = VT.getVectorElementType(); 752 unsigned NElts = VT.getVectorNumElements(); 753 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 754 EVT SVT = (MVT::SimpleValueType)nVT; 755 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 756 SVT.getVectorNumElements() > NElts && NElts != 1) { 757 TransformToType[i] = SVT; 758 ValueTypeActions.setTypeAction(VT, Promote); 759 IsLegalWiderType = true; 760 break; 761 } 762 } 763 if (!IsLegalWiderType) { 764 EVT NVT = VT.getPow2VectorType(); 765 if (NVT == VT) { 766 // Type is already a power of 2. The default action is to split. 767 TransformToType[i] = MVT::Other; 768 ValueTypeActions.setTypeAction(VT, Expand); 769 } else { 770 TransformToType[i] = NVT; 771 ValueTypeActions.setTypeAction(VT, Promote); 772 } 773 } 774 } 775 } 776} 777 778const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 779 return NULL; 780} 781 782 783MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 784 return PointerTy.SimpleTy; 785} 786 787MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 788 return MVT::i32; // return the default value 789} 790 791/// getVectorTypeBreakdown - Vector types are broken down into some number of 792/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 793/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 794/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 795/// 796/// This method returns the number of registers needed, and the VT for each 797/// register. It also returns the VT and quantity of the intermediate values 798/// before they are promoted/expanded. 799/// 800unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 801 EVT &IntermediateVT, 802 unsigned &NumIntermediates, 803 EVT &RegisterVT) const { 804 // Figure out the right, legal destination reg to copy into. 805 unsigned NumElts = VT.getVectorNumElements(); 806 EVT EltTy = VT.getVectorElementType(); 807 808 unsigned NumVectorRegs = 1; 809 810 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 811 // could break down into LHS/RHS like LegalizeDAG does. 812 if (!isPowerOf2_32(NumElts)) { 813 NumVectorRegs = NumElts; 814 NumElts = 1; 815 } 816 817 // Divide the input until we get to a supported size. This will always 818 // end with a scalar if the target doesn't support vectors. 819 while (NumElts > 1 && !isTypeLegal( 820 EVT::getVectorVT(Context, EltTy, NumElts))) { 821 NumElts >>= 1; 822 NumVectorRegs <<= 1; 823 } 824 825 NumIntermediates = NumVectorRegs; 826 827 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 828 if (!isTypeLegal(NewVT)) 829 NewVT = EltTy; 830 IntermediateVT = NewVT; 831 832 EVT DestVT = getRegisterType(Context, NewVT); 833 RegisterVT = DestVT; 834 if (DestVT.bitsLT(NewVT)) { 835 // Value is expanded, e.g. i64 -> i16. 836 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 837 } else { 838 // Otherwise, promotion or legal types use the same number of registers as 839 // the vector decimated to the appropriate level. 840 return NumVectorRegs; 841 } 842 843 return 1; 844} 845 846/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 847/// function arguments in the caller parameter area. This is the actual 848/// alignment, not its logarithm. 849unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 850 return TD->getCallFrameTypeAlignment(Ty); 851} 852 853/// getJumpTableEncoding - Return the entry encoding for a jump table in the 854/// current function. The returned value is a member of the 855/// MachineJumpTableInfo::JTEntryKind enum. 856unsigned TargetLowering::getJumpTableEncoding() const { 857 // In non-pic modes, just use the address of a block. 858 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 859 return MachineJumpTableInfo::EK_BlockAddress; 860 861 // In PIC mode, if the target supports a GPRel32 directive, use it. 862 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 863 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 864 865 // Otherwise, use a label difference. 866 return MachineJumpTableInfo::EK_LabelDifference32; 867} 868 869SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 870 SelectionDAG &DAG) const { 871 // If our PIC model is GP relative, use the global offset table as the base. 872 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 873 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 874 return Table; 875} 876 877/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 878/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 879/// MCExpr. 880const MCExpr * 881TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 882 unsigned JTI,MCContext &Ctx) const{ 883 // The normal PIC reloc base is the label at the start of the jump table. 884 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 885} 886 887bool 888TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 889 // Assume that everything is safe in static mode. 890 if (getTargetMachine().getRelocationModel() == Reloc::Static) 891 return true; 892 893 // In dynamic-no-pic mode, assume that known defined values are safe. 894 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 895 GA && 896 !GA->getGlobal()->isDeclaration() && 897 !GA->getGlobal()->isWeakForLinker()) 898 return true; 899 900 // Otherwise assume nothing is safe. 901 return false; 902} 903 904//===----------------------------------------------------------------------===// 905// Optimization Methods 906//===----------------------------------------------------------------------===// 907 908/// ShrinkDemandedConstant - Check to see if the specified operand of the 909/// specified instruction is a constant integer. If so, check to see if there 910/// are any bits set in the constant that are not demanded. If so, shrink the 911/// constant and return true. 912bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 913 const APInt &Demanded) { 914 DebugLoc dl = Op.getDebugLoc(); 915 916 // FIXME: ISD::SELECT, ISD::SELECT_CC 917 switch (Op.getOpcode()) { 918 default: break; 919 case ISD::XOR: 920 case ISD::AND: 921 case ISD::OR: { 922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 923 if (!C) return false; 924 925 if (Op.getOpcode() == ISD::XOR && 926 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 927 return false; 928 929 // if we can expand it to have all bits set, do it 930 if (C->getAPIntValue().intersects(~Demanded)) { 931 EVT VT = Op.getValueType(); 932 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 933 DAG.getConstant(Demanded & 934 C->getAPIntValue(), 935 VT)); 936 return CombineTo(Op, New); 937 } 938 939 break; 940 } 941 } 942 943 return false; 944} 945 946/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 947/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 948/// cast, but it could be generalized for targets with other types of 949/// implicit widening casts. 950bool 951TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 952 unsigned BitWidth, 953 const APInt &Demanded, 954 DebugLoc dl) { 955 assert(Op.getNumOperands() == 2 && 956 "ShrinkDemandedOp only supports binary operators!"); 957 assert(Op.getNode()->getNumValues() == 1 && 958 "ShrinkDemandedOp only supports nodes with one result!"); 959 960 // Don't do this if the node has another user, which may require the 961 // full value. 962 if (!Op.getNode()->hasOneUse()) 963 return false; 964 965 // Search for the smallest integer type with free casts to and from 966 // Op's type. For expedience, just check power-of-2 integer types. 967 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 968 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 969 if (!isPowerOf2_32(SmallVTBits)) 970 SmallVTBits = NextPowerOf2(SmallVTBits); 971 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 972 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 973 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 974 TLI.isZExtFree(SmallVT, Op.getValueType())) { 975 // We found a type with free casts. 976 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 977 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 978 Op.getNode()->getOperand(0)), 979 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 980 Op.getNode()->getOperand(1))); 981 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 982 return CombineTo(Op, Z); 983 } 984 } 985 return false; 986} 987 988/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 989/// DemandedMask bits of the result of Op are ever used downstream. If we can 990/// use this information to simplify Op, create a new simplified DAG node and 991/// return true, returning the original and new nodes in Old and New. Otherwise, 992/// analyze the expression and return a mask of KnownOne and KnownZero bits for 993/// the expression (used to simplify the caller). The KnownZero/One bits may 994/// only be accurate for those bits in the DemandedMask. 995bool TargetLowering::SimplifyDemandedBits(SDValue Op, 996 const APInt &DemandedMask, 997 APInt &KnownZero, 998 APInt &KnownOne, 999 TargetLoweringOpt &TLO, 1000 unsigned Depth) const { 1001 unsigned BitWidth = DemandedMask.getBitWidth(); 1002 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1003 "Mask size mismatches value type size!"); 1004 APInt NewMask = DemandedMask; 1005 DebugLoc dl = Op.getDebugLoc(); 1006 1007 // Don't know anything. 1008 KnownZero = KnownOne = APInt(BitWidth, 0); 1009 1010 // Other users may use these bits. 1011 if (!Op.getNode()->hasOneUse()) { 1012 if (Depth != 0) { 1013 // If not at the root, Just compute the KnownZero/KnownOne bits to 1014 // simplify things downstream. 1015 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1016 return false; 1017 } 1018 // If this is the root being simplified, allow it to have multiple uses, 1019 // just set the NewMask to all bits. 1020 NewMask = APInt::getAllOnesValue(BitWidth); 1021 } else if (DemandedMask == 0) { 1022 // Not demanding any bits from Op. 1023 if (Op.getOpcode() != ISD::UNDEF) 1024 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1025 return false; 1026 } else if (Depth == 6) { // Limit search depth. 1027 return false; 1028 } 1029 1030 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1031 switch (Op.getOpcode()) { 1032 case ISD::Constant: 1033 // We know all of the bits for a constant! 1034 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1035 KnownZero = ~KnownOne & NewMask; 1036 return false; // Don't fall through, will infinitely loop. 1037 case ISD::AND: 1038 // If the RHS is a constant, check to see if the LHS would be zero without 1039 // using the bits from the RHS. Below, we use knowledge about the RHS to 1040 // simplify the LHS, here we're using information from the LHS to simplify 1041 // the RHS. 1042 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1043 APInt LHSZero, LHSOne; 1044 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1045 LHSZero, LHSOne, Depth+1); 1046 // If the LHS already has zeros where RHSC does, this and is dead. 1047 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1048 return TLO.CombineTo(Op, Op.getOperand(0)); 1049 // If any of the set bits in the RHS are known zero on the LHS, shrink 1050 // the constant. 1051 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1052 return true; 1053 } 1054 1055 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1056 KnownOne, TLO, Depth+1)) 1057 return true; 1058 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1059 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1060 KnownZero2, KnownOne2, TLO, Depth+1)) 1061 return true; 1062 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1063 1064 // If all of the demanded bits are known one on one side, return the other. 1065 // These bits cannot contribute to the result of the 'and'. 1066 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1067 return TLO.CombineTo(Op, Op.getOperand(0)); 1068 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1069 return TLO.CombineTo(Op, Op.getOperand(1)); 1070 // If all of the demanded bits in the inputs are known zeros, return zero. 1071 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1072 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1073 // If the RHS is a constant, see if we can simplify it. 1074 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1075 return true; 1076 // If the operation can be done in a smaller type, do so. 1077 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1078 return true; 1079 1080 // Output known-1 bits are only known if set in both the LHS & RHS. 1081 KnownOne &= KnownOne2; 1082 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1083 KnownZero |= KnownZero2; 1084 break; 1085 case ISD::OR: 1086 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1087 KnownOne, TLO, Depth+1)) 1088 return true; 1089 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1090 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1091 KnownZero2, KnownOne2, TLO, Depth+1)) 1092 return true; 1093 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1094 1095 // If all of the demanded bits are known zero on one side, return the other. 1096 // These bits cannot contribute to the result of the 'or'. 1097 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1098 return TLO.CombineTo(Op, Op.getOperand(0)); 1099 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1100 return TLO.CombineTo(Op, Op.getOperand(1)); 1101 // If all of the potentially set bits on one side are known to be set on 1102 // the other side, just use the 'other' side. 1103 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1104 return TLO.CombineTo(Op, Op.getOperand(0)); 1105 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1106 return TLO.CombineTo(Op, Op.getOperand(1)); 1107 // If the RHS is a constant, see if we can simplify it. 1108 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1109 return true; 1110 // If the operation can be done in a smaller type, do so. 1111 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1112 return true; 1113 1114 // Output known-0 bits are only known if clear in both the LHS & RHS. 1115 KnownZero &= KnownZero2; 1116 // Output known-1 are known to be set if set in either the LHS | RHS. 1117 KnownOne |= KnownOne2; 1118 break; 1119 case ISD::XOR: 1120 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1121 KnownOne, TLO, Depth+1)) 1122 return true; 1123 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1124 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1125 KnownOne2, TLO, Depth+1)) 1126 return true; 1127 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1128 1129 // If all of the demanded bits are known zero on one side, return the other. 1130 // These bits cannot contribute to the result of the 'xor'. 1131 if ((KnownZero & NewMask) == NewMask) 1132 return TLO.CombineTo(Op, Op.getOperand(0)); 1133 if ((KnownZero2 & NewMask) == NewMask) 1134 return TLO.CombineTo(Op, Op.getOperand(1)); 1135 // If the operation can be done in a smaller type, do so. 1136 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1137 return true; 1138 1139 // If all of the unknown bits are known to be zero on one side or the other 1140 // (but not both) turn this into an *inclusive* or. 1141 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1142 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1143 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1144 Op.getOperand(0), 1145 Op.getOperand(1))); 1146 1147 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1148 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1149 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1150 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1151 1152 // If all of the demanded bits on one side are known, and all of the set 1153 // bits on that side are also known to be set on the other side, turn this 1154 // into an AND, as we know the bits will be cleared. 1155 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1156 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1157 if ((KnownOne & KnownOne2) == KnownOne) { 1158 EVT VT = Op.getValueType(); 1159 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1160 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1161 Op.getOperand(0), ANDC)); 1162 } 1163 } 1164 1165 // If the RHS is a constant, see if we can simplify it. 1166 // for XOR, we prefer to force bits to 1 if they will make a -1. 1167 // if we can't force bits, try to shrink constant 1168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1169 APInt Expanded = C->getAPIntValue() | (~NewMask); 1170 // if we can expand it to have all bits set, do it 1171 if (Expanded.isAllOnesValue()) { 1172 if (Expanded != C->getAPIntValue()) { 1173 EVT VT = Op.getValueType(); 1174 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1175 TLO.DAG.getConstant(Expanded, VT)); 1176 return TLO.CombineTo(Op, New); 1177 } 1178 // if it already has all the bits set, nothing to change 1179 // but don't shrink either! 1180 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1181 return true; 1182 } 1183 } 1184 1185 KnownZero = KnownZeroOut; 1186 KnownOne = KnownOneOut; 1187 break; 1188 case ISD::SELECT: 1189 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1190 KnownOne, TLO, Depth+1)) 1191 return true; 1192 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1193 KnownOne2, TLO, Depth+1)) 1194 return true; 1195 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1196 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1197 1198 // If the operands are constants, see if we can simplify them. 1199 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1200 return true; 1201 1202 // Only known if known in both the LHS and RHS. 1203 KnownOne &= KnownOne2; 1204 KnownZero &= KnownZero2; 1205 break; 1206 case ISD::SELECT_CC: 1207 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1208 KnownOne, TLO, Depth+1)) 1209 return true; 1210 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1211 KnownOne2, TLO, Depth+1)) 1212 return true; 1213 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1214 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1215 1216 // If the operands are constants, see if we can simplify them. 1217 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1218 return true; 1219 1220 // Only known if known in both the LHS and RHS. 1221 KnownOne &= KnownOne2; 1222 KnownZero &= KnownZero2; 1223 break; 1224 case ISD::SHL: 1225 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1226 unsigned ShAmt = SA->getZExtValue(); 1227 SDValue InOp = Op.getOperand(0); 1228 1229 // If the shift count is an invalid immediate, don't do anything. 1230 if (ShAmt >= BitWidth) 1231 break; 1232 1233 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1234 // single shift. We can do this if the bottom bits (which are shifted 1235 // out) are never demanded. 1236 if (InOp.getOpcode() == ISD::SRL && 1237 isa<ConstantSDNode>(InOp.getOperand(1))) { 1238 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1239 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1240 unsigned Opc = ISD::SHL; 1241 int Diff = ShAmt-C1; 1242 if (Diff < 0) { 1243 Diff = -Diff; 1244 Opc = ISD::SRL; 1245 } 1246 1247 SDValue NewSA = 1248 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1249 EVT VT = Op.getValueType(); 1250 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1251 InOp.getOperand(0), NewSA)); 1252 } 1253 } 1254 1255 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1256 KnownZero, KnownOne, TLO, Depth+1)) 1257 return true; 1258 KnownZero <<= SA->getZExtValue(); 1259 KnownOne <<= SA->getZExtValue(); 1260 // low bits known zero. 1261 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1262 } 1263 break; 1264 case ISD::SRL: 1265 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1266 EVT VT = Op.getValueType(); 1267 unsigned ShAmt = SA->getZExtValue(); 1268 unsigned VTSize = VT.getSizeInBits(); 1269 SDValue InOp = Op.getOperand(0); 1270 1271 // If the shift count is an invalid immediate, don't do anything. 1272 if (ShAmt >= BitWidth) 1273 break; 1274 1275 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1276 // single shift. We can do this if the top bits (which are shifted out) 1277 // are never demanded. 1278 if (InOp.getOpcode() == ISD::SHL && 1279 isa<ConstantSDNode>(InOp.getOperand(1))) { 1280 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1281 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1282 unsigned Opc = ISD::SRL; 1283 int Diff = ShAmt-C1; 1284 if (Diff < 0) { 1285 Diff = -Diff; 1286 Opc = ISD::SHL; 1287 } 1288 1289 SDValue NewSA = 1290 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1291 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1292 InOp.getOperand(0), NewSA)); 1293 } 1294 } 1295 1296 // Compute the new bits that are at the top now. 1297 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1298 KnownZero, KnownOne, TLO, Depth+1)) 1299 return true; 1300 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1301 KnownZero = KnownZero.lshr(ShAmt); 1302 KnownOne = KnownOne.lshr(ShAmt); 1303 1304 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1305 KnownZero |= HighBits; // High bits known zero. 1306 } 1307 break; 1308 case ISD::SRA: 1309 // If this is an arithmetic shift right and only the low-bit is set, we can 1310 // always convert this into a logical shr, even if the shift amount is 1311 // variable. The low bit of the shift cannot be an input sign bit unless 1312 // the shift amount is >= the size of the datatype, which is undefined. 1313 if (DemandedMask == 1) 1314 return TLO.CombineTo(Op, 1315 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1316 Op.getOperand(0), Op.getOperand(1))); 1317 1318 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1319 EVT VT = Op.getValueType(); 1320 unsigned ShAmt = SA->getZExtValue(); 1321 1322 // If the shift count is an invalid immediate, don't do anything. 1323 if (ShAmt >= BitWidth) 1324 break; 1325 1326 APInt InDemandedMask = (NewMask << ShAmt); 1327 1328 // If any of the demanded bits are produced by the sign extension, we also 1329 // demand the input sign bit. 1330 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1331 if (HighBits.intersects(NewMask)) 1332 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1333 1334 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1335 KnownZero, KnownOne, TLO, Depth+1)) 1336 return true; 1337 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1338 KnownZero = KnownZero.lshr(ShAmt); 1339 KnownOne = KnownOne.lshr(ShAmt); 1340 1341 // Handle the sign bit, adjusted to where it is now in the mask. 1342 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1343 1344 // If the input sign bit is known to be zero, or if none of the top bits 1345 // are demanded, turn this into an unsigned shift right. 1346 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1347 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1348 Op.getOperand(0), 1349 Op.getOperand(1))); 1350 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1351 KnownOne |= HighBits; 1352 } 1353 } 1354 break; 1355 case ISD::SIGN_EXTEND_INREG: { 1356 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1357 1358 // Sign extension. Compute the demanded bits in the result that are not 1359 // present in the input. 1360 APInt NewBits = 1361 APInt::getHighBitsSet(BitWidth, 1362 BitWidth - EVT.getScalarType().getSizeInBits()) & 1363 NewMask; 1364 1365 // If none of the extended bits are demanded, eliminate the sextinreg. 1366 if (NewBits == 0) 1367 return TLO.CombineTo(Op, Op.getOperand(0)); 1368 1369 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1370 InSignBit.zext(BitWidth); 1371 APInt InputDemandedBits = 1372 APInt::getLowBitsSet(BitWidth, 1373 EVT.getScalarType().getSizeInBits()) & 1374 NewMask; 1375 1376 // Since the sign extended bits are demanded, we know that the sign 1377 // bit is demanded. 1378 InputDemandedBits |= InSignBit; 1379 1380 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1381 KnownZero, KnownOne, TLO, Depth+1)) 1382 return true; 1383 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1384 1385 // If the sign bit of the input is known set or clear, then we know the 1386 // top bits of the result. 1387 1388 // If the input sign bit is known zero, convert this into a zero extension. 1389 if (KnownZero.intersects(InSignBit)) 1390 return TLO.CombineTo(Op, 1391 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1392 1393 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1394 KnownOne |= NewBits; 1395 KnownZero &= ~NewBits; 1396 } else { // Input sign bit unknown 1397 KnownZero &= ~NewBits; 1398 KnownOne &= ~NewBits; 1399 } 1400 break; 1401 } 1402 case ISD::ZERO_EXTEND: { 1403 unsigned OperandBitWidth = 1404 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1405 APInt InMask = NewMask; 1406 InMask.trunc(OperandBitWidth); 1407 1408 // If none of the top bits are demanded, convert this into an any_extend. 1409 APInt NewBits = 1410 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1411 if (!NewBits.intersects(NewMask)) 1412 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1413 Op.getValueType(), 1414 Op.getOperand(0))); 1415 1416 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1417 KnownZero, KnownOne, TLO, Depth+1)) 1418 return true; 1419 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1420 KnownZero.zext(BitWidth); 1421 KnownOne.zext(BitWidth); 1422 KnownZero |= NewBits; 1423 break; 1424 } 1425 case ISD::SIGN_EXTEND: { 1426 EVT InVT = Op.getOperand(0).getValueType(); 1427 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1428 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1429 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1430 APInt NewBits = ~InMask & NewMask; 1431 1432 // If none of the top bits are demanded, convert this into an any_extend. 1433 if (NewBits == 0) 1434 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1435 Op.getValueType(), 1436 Op.getOperand(0))); 1437 1438 // Since some of the sign extended bits are demanded, we know that the sign 1439 // bit is demanded. 1440 APInt InDemandedBits = InMask & NewMask; 1441 InDemandedBits |= InSignBit; 1442 InDemandedBits.trunc(InBits); 1443 1444 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1445 KnownOne, TLO, Depth+1)) 1446 return true; 1447 KnownZero.zext(BitWidth); 1448 KnownOne.zext(BitWidth); 1449 1450 // If the sign bit is known zero, convert this to a zero extend. 1451 if (KnownZero.intersects(InSignBit)) 1452 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1453 Op.getValueType(), 1454 Op.getOperand(0))); 1455 1456 // If the sign bit is known one, the top bits match. 1457 if (KnownOne.intersects(InSignBit)) { 1458 KnownOne |= NewBits; 1459 KnownZero &= ~NewBits; 1460 } else { // Otherwise, top bits aren't known. 1461 KnownOne &= ~NewBits; 1462 KnownZero &= ~NewBits; 1463 } 1464 break; 1465 } 1466 case ISD::ANY_EXTEND: { 1467 unsigned OperandBitWidth = 1468 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1469 APInt InMask = NewMask; 1470 InMask.trunc(OperandBitWidth); 1471 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1472 KnownZero, KnownOne, TLO, Depth+1)) 1473 return true; 1474 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1475 KnownZero.zext(BitWidth); 1476 KnownOne.zext(BitWidth); 1477 break; 1478 } 1479 case ISD::TRUNCATE: { 1480 // Simplify the input, using demanded bit information, and compute the known 1481 // zero/one bits live out. 1482 unsigned OperandBitWidth = 1483 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1484 APInt TruncMask = NewMask; 1485 TruncMask.zext(OperandBitWidth); 1486 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1487 KnownZero, KnownOne, TLO, Depth+1)) 1488 return true; 1489 KnownZero.trunc(BitWidth); 1490 KnownOne.trunc(BitWidth); 1491 1492 // If the input is only used by this truncate, see if we can shrink it based 1493 // on the known demanded bits. 1494 if (Op.getOperand(0).getNode()->hasOneUse()) { 1495 SDValue In = Op.getOperand(0); 1496 switch (In.getOpcode()) { 1497 default: break; 1498 case ISD::SRL: 1499 // Shrink SRL by a constant if none of the high bits shifted in are 1500 // demanded. 1501 if (TLO.LegalTypes() && 1502 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1503 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1504 // undesirable. 1505 break; 1506 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1507 if (!ShAmt) 1508 break; 1509 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1510 OperandBitWidth - BitWidth); 1511 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1512 HighBits.trunc(BitWidth); 1513 1514 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1515 // None of the shifted in bits are needed. Add a truncate of the 1516 // shift input, then shift it. 1517 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1518 Op.getValueType(), 1519 In.getOperand(0)); 1520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1521 Op.getValueType(), 1522 NewTrunc, 1523 In.getOperand(1))); 1524 } 1525 break; 1526 } 1527 } 1528 1529 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1530 break; 1531 } 1532 case ISD::AssertZext: { 1533 // Demand all the bits of the input that are demanded in the output. 1534 // The low bits are obvious; the high bits are demanded because we're 1535 // asserting that they're zero here. 1536 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1537 KnownZero, KnownOne, TLO, Depth+1)) 1538 return true; 1539 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1540 1541 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1542 APInt InMask = APInt::getLowBitsSet(BitWidth, 1543 VT.getSizeInBits()); 1544 KnownZero |= ~InMask & NewMask; 1545 break; 1546 } 1547 case ISD::BIT_CONVERT: 1548#if 0 1549 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1550 // is demanded, turn this into a FGETSIGN. 1551 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1552 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1553 !MVT::isVector(Op.getOperand(0).getValueType())) { 1554 // Only do this xform if FGETSIGN is valid or if before legalize. 1555 if (!TLO.AfterLegalize || 1556 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1557 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1558 // place. We expect the SHL to be eliminated by other optimizations. 1559 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1560 Op.getOperand(0)); 1561 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1562 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1563 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1564 Sign, ShAmt)); 1565 } 1566 } 1567#endif 1568 break; 1569 case ISD::ADD: 1570 case ISD::MUL: 1571 case ISD::SUB: { 1572 // Add, Sub, and Mul don't demand any bits in positions beyond that 1573 // of the highest bit demanded of them. 1574 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1575 BitWidth - NewMask.countLeadingZeros()); 1576 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1577 KnownOne2, TLO, Depth+1)) 1578 return true; 1579 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1580 KnownOne2, TLO, Depth+1)) 1581 return true; 1582 // See if the operation should be performed at a smaller bit width. 1583 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1584 return true; 1585 } 1586 // FALL THROUGH 1587 default: 1588 // Just use ComputeMaskedBits to compute output bits. 1589 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1590 break; 1591 } 1592 1593 // If we know the value of all of the demanded bits, return this as a 1594 // constant. 1595 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1596 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1597 1598 return false; 1599} 1600 1601/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1602/// in Mask are known to be either zero or one and return them in the 1603/// KnownZero/KnownOne bitsets. 1604void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1605 const APInt &Mask, 1606 APInt &KnownZero, 1607 APInt &KnownOne, 1608 const SelectionDAG &DAG, 1609 unsigned Depth) const { 1610 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1611 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1612 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1613 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1614 "Should use MaskedValueIsZero if you don't know whether Op" 1615 " is a target node!"); 1616 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1617} 1618 1619/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1620/// targets that want to expose additional information about sign bits to the 1621/// DAG Combiner. 1622unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1623 unsigned Depth) const { 1624 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1625 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1626 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1627 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1628 "Should use ComputeNumSignBits if you don't know whether Op" 1629 " is a target node!"); 1630 return 1; 1631} 1632 1633/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1634/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1635/// determine which bit is set. 1636/// 1637static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1638 // A left-shift of a constant one will have exactly one bit set, because 1639 // shifting the bit off the end is undefined. 1640 if (Val.getOpcode() == ISD::SHL) 1641 if (ConstantSDNode *C = 1642 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1643 if (C->getAPIntValue() == 1) 1644 return true; 1645 1646 // Similarly, a right-shift of a constant sign-bit will have exactly 1647 // one bit set. 1648 if (Val.getOpcode() == ISD::SRL) 1649 if (ConstantSDNode *C = 1650 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1651 if (C->getAPIntValue().isSignBit()) 1652 return true; 1653 1654 // More could be done here, though the above checks are enough 1655 // to handle some common cases. 1656 1657 // Fall back to ComputeMaskedBits to catch other known cases. 1658 EVT OpVT = Val.getValueType(); 1659 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1660 APInt Mask = APInt::getAllOnesValue(BitWidth); 1661 APInt KnownZero, KnownOne; 1662 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1663 return (KnownZero.countPopulation() == BitWidth - 1) && 1664 (KnownOne.countPopulation() == 1); 1665} 1666 1667/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1668/// and cc. If it is unable to simplify it, return a null SDValue. 1669SDValue 1670TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1671 ISD::CondCode Cond, bool foldBooleans, 1672 DAGCombinerInfo &DCI, DebugLoc dl) const { 1673 SelectionDAG &DAG = DCI.DAG; 1674 LLVMContext &Context = *DAG.getContext(); 1675 1676 // These setcc operations always fold. 1677 switch (Cond) { 1678 default: break; 1679 case ISD::SETFALSE: 1680 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1681 case ISD::SETTRUE: 1682 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1683 } 1684 1685 if (isa<ConstantSDNode>(N0.getNode())) { 1686 // Ensure that the constant occurs on the RHS, and fold constant 1687 // comparisons. 1688 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1689 } 1690 1691 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1692 const APInt &C1 = N1C->getAPIntValue(); 1693 1694 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1695 // equality comparison, then we're just comparing whether X itself is 1696 // zero. 1697 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1698 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1699 N0.getOperand(1).getOpcode() == ISD::Constant) { 1700 const APInt &ShAmt 1701 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1702 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1703 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1704 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1705 // (srl (ctlz x), 5) == 0 -> X != 0 1706 // (srl (ctlz x), 5) != 1 -> X != 0 1707 Cond = ISD::SETNE; 1708 } else { 1709 // (srl (ctlz x), 5) != 0 -> X == 0 1710 // (srl (ctlz x), 5) == 1 -> X == 0 1711 Cond = ISD::SETEQ; 1712 } 1713 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1714 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1715 Zero, Cond); 1716 } 1717 } 1718 1719 // If the LHS is '(and load, const)', the RHS is 0, 1720 // the test is for equality or unsigned, and all 1 bits of the const are 1721 // in the same partial word, see if we can shorten the load. 1722 if (DCI.isBeforeLegalize() && 1723 N0.getOpcode() == ISD::AND && C1 == 0 && 1724 N0.getNode()->hasOneUse() && 1725 isa<LoadSDNode>(N0.getOperand(0)) && 1726 N0.getOperand(0).getNode()->hasOneUse() && 1727 isa<ConstantSDNode>(N0.getOperand(1))) { 1728 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1729 APInt bestMask; 1730 unsigned bestWidth = 0, bestOffset = 0; 1731 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1732 unsigned origWidth = N0.getValueType().getSizeInBits(); 1733 unsigned maskWidth = origWidth; 1734 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1735 // 8 bits, but have to be careful... 1736 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1737 origWidth = Lod->getMemoryVT().getSizeInBits(); 1738 const APInt &Mask = 1739 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1740 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1741 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1742 for (unsigned offset=0; offset<origWidth/width; offset++) { 1743 if ((newMask & Mask) == Mask) { 1744 if (!TD->isLittleEndian()) 1745 bestOffset = (origWidth/width - offset - 1) * (width/8); 1746 else 1747 bestOffset = (uint64_t)offset * (width/8); 1748 bestMask = Mask.lshr(offset * (width/8) * 8); 1749 bestWidth = width; 1750 break; 1751 } 1752 newMask = newMask << width; 1753 } 1754 } 1755 } 1756 if (bestWidth) { 1757 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1758 if (newVT.isRound()) { 1759 EVT PtrType = Lod->getOperand(1).getValueType(); 1760 SDValue Ptr = Lod->getBasePtr(); 1761 if (bestOffset != 0) 1762 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1763 DAG.getConstant(bestOffset, PtrType)); 1764 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1765 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1766 Lod->getSrcValue(), 1767 Lod->getSrcValueOffset() + bestOffset, 1768 false, false, NewAlign); 1769 return DAG.getSetCC(dl, VT, 1770 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1771 DAG.getConstant(bestMask.trunc(bestWidth), 1772 newVT)), 1773 DAG.getConstant(0LL, newVT), Cond); 1774 } 1775 } 1776 } 1777 1778 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1779 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1780 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1781 1782 // If the comparison constant has bits in the upper part, the 1783 // zero-extended value could never match. 1784 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1785 C1.getBitWidth() - InSize))) { 1786 switch (Cond) { 1787 case ISD::SETUGT: 1788 case ISD::SETUGE: 1789 case ISD::SETEQ: return DAG.getConstant(0, VT); 1790 case ISD::SETULT: 1791 case ISD::SETULE: 1792 case ISD::SETNE: return DAG.getConstant(1, VT); 1793 case ISD::SETGT: 1794 case ISD::SETGE: 1795 // True if the sign bit of C1 is set. 1796 return DAG.getConstant(C1.isNegative(), VT); 1797 case ISD::SETLT: 1798 case ISD::SETLE: 1799 // True if the sign bit of C1 isn't set. 1800 return DAG.getConstant(C1.isNonNegative(), VT); 1801 default: 1802 break; 1803 } 1804 } 1805 1806 // Otherwise, we can perform the comparison with the low bits. 1807 switch (Cond) { 1808 case ISD::SETEQ: 1809 case ISD::SETNE: 1810 case ISD::SETUGT: 1811 case ISD::SETUGE: 1812 case ISD::SETULT: 1813 case ISD::SETULE: { 1814 EVT newVT = N0.getOperand(0).getValueType(); 1815 if (DCI.isBeforeLegalizeOps() || 1816 (isOperationLegal(ISD::SETCC, newVT) && 1817 getCondCodeAction(Cond, newVT)==Legal)) 1818 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1819 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1820 Cond); 1821 break; 1822 } 1823 default: 1824 break; // todo, be more careful with signed comparisons 1825 } 1826 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1827 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1828 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1829 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1830 EVT ExtDstTy = N0.getValueType(); 1831 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1832 1833 // If the extended part has any inconsistent bits, it cannot ever 1834 // compare equal. In other words, they have to be all ones or all 1835 // zeros. 1836 APInt ExtBits = 1837 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1838 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1839 return DAG.getConstant(Cond == ISD::SETNE, VT); 1840 1841 SDValue ZextOp; 1842 EVT Op0Ty = N0.getOperand(0).getValueType(); 1843 if (Op0Ty == ExtSrcTy) { 1844 ZextOp = N0.getOperand(0); 1845 } else { 1846 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1847 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1848 DAG.getConstant(Imm, Op0Ty)); 1849 } 1850 if (!DCI.isCalledByLegalizer()) 1851 DCI.AddToWorklist(ZextOp.getNode()); 1852 // Otherwise, make this a use of a zext. 1853 return DAG.getSetCC(dl, VT, ZextOp, 1854 DAG.getConstant(C1 & APInt::getLowBitsSet( 1855 ExtDstTyBits, 1856 ExtSrcTyBits), 1857 ExtDstTy), 1858 Cond); 1859 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1860 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1861 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1862 if (N0.getOpcode() == ISD::SETCC && 1863 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1864 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1865 if (TrueWhenTrue) 1866 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1867 // Invert the condition. 1868 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1869 CC = ISD::getSetCCInverse(CC, 1870 N0.getOperand(0).getValueType().isInteger()); 1871 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1872 } 1873 1874 if ((N0.getOpcode() == ISD::XOR || 1875 (N0.getOpcode() == ISD::AND && 1876 N0.getOperand(0).getOpcode() == ISD::XOR && 1877 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1878 isa<ConstantSDNode>(N0.getOperand(1)) && 1879 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1880 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1881 // can only do this if the top bits are known zero. 1882 unsigned BitWidth = N0.getValueSizeInBits(); 1883 if (DAG.MaskedValueIsZero(N0, 1884 APInt::getHighBitsSet(BitWidth, 1885 BitWidth-1))) { 1886 // Okay, get the un-inverted input value. 1887 SDValue Val; 1888 if (N0.getOpcode() == ISD::XOR) 1889 Val = N0.getOperand(0); 1890 else { 1891 assert(N0.getOpcode() == ISD::AND && 1892 N0.getOperand(0).getOpcode() == ISD::XOR); 1893 // ((X^1)&1)^1 -> X & 1 1894 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1895 N0.getOperand(0).getOperand(0), 1896 N0.getOperand(1)); 1897 } 1898 1899 return DAG.getSetCC(dl, VT, Val, N1, 1900 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1901 } 1902 } else if (N1C->getAPIntValue() == 1 && 1903 (VT == MVT::i1 || 1904 getBooleanContents() == ZeroOrOneBooleanContent)) { 1905 SDValue Op0 = N0; 1906 if (Op0.getOpcode() == ISD::TRUNCATE) 1907 Op0 = Op0.getOperand(0); 1908 1909 if ((Op0.getOpcode() == ISD::XOR) && 1910 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1911 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1912 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1913 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1914 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1915 Cond); 1916 } else if (Op0.getOpcode() == ISD::AND && 1917 isa<ConstantSDNode>(Op0.getOperand(1)) && 1918 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1919 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1920 if (Op0.getValueType().bitsGT(VT)) 1921 Op0 = DAG.getNode(ISD::AND, dl, VT, 1922 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1923 DAG.getConstant(1, VT)); 1924 else if (Op0.getValueType().bitsLT(VT)) 1925 Op0 = DAG.getNode(ISD::AND, dl, VT, 1926 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1927 DAG.getConstant(1, VT)); 1928 1929 return DAG.getSetCC(dl, VT, Op0, 1930 DAG.getConstant(0, Op0.getValueType()), 1931 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1932 } 1933 } 1934 } 1935 1936 APInt MinVal, MaxVal; 1937 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1938 if (ISD::isSignedIntSetCC(Cond)) { 1939 MinVal = APInt::getSignedMinValue(OperandBitSize); 1940 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1941 } else { 1942 MinVal = APInt::getMinValue(OperandBitSize); 1943 MaxVal = APInt::getMaxValue(OperandBitSize); 1944 } 1945 1946 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1947 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1948 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1949 // X >= C0 --> X > (C0-1) 1950 return DAG.getSetCC(dl, VT, N0, 1951 DAG.getConstant(C1-1, N1.getValueType()), 1952 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1953 } 1954 1955 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1956 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1957 // X <= C0 --> X < (C0+1) 1958 return DAG.getSetCC(dl, VT, N0, 1959 DAG.getConstant(C1+1, N1.getValueType()), 1960 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1961 } 1962 1963 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1964 return DAG.getConstant(0, VT); // X < MIN --> false 1965 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1966 return DAG.getConstant(1, VT); // X >= MIN --> true 1967 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1968 return DAG.getConstant(0, VT); // X > MAX --> false 1969 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1970 return DAG.getConstant(1, VT); // X <= MAX --> true 1971 1972 // Canonicalize setgt X, Min --> setne X, Min 1973 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1974 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1975 // Canonicalize setlt X, Max --> setne X, Max 1976 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1977 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1978 1979 // If we have setult X, 1, turn it into seteq X, 0 1980 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1981 return DAG.getSetCC(dl, VT, N0, 1982 DAG.getConstant(MinVal, N0.getValueType()), 1983 ISD::SETEQ); 1984 // If we have setugt X, Max-1, turn it into seteq X, Max 1985 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1986 return DAG.getSetCC(dl, VT, N0, 1987 DAG.getConstant(MaxVal, N0.getValueType()), 1988 ISD::SETEQ); 1989 1990 // If we have "setcc X, C0", check to see if we can shrink the immediate 1991 // by changing cc. 1992 1993 // SETUGT X, SINTMAX -> SETLT X, 0 1994 if (Cond == ISD::SETUGT && 1995 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1996 return DAG.getSetCC(dl, VT, N0, 1997 DAG.getConstant(0, N1.getValueType()), 1998 ISD::SETLT); 1999 2000 // SETULT X, SINTMIN -> SETGT X, -1 2001 if (Cond == ISD::SETULT && 2002 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2003 SDValue ConstMinusOne = 2004 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2005 N1.getValueType()); 2006 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2007 } 2008 2009 // Fold bit comparisons when we can. 2010 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2011 (VT == N0.getValueType() || 2012 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2013 N0.getOpcode() == ISD::AND) 2014 if (ConstantSDNode *AndRHS = 2015 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2016 EVT ShiftTy = DCI.isBeforeLegalize() ? 2017 getPointerTy() : getShiftAmountTy(); 2018 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2019 // Perform the xform if the AND RHS is a single bit. 2020 if (AndRHS->getAPIntValue().isPowerOf2()) { 2021 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2022 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2023 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2024 } 2025 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2026 // (X & 8) == 8 --> (X & 8) >> 3 2027 // Perform the xform if C1 is a single bit. 2028 if (C1.isPowerOf2()) { 2029 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2030 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2031 DAG.getConstant(C1.logBase2(), ShiftTy))); 2032 } 2033 } 2034 } 2035 } 2036 2037 if (isa<ConstantFPSDNode>(N0.getNode())) { 2038 // Constant fold or commute setcc. 2039 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2040 if (O.getNode()) return O; 2041 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2042 // If the RHS of an FP comparison is a constant, simplify it away in 2043 // some cases. 2044 if (CFP->getValueAPF().isNaN()) { 2045 // If an operand is known to be a nan, we can fold it. 2046 switch (ISD::getUnorderedFlavor(Cond)) { 2047 default: llvm_unreachable("Unknown flavor!"); 2048 case 0: // Known false. 2049 return DAG.getConstant(0, VT); 2050 case 1: // Known true. 2051 return DAG.getConstant(1, VT); 2052 case 2: // Undefined. 2053 return DAG.getUNDEF(VT); 2054 } 2055 } 2056 2057 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2058 // constant if knowing that the operand is non-nan is enough. We prefer to 2059 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2060 // materialize 0.0. 2061 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2062 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2063 2064 // If the condition is not legal, see if we can find an equivalent one 2065 // which is legal. 2066 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2067 // If the comparison was an awkward floating-point == or != and one of 2068 // the comparison operands is infinity or negative infinity, convert the 2069 // condition to a less-awkward <= or >=. 2070 if (CFP->getValueAPF().isInfinity()) { 2071 if (CFP->getValueAPF().isNegative()) { 2072 if (Cond == ISD::SETOEQ && 2073 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2074 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2075 if (Cond == ISD::SETUEQ && 2076 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2077 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2078 if (Cond == ISD::SETUNE && 2079 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2080 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2081 if (Cond == ISD::SETONE && 2082 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2083 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2084 } else { 2085 if (Cond == ISD::SETOEQ && 2086 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2087 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2088 if (Cond == ISD::SETUEQ && 2089 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2090 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2091 if (Cond == ISD::SETUNE && 2092 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2093 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2094 if (Cond == ISD::SETONE && 2095 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2096 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2097 } 2098 } 2099 } 2100 } 2101 2102 if (N0 == N1) { 2103 // We can always fold X == X for integer setcc's. 2104 if (N0.getValueType().isInteger()) 2105 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2106 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2107 if (UOF == 2) // FP operators that are undefined on NaNs. 2108 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2109 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2110 return DAG.getConstant(UOF, VT); 2111 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2112 // if it is not already. 2113 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2114 if (NewCond != Cond) 2115 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2116 } 2117 2118 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2119 N0.getValueType().isInteger()) { 2120 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2121 N0.getOpcode() == ISD::XOR) { 2122 // Simplify (X+Y) == (X+Z) --> Y == Z 2123 if (N0.getOpcode() == N1.getOpcode()) { 2124 if (N0.getOperand(0) == N1.getOperand(0)) 2125 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2126 if (N0.getOperand(1) == N1.getOperand(1)) 2127 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2128 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2129 // If X op Y == Y op X, try other combinations. 2130 if (N0.getOperand(0) == N1.getOperand(1)) 2131 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2132 Cond); 2133 if (N0.getOperand(1) == N1.getOperand(0)) 2134 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2135 Cond); 2136 } 2137 } 2138 2139 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2140 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2141 // Turn (X+C1) == C2 --> X == C2-C1 2142 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2143 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2144 DAG.getConstant(RHSC->getAPIntValue()- 2145 LHSR->getAPIntValue(), 2146 N0.getValueType()), Cond); 2147 } 2148 2149 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2150 if (N0.getOpcode() == ISD::XOR) 2151 // If we know that all of the inverted bits are zero, don't bother 2152 // performing the inversion. 2153 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2154 return 2155 DAG.getSetCC(dl, VT, N0.getOperand(0), 2156 DAG.getConstant(LHSR->getAPIntValue() ^ 2157 RHSC->getAPIntValue(), 2158 N0.getValueType()), 2159 Cond); 2160 } 2161 2162 // Turn (C1-X) == C2 --> X == C1-C2 2163 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2164 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2165 return 2166 DAG.getSetCC(dl, VT, N0.getOperand(1), 2167 DAG.getConstant(SUBC->getAPIntValue() - 2168 RHSC->getAPIntValue(), 2169 N0.getValueType()), 2170 Cond); 2171 } 2172 } 2173 } 2174 2175 // Simplify (X+Z) == X --> Z == 0 2176 if (N0.getOperand(0) == N1) 2177 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2178 DAG.getConstant(0, N0.getValueType()), Cond); 2179 if (N0.getOperand(1) == N1) { 2180 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2181 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2182 DAG.getConstant(0, N0.getValueType()), Cond); 2183 else if (N0.getNode()->hasOneUse()) { 2184 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2185 // (Z-X) == X --> Z == X<<1 2186 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2187 N1, 2188 DAG.getConstant(1, getShiftAmountTy())); 2189 if (!DCI.isCalledByLegalizer()) 2190 DCI.AddToWorklist(SH.getNode()); 2191 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2192 } 2193 } 2194 } 2195 2196 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2197 N1.getOpcode() == ISD::XOR) { 2198 // Simplify X == (X+Z) --> Z == 0 2199 if (N1.getOperand(0) == N0) { 2200 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2201 DAG.getConstant(0, N1.getValueType()), Cond); 2202 } else if (N1.getOperand(1) == N0) { 2203 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2204 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2205 DAG.getConstant(0, N1.getValueType()), Cond); 2206 } else if (N1.getNode()->hasOneUse()) { 2207 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2208 // X == (Z-X) --> X<<1 == Z 2209 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2210 DAG.getConstant(1, getShiftAmountTy())); 2211 if (!DCI.isCalledByLegalizer()) 2212 DCI.AddToWorklist(SH.getNode()); 2213 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2214 } 2215 } 2216 } 2217 2218 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2219 // Note that where y is variable and is known to have at most 2220 // one bit set (for example, if it is z&1) we cannot do this; 2221 // the expressions are not equivalent when y==0. 2222 if (N0.getOpcode() == ISD::AND) 2223 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2224 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2225 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2226 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2227 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2228 } 2229 } 2230 if (N1.getOpcode() == ISD::AND) 2231 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2232 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2233 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2234 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2235 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2236 } 2237 } 2238 } 2239 2240 // Fold away ALL boolean setcc's. 2241 SDValue Temp; 2242 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2243 switch (Cond) { 2244 default: llvm_unreachable("Unknown integer setcc!"); 2245 case ISD::SETEQ: // X == Y -> ~(X^Y) 2246 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2247 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2248 if (!DCI.isCalledByLegalizer()) 2249 DCI.AddToWorklist(Temp.getNode()); 2250 break; 2251 case ISD::SETNE: // X != Y --> (X^Y) 2252 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2253 break; 2254 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2255 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2256 Temp = DAG.getNOT(dl, N0, MVT::i1); 2257 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2258 if (!DCI.isCalledByLegalizer()) 2259 DCI.AddToWorklist(Temp.getNode()); 2260 break; 2261 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2262 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2263 Temp = DAG.getNOT(dl, N1, MVT::i1); 2264 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2265 if (!DCI.isCalledByLegalizer()) 2266 DCI.AddToWorklist(Temp.getNode()); 2267 break; 2268 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2269 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2270 Temp = DAG.getNOT(dl, N0, MVT::i1); 2271 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2272 if (!DCI.isCalledByLegalizer()) 2273 DCI.AddToWorklist(Temp.getNode()); 2274 break; 2275 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2276 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2277 Temp = DAG.getNOT(dl, N1, MVT::i1); 2278 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2279 break; 2280 } 2281 if (VT != MVT::i1) { 2282 if (!DCI.isCalledByLegalizer()) 2283 DCI.AddToWorklist(N0.getNode()); 2284 // FIXME: If running after legalize, we probably can't do this. 2285 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2286 } 2287 return N0; 2288 } 2289 2290 // Could not fold it. 2291 return SDValue(); 2292} 2293 2294/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2295/// node is a GlobalAddress + offset. 2296bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2297 int64_t &Offset) const { 2298 if (isa<GlobalAddressSDNode>(N)) { 2299 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2300 GA = GASD->getGlobal(); 2301 Offset += GASD->getOffset(); 2302 return true; 2303 } 2304 2305 if (N->getOpcode() == ISD::ADD) { 2306 SDValue N1 = N->getOperand(0); 2307 SDValue N2 = N->getOperand(1); 2308 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2309 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2310 if (V) { 2311 Offset += V->getSExtValue(); 2312 return true; 2313 } 2314 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2315 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2316 if (V) { 2317 Offset += V->getSExtValue(); 2318 return true; 2319 } 2320 } 2321 } 2322 return false; 2323} 2324 2325 2326SDValue TargetLowering:: 2327PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2328 // Default implementation: no optimization. 2329 return SDValue(); 2330} 2331 2332//===----------------------------------------------------------------------===// 2333// Inline Assembler Implementation Methods 2334//===----------------------------------------------------------------------===// 2335 2336 2337TargetLowering::ConstraintType 2338TargetLowering::getConstraintType(const std::string &Constraint) const { 2339 // FIXME: lots more standard ones to handle. 2340 if (Constraint.size() == 1) { 2341 switch (Constraint[0]) { 2342 default: break; 2343 case 'r': return C_RegisterClass; 2344 case 'm': // memory 2345 case 'o': // offsetable 2346 case 'V': // not offsetable 2347 return C_Memory; 2348 case 'i': // Simple Integer or Relocatable Constant 2349 case 'n': // Simple Integer 2350 case 's': // Relocatable Constant 2351 case 'X': // Allow ANY value. 2352 case 'I': // Target registers. 2353 case 'J': 2354 case 'K': 2355 case 'L': 2356 case 'M': 2357 case 'N': 2358 case 'O': 2359 case 'P': 2360 return C_Other; 2361 } 2362 } 2363 2364 if (Constraint.size() > 1 && Constraint[0] == '{' && 2365 Constraint[Constraint.size()-1] == '}') 2366 return C_Register; 2367 return C_Unknown; 2368} 2369 2370/// LowerXConstraint - try to replace an X constraint, which matches anything, 2371/// with another that has more specific requirements based on the type of the 2372/// corresponding operand. 2373const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2374 if (ConstraintVT.isInteger()) 2375 return "r"; 2376 if (ConstraintVT.isFloatingPoint()) 2377 return "f"; // works for many targets 2378 return 0; 2379} 2380 2381/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2382/// vector. If it is invalid, don't add anything to Ops. 2383void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2384 char ConstraintLetter, 2385 bool hasMemory, 2386 std::vector<SDValue> &Ops, 2387 SelectionDAG &DAG) const { 2388 switch (ConstraintLetter) { 2389 default: break; 2390 case 'X': // Allows any operand; labels (basic block) use this. 2391 if (Op.getOpcode() == ISD::BasicBlock) { 2392 Ops.push_back(Op); 2393 return; 2394 } 2395 // fall through 2396 case 'i': // Simple Integer or Relocatable Constant 2397 case 'n': // Simple Integer 2398 case 's': { // Relocatable Constant 2399 // These operands are interested in values of the form (GV+C), where C may 2400 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2401 // is possible and fine if either GV or C are missing. 2402 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2403 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2404 2405 // If we have "(add GV, C)", pull out GV/C 2406 if (Op.getOpcode() == ISD::ADD) { 2407 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2408 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2409 if (C == 0 || GA == 0) { 2410 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2411 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2412 } 2413 if (C == 0 || GA == 0) 2414 C = 0, GA = 0; 2415 } 2416 2417 // If we find a valid operand, map to the TargetXXX version so that the 2418 // value itself doesn't get selected. 2419 if (GA) { // Either &GV or &GV+C 2420 if (ConstraintLetter != 'n') { 2421 int64_t Offs = GA->getOffset(); 2422 if (C) Offs += C->getZExtValue(); 2423 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2424 Op.getValueType(), Offs)); 2425 return; 2426 } 2427 } 2428 if (C) { // just C, no GV. 2429 // Simple constants are not allowed for 's'. 2430 if (ConstraintLetter != 's') { 2431 // gcc prints these as sign extended. Sign extend value to 64 bits 2432 // now; without this it would get ZExt'd later in 2433 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2434 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2435 MVT::i64)); 2436 return; 2437 } 2438 } 2439 break; 2440 } 2441 } 2442} 2443 2444std::vector<unsigned> TargetLowering:: 2445getRegClassForInlineAsmConstraint(const std::string &Constraint, 2446 EVT VT) const { 2447 return std::vector<unsigned>(); 2448} 2449 2450 2451std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2452getRegForInlineAsmConstraint(const std::string &Constraint, 2453 EVT VT) const { 2454 if (Constraint[0] != '{') 2455 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2456 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2457 2458 // Remove the braces from around the name. 2459 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2460 2461 // Figure out which register class contains this reg. 2462 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2463 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2464 E = RI->regclass_end(); RCI != E; ++RCI) { 2465 const TargetRegisterClass *RC = *RCI; 2466 2467 // If none of the value types for this register class are valid, we 2468 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2469 bool isLegal = false; 2470 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2471 I != E; ++I) { 2472 if (isTypeLegal(*I)) { 2473 isLegal = true; 2474 break; 2475 } 2476 } 2477 2478 if (!isLegal) continue; 2479 2480 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2481 I != E; ++I) { 2482 if (RegName.equals_lower(RI->getName(*I))) 2483 return std::make_pair(*I, RC); 2484 } 2485 } 2486 2487 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2488} 2489 2490//===----------------------------------------------------------------------===// 2491// Constraint Selection. 2492 2493/// isMatchingInputConstraint - Return true of this is an input operand that is 2494/// a matching constraint like "4". 2495bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2496 assert(!ConstraintCode.empty() && "No known constraint!"); 2497 return isdigit(ConstraintCode[0]); 2498} 2499 2500/// getMatchedOperand - If this is an input matching constraint, this method 2501/// returns the output operand it matches. 2502unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2503 assert(!ConstraintCode.empty() && "No known constraint!"); 2504 return atoi(ConstraintCode.c_str()); 2505} 2506 2507 2508/// getConstraintGenerality - Return an integer indicating how general CT 2509/// is. 2510static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2511 switch (CT) { 2512 default: llvm_unreachable("Unknown constraint type!"); 2513 case TargetLowering::C_Other: 2514 case TargetLowering::C_Unknown: 2515 return 0; 2516 case TargetLowering::C_Register: 2517 return 1; 2518 case TargetLowering::C_RegisterClass: 2519 return 2; 2520 case TargetLowering::C_Memory: 2521 return 3; 2522 } 2523} 2524 2525/// ChooseConstraint - If there are multiple different constraints that we 2526/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2527/// This is somewhat tricky: constraints fall into four classes: 2528/// Other -> immediates and magic values 2529/// Register -> one specific register 2530/// RegisterClass -> a group of regs 2531/// Memory -> memory 2532/// Ideally, we would pick the most specific constraint possible: if we have 2533/// something that fits into a register, we would pick it. The problem here 2534/// is that if we have something that could either be in a register or in 2535/// memory that use of the register could cause selection of *other* 2536/// operands to fail: they might only succeed if we pick memory. Because of 2537/// this the heuristic we use is: 2538/// 2539/// 1) If there is an 'other' constraint, and if the operand is valid for 2540/// that constraint, use it. This makes us take advantage of 'i' 2541/// constraints when available. 2542/// 2) Otherwise, pick the most general constraint present. This prefers 2543/// 'm' over 'r', for example. 2544/// 2545static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2546 bool hasMemory, const TargetLowering &TLI, 2547 SDValue Op, SelectionDAG *DAG) { 2548 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2549 unsigned BestIdx = 0; 2550 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2551 int BestGenerality = -1; 2552 2553 // Loop over the options, keeping track of the most general one. 2554 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2555 TargetLowering::ConstraintType CType = 2556 TLI.getConstraintType(OpInfo.Codes[i]); 2557 2558 // If this is an 'other' constraint, see if the operand is valid for it. 2559 // For example, on X86 we might have an 'rI' constraint. If the operand 2560 // is an integer in the range [0..31] we want to use I (saving a load 2561 // of a register), otherwise we must use 'r'. 2562 if (CType == TargetLowering::C_Other && Op.getNode()) { 2563 assert(OpInfo.Codes[i].size() == 1 && 2564 "Unhandled multi-letter 'other' constraint"); 2565 std::vector<SDValue> ResultOps; 2566 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2567 ResultOps, *DAG); 2568 if (!ResultOps.empty()) { 2569 BestType = CType; 2570 BestIdx = i; 2571 break; 2572 } 2573 } 2574 2575 // This constraint letter is more general than the previous one, use it. 2576 int Generality = getConstraintGenerality(CType); 2577 if (Generality > BestGenerality) { 2578 BestType = CType; 2579 BestIdx = i; 2580 BestGenerality = Generality; 2581 } 2582 } 2583 2584 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2585 OpInfo.ConstraintType = BestType; 2586} 2587 2588/// ComputeConstraintToUse - Determines the constraint code and constraint 2589/// type to use for the specific AsmOperandInfo, setting 2590/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2591void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2592 SDValue Op, 2593 bool hasMemory, 2594 SelectionDAG *DAG) const { 2595 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2596 2597 // Single-letter constraints ('r') are very common. 2598 if (OpInfo.Codes.size() == 1) { 2599 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2600 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2601 } else { 2602 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2603 } 2604 2605 // 'X' matches anything. 2606 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2607 // Labels and constants are handled elsewhere ('X' is the only thing 2608 // that matches labels). For Functions, the type here is the type of 2609 // the result, which is not what we want to look at; leave them alone. 2610 Value *v = OpInfo.CallOperandVal; 2611 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2612 OpInfo.CallOperandVal = v; 2613 return; 2614 } 2615 2616 // Otherwise, try to resolve it to something we know about by looking at 2617 // the actual operand type. 2618 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2619 OpInfo.ConstraintCode = Repl; 2620 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2621 } 2622 } 2623} 2624 2625//===----------------------------------------------------------------------===// 2626// Loop Strength Reduction hooks 2627//===----------------------------------------------------------------------===// 2628 2629/// isLegalAddressingMode - Return true if the addressing mode represented 2630/// by AM is legal for this target, for a load/store of the specified type. 2631bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2632 const Type *Ty) const { 2633 // The default implementation of this implements a conservative RISCy, r+r and 2634 // r+i addr mode. 2635 2636 // Allows a sign-extended 16-bit immediate field. 2637 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2638 return false; 2639 2640 // No global is ever allowed as a base. 2641 if (AM.BaseGV) 2642 return false; 2643 2644 // Only support r+r, 2645 switch (AM.Scale) { 2646 case 0: // "r+i" or just "i", depending on HasBaseReg. 2647 break; 2648 case 1: 2649 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2650 return false; 2651 // Otherwise we have r+r or r+i. 2652 break; 2653 case 2: 2654 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2655 return false; 2656 // Allow 2*r as r+r. 2657 break; 2658 } 2659 2660 return true; 2661} 2662 2663/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2664/// return a DAG expression to select that will generate the same value by 2665/// multiplying by a magic number. See: 2666/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2667SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2668 std::vector<SDNode*>* Created) const { 2669 EVT VT = N->getValueType(0); 2670 DebugLoc dl= N->getDebugLoc(); 2671 2672 // Check to see if we can do this. 2673 // FIXME: We should be more aggressive here. 2674 if (!isTypeLegal(VT)) 2675 return SDValue(); 2676 2677 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2678 APInt::ms magics = d.magic(); 2679 2680 // Multiply the numerator (operand 0) by the magic value 2681 // FIXME: We should support doing a MUL in a wider type 2682 SDValue Q; 2683 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2684 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2685 DAG.getConstant(magics.m, VT)); 2686 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2687 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2688 N->getOperand(0), 2689 DAG.getConstant(magics.m, VT)).getNode(), 1); 2690 else 2691 return SDValue(); // No mulhs or equvialent 2692 // If d > 0 and m < 0, add the numerator 2693 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2694 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2695 if (Created) 2696 Created->push_back(Q.getNode()); 2697 } 2698 // If d < 0 and m > 0, subtract the numerator. 2699 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2700 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2701 if (Created) 2702 Created->push_back(Q.getNode()); 2703 } 2704 // Shift right algebraic if shift value is nonzero 2705 if (magics.s > 0) { 2706 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2707 DAG.getConstant(magics.s, getShiftAmountTy())); 2708 if (Created) 2709 Created->push_back(Q.getNode()); 2710 } 2711 // Extract the sign bit and add it to the quotient 2712 SDValue T = 2713 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2714 getShiftAmountTy())); 2715 if (Created) 2716 Created->push_back(T.getNode()); 2717 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2718} 2719 2720/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2721/// return a DAG expression to select that will generate the same value by 2722/// multiplying by a magic number. See: 2723/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2724SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2725 std::vector<SDNode*>* Created) const { 2726 EVT VT = N->getValueType(0); 2727 DebugLoc dl = N->getDebugLoc(); 2728 2729 // Check to see if we can do this. 2730 // FIXME: We should be more aggressive here. 2731 if (!isTypeLegal(VT)) 2732 return SDValue(); 2733 2734 // FIXME: We should use a narrower constant when the upper 2735 // bits are known to be zero. 2736 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2737 APInt::mu magics = N1C->getAPIntValue().magicu(); 2738 2739 // Multiply the numerator (operand 0) by the magic value 2740 // FIXME: We should support doing a MUL in a wider type 2741 SDValue Q; 2742 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2743 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2744 DAG.getConstant(magics.m, VT)); 2745 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2746 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2747 N->getOperand(0), 2748 DAG.getConstant(magics.m, VT)).getNode(), 1); 2749 else 2750 return SDValue(); // No mulhu or equvialent 2751 if (Created) 2752 Created->push_back(Q.getNode()); 2753 2754 if (magics.a == 0) { 2755 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2756 "We shouldn't generate an undefined shift!"); 2757 return DAG.getNode(ISD::SRL, dl, VT, Q, 2758 DAG.getConstant(magics.s, getShiftAmountTy())); 2759 } else { 2760 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2761 if (Created) 2762 Created->push_back(NPQ.getNode()); 2763 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2764 DAG.getConstant(1, getShiftAmountTy())); 2765 if (Created) 2766 Created->push_back(NPQ.getNode()); 2767 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2768 if (Created) 2769 Created->push_back(NPQ.getNode()); 2770 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2771 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2772 } 2773} 2774