TargetLowering.cpp revision e36bfe678df09f46e1eac60b15105c1ccd2c5382
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetAsmInfo.h" 15#include "llvm/Target/TargetLowering.h" 16#include "llvm/Target/TargetSubtarget.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/GlobalVariable.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/ADT/StringExtras.h" 25#include "llvm/ADT/STLExtras.h" 26#include "llvm/Support/MathExtras.h" 27using namespace llvm; 28 29/// InitLibcallNames - Set default libcall names. 30/// 31static void InitLibcallNames(const char **Names) { 32 Names[RTLIB::SHL_I32] = "__ashlsi3"; 33 Names[RTLIB::SHL_I64] = "__ashldi3"; 34 Names[RTLIB::SHL_I128] = "__ashlti3"; 35 Names[RTLIB::SRL_I32] = "__lshrsi3"; 36 Names[RTLIB::SRL_I64] = "__lshrdi3"; 37 Names[RTLIB::SRL_I128] = "__lshrti3"; 38 Names[RTLIB::SRA_I32] = "__ashrsi3"; 39 Names[RTLIB::SRA_I64] = "__ashrdi3"; 40 Names[RTLIB::SRA_I128] = "__ashrti3"; 41 Names[RTLIB::MUL_I32] = "__mulsi3"; 42 Names[RTLIB::MUL_I64] = "__muldi3"; 43 Names[RTLIB::MUL_I128] = "__multi3"; 44 Names[RTLIB::SDIV_I32] = "__divsi3"; 45 Names[RTLIB::SDIV_I64] = "__divdi3"; 46 Names[RTLIB::SDIV_I128] = "__divti3"; 47 Names[RTLIB::UDIV_I32] = "__udivsi3"; 48 Names[RTLIB::UDIV_I64] = "__udivdi3"; 49 Names[RTLIB::UDIV_I128] = "__udivti3"; 50 Names[RTLIB::SREM_I32] = "__modsi3"; 51 Names[RTLIB::SREM_I64] = "__moddi3"; 52 Names[RTLIB::SREM_I128] = "__modti3"; 53 Names[RTLIB::UREM_I32] = "__umodsi3"; 54 Names[RTLIB::UREM_I64] = "__umoddi3"; 55 Names[RTLIB::UREM_I128] = "__umodti3"; 56 Names[RTLIB::NEG_I32] = "__negsi2"; 57 Names[RTLIB::NEG_I64] = "__negdi2"; 58 Names[RTLIB::ADD_F32] = "__addsf3"; 59 Names[RTLIB::ADD_F64] = "__adddf3"; 60 Names[RTLIB::ADD_F80] = "__addxf3"; 61 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 62 Names[RTLIB::SUB_F32] = "__subsf3"; 63 Names[RTLIB::SUB_F64] = "__subdf3"; 64 Names[RTLIB::SUB_F80] = "__subxf3"; 65 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 66 Names[RTLIB::MUL_F32] = "__mulsf3"; 67 Names[RTLIB::MUL_F64] = "__muldf3"; 68 Names[RTLIB::MUL_F80] = "__mulxf3"; 69 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 70 Names[RTLIB::DIV_F32] = "__divsf3"; 71 Names[RTLIB::DIV_F64] = "__divdf3"; 72 Names[RTLIB::DIV_F80] = "__divxf3"; 73 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 74 Names[RTLIB::REM_F32] = "fmodf"; 75 Names[RTLIB::REM_F64] = "fmod"; 76 Names[RTLIB::REM_F80] = "fmodl"; 77 Names[RTLIB::REM_PPCF128] = "fmodl"; 78 Names[RTLIB::POWI_F32] = "__powisf2"; 79 Names[RTLIB::POWI_F64] = "__powidf2"; 80 Names[RTLIB::POWI_F80] = "__powixf2"; 81 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 82 Names[RTLIB::SQRT_F32] = "sqrtf"; 83 Names[RTLIB::SQRT_F64] = "sqrt"; 84 Names[RTLIB::SQRT_F80] = "sqrtl"; 85 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 86 Names[RTLIB::SIN_F32] = "sinf"; 87 Names[RTLIB::SIN_F64] = "sin"; 88 Names[RTLIB::SIN_F80] = "sinl"; 89 Names[RTLIB::SIN_PPCF128] = "sinl"; 90 Names[RTLIB::COS_F32] = "cosf"; 91 Names[RTLIB::COS_F64] = "cos"; 92 Names[RTLIB::COS_F80] = "cosl"; 93 Names[RTLIB::COS_PPCF128] = "cosl"; 94 Names[RTLIB::POW_F32] = "powf"; 95 Names[RTLIB::POW_F64] = "pow"; 96 Names[RTLIB::POW_F80] = "powl"; 97 Names[RTLIB::POW_PPCF128] = "powl"; 98 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 99 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 100 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 101 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 102 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 103 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 104 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 105 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 106 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 107 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 108 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 109 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 110 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 111 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 112 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 113 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 114 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 115 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 116 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 117 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 118 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 119 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 120 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 121 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 122 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 123 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 124 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 125 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 126 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 127 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 128 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 129 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 130 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 131 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 132 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 133 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 134 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 135 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 136 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 137 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 138 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 139 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 140 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 141 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 142 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 143 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 144 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 145 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 146 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 147 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 148 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 149 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 150 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 151 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 152 Names[RTLIB::OEQ_F32] = "__eqsf2"; 153 Names[RTLIB::OEQ_F64] = "__eqdf2"; 154 Names[RTLIB::UNE_F32] = "__nesf2"; 155 Names[RTLIB::UNE_F64] = "__nedf2"; 156 Names[RTLIB::OGE_F32] = "__gesf2"; 157 Names[RTLIB::OGE_F64] = "__gedf2"; 158 Names[RTLIB::OLT_F32] = "__ltsf2"; 159 Names[RTLIB::OLT_F64] = "__ltdf2"; 160 Names[RTLIB::OLE_F32] = "__lesf2"; 161 Names[RTLIB::OLE_F64] = "__ledf2"; 162 Names[RTLIB::OGT_F32] = "__gtsf2"; 163 Names[RTLIB::OGT_F64] = "__gtdf2"; 164 Names[RTLIB::UO_F32] = "__unordsf2"; 165 Names[RTLIB::UO_F64] = "__unorddf2"; 166 Names[RTLIB::O_F32] = "__unordsf2"; 167 Names[RTLIB::O_F64] = "__unorddf2"; 168} 169 170/// getFPEXT - Return the FPEXT_*_* value for the given types, or 171/// UNKNOWN_LIBCALL if there is none. 172RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 173 if (OpVT == MVT::f32) { 174 if (RetVT == MVT::f64) 175 return FPEXT_F32_F64; 176 } 177 return UNKNOWN_LIBCALL; 178} 179 180/// getFPROUND - Return the FPROUND_*_* value for the given types, or 181/// UNKNOWN_LIBCALL if there is none. 182RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 183 if (RetVT == MVT::f32) { 184 if (OpVT == MVT::f64) 185 return FPROUND_F64_F32; 186 if (OpVT == MVT::f80) 187 return FPROUND_F80_F32; 188 if (OpVT == MVT::ppcf128) 189 return FPROUND_PPCF128_F32; 190 } else if (RetVT == MVT::f64) { 191 if (OpVT == MVT::f80) 192 return FPROUND_F80_F64; 193 if (OpVT == MVT::ppcf128) 194 return FPROUND_PPCF128_F64; 195 } 196 return UNKNOWN_LIBCALL; 197} 198 199/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 200/// UNKNOWN_LIBCALL if there is none. 201RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 202 if (OpVT == MVT::f32) { 203 if (RetVT == MVT::i32) 204 return FPTOSINT_F32_I32; 205 if (RetVT == MVT::i64) 206 return FPTOSINT_F32_I64; 207 if (RetVT == MVT::i128) 208 return FPTOSINT_F32_I128; 209 } else if (OpVT == MVT::f64) { 210 if (RetVT == MVT::i32) 211 return FPTOSINT_F64_I32; 212 if (RetVT == MVT::i64) 213 return FPTOSINT_F64_I64; 214 if (RetVT == MVT::i128) 215 return FPTOSINT_F64_I128; 216 } else if (OpVT == MVT::f80) { 217 if (RetVT == MVT::i32) 218 return FPTOSINT_F80_I32; 219 if (RetVT == MVT::i64) 220 return FPTOSINT_F80_I64; 221 if (RetVT == MVT::i128) 222 return FPTOSINT_F80_I128; 223 } else if (OpVT == MVT::ppcf128) { 224 if (RetVT == MVT::i32) 225 return FPTOSINT_PPCF128_I32; 226 if (RetVT == MVT::i64) 227 return FPTOSINT_PPCF128_I64; 228 if (RetVT == MVT::i128) 229 return FPTOSINT_PPCF128_I128; 230 } 231 return UNKNOWN_LIBCALL; 232} 233 234/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 235/// UNKNOWN_LIBCALL if there is none. 236RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 237 if (OpVT == MVT::f32) { 238 if (RetVT == MVT::i32) 239 return FPTOUINT_F32_I32; 240 if (RetVT == MVT::i64) 241 return FPTOUINT_F32_I64; 242 if (RetVT == MVT::i128) 243 return FPTOUINT_F32_I128; 244 } else if (OpVT == MVT::f64) { 245 if (RetVT == MVT::i32) 246 return FPTOUINT_F64_I32; 247 if (RetVT == MVT::i64) 248 return FPTOUINT_F64_I64; 249 if (RetVT == MVT::i128) 250 return FPTOUINT_F64_I128; 251 } else if (OpVT == MVT::f80) { 252 if (RetVT == MVT::i32) 253 return FPTOUINT_F80_I32; 254 if (RetVT == MVT::i64) 255 return FPTOUINT_F80_I64; 256 if (RetVT == MVT::i128) 257 return FPTOUINT_F80_I128; 258 } else if (OpVT == MVT::ppcf128) { 259 if (RetVT == MVT::i32) 260 return FPTOUINT_PPCF128_I32; 261 if (RetVT == MVT::i64) 262 return FPTOUINT_PPCF128_I64; 263 if (RetVT == MVT::i128) 264 return FPTOUINT_PPCF128_I128; 265 } 266 return UNKNOWN_LIBCALL; 267} 268 269/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 270/// UNKNOWN_LIBCALL if there is none. 271RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 272 if (OpVT == MVT::i32) { 273 if (RetVT == MVT::f32) 274 return SINTTOFP_I32_F32; 275 else if (RetVT == MVT::f64) 276 return SINTTOFP_I32_F64; 277 else if (RetVT == MVT::f80) 278 return SINTTOFP_I32_F80; 279 else if (RetVT == MVT::ppcf128) 280 return SINTTOFP_I32_PPCF128; 281 } else if (OpVT == MVT::i64) { 282 if (RetVT == MVT::f32) 283 return SINTTOFP_I64_F32; 284 else if (RetVT == MVT::f64) 285 return SINTTOFP_I64_F64; 286 else if (RetVT == MVT::f80) 287 return SINTTOFP_I64_F80; 288 else if (RetVT == MVT::ppcf128) 289 return SINTTOFP_I64_PPCF128; 290 } else if (OpVT == MVT::i128) { 291 if (RetVT == MVT::f32) 292 return SINTTOFP_I128_F32; 293 else if (RetVT == MVT::f64) 294 return SINTTOFP_I128_F64; 295 else if (RetVT == MVT::f80) 296 return SINTTOFP_I128_F80; 297 else if (RetVT == MVT::ppcf128) 298 return SINTTOFP_I128_PPCF128; 299 } 300 return UNKNOWN_LIBCALL; 301} 302 303/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 304/// UNKNOWN_LIBCALL if there is none. 305RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 306 if (OpVT == MVT::i32) { 307 if (RetVT == MVT::f32) 308 return UINTTOFP_I32_F32; 309 else if (RetVT == MVT::f64) 310 return UINTTOFP_I32_F64; 311 else if (RetVT == MVT::f80) 312 return UINTTOFP_I32_F80; 313 else if (RetVT == MVT::ppcf128) 314 return UINTTOFP_I32_PPCF128; 315 } else if (OpVT == MVT::i64) { 316 if (RetVT == MVT::f32) 317 return UINTTOFP_I64_F32; 318 else if (RetVT == MVT::f64) 319 return UINTTOFP_I64_F64; 320 else if (RetVT == MVT::f80) 321 return UINTTOFP_I64_F80; 322 else if (RetVT == MVT::ppcf128) 323 return UINTTOFP_I64_PPCF128; 324 } else if (OpVT == MVT::i128) { 325 if (RetVT == MVT::f32) 326 return UINTTOFP_I128_F32; 327 else if (RetVT == MVT::f64) 328 return UINTTOFP_I128_F64; 329 else if (RetVT == MVT::f80) 330 return UINTTOFP_I128_F80; 331 else if (RetVT == MVT::ppcf128) 332 return UINTTOFP_I128_PPCF128; 333 } 334 return UNKNOWN_LIBCALL; 335} 336 337/// InitCmpLibcallCCs - Set default comparison libcall CC. 338/// 339static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 340 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 341 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 342 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 343 CCs[RTLIB::UNE_F32] = ISD::SETNE; 344 CCs[RTLIB::UNE_F64] = ISD::SETNE; 345 CCs[RTLIB::OGE_F32] = ISD::SETGE; 346 CCs[RTLIB::OGE_F64] = ISD::SETGE; 347 CCs[RTLIB::OLT_F32] = ISD::SETLT; 348 CCs[RTLIB::OLT_F64] = ISD::SETLT; 349 CCs[RTLIB::OLE_F32] = ISD::SETLE; 350 CCs[RTLIB::OLE_F64] = ISD::SETLE; 351 CCs[RTLIB::OGT_F32] = ISD::SETGT; 352 CCs[RTLIB::OGT_F64] = ISD::SETGT; 353 CCs[RTLIB::UO_F32] = ISD::SETNE; 354 CCs[RTLIB::UO_F64] = ISD::SETNE; 355 CCs[RTLIB::O_F32] = ISD::SETEQ; 356 CCs[RTLIB::O_F64] = ISD::SETEQ; 357} 358 359TargetLowering::TargetLowering(TargetMachine &tm) 360 : TM(tm), TD(TM.getTargetData()) { 361 assert(ISD::BUILTIN_OP_END <= OpActionsCapacity && 362 "Fixed size array in TargetLowering is not large enough!"); 363 // All operations default to being supported. 364 memset(OpActions, 0, sizeof(OpActions)); 365 memset(LoadXActions, 0, sizeof(LoadXActions)); 366 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 367 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 368 memset(ConvertActions, 0, sizeof(ConvertActions)); 369 370 // Set default actions for various operations. 371 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 372 // Default all indexed load / store to expand. 373 for (unsigned IM = (unsigned)ISD::PRE_INC; 374 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 375 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 376 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 377 } 378 379 // These operations default to expand. 380 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 381 } 382 383 // Most targets ignore the @llvm.prefetch intrinsic. 384 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 385 386 // ConstantFP nodes default to expand. Targets can either change this to 387 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 388 // to optimize expansions for certain constants. 389 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 390 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 391 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 392 393 // Default ISD::TRAP to expand (which turns it into abort). 394 setOperationAction(ISD::TRAP, MVT::Other, Expand); 395 396 IsLittleEndian = TD->isLittleEndian(); 397 UsesGlobalOffsetTable = false; 398 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 399 ShiftAmtHandling = Undefined; 400 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 401 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 402 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 403 allowUnalignedMemoryAccesses = false; 404 UseUnderscoreSetJmp = false; 405 UseUnderscoreLongJmp = false; 406 SelectIsExpensive = false; 407 IntDivIsCheap = false; 408 Pow2DivIsCheap = false; 409 StackPointerRegisterToSaveRestore = 0; 410 ExceptionPointerRegister = 0; 411 ExceptionSelectorRegister = 0; 412 SetCCResultContents = UndefinedSetCCResult; 413 SchedPreferenceInfo = SchedulingForLatency; 414 JumpBufSize = 0; 415 JumpBufAlignment = 0; 416 IfCvtBlockSizeLimit = 2; 417 IfCvtDupBlockSizeLimit = 0; 418 PrefLoopAlignment = 0; 419 420 InitLibcallNames(LibcallRoutineNames); 421 InitCmpLibcallCCs(CmpLibcallCCs); 422 423 // Tell Legalize whether the assembler supports DEBUG_LOC. 424 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) 425 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 426} 427 428TargetLowering::~TargetLowering() {} 429 430/// computeRegisterProperties - Once all of the register classes are added, 431/// this allows us to compute derived properties we expose. 432void TargetLowering::computeRegisterProperties() { 433 assert(MVT::LAST_VALUETYPE <= 32 && 434 "Too many value types for ValueTypeActions to hold!"); 435 436 // Everything defaults to needing one register. 437 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 438 NumRegistersForVT[i] = 1; 439 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 440 } 441 // ...except isVoid, which doesn't need any registers. 442 NumRegistersForVT[MVT::isVoid] = 0; 443 444 // Find the largest integer register class. 445 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 446 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 447 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 448 449 // Every integer value type larger than this largest register takes twice as 450 // many registers to represent as the previous ValueType. 451 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 452 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 453 if (!EVT.isInteger()) 454 break; 455 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 456 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 457 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 458 ValueTypeActions.setTypeAction(EVT, Expand); 459 } 460 461 // Inspect all of the ValueType's smaller than the largest integer 462 // register to see which ones need promotion. 463 unsigned LegalIntReg = LargestIntReg; 464 for (unsigned IntReg = LargestIntReg - 1; 465 IntReg >= (unsigned)MVT::i1; --IntReg) { 466 MVT IVT = (MVT::SimpleValueType)IntReg; 467 if (isTypeLegal(IVT)) { 468 LegalIntReg = IntReg; 469 } else { 470 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 471 (MVT::SimpleValueType)LegalIntReg; 472 ValueTypeActions.setTypeAction(IVT, Promote); 473 } 474 } 475 476 // ppcf128 type is really two f64's. 477 if (!isTypeLegal(MVT::ppcf128)) { 478 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 479 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 480 TransformToType[MVT::ppcf128] = MVT::f64; 481 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 482 } 483 484 // Decide how to handle f64. If the target does not have native f64 support, 485 // expand it to i64 and we will be generating soft float library calls. 486 if (!isTypeLegal(MVT::f64)) { 487 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 488 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 489 TransformToType[MVT::f64] = MVT::i64; 490 ValueTypeActions.setTypeAction(MVT::f64, Expand); 491 } 492 493 // Decide how to handle f32. If the target does not have native support for 494 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 495 if (!isTypeLegal(MVT::f32)) { 496 if (isTypeLegal(MVT::f64)) { 497 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 498 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 499 TransformToType[MVT::f32] = MVT::f64; 500 ValueTypeActions.setTypeAction(MVT::f32, Promote); 501 } else { 502 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 503 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 504 TransformToType[MVT::f32] = MVT::i32; 505 ValueTypeActions.setTypeAction(MVT::f32, Expand); 506 } 507 } 508 509 // Loop over all of the vector value types to see which need transformations. 510 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 511 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 512 MVT VT = (MVT::SimpleValueType)i; 513 if (!isTypeLegal(VT)) { 514 MVT IntermediateVT, RegisterVT; 515 unsigned NumIntermediates; 516 NumRegistersForVT[i] = 517 getVectorTypeBreakdown(VT, 518 IntermediateVT, NumIntermediates, 519 RegisterVT); 520 RegisterTypeForVT[i] = RegisterVT; 521 TransformToType[i] = MVT::Other; // this isn't actually used 522 ValueTypeActions.setTypeAction(VT, Expand); 523 } 524 } 525} 526 527const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 528 return NULL; 529} 530 531 532MVT TargetLowering::getSetCCResultType(const SDValue &) const { 533 return getValueType(TD->getIntPtrType()); 534} 535 536 537/// getVectorTypeBreakdown - Vector types are broken down into some number of 538/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 539/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 540/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 541/// 542/// This method returns the number of registers needed, and the VT for each 543/// register. It also returns the VT and quantity of the intermediate values 544/// before they are promoted/expanded. 545/// 546unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 547 MVT &IntermediateVT, 548 unsigned &NumIntermediates, 549 MVT &RegisterVT) const { 550 // Figure out the right, legal destination reg to copy into. 551 unsigned NumElts = VT.getVectorNumElements(); 552 MVT EltTy = VT.getVectorElementType(); 553 554 unsigned NumVectorRegs = 1; 555 556 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 557 // could break down into LHS/RHS like LegalizeDAG does. 558 if (!isPowerOf2_32(NumElts)) { 559 NumVectorRegs = NumElts; 560 NumElts = 1; 561 } 562 563 // Divide the input until we get to a supported size. This will always 564 // end with a scalar if the target doesn't support vectors. 565 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 566 NumElts >>= 1; 567 NumVectorRegs <<= 1; 568 } 569 570 NumIntermediates = NumVectorRegs; 571 572 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 573 if (!isTypeLegal(NewVT)) 574 NewVT = EltTy; 575 IntermediateVT = NewVT; 576 577 MVT DestVT = getTypeToTransformTo(NewVT); 578 RegisterVT = DestVT; 579 if (DestVT.bitsLT(NewVT)) { 580 // Value is expanded, e.g. i64 -> i16. 581 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 582 } else { 583 // Otherwise, promotion or legal types use the same number of registers as 584 // the vector decimated to the appropriate level. 585 return NumVectorRegs; 586 } 587 588 return 1; 589} 590 591/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 592/// function arguments in the caller parameter area. This is the actual 593/// alignment, not its logarithm. 594unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 595 return TD->getCallFrameTypeAlignment(Ty); 596} 597 598SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 599 SelectionDAG &DAG) const { 600 if (usesGlobalOffsetTable()) 601 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); 602 return Table; 603} 604 605//===----------------------------------------------------------------------===// 606// Optimization Methods 607//===----------------------------------------------------------------------===// 608 609/// ShrinkDemandedConstant - Check to see if the specified operand of the 610/// specified instruction is a constant integer. If so, check to see if there 611/// are any bits set in the constant that are not demanded. If so, shrink the 612/// constant and return true. 613bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 614 const APInt &Demanded) { 615 // FIXME: ISD::SELECT, ISD::SELECT_CC 616 switch(Op.getOpcode()) { 617 default: break; 618 case ISD::AND: 619 case ISD::OR: 620 case ISD::XOR: 621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 622 if (C->getAPIntValue().intersects(~Demanded)) { 623 MVT VT = Op.getValueType(); 624 SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 625 DAG.getConstant(Demanded & 626 C->getAPIntValue(), 627 VT)); 628 return CombineTo(Op, New); 629 } 630 break; 631 } 632 return false; 633} 634 635/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 636/// DemandedMask bits of the result of Op are ever used downstream. If we can 637/// use this information to simplify Op, create a new simplified DAG node and 638/// return true, returning the original and new nodes in Old and New. Otherwise, 639/// analyze the expression and return a mask of KnownOne and KnownZero bits for 640/// the expression (used to simplify the caller). The KnownZero/One bits may 641/// only be accurate for those bits in the DemandedMask. 642bool TargetLowering::SimplifyDemandedBits(SDValue Op, 643 const APInt &DemandedMask, 644 APInt &KnownZero, 645 APInt &KnownOne, 646 TargetLoweringOpt &TLO, 647 unsigned Depth) const { 648 unsigned BitWidth = DemandedMask.getBitWidth(); 649 assert(Op.getValueSizeInBits() == BitWidth && 650 "Mask size mismatches value type size!"); 651 APInt NewMask = DemandedMask; 652 653 // Don't know anything. 654 KnownZero = KnownOne = APInt(BitWidth, 0); 655 656 // Other users may use these bits. 657 if (!Op.Val->hasOneUse()) { 658 if (Depth != 0) { 659 // If not at the root, Just compute the KnownZero/KnownOne bits to 660 // simplify things downstream. 661 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 662 return false; 663 } 664 // If this is the root being simplified, allow it to have multiple uses, 665 // just set the NewMask to all bits. 666 NewMask = APInt::getAllOnesValue(BitWidth); 667 } else if (DemandedMask == 0) { 668 // Not demanding any bits from Op. 669 if (Op.getOpcode() != ISD::UNDEF) 670 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType())); 671 return false; 672 } else if (Depth == 6) { // Limit search depth. 673 return false; 674 } 675 676 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 677 switch (Op.getOpcode()) { 678 case ISD::Constant: 679 // We know all of the bits for a constant! 680 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 681 KnownZero = ~KnownOne & NewMask; 682 return false; // Don't fall through, will infinitely loop. 683 case ISD::AND: 684 // If the RHS is a constant, check to see if the LHS would be zero without 685 // using the bits from the RHS. Below, we use knowledge about the RHS to 686 // simplify the LHS, here we're using information from the LHS to simplify 687 // the RHS. 688 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 689 APInt LHSZero, LHSOne; 690 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 691 LHSZero, LHSOne, Depth+1); 692 // If the LHS already has zeros where RHSC does, this and is dead. 693 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 694 return TLO.CombineTo(Op, Op.getOperand(0)); 695 // If any of the set bits in the RHS are known zero on the LHS, shrink 696 // the constant. 697 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 698 return true; 699 } 700 701 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 702 KnownOne, TLO, Depth+1)) 703 return true; 704 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 705 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 706 KnownZero2, KnownOne2, TLO, Depth+1)) 707 return true; 708 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 709 710 // If all of the demanded bits are known one on one side, return the other. 711 // These bits cannot contribute to the result of the 'and'. 712 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 713 return TLO.CombineTo(Op, Op.getOperand(0)); 714 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 715 return TLO.CombineTo(Op, Op.getOperand(1)); 716 // If all of the demanded bits in the inputs are known zeros, return zero. 717 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 718 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 719 // If the RHS is a constant, see if we can simplify it. 720 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 721 return true; 722 723 // Output known-1 bits are only known if set in both the LHS & RHS. 724 KnownOne &= KnownOne2; 725 // Output known-0 are known to be clear if zero in either the LHS | RHS. 726 KnownZero |= KnownZero2; 727 break; 728 case ISD::OR: 729 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 730 KnownOne, TLO, Depth+1)) 731 return true; 732 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 733 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 734 KnownZero2, KnownOne2, TLO, Depth+1)) 735 return true; 736 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 737 738 // If all of the demanded bits are known zero on one side, return the other. 739 // These bits cannot contribute to the result of the 'or'. 740 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 741 return TLO.CombineTo(Op, Op.getOperand(0)); 742 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 743 return TLO.CombineTo(Op, Op.getOperand(1)); 744 // If all of the potentially set bits on one side are known to be set on 745 // the other side, just use the 'other' side. 746 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 747 return TLO.CombineTo(Op, Op.getOperand(0)); 748 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 749 return TLO.CombineTo(Op, Op.getOperand(1)); 750 // If the RHS is a constant, see if we can simplify it. 751 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 752 return true; 753 754 // Output known-0 bits are only known if clear in both the LHS & RHS. 755 KnownZero &= KnownZero2; 756 // Output known-1 are known to be set if set in either the LHS | RHS. 757 KnownOne |= KnownOne2; 758 break; 759 case ISD::XOR: 760 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 761 KnownOne, TLO, Depth+1)) 762 return true; 763 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 764 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 765 KnownOne2, TLO, Depth+1)) 766 return true; 767 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 768 769 // If all of the demanded bits are known zero on one side, return the other. 770 // These bits cannot contribute to the result of the 'xor'. 771 if ((KnownZero & NewMask) == NewMask) 772 return TLO.CombineTo(Op, Op.getOperand(0)); 773 if ((KnownZero2 & NewMask) == NewMask) 774 return TLO.CombineTo(Op, Op.getOperand(1)); 775 776 // If all of the unknown bits are known to be zero on one side or the other 777 // (but not both) turn this into an *inclusive* or. 778 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 779 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 780 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(), 781 Op.getOperand(0), 782 Op.getOperand(1))); 783 784 // Output known-0 bits are known if clear or set in both the LHS & RHS. 785 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 786 // Output known-1 are known to be set if set in only one of the LHS, RHS. 787 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 788 789 // If all of the demanded bits on one side are known, and all of the set 790 // bits on that side are also known to be set on the other side, turn this 791 // into an AND, as we know the bits will be cleared. 792 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 793 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 794 if ((KnownOne & KnownOne2) == KnownOne) { 795 MVT VT = Op.getValueType(); 796 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 797 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), 798 ANDC)); 799 } 800 } 801 802 // If the RHS is a constant, see if we can simplify it. 803 // for XOR, we prefer to force bits to 1 if they will make a -1. 804 // if we can't force bits, try to shrink constant 805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 806 APInt Expanded = C->getAPIntValue() | (~NewMask); 807 // if we can expand it to have all bits set, do it 808 if (Expanded.isAllOnesValue()) { 809 if (Expanded != C->getAPIntValue()) { 810 MVT VT = Op.getValueType(); 811 SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), 812 TLO.DAG.getConstant(Expanded, VT)); 813 return TLO.CombineTo(Op, New); 814 } 815 // if it already has all the bits set, nothing to change 816 // but don't shrink either! 817 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 818 return true; 819 } 820 } 821 822 KnownZero = KnownZeroOut; 823 KnownOne = KnownOneOut; 824 break; 825 case ISD::SELECT: 826 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 827 KnownOne, TLO, Depth+1)) 828 return true; 829 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 830 KnownOne2, TLO, Depth+1)) 831 return true; 832 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 833 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 834 835 // If the operands are constants, see if we can simplify them. 836 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 837 return true; 838 839 // Only known if known in both the LHS and RHS. 840 KnownOne &= KnownOne2; 841 KnownZero &= KnownZero2; 842 break; 843 case ISD::SELECT_CC: 844 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 845 KnownOne, TLO, Depth+1)) 846 return true; 847 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 848 KnownOne2, TLO, Depth+1)) 849 return true; 850 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 851 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 852 853 // If the operands are constants, see if we can simplify them. 854 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 855 return true; 856 857 // Only known if known in both the LHS and RHS. 858 KnownOne &= KnownOne2; 859 KnownZero &= KnownZero2; 860 break; 861 case ISD::SHL: 862 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 863 unsigned ShAmt = SA->getValue(); 864 SDValue InOp = Op.getOperand(0); 865 866 // If the shift count is an invalid immediate, don't do anything. 867 if (ShAmt >= BitWidth) 868 break; 869 870 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 871 // single shift. We can do this if the bottom bits (which are shifted 872 // out) are never demanded. 873 if (InOp.getOpcode() == ISD::SRL && 874 isa<ConstantSDNode>(InOp.getOperand(1))) { 875 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 876 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 877 unsigned Opc = ISD::SHL; 878 int Diff = ShAmt-C1; 879 if (Diff < 0) { 880 Diff = -Diff; 881 Opc = ISD::SRL; 882 } 883 884 SDValue NewSA = 885 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 886 MVT VT = Op.getValueType(); 887 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 888 InOp.getOperand(0), NewSA)); 889 } 890 } 891 892 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 893 KnownZero, KnownOne, TLO, Depth+1)) 894 return true; 895 KnownZero <<= SA->getValue(); 896 KnownOne <<= SA->getValue(); 897 // low bits known zero. 898 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue()); 899 } 900 break; 901 case ISD::SRL: 902 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 903 MVT VT = Op.getValueType(); 904 unsigned ShAmt = SA->getValue(); 905 unsigned VTSize = VT.getSizeInBits(); 906 SDValue InOp = Op.getOperand(0); 907 908 // If the shift count is an invalid immediate, don't do anything. 909 if (ShAmt >= BitWidth) 910 break; 911 912 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 913 // single shift. We can do this if the top bits (which are shifted out) 914 // are never demanded. 915 if (InOp.getOpcode() == ISD::SHL && 916 isa<ConstantSDNode>(InOp.getOperand(1))) { 917 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 918 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue(); 919 unsigned Opc = ISD::SRL; 920 int Diff = ShAmt-C1; 921 if (Diff < 0) { 922 Diff = -Diff; 923 Opc = ISD::SHL; 924 } 925 926 SDValue NewSA = 927 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 928 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, 929 InOp.getOperand(0), NewSA)); 930 } 931 } 932 933 // Compute the new bits that are at the top now. 934 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 935 KnownZero, KnownOne, TLO, Depth+1)) 936 return true; 937 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 938 KnownZero = KnownZero.lshr(ShAmt); 939 KnownOne = KnownOne.lshr(ShAmt); 940 941 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 942 KnownZero |= HighBits; // High bits known zero. 943 } 944 break; 945 case ISD::SRA: 946 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 947 MVT VT = Op.getValueType(); 948 unsigned ShAmt = SA->getValue(); 949 950 // If the shift count is an invalid immediate, don't do anything. 951 if (ShAmt >= BitWidth) 952 break; 953 954 APInt InDemandedMask = (NewMask << ShAmt); 955 956 // If any of the demanded bits are produced by the sign extension, we also 957 // demand the input sign bit. 958 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 959 if (HighBits.intersects(NewMask)) 960 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 961 962 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 963 KnownZero, KnownOne, TLO, Depth+1)) 964 return true; 965 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 966 KnownZero = KnownZero.lshr(ShAmt); 967 KnownOne = KnownOne.lshr(ShAmt); 968 969 // Handle the sign bit, adjusted to where it is now in the mask. 970 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 971 972 // If the input sign bit is known to be zero, or if none of the top bits 973 // are demanded, turn this into an unsigned shift right. 974 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 975 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0), 976 Op.getOperand(1))); 977 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 978 KnownOne |= HighBits; 979 } 980 } 981 break; 982 case ISD::SIGN_EXTEND_INREG: { 983 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 984 985 // Sign extension. Compute the demanded bits in the result that are not 986 // present in the input. 987 APInt NewBits = APInt::getHighBitsSet(BitWidth, 988 BitWidth - EVT.getSizeInBits()) & 989 NewMask; 990 991 // If none of the extended bits are demanded, eliminate the sextinreg. 992 if (NewBits == 0) 993 return TLO.CombineTo(Op, Op.getOperand(0)); 994 995 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 996 InSignBit.zext(BitWidth); 997 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 998 EVT.getSizeInBits()) & 999 NewMask; 1000 1001 // Since the sign extended bits are demanded, we know that the sign 1002 // bit is demanded. 1003 InputDemandedBits |= InSignBit; 1004 1005 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1006 KnownZero, KnownOne, TLO, Depth+1)) 1007 return true; 1008 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1009 1010 // If the sign bit of the input is known set or clear, then we know the 1011 // top bits of the result. 1012 1013 // If the input sign bit is known zero, convert this into a zero extension. 1014 if (KnownZero.intersects(InSignBit)) 1015 return TLO.CombineTo(Op, 1016 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT)); 1017 1018 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1019 KnownOne |= NewBits; 1020 KnownZero &= ~NewBits; 1021 } else { // Input sign bit unknown 1022 KnownZero &= ~NewBits; 1023 KnownOne &= ~NewBits; 1024 } 1025 break; 1026 } 1027 case ISD::ZERO_EXTEND: { 1028 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1029 APInt InMask = NewMask; 1030 InMask.trunc(OperandBitWidth); 1031 1032 // If none of the top bits are demanded, convert this into an any_extend. 1033 APInt NewBits = 1034 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1035 if (!NewBits.intersects(NewMask)) 1036 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, 1037 Op.getValueType(), 1038 Op.getOperand(0))); 1039 1040 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1041 KnownZero, KnownOne, TLO, Depth+1)) 1042 return true; 1043 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1044 KnownZero.zext(BitWidth); 1045 KnownOne.zext(BitWidth); 1046 KnownZero |= NewBits; 1047 break; 1048 } 1049 case ISD::SIGN_EXTEND: { 1050 MVT InVT = Op.getOperand(0).getValueType(); 1051 unsigned InBits = InVT.getSizeInBits(); 1052 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1053 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1054 APInt NewBits = ~InMask & NewMask; 1055 1056 // If none of the top bits are demanded, convert this into an any_extend. 1057 if (NewBits == 0) 1058 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), 1059 Op.getOperand(0))); 1060 1061 // Since some of the sign extended bits are demanded, we know that the sign 1062 // bit is demanded. 1063 APInt InDemandedBits = InMask & NewMask; 1064 InDemandedBits |= InSignBit; 1065 InDemandedBits.trunc(InBits); 1066 1067 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1068 KnownOne, TLO, Depth+1)) 1069 return true; 1070 KnownZero.zext(BitWidth); 1071 KnownOne.zext(BitWidth); 1072 1073 // If the sign bit is known zero, convert this to a zero extend. 1074 if (KnownZero.intersects(InSignBit)) 1075 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, 1076 Op.getValueType(), 1077 Op.getOperand(0))); 1078 1079 // If the sign bit is known one, the top bits match. 1080 if (KnownOne.intersects(InSignBit)) { 1081 KnownOne |= NewBits; 1082 KnownZero &= ~NewBits; 1083 } else { // Otherwise, top bits aren't known. 1084 KnownOne &= ~NewBits; 1085 KnownZero &= ~NewBits; 1086 } 1087 break; 1088 } 1089 case ISD::ANY_EXTEND: { 1090 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1091 APInt InMask = NewMask; 1092 InMask.trunc(OperandBitWidth); 1093 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1094 KnownZero, KnownOne, TLO, Depth+1)) 1095 return true; 1096 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1097 KnownZero.zext(BitWidth); 1098 KnownOne.zext(BitWidth); 1099 break; 1100 } 1101 case ISD::TRUNCATE: { 1102 // Simplify the input, using demanded bit information, and compute the known 1103 // zero/one bits live out. 1104 APInt TruncMask = NewMask; 1105 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1106 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1107 KnownZero, KnownOne, TLO, Depth+1)) 1108 return true; 1109 KnownZero.trunc(BitWidth); 1110 KnownOne.trunc(BitWidth); 1111 1112 // If the input is only used by this truncate, see if we can shrink it based 1113 // on the known demanded bits. 1114 if (Op.getOperand(0).Val->hasOneUse()) { 1115 SDValue In = Op.getOperand(0); 1116 unsigned InBitWidth = In.getValueSizeInBits(); 1117 switch (In.getOpcode()) { 1118 default: break; 1119 case ISD::SRL: 1120 // Shrink SRL by a constant if none of the high bits shifted in are 1121 // demanded. 1122 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1123 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1124 InBitWidth - BitWidth); 1125 HighBits = HighBits.lshr(ShAmt->getValue()); 1126 HighBits.trunc(BitWidth); 1127 1128 if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) { 1129 // None of the shifted in bits are needed. Add a truncate of the 1130 // shift input, then shift it. 1131 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, 1132 Op.getValueType(), 1133 In.getOperand(0)); 1134 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), 1135 NewTrunc, In.getOperand(1))); 1136 } 1137 } 1138 break; 1139 } 1140 } 1141 1142 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1143 break; 1144 } 1145 case ISD::AssertZext: { 1146 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1147 APInt InMask = APInt::getLowBitsSet(BitWidth, 1148 VT.getSizeInBits()); 1149 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1150 KnownZero, KnownOne, TLO, Depth+1)) 1151 return true; 1152 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1153 KnownZero |= ~InMask & NewMask; 1154 break; 1155 } 1156 case ISD::BIT_CONVERT: 1157#if 0 1158 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1159 // is demanded, turn this into a FGETSIGN. 1160 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1161 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1162 !MVT::isVector(Op.getOperand(0).getValueType())) { 1163 // Only do this xform if FGETSIGN is valid or if before legalize. 1164 if (!TLO.AfterLegalize || 1165 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1166 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1167 // place. We expect the SHL to be eliminated by other optimizations. 1168 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1169 Op.getOperand(0)); 1170 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1171 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1172 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1173 Sign, ShAmt)); 1174 } 1175 } 1176#endif 1177 break; 1178 default: 1179 // Just use ComputeMaskedBits to compute output bits. 1180 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1181 break; 1182 } 1183 1184 // If we know the value of all of the demanded bits, return this as a 1185 // constant. 1186 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1187 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1188 1189 return false; 1190} 1191 1192/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1193/// in Mask are known to be either zero or one and return them in the 1194/// KnownZero/KnownOne bitsets. 1195void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1196 const APInt &Mask, 1197 APInt &KnownZero, 1198 APInt &KnownOne, 1199 const SelectionDAG &DAG, 1200 unsigned Depth) const { 1201 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1202 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1203 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1204 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1205 "Should use MaskedValueIsZero if you don't know whether Op" 1206 " is a target node!"); 1207 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1208} 1209 1210/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1211/// targets that want to expose additional information about sign bits to the 1212/// DAG Combiner. 1213unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1214 unsigned Depth) const { 1215 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1216 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1217 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1218 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1219 "Should use ComputeNumSignBits if you don't know whether Op" 1220 " is a target node!"); 1221 return 1; 1222} 1223 1224 1225/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1226/// and cc. If it is unable to simplify it, return a null SDValue. 1227SDValue 1228TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1229 ISD::CondCode Cond, bool foldBooleans, 1230 DAGCombinerInfo &DCI) const { 1231 SelectionDAG &DAG = DCI.DAG; 1232 1233 // These setcc operations always fold. 1234 switch (Cond) { 1235 default: break; 1236 case ISD::SETFALSE: 1237 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1238 case ISD::SETTRUE: 1239 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1240 } 1241 1242 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1243 const APInt &C1 = N1C->getAPIntValue(); 1244 if (isa<ConstantSDNode>(N0.Val)) { 1245 return DAG.FoldSetCC(VT, N0, N1, Cond); 1246 } else { 1247 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1248 // equality comparison, then we're just comparing whether X itself is 1249 // zero. 1250 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1251 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1252 N0.getOperand(1).getOpcode() == ISD::Constant) { 1253 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1254 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1255 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1256 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1257 // (srl (ctlz x), 5) == 0 -> X != 0 1258 // (srl (ctlz x), 5) != 1 -> X != 0 1259 Cond = ISD::SETNE; 1260 } else { 1261 // (srl (ctlz x), 5) != 0 -> X == 0 1262 // (srl (ctlz x), 5) == 1 -> X == 0 1263 Cond = ISD::SETEQ; 1264 } 1265 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1266 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), 1267 Zero, Cond); 1268 } 1269 } 1270 1271 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1272 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1273 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1274 1275 // If the comparison constant has bits in the upper part, the 1276 // zero-extended value could never match. 1277 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1278 C1.getBitWidth() - InSize))) { 1279 switch (Cond) { 1280 case ISD::SETUGT: 1281 case ISD::SETUGE: 1282 case ISD::SETEQ: return DAG.getConstant(0, VT); 1283 case ISD::SETULT: 1284 case ISD::SETULE: 1285 case ISD::SETNE: return DAG.getConstant(1, VT); 1286 case ISD::SETGT: 1287 case ISD::SETGE: 1288 // True if the sign bit of C1 is set. 1289 return DAG.getConstant(C1.isNegative(), VT); 1290 case ISD::SETLT: 1291 case ISD::SETLE: 1292 // True if the sign bit of C1 isn't set. 1293 return DAG.getConstant(C1.isNonNegative(), VT); 1294 default: 1295 break; 1296 } 1297 } 1298 1299 // Otherwise, we can perform the comparison with the low bits. 1300 switch (Cond) { 1301 case ISD::SETEQ: 1302 case ISD::SETNE: 1303 case ISD::SETUGT: 1304 case ISD::SETUGE: 1305 case ISD::SETULT: 1306 case ISD::SETULE: 1307 return DAG.getSetCC(VT, N0.getOperand(0), 1308 DAG.getConstant(APInt(C1).trunc(InSize), 1309 N0.getOperand(0).getValueType()), 1310 Cond); 1311 default: 1312 break; // todo, be more careful with signed comparisons 1313 } 1314 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1315 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1316 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1317 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1318 MVT ExtDstTy = N0.getValueType(); 1319 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1320 1321 // If the extended part has any inconsistent bits, it cannot ever 1322 // compare equal. In other words, they have to be all ones or all 1323 // zeros. 1324 APInt ExtBits = 1325 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1326 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1327 return DAG.getConstant(Cond == ISD::SETNE, VT); 1328 1329 SDValue ZextOp; 1330 MVT Op0Ty = N0.getOperand(0).getValueType(); 1331 if (Op0Ty == ExtSrcTy) { 1332 ZextOp = N0.getOperand(0); 1333 } else { 1334 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1335 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1336 DAG.getConstant(Imm, Op0Ty)); 1337 } 1338 if (!DCI.isCalledByLegalizer()) 1339 DCI.AddToWorklist(ZextOp.Val); 1340 // Otherwise, make this a use of a zext. 1341 return DAG.getSetCC(VT, ZextOp, 1342 DAG.getConstant(C1 & APInt::getLowBitsSet( 1343 ExtDstTyBits, 1344 ExtSrcTyBits), 1345 ExtDstTy), 1346 Cond); 1347 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1348 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1349 1350 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1351 if (N0.getOpcode() == ISD::SETCC) { 1352 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); 1353 if (TrueWhenTrue) 1354 return N0; 1355 1356 // Invert the condition. 1357 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1358 CC = ISD::getSetCCInverse(CC, 1359 N0.getOperand(0).getValueType().isInteger()); 1360 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC); 1361 } 1362 1363 if ((N0.getOpcode() == ISD::XOR || 1364 (N0.getOpcode() == ISD::AND && 1365 N0.getOperand(0).getOpcode() == ISD::XOR && 1366 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1367 isa<ConstantSDNode>(N0.getOperand(1)) && 1368 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1369 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1370 // can only do this if the top bits are known zero. 1371 unsigned BitWidth = N0.getValueSizeInBits(); 1372 if (DAG.MaskedValueIsZero(N0, 1373 APInt::getHighBitsSet(BitWidth, 1374 BitWidth-1))) { 1375 // Okay, get the un-inverted input value. 1376 SDValue Val; 1377 if (N0.getOpcode() == ISD::XOR) 1378 Val = N0.getOperand(0); 1379 else { 1380 assert(N0.getOpcode() == ISD::AND && 1381 N0.getOperand(0).getOpcode() == ISD::XOR); 1382 // ((X^1)&1)^1 -> X & 1 1383 Val = DAG.getNode(ISD::AND, N0.getValueType(), 1384 N0.getOperand(0).getOperand(0), 1385 N0.getOperand(1)); 1386 } 1387 return DAG.getSetCC(VT, Val, N1, 1388 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1389 } 1390 } 1391 } 1392 1393 APInt MinVal, MaxVal; 1394 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1395 if (ISD::isSignedIntSetCC(Cond)) { 1396 MinVal = APInt::getSignedMinValue(OperandBitSize); 1397 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1398 } else { 1399 MinVal = APInt::getMinValue(OperandBitSize); 1400 MaxVal = APInt::getMaxValue(OperandBitSize); 1401 } 1402 1403 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1404 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1405 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1406 // X >= C0 --> X > (C0-1) 1407 return DAG.getSetCC(VT, N0, DAG.getConstant(C1-1, N1.getValueType()), 1408 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1409 } 1410 1411 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1412 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1413 // X <= C0 --> X < (C0+1) 1414 return DAG.getSetCC(VT, N0, DAG.getConstant(C1+1, N1.getValueType()), 1415 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1416 } 1417 1418 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1419 return DAG.getConstant(0, VT); // X < MIN --> false 1420 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1421 return DAG.getConstant(1, VT); // X >= MIN --> true 1422 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1423 return DAG.getConstant(0, VT); // X > MAX --> false 1424 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1425 return DAG.getConstant(1, VT); // X <= MAX --> true 1426 1427 // Canonicalize setgt X, Min --> setne X, Min 1428 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1429 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1430 // Canonicalize setlt X, Max --> setne X, Max 1431 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1432 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1433 1434 // If we have setult X, 1, turn it into seteq X, 0 1435 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1436 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1437 ISD::SETEQ); 1438 // If we have setugt X, Max-1, turn it into seteq X, Max 1439 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1440 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1441 ISD::SETEQ); 1442 1443 // If we have "setcc X, C0", check to see if we can shrink the immediate 1444 // by changing cc. 1445 1446 // SETUGT X, SINTMAX -> SETLT X, 0 1447 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1448 C1 == (~0ULL >> (65-OperandBitSize))) 1449 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1450 ISD::SETLT); 1451 1452 // FIXME: Implement the rest of these. 1453 1454 // Fold bit comparisons when we can. 1455 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1456 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1457 if (ConstantSDNode *AndRHS = 1458 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1459 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1460 // Perform the xform if the AND RHS is a single bit. 1461 if (isPowerOf2_64(AndRHS->getValue())) { 1462 return DAG.getNode(ISD::SRL, VT, N0, 1463 DAG.getConstant(Log2_64(AndRHS->getValue()), 1464 getShiftAmountTy())); 1465 } 1466 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1467 // (X & 8) == 8 --> (X & 8) >> 3 1468 // Perform the xform if C1 is a single bit. 1469 if (C1.isPowerOf2()) { 1470 return DAG.getNode(ISD::SRL, VT, N0, 1471 DAG.getConstant(C1.logBase2(), getShiftAmountTy())); 1472 } 1473 } 1474 } 1475 } 1476 } else if (isa<ConstantSDNode>(N0.Val)) { 1477 // Ensure that the constant occurs on the RHS. 1478 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1479 } 1480 1481 if (isa<ConstantFPSDNode>(N0.Val)) { 1482 // Constant fold or commute setcc. 1483 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); 1484 if (O.Val) return O; 1485 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.Val)) { 1486 // If the RHS of an FP comparison is a constant, simplify it away in 1487 // some cases. 1488 if (CFP->getValueAPF().isNaN()) { 1489 // If an operand is known to be a nan, we can fold it. 1490 switch (ISD::getUnorderedFlavor(Cond)) { 1491 default: assert(0 && "Unknown flavor!"); 1492 case 0: // Known false. 1493 return DAG.getConstant(0, VT); 1494 case 1: // Known true. 1495 return DAG.getConstant(1, VT); 1496 case 2: // Undefined. 1497 return DAG.getNode(ISD::UNDEF, VT); 1498 } 1499 } 1500 1501 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1502 // constant if knowing that the operand is non-nan is enough. We prefer to 1503 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1504 // materialize 0.0. 1505 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1506 return DAG.getSetCC(VT, N0, N0, Cond); 1507 } 1508 1509 if (N0 == N1) { 1510 // We can always fold X == X for integer setcc's. 1511 if (N0.getValueType().isInteger()) 1512 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1513 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1514 if (UOF == 2) // FP operators that are undefined on NaNs. 1515 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1516 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1517 return DAG.getConstant(UOF, VT); 1518 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1519 // if it is not already. 1520 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1521 if (NewCond != Cond) 1522 return DAG.getSetCC(VT, N0, N1, NewCond); 1523 } 1524 1525 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1526 N0.getValueType().isInteger()) { 1527 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1528 N0.getOpcode() == ISD::XOR) { 1529 // Simplify (X+Y) == (X+Z) --> Y == Z 1530 if (N0.getOpcode() == N1.getOpcode()) { 1531 if (N0.getOperand(0) == N1.getOperand(0)) 1532 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 1533 if (N0.getOperand(1) == N1.getOperand(1)) 1534 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 1535 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1536 // If X op Y == Y op X, try other combinations. 1537 if (N0.getOperand(0) == N1.getOperand(1)) 1538 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 1539 if (N0.getOperand(1) == N1.getOperand(0)) 1540 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 1541 } 1542 } 1543 1544 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1545 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1546 // Turn (X+C1) == C2 --> X == C2-C1 1547 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 1548 return DAG.getSetCC(VT, N0.getOperand(0), 1549 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 1550 N0.getValueType()), Cond); 1551 } 1552 1553 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1554 if (N0.getOpcode() == ISD::XOR) 1555 // If we know that all of the inverted bits are zero, don't bother 1556 // performing the inversion. 1557 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1558 return 1559 DAG.getSetCC(VT, N0.getOperand(0), 1560 DAG.getConstant(LHSR->getAPIntValue() ^ 1561 RHSC->getAPIntValue(), 1562 N0.getValueType()), 1563 Cond); 1564 } 1565 1566 // Turn (C1-X) == C2 --> X == C1-C2 1567 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1568 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 1569 return 1570 DAG.getSetCC(VT, N0.getOperand(1), 1571 DAG.getConstant(SUBC->getAPIntValue() - 1572 RHSC->getAPIntValue(), 1573 N0.getValueType()), 1574 Cond); 1575 } 1576 } 1577 } 1578 1579 // Simplify (X+Z) == X --> Z == 0 1580 if (N0.getOperand(0) == N1) 1581 return DAG.getSetCC(VT, N0.getOperand(1), 1582 DAG.getConstant(0, N0.getValueType()), Cond); 1583 if (N0.getOperand(1) == N1) { 1584 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1585 return DAG.getSetCC(VT, N0.getOperand(0), 1586 DAG.getConstant(0, N0.getValueType()), Cond); 1587 else if (N0.Val->hasOneUse()) { 1588 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1589 // (Z-X) == X --> Z == X<<1 1590 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), 1591 N1, 1592 DAG.getConstant(1, getShiftAmountTy())); 1593 if (!DCI.isCalledByLegalizer()) 1594 DCI.AddToWorklist(SH.Val); 1595 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 1596 } 1597 } 1598 } 1599 1600 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1601 N1.getOpcode() == ISD::XOR) { 1602 // Simplify X == (X+Z) --> Z == 0 1603 if (N1.getOperand(0) == N0) { 1604 return DAG.getSetCC(VT, N1.getOperand(1), 1605 DAG.getConstant(0, N1.getValueType()), Cond); 1606 } else if (N1.getOperand(1) == N0) { 1607 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1608 return DAG.getSetCC(VT, N1.getOperand(0), 1609 DAG.getConstant(0, N1.getValueType()), Cond); 1610 } else if (N1.Val->hasOneUse()) { 1611 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1612 // X == (Z-X) --> X<<1 == Z 1613 SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 1614 DAG.getConstant(1, getShiftAmountTy())); 1615 if (!DCI.isCalledByLegalizer()) 1616 DCI.AddToWorklist(SH.Val); 1617 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 1618 } 1619 } 1620 } 1621 } 1622 1623 // Fold away ALL boolean setcc's. 1624 SDValue Temp; 1625 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1626 switch (Cond) { 1627 default: assert(0 && "Unknown integer setcc!"); 1628 case ISD::SETEQ: // X == Y -> (X^Y)^1 1629 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1630 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 1631 if (!DCI.isCalledByLegalizer()) 1632 DCI.AddToWorklist(Temp.Val); 1633 break; 1634 case ISD::SETNE: // X != Y --> (X^Y) 1635 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 1636 break; 1637 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 1638 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 1639 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1640 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 1641 if (!DCI.isCalledByLegalizer()) 1642 DCI.AddToWorklist(Temp.Val); 1643 break; 1644 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 1645 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 1646 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1647 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 1648 if (!DCI.isCalledByLegalizer()) 1649 DCI.AddToWorklist(Temp.Val); 1650 break; 1651 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 1652 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 1653 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 1654 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 1655 if (!DCI.isCalledByLegalizer()) 1656 DCI.AddToWorklist(Temp.Val); 1657 break; 1658 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 1659 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 1660 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 1661 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 1662 break; 1663 } 1664 if (VT != MVT::i1) { 1665 if (!DCI.isCalledByLegalizer()) 1666 DCI.AddToWorklist(N0.Val); 1667 // FIXME: If running after legalize, we probably can't do this. 1668 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1669 } 1670 return N0; 1671 } 1672 1673 // Could not fold it. 1674 return SDValue(); 1675} 1676 1677/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1678/// node is a GlobalAddress + offset. 1679bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 1680 int64_t &Offset) const { 1681 if (isa<GlobalAddressSDNode>(N)) { 1682 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1683 GA = GASD->getGlobal(); 1684 Offset += GASD->getOffset(); 1685 return true; 1686 } 1687 1688 if (N->getOpcode() == ISD::ADD) { 1689 SDValue N1 = N->getOperand(0); 1690 SDValue N2 = N->getOperand(1); 1691 if (isGAPlusOffset(N1.Val, GA, Offset)) { 1692 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1693 if (V) { 1694 Offset += V->getSignExtended(); 1695 return true; 1696 } 1697 } else if (isGAPlusOffset(N2.Val, GA, Offset)) { 1698 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1699 if (V) { 1700 Offset += V->getSignExtended(); 1701 return true; 1702 } 1703 } 1704 } 1705 return false; 1706} 1707 1708 1709/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is 1710/// loading 'Bytes' bytes from a location that is 'Dist' units away from the 1711/// location that the 'Base' load is loading from. 1712bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, 1713 unsigned Bytes, int Dist, 1714 const MachineFrameInfo *MFI) const { 1715 if (LD->getOperand(0).Val != Base->getOperand(0).Val) 1716 return false; 1717 MVT VT = LD->getValueType(0); 1718 if (VT.getSizeInBits() / 8 != Bytes) 1719 return false; 1720 1721 SDValue Loc = LD->getOperand(1); 1722 SDValue BaseLoc = Base->getOperand(1); 1723 if (Loc.getOpcode() == ISD::FrameIndex) { 1724 if (BaseLoc.getOpcode() != ISD::FrameIndex) 1725 return false; 1726 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 1727 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 1728 int FS = MFI->getObjectSize(FI); 1729 int BFS = MFI->getObjectSize(BFI); 1730 if (FS != BFS || FS != (int)Bytes) return false; 1731 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 1732 } 1733 1734 GlobalValue *GV1 = NULL; 1735 GlobalValue *GV2 = NULL; 1736 int64_t Offset1 = 0; 1737 int64_t Offset2 = 0; 1738 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); 1739 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); 1740 if (isGA1 && isGA2 && GV1 == GV2) 1741 return Offset1 == (Offset2 + Dist*Bytes); 1742 return false; 1743} 1744 1745 1746SDValue TargetLowering:: 1747PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1748 // Default implementation: no optimization. 1749 return SDValue(); 1750} 1751 1752//===----------------------------------------------------------------------===// 1753// Inline Assembler Implementation Methods 1754//===----------------------------------------------------------------------===// 1755 1756 1757TargetLowering::ConstraintType 1758TargetLowering::getConstraintType(const std::string &Constraint) const { 1759 // FIXME: lots more standard ones to handle. 1760 if (Constraint.size() == 1) { 1761 switch (Constraint[0]) { 1762 default: break; 1763 case 'r': return C_RegisterClass; 1764 case 'm': // memory 1765 case 'o': // offsetable 1766 case 'V': // not offsetable 1767 return C_Memory; 1768 case 'i': // Simple Integer or Relocatable Constant 1769 case 'n': // Simple Integer 1770 case 's': // Relocatable Constant 1771 case 'X': // Allow ANY value. 1772 case 'I': // Target registers. 1773 case 'J': 1774 case 'K': 1775 case 'L': 1776 case 'M': 1777 case 'N': 1778 case 'O': 1779 case 'P': 1780 return C_Other; 1781 } 1782 } 1783 1784 if (Constraint.size() > 1 && Constraint[0] == '{' && 1785 Constraint[Constraint.size()-1] == '}') 1786 return C_Register; 1787 return C_Unknown; 1788} 1789 1790/// LowerXConstraint - try to replace an X constraint, which matches anything, 1791/// with another that has more specific requirements based on the type of the 1792/// corresponding operand. 1793const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 1794 if (ConstraintVT.isInteger()) 1795 return "r"; 1796 if (ConstraintVT.isFloatingPoint()) 1797 return "f"; // works for many targets 1798 return 0; 1799} 1800 1801/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1802/// vector. If it is invalid, don't add anything to Ops. 1803void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1804 char ConstraintLetter, 1805 std::vector<SDValue> &Ops, 1806 SelectionDAG &DAG) const { 1807 switch (ConstraintLetter) { 1808 default: break; 1809 case 'X': // Allows any operand; labels (basic block) use this. 1810 if (Op.getOpcode() == ISD::BasicBlock) { 1811 Ops.push_back(Op); 1812 return; 1813 } 1814 // fall through 1815 case 'i': // Simple Integer or Relocatable Constant 1816 case 'n': // Simple Integer 1817 case 's': { // Relocatable Constant 1818 // These operands are interested in values of the form (GV+C), where C may 1819 // be folded in as an offset of GV, or it may be explicitly added. Also, it 1820 // is possible and fine if either GV or C are missing. 1821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1822 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 1823 1824 // If we have "(add GV, C)", pull out GV/C 1825 if (Op.getOpcode() == ISD::ADD) { 1826 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1827 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 1828 if (C == 0 || GA == 0) { 1829 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 1830 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 1831 } 1832 if (C == 0 || GA == 0) 1833 C = 0, GA = 0; 1834 } 1835 1836 // If we find a valid operand, map to the TargetXXX version so that the 1837 // value itself doesn't get selected. 1838 if (GA) { // Either &GV or &GV+C 1839 if (ConstraintLetter != 'n') { 1840 int64_t Offs = GA->getOffset(); 1841 if (C) Offs += C->getValue(); 1842 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 1843 Op.getValueType(), Offs)); 1844 return; 1845 } 1846 } 1847 if (C) { // just C, no GV. 1848 // Simple constants are not allowed for 's'. 1849 if (ConstraintLetter != 's') { 1850 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); 1851 return; 1852 } 1853 } 1854 break; 1855 } 1856 } 1857} 1858 1859std::vector<unsigned> TargetLowering:: 1860getRegClassForInlineAsmConstraint(const std::string &Constraint, 1861 MVT VT) const { 1862 return std::vector<unsigned>(); 1863} 1864 1865 1866std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 1867getRegForInlineAsmConstraint(const std::string &Constraint, 1868 MVT VT) const { 1869 if (Constraint[0] != '{') 1870 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1871 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 1872 1873 // Remove the braces from around the name. 1874 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 1875 1876 // Figure out which register class contains this reg. 1877 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 1878 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 1879 E = RI->regclass_end(); RCI != E; ++RCI) { 1880 const TargetRegisterClass *RC = *RCI; 1881 1882 // If none of the the value types for this register class are valid, we 1883 // can't use it. For example, 64-bit reg classes on 32-bit targets. 1884 bool isLegal = false; 1885 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1886 I != E; ++I) { 1887 if (isTypeLegal(*I)) { 1888 isLegal = true; 1889 break; 1890 } 1891 } 1892 1893 if (!isLegal) continue; 1894 1895 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1896 I != E; ++I) { 1897 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 1898 return std::make_pair(*I, RC); 1899 } 1900 } 1901 1902 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 1903} 1904 1905//===----------------------------------------------------------------------===// 1906// Constraint Selection. 1907 1908/// getConstraintGenerality - Return an integer indicating how general CT 1909/// is. 1910static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 1911 switch (CT) { 1912 default: assert(0 && "Unknown constraint type!"); 1913 case TargetLowering::C_Other: 1914 case TargetLowering::C_Unknown: 1915 return 0; 1916 case TargetLowering::C_Register: 1917 return 1; 1918 case TargetLowering::C_RegisterClass: 1919 return 2; 1920 case TargetLowering::C_Memory: 1921 return 3; 1922 } 1923} 1924 1925/// ChooseConstraint - If there are multiple different constraints that we 1926/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 1927/// This is somewhat tricky: constraints fall into four classes: 1928/// Other -> immediates and magic values 1929/// Register -> one specific register 1930/// RegisterClass -> a group of regs 1931/// Memory -> memory 1932/// Ideally, we would pick the most specific constraint possible: if we have 1933/// something that fits into a register, we would pick it. The problem here 1934/// is that if we have something that could either be in a register or in 1935/// memory that use of the register could cause selection of *other* 1936/// operands to fail: they might only succeed if we pick memory. Because of 1937/// this the heuristic we use is: 1938/// 1939/// 1) If there is an 'other' constraint, and if the operand is valid for 1940/// that constraint, use it. This makes us take advantage of 'i' 1941/// constraints when available. 1942/// 2) Otherwise, pick the most general constraint present. This prefers 1943/// 'm' over 'r', for example. 1944/// 1945static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 1946 const TargetLowering &TLI, 1947 SDValue Op, SelectionDAG *DAG) { 1948 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 1949 unsigned BestIdx = 0; 1950 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 1951 int BestGenerality = -1; 1952 1953 // Loop over the options, keeping track of the most general one. 1954 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 1955 TargetLowering::ConstraintType CType = 1956 TLI.getConstraintType(OpInfo.Codes[i]); 1957 1958 // If this is an 'other' constraint, see if the operand is valid for it. 1959 // For example, on X86 we might have an 'rI' constraint. If the operand 1960 // is an integer in the range [0..31] we want to use I (saving a load 1961 // of a register), otherwise we must use 'r'. 1962 if (CType == TargetLowering::C_Other && Op.Val) { 1963 assert(OpInfo.Codes[i].size() == 1 && 1964 "Unhandled multi-letter 'other' constraint"); 1965 std::vector<SDValue> ResultOps; 1966 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 1967 ResultOps, *DAG); 1968 if (!ResultOps.empty()) { 1969 BestType = CType; 1970 BestIdx = i; 1971 break; 1972 } 1973 } 1974 1975 // This constraint letter is more general than the previous one, use it. 1976 int Generality = getConstraintGenerality(CType); 1977 if (Generality > BestGenerality) { 1978 BestType = CType; 1979 BestIdx = i; 1980 BestGenerality = Generality; 1981 } 1982 } 1983 1984 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 1985 OpInfo.ConstraintType = BestType; 1986} 1987 1988/// ComputeConstraintToUse - Determines the constraint code and constraint 1989/// type to use for the specific AsmOperandInfo, setting 1990/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 1991void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1992 SDValue Op, 1993 SelectionDAG *DAG) const { 1994 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 1995 1996 // Single-letter constraints ('r') are very common. 1997 if (OpInfo.Codes.size() == 1) { 1998 OpInfo.ConstraintCode = OpInfo.Codes[0]; 1999 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2000 } else { 2001 ChooseConstraint(OpInfo, *this, Op, DAG); 2002 } 2003 2004 // 'X' matches anything. 2005 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2006 // Labels and constants are handled elsewhere ('X' is the only thing 2007 // that matches labels). 2008 if (isa<BasicBlock>(OpInfo.CallOperandVal) || 2009 isa<ConstantInt>(OpInfo.CallOperandVal)) 2010 return; 2011 2012 // Otherwise, try to resolve it to something we know about by looking at 2013 // the actual operand type. 2014 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2015 OpInfo.ConstraintCode = Repl; 2016 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2017 } 2018 } 2019} 2020 2021//===----------------------------------------------------------------------===// 2022// Loop Strength Reduction hooks 2023//===----------------------------------------------------------------------===// 2024 2025/// isLegalAddressingMode - Return true if the addressing mode represented 2026/// by AM is legal for this target, for a load/store of the specified type. 2027bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2028 const Type *Ty) const { 2029 // The default implementation of this implements a conservative RISCy, r+r and 2030 // r+i addr mode. 2031 2032 // Allows a sign-extended 16-bit immediate field. 2033 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2034 return false; 2035 2036 // No global is ever allowed as a base. 2037 if (AM.BaseGV) 2038 return false; 2039 2040 // Only support r+r, 2041 switch (AM.Scale) { 2042 case 0: // "r+i" or just "i", depending on HasBaseReg. 2043 break; 2044 case 1: 2045 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2046 return false; 2047 // Otherwise we have r+r or r+i. 2048 break; 2049 case 2: 2050 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2051 return false; 2052 // Allow 2*r as r+r. 2053 break; 2054 } 2055 2056 return true; 2057} 2058 2059// Magic for divide replacement 2060 2061struct ms { 2062 int64_t m; // magic number 2063 int64_t s; // shift amount 2064}; 2065 2066struct mu { 2067 uint64_t m; // magic number 2068 int64_t a; // add indicator 2069 int64_t s; // shift amount 2070}; 2071 2072/// magic - calculate the magic numbers required to codegen an integer sdiv as 2073/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2074/// or -1. 2075static ms magic32(int32_t d) { 2076 int32_t p; 2077 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 2078 const uint32_t two31 = 0x80000000U; 2079 struct ms mag; 2080 2081 ad = abs(d); 2082 t = two31 + ((uint32_t)d >> 31); 2083 anc = t - 1 - t%ad; // absolute value of nc 2084 p = 31; // initialize p 2085 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 2086 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2087 q2 = two31/ad; // initialize q2 = 2p/abs(d) 2088 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2089 do { 2090 p = p + 1; 2091 q1 = 2*q1; // update q1 = 2p/abs(nc) 2092 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2093 if (r1 >= anc) { // must be unsigned comparison 2094 q1 = q1 + 1; 2095 r1 = r1 - anc; 2096 } 2097 q2 = 2*q2; // update q2 = 2p/abs(d) 2098 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2099 if (r2 >= ad) { // must be unsigned comparison 2100 q2 = q2 + 1; 2101 r2 = r2 - ad; 2102 } 2103 delta = ad - r2; 2104 } while (q1 < delta || (q1 == delta && r1 == 0)); 2105 2106 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 2107 if (d < 0) mag.m = -mag.m; // resulting magic number 2108 mag.s = p - 32; // resulting shift 2109 return mag; 2110} 2111 2112/// magicu - calculate the magic numbers required to codegen an integer udiv as 2113/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2114static mu magicu32(uint32_t d) { 2115 int32_t p; 2116 uint32_t nc, delta, q1, r1, q2, r2; 2117 struct mu magu; 2118 magu.a = 0; // initialize "add" indicator 2119 nc = - 1 - (-d)%d; 2120 p = 31; // initialize p 2121 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 2122 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 2123 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 2124 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 2125 do { 2126 p = p + 1; 2127 if (r1 >= nc - r1 ) { 2128 q1 = 2*q1 + 1; // update q1 2129 r1 = 2*r1 - nc; // update r1 2130 } 2131 else { 2132 q1 = 2*q1; // update q1 2133 r1 = 2*r1; // update r1 2134 } 2135 if (r2 + 1 >= d - r2) { 2136 if (q2 >= 0x7FFFFFFF) magu.a = 1; 2137 q2 = 2*q2 + 1; // update q2 2138 r2 = 2*r2 + 1 - d; // update r2 2139 } 2140 else { 2141 if (q2 >= 0x80000000) magu.a = 1; 2142 q2 = 2*q2; // update q2 2143 r2 = 2*r2 + 1; // update r2 2144 } 2145 delta = d - 1 - r2; 2146 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 2147 magu.m = q2 + 1; // resulting magic number 2148 magu.s = p - 32; // resulting shift 2149 return magu; 2150} 2151 2152/// magic - calculate the magic numbers required to codegen an integer sdiv as 2153/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 2154/// or -1. 2155static ms magic64(int64_t d) { 2156 int64_t p; 2157 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 2158 const uint64_t two63 = 9223372036854775808ULL; // 2^63 2159 struct ms mag; 2160 2161 ad = d >= 0 ? d : -d; 2162 t = two63 + ((uint64_t)d >> 63); 2163 anc = t - 1 - t%ad; // absolute value of nc 2164 p = 63; // initialize p 2165 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 2166 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 2167 q2 = two63/ad; // initialize q2 = 2p/abs(d) 2168 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 2169 do { 2170 p = p + 1; 2171 q1 = 2*q1; // update q1 = 2p/abs(nc) 2172 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 2173 if (r1 >= anc) { // must be unsigned comparison 2174 q1 = q1 + 1; 2175 r1 = r1 - anc; 2176 } 2177 q2 = 2*q2; // update q2 = 2p/abs(d) 2178 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 2179 if (r2 >= ad) { // must be unsigned comparison 2180 q2 = q2 + 1; 2181 r2 = r2 - ad; 2182 } 2183 delta = ad - r2; 2184 } while (q1 < delta || (q1 == delta && r1 == 0)); 2185 2186 mag.m = q2 + 1; 2187 if (d < 0) mag.m = -mag.m; // resulting magic number 2188 mag.s = p - 64; // resulting shift 2189 return mag; 2190} 2191 2192/// magicu - calculate the magic numbers required to codegen an integer udiv as 2193/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 2194static mu magicu64(uint64_t d) 2195{ 2196 int64_t p; 2197 uint64_t nc, delta, q1, r1, q2, r2; 2198 struct mu magu; 2199 magu.a = 0; // initialize "add" indicator 2200 nc = - 1 - (-d)%d; 2201 p = 63; // initialize p 2202 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 2203 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 2204 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 2205 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 2206 do { 2207 p = p + 1; 2208 if (r1 >= nc - r1 ) { 2209 q1 = 2*q1 + 1; // update q1 2210 r1 = 2*r1 - nc; // update r1 2211 } 2212 else { 2213 q1 = 2*q1; // update q1 2214 r1 = 2*r1; // update r1 2215 } 2216 if (r2 + 1 >= d - r2) { 2217 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 2218 q2 = 2*q2 + 1; // update q2 2219 r2 = 2*r2 + 1 - d; // update r2 2220 } 2221 else { 2222 if (q2 >= 0x8000000000000000ull) magu.a = 1; 2223 q2 = 2*q2; // update q2 2224 r2 = 2*r2 + 1; // update r2 2225 } 2226 delta = d - 1 - r2; 2227 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0))); 2228 magu.m = q2 + 1; // resulting magic number 2229 magu.s = p - 64; // resulting shift 2230 return magu; 2231} 2232 2233/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2234/// return a DAG expression to select that will generate the same value by 2235/// multiplying by a magic number. See: 2236/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2237SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2238 std::vector<SDNode*>* Created) const { 2239 MVT VT = N->getValueType(0); 2240 2241 // Check to see if we can do this. 2242 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2243 return SDValue(); // BuildSDIV only operates on i32 or i64 2244 2245 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2246 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2247 2248 // Multiply the numerator (operand 0) by the magic value 2249 SDValue Q; 2250 if (isOperationLegal(ISD::MULHS, VT)) 2251 Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2252 DAG.getConstant(magics.m, VT)); 2253 else if (isOperationLegal(ISD::SMUL_LOHI, VT)) 2254 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), 2255 N->getOperand(0), 2256 DAG.getConstant(magics.m, VT)).Val, 1); 2257 else 2258 return SDValue(); // No mulhs or equvialent 2259 // If d > 0 and m < 0, add the numerator 2260 if (d > 0 && magics.m < 0) { 2261 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2262 if (Created) 2263 Created->push_back(Q.Val); 2264 } 2265 // If d < 0 and m > 0, subtract the numerator. 2266 if (d < 0 && magics.m > 0) { 2267 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2268 if (Created) 2269 Created->push_back(Q.Val); 2270 } 2271 // Shift right algebraic if shift value is nonzero 2272 if (magics.s > 0) { 2273 Q = DAG.getNode(ISD::SRA, VT, Q, 2274 DAG.getConstant(magics.s, getShiftAmountTy())); 2275 if (Created) 2276 Created->push_back(Q.Val); 2277 } 2278 // Extract the sign bit and add it to the quotient 2279 SDValue T = 2280 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2281 getShiftAmountTy())); 2282 if (Created) 2283 Created->push_back(T.Val); 2284 return DAG.getNode(ISD::ADD, VT, Q, T); 2285} 2286 2287/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2288/// return a DAG expression to select that will generate the same value by 2289/// multiplying by a magic number. See: 2290/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2291SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2292 std::vector<SDNode*>* Created) const { 2293 MVT VT = N->getValueType(0); 2294 2295 // Check to see if we can do this. 2296 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2297 return SDValue(); // BuildUDIV only operates on i32 or i64 2298 2299 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2300 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2301 2302 // Multiply the numerator (operand 0) by the magic value 2303 SDValue Q; 2304 if (isOperationLegal(ISD::MULHU, VT)) 2305 Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2306 DAG.getConstant(magics.m, VT)); 2307 else if (isOperationLegal(ISD::UMUL_LOHI, VT)) 2308 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), 2309 N->getOperand(0), 2310 DAG.getConstant(magics.m, VT)).Val, 1); 2311 else 2312 return SDValue(); // No mulhu or equvialent 2313 if (Created) 2314 Created->push_back(Q.Val); 2315 2316 if (magics.a == 0) { 2317 return DAG.getNode(ISD::SRL, VT, Q, 2318 DAG.getConstant(magics.s, getShiftAmountTy())); 2319 } else { 2320 SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2321 if (Created) 2322 Created->push_back(NPQ.Val); 2323 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2324 DAG.getConstant(1, getShiftAmountTy())); 2325 if (Created) 2326 Created->push_back(NPQ.Val); 2327 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2328 if (Created) 2329 Created->push_back(NPQ.Val); 2330 return DAG.getNode(ISD::SRL, VT, NPQ, 2331 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2332 } 2333} 2334