TargetLowering.cpp revision e46f5508dcf45c7f4833913a49dfa3cd95ea74b3 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetAsmInfo.h"
15#include "llvm/Target/TargetLowering.h"
16#include "llvm/Target/TargetSubtarget.h"
17#include "llvm/Target/TargetData.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetRegisterInfo.h"
20#include "llvm/GlobalVariable.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/ADT/StringExtras.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/Support/MathExtras.h"
27using namespace llvm;
28
29namespace llvm {
30TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
31  bool isLocal = GV->hasLocalLinkage();
32  bool isDeclaration = GV->isDeclaration();
33  // FIXME: what should we do for protected and internal visibility?
34  // For variables, is internal different from hidden?
35  bool isHidden = GV->hasHiddenVisibility();
36
37  if (reloc == Reloc::PIC_) {
38    if (isLocal || isHidden)
39      return TLSModel::LocalDynamic;
40    else
41      return TLSModel::GeneralDynamic;
42  } else {
43    if (!isDeclaration || isHidden)
44      return TLSModel::LocalExec;
45    else
46      return TLSModel::InitialExec;
47  }
48}
49}
50
51/// InitLibcallNames - Set default libcall names.
52///
53static void InitLibcallNames(const char **Names) {
54  Names[RTLIB::SHL_I16] = "__ashli16";
55  Names[RTLIB::SHL_I32] = "__ashlsi3";
56  Names[RTLIB::SHL_I64] = "__ashldi3";
57  Names[RTLIB::SHL_I128] = "__ashlti3";
58  Names[RTLIB::SRL_I16] = "__lshri16";
59  Names[RTLIB::SRL_I32] = "__lshrsi3";
60  Names[RTLIB::SRL_I64] = "__lshrdi3";
61  Names[RTLIB::SRL_I128] = "__lshrti3";
62  Names[RTLIB::SRA_I16] = "__ashri16";
63  Names[RTLIB::SRA_I32] = "__ashrsi3";
64  Names[RTLIB::SRA_I64] = "__ashrdi3";
65  Names[RTLIB::SRA_I128] = "__ashrti3";
66  Names[RTLIB::MUL_I16] = "__muli16";
67  Names[RTLIB::MUL_I32] = "__mulsi3";
68  Names[RTLIB::MUL_I64] = "__muldi3";
69  Names[RTLIB::MUL_I128] = "__multi3";
70  Names[RTLIB::SDIV_I32] = "__divsi3";
71  Names[RTLIB::SDIV_I64] = "__divdi3";
72  Names[RTLIB::SDIV_I128] = "__divti3";
73  Names[RTLIB::UDIV_I32] = "__udivsi3";
74  Names[RTLIB::UDIV_I64] = "__udivdi3";
75  Names[RTLIB::UDIV_I128] = "__udivti3";
76  Names[RTLIB::SREM_I32] = "__modsi3";
77  Names[RTLIB::SREM_I64] = "__moddi3";
78  Names[RTLIB::SREM_I128] = "__modti3";
79  Names[RTLIB::UREM_I32] = "__umodsi3";
80  Names[RTLIB::UREM_I64] = "__umoddi3";
81  Names[RTLIB::UREM_I128] = "__umodti3";
82  Names[RTLIB::NEG_I32] = "__negsi2";
83  Names[RTLIB::NEG_I64] = "__negdi2";
84  Names[RTLIB::ADD_F32] = "__addsf3";
85  Names[RTLIB::ADD_F64] = "__adddf3";
86  Names[RTLIB::ADD_F80] = "__addxf3";
87  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
88  Names[RTLIB::SUB_F32] = "__subsf3";
89  Names[RTLIB::SUB_F64] = "__subdf3";
90  Names[RTLIB::SUB_F80] = "__subxf3";
91  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
92  Names[RTLIB::MUL_F32] = "__mulsf3";
93  Names[RTLIB::MUL_F64] = "__muldf3";
94  Names[RTLIB::MUL_F80] = "__mulxf3";
95  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
96  Names[RTLIB::DIV_F32] = "__divsf3";
97  Names[RTLIB::DIV_F64] = "__divdf3";
98  Names[RTLIB::DIV_F80] = "__divxf3";
99  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
100  Names[RTLIB::REM_F32] = "fmodf";
101  Names[RTLIB::REM_F64] = "fmod";
102  Names[RTLIB::REM_F80] = "fmodl";
103  Names[RTLIB::REM_PPCF128] = "fmodl";
104  Names[RTLIB::POWI_F32] = "__powisf2";
105  Names[RTLIB::POWI_F64] = "__powidf2";
106  Names[RTLIB::POWI_F80] = "__powixf2";
107  Names[RTLIB::POWI_PPCF128] = "__powitf2";
108  Names[RTLIB::SQRT_F32] = "sqrtf";
109  Names[RTLIB::SQRT_F64] = "sqrt";
110  Names[RTLIB::SQRT_F80] = "sqrtl";
111  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
112  Names[RTLIB::LOG_F32] = "logf";
113  Names[RTLIB::LOG_F64] = "log";
114  Names[RTLIB::LOG_F80] = "logl";
115  Names[RTLIB::LOG_PPCF128] = "logl";
116  Names[RTLIB::LOG2_F32] = "log2f";
117  Names[RTLIB::LOG2_F64] = "log2";
118  Names[RTLIB::LOG2_F80] = "log2l";
119  Names[RTLIB::LOG2_PPCF128] = "log2l";
120  Names[RTLIB::LOG10_F32] = "log10f";
121  Names[RTLIB::LOG10_F64] = "log10";
122  Names[RTLIB::LOG10_F80] = "log10l";
123  Names[RTLIB::LOG10_PPCF128] = "log10l";
124  Names[RTLIB::EXP_F32] = "expf";
125  Names[RTLIB::EXP_F64] = "exp";
126  Names[RTLIB::EXP_F80] = "expl";
127  Names[RTLIB::EXP_PPCF128] = "expl";
128  Names[RTLIB::EXP2_F32] = "exp2f";
129  Names[RTLIB::EXP2_F64] = "exp2";
130  Names[RTLIB::EXP2_F80] = "exp2l";
131  Names[RTLIB::EXP2_PPCF128] = "exp2l";
132  Names[RTLIB::SIN_F32] = "sinf";
133  Names[RTLIB::SIN_F64] = "sin";
134  Names[RTLIB::SIN_F80] = "sinl";
135  Names[RTLIB::SIN_PPCF128] = "sinl";
136  Names[RTLIB::COS_F32] = "cosf";
137  Names[RTLIB::COS_F64] = "cos";
138  Names[RTLIB::COS_F80] = "cosl";
139  Names[RTLIB::COS_PPCF128] = "cosl";
140  Names[RTLIB::POW_F32] = "powf";
141  Names[RTLIB::POW_F64] = "pow";
142  Names[RTLIB::POW_F80] = "powl";
143  Names[RTLIB::POW_PPCF128] = "powl";
144  Names[RTLIB::CEIL_F32] = "ceilf";
145  Names[RTLIB::CEIL_F64] = "ceil";
146  Names[RTLIB::CEIL_F80] = "ceill";
147  Names[RTLIB::CEIL_PPCF128] = "ceill";
148  Names[RTLIB::TRUNC_F32] = "truncf";
149  Names[RTLIB::TRUNC_F64] = "trunc";
150  Names[RTLIB::TRUNC_F80] = "truncl";
151  Names[RTLIB::TRUNC_PPCF128] = "truncl";
152  Names[RTLIB::RINT_F32] = "rintf";
153  Names[RTLIB::RINT_F64] = "rint";
154  Names[RTLIB::RINT_F80] = "rintl";
155  Names[RTLIB::RINT_PPCF128] = "rintl";
156  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
157  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
158  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
159  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
160  Names[RTLIB::FLOOR_F32] = "floorf";
161  Names[RTLIB::FLOOR_F64] = "floor";
162  Names[RTLIB::FLOOR_F80] = "floorl";
163  Names[RTLIB::FLOOR_PPCF128] = "floorl";
164  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
165  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
166  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
167  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
168  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
169  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
170  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
171  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
172  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
173  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
174  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
175  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
176  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
177  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
178  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
179  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
180  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
181  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
182  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
183  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
184  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
185  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
186  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
187  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
188  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
189  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
190  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
191  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
192  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
193  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
194  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
195  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
196  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
197  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
198  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
199  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
200  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
201  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
202  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
203  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
204  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
205  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
206  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
207  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
208  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
209  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
210  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
211  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
212  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
213  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
214  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
215  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
216  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
217  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
218  Names[RTLIB::OEQ_F32] = "__eqsf2";
219  Names[RTLIB::OEQ_F64] = "__eqdf2";
220  Names[RTLIB::UNE_F32] = "__nesf2";
221  Names[RTLIB::UNE_F64] = "__nedf2";
222  Names[RTLIB::OGE_F32] = "__gesf2";
223  Names[RTLIB::OGE_F64] = "__gedf2";
224  Names[RTLIB::OLT_F32] = "__ltsf2";
225  Names[RTLIB::OLT_F64] = "__ltdf2";
226  Names[RTLIB::OLE_F32] = "__lesf2";
227  Names[RTLIB::OLE_F64] = "__ledf2";
228  Names[RTLIB::OGT_F32] = "__gtsf2";
229  Names[RTLIB::OGT_F64] = "__gtdf2";
230  Names[RTLIB::UO_F32] = "__unordsf2";
231  Names[RTLIB::UO_F64] = "__unorddf2";
232  Names[RTLIB::O_F32] = "__unordsf2";
233  Names[RTLIB::O_F64] = "__unorddf2";
234}
235
236/// getFPEXT - Return the FPEXT_*_* value for the given types, or
237/// UNKNOWN_LIBCALL if there is none.
238RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
239  if (OpVT == MVT::f32) {
240    if (RetVT == MVT::f64)
241      return FPEXT_F32_F64;
242  }
243  return UNKNOWN_LIBCALL;
244}
245
246/// getFPROUND - Return the FPROUND_*_* value for the given types, or
247/// UNKNOWN_LIBCALL if there is none.
248RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
249  if (RetVT == MVT::f32) {
250    if (OpVT == MVT::f64)
251      return FPROUND_F64_F32;
252    if (OpVT == MVT::f80)
253      return FPROUND_F80_F32;
254    if (OpVT == MVT::ppcf128)
255      return FPROUND_PPCF128_F32;
256  } else if (RetVT == MVT::f64) {
257    if (OpVT == MVT::f80)
258      return FPROUND_F80_F64;
259    if (OpVT == MVT::ppcf128)
260      return FPROUND_PPCF128_F64;
261  }
262  return UNKNOWN_LIBCALL;
263}
264
265/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
266/// UNKNOWN_LIBCALL if there is none.
267RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
268  if (OpVT == MVT::f32) {
269    if (RetVT == MVT::i32)
270      return FPTOSINT_F32_I32;
271    if (RetVT == MVT::i64)
272      return FPTOSINT_F32_I64;
273    if (RetVT == MVT::i128)
274      return FPTOSINT_F32_I128;
275  } else if (OpVT == MVT::f64) {
276    if (RetVT == MVT::i32)
277      return FPTOSINT_F64_I32;
278    if (RetVT == MVT::i64)
279      return FPTOSINT_F64_I64;
280    if (RetVT == MVT::i128)
281      return FPTOSINT_F64_I128;
282  } else if (OpVT == MVT::f80) {
283    if (RetVT == MVT::i32)
284      return FPTOSINT_F80_I32;
285    if (RetVT == MVT::i64)
286      return FPTOSINT_F80_I64;
287    if (RetVT == MVT::i128)
288      return FPTOSINT_F80_I128;
289  } else if (OpVT == MVT::ppcf128) {
290    if (RetVT == MVT::i32)
291      return FPTOSINT_PPCF128_I32;
292    if (RetVT == MVT::i64)
293      return FPTOSINT_PPCF128_I64;
294    if (RetVT == MVT::i128)
295      return FPTOSINT_PPCF128_I128;
296  }
297  return UNKNOWN_LIBCALL;
298}
299
300/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
301/// UNKNOWN_LIBCALL if there is none.
302RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
303  if (OpVT == MVT::f32) {
304    if (RetVT == MVT::i32)
305      return FPTOUINT_F32_I32;
306    if (RetVT == MVT::i64)
307      return FPTOUINT_F32_I64;
308    if (RetVT == MVT::i128)
309      return FPTOUINT_F32_I128;
310  } else if (OpVT == MVT::f64) {
311    if (RetVT == MVT::i32)
312      return FPTOUINT_F64_I32;
313    if (RetVT == MVT::i64)
314      return FPTOUINT_F64_I64;
315    if (RetVT == MVT::i128)
316      return FPTOUINT_F64_I128;
317  } else if (OpVT == MVT::f80) {
318    if (RetVT == MVT::i32)
319      return FPTOUINT_F80_I32;
320    if (RetVT == MVT::i64)
321      return FPTOUINT_F80_I64;
322    if (RetVT == MVT::i128)
323      return FPTOUINT_F80_I128;
324  } else if (OpVT == MVT::ppcf128) {
325    if (RetVT == MVT::i32)
326      return FPTOUINT_PPCF128_I32;
327    if (RetVT == MVT::i64)
328      return FPTOUINT_PPCF128_I64;
329    if (RetVT == MVT::i128)
330      return FPTOUINT_PPCF128_I128;
331  }
332  return UNKNOWN_LIBCALL;
333}
334
335/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
336/// UNKNOWN_LIBCALL if there is none.
337RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
338  if (OpVT == MVT::i32) {
339    if (RetVT == MVT::f32)
340      return SINTTOFP_I32_F32;
341    else if (RetVT == MVT::f64)
342      return SINTTOFP_I32_F64;
343    else if (RetVT == MVT::f80)
344      return SINTTOFP_I32_F80;
345    else if (RetVT == MVT::ppcf128)
346      return SINTTOFP_I32_PPCF128;
347  } else if (OpVT == MVT::i64) {
348    if (RetVT == MVT::f32)
349      return SINTTOFP_I64_F32;
350    else if (RetVT == MVT::f64)
351      return SINTTOFP_I64_F64;
352    else if (RetVT == MVT::f80)
353      return SINTTOFP_I64_F80;
354    else if (RetVT == MVT::ppcf128)
355      return SINTTOFP_I64_PPCF128;
356  } else if (OpVT == MVT::i128) {
357    if (RetVT == MVT::f32)
358      return SINTTOFP_I128_F32;
359    else if (RetVT == MVT::f64)
360      return SINTTOFP_I128_F64;
361    else if (RetVT == MVT::f80)
362      return SINTTOFP_I128_F80;
363    else if (RetVT == MVT::ppcf128)
364      return SINTTOFP_I128_PPCF128;
365  }
366  return UNKNOWN_LIBCALL;
367}
368
369/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
370/// UNKNOWN_LIBCALL if there is none.
371RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
372  if (OpVT == MVT::i32) {
373    if (RetVT == MVT::f32)
374      return UINTTOFP_I32_F32;
375    else if (RetVT == MVT::f64)
376      return UINTTOFP_I32_F64;
377    else if (RetVT == MVT::f80)
378      return UINTTOFP_I32_F80;
379    else if (RetVT == MVT::ppcf128)
380      return UINTTOFP_I32_PPCF128;
381  } else if (OpVT == MVT::i64) {
382    if (RetVT == MVT::f32)
383      return UINTTOFP_I64_F32;
384    else if (RetVT == MVT::f64)
385      return UINTTOFP_I64_F64;
386    else if (RetVT == MVT::f80)
387      return UINTTOFP_I64_F80;
388    else if (RetVT == MVT::ppcf128)
389      return UINTTOFP_I64_PPCF128;
390  } else if (OpVT == MVT::i128) {
391    if (RetVT == MVT::f32)
392      return UINTTOFP_I128_F32;
393    else if (RetVT == MVT::f64)
394      return UINTTOFP_I128_F64;
395    else if (RetVT == MVT::f80)
396      return UINTTOFP_I128_F80;
397    else if (RetVT == MVT::ppcf128)
398      return UINTTOFP_I128_PPCF128;
399  }
400  return UNKNOWN_LIBCALL;
401}
402
403/// InitCmpLibcallCCs - Set default comparison libcall CC.
404///
405static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
406  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
407  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
408  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
409  CCs[RTLIB::UNE_F32] = ISD::SETNE;
410  CCs[RTLIB::UNE_F64] = ISD::SETNE;
411  CCs[RTLIB::OGE_F32] = ISD::SETGE;
412  CCs[RTLIB::OGE_F64] = ISD::SETGE;
413  CCs[RTLIB::OLT_F32] = ISD::SETLT;
414  CCs[RTLIB::OLT_F64] = ISD::SETLT;
415  CCs[RTLIB::OLE_F32] = ISD::SETLE;
416  CCs[RTLIB::OLE_F64] = ISD::SETLE;
417  CCs[RTLIB::OGT_F32] = ISD::SETGT;
418  CCs[RTLIB::OGT_F64] = ISD::SETGT;
419  CCs[RTLIB::UO_F32] = ISD::SETNE;
420  CCs[RTLIB::UO_F64] = ISD::SETNE;
421  CCs[RTLIB::O_F32] = ISD::SETEQ;
422  CCs[RTLIB::O_F64] = ISD::SETEQ;
423}
424
425TargetLowering::TargetLowering(TargetMachine &tm)
426  : TM(tm), TD(TM.getTargetData()) {
427  // All operations default to being supported.
428  memset(OpActions, 0, sizeof(OpActions));
429  memset(LoadExtActions, 0, sizeof(LoadExtActions));
430  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
431  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
432  memset(ConvertActions, 0, sizeof(ConvertActions));
433  memset(CondCodeActions, 0, sizeof(CondCodeActions));
434
435  // Set default actions for various operations.
436  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
437    // Default all indexed load / store to expand.
438    for (unsigned IM = (unsigned)ISD::PRE_INC;
439         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
440      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
441      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
442    }
443
444    // These operations default to expand.
445    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
446  }
447
448  // Most targets ignore the @llvm.prefetch intrinsic.
449  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
450
451  // ConstantFP nodes default to expand.  Targets can either change this to
452  // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
453  // to optimize expansions for certain constants.
454  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
455  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
456  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
457
458  // These library functions default to expand.
459  setOperationAction(ISD::FLOG , MVT::f64, Expand);
460  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
461  setOperationAction(ISD::FLOG10,MVT::f64, Expand);
462  setOperationAction(ISD::FEXP , MVT::f64, Expand);
463  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
464  setOperationAction(ISD::FLOG , MVT::f32, Expand);
465  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
466  setOperationAction(ISD::FLOG10,MVT::f32, Expand);
467  setOperationAction(ISD::FEXP , MVT::f32, Expand);
468  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
469
470  // Default ISD::TRAP to expand (which turns it into abort).
471  setOperationAction(ISD::TRAP, MVT::Other, Expand);
472
473  IsLittleEndian = TD->isLittleEndian();
474  UsesGlobalOffsetTable = false;
475  ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
476  ShiftAmtHandling = Undefined;
477  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
478  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
479  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
480  allowUnalignedMemoryAccesses = false;
481  UseUnderscoreSetJmp = false;
482  UseUnderscoreLongJmp = false;
483  SelectIsExpensive = false;
484  IntDivIsCheap = false;
485  Pow2DivIsCheap = false;
486  StackPointerRegisterToSaveRestore = 0;
487  ExceptionPointerRegister = 0;
488  ExceptionSelectorRegister = 0;
489  BooleanContents = UndefinedBooleanContent;
490  SchedPreferenceInfo = SchedulingForLatency;
491  JumpBufSize = 0;
492  JumpBufAlignment = 0;
493  IfCvtBlockSizeLimit = 2;
494  IfCvtDupBlockSizeLimit = 0;
495  PrefLoopAlignment = 0;
496
497  InitLibcallNames(LibcallRoutineNames);
498  InitCmpLibcallCCs(CmpLibcallCCs);
499
500  // Tell Legalize whether the assembler supports DEBUG_LOC.
501  const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
502  if (!TASM || !TASM->hasDotLocAndDotFile())
503    setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
504}
505
506TargetLowering::~TargetLowering() {}
507
508/// computeRegisterProperties - Once all of the register classes are added,
509/// this allows us to compute derived properties we expose.
510void TargetLowering::computeRegisterProperties() {
511  assert(MVT::LAST_VALUETYPE <= 32 &&
512         "Too many value types for ValueTypeActions to hold!");
513
514  // Everything defaults to needing one register.
515  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
516    NumRegistersForVT[i] = 1;
517    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
518  }
519  // ...except isVoid, which doesn't need any registers.
520  NumRegistersForVT[MVT::isVoid] = 0;
521
522  // Find the largest integer register class.
523  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
524  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
525    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
526
527  // Every integer value type larger than this largest register takes twice as
528  // many registers to represent as the previous ValueType.
529  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
530    MVT EVT = (MVT::SimpleValueType)ExpandedReg;
531    if (!EVT.isInteger())
532      break;
533    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
534    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
535    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
536    ValueTypeActions.setTypeAction(EVT, Expand);
537  }
538
539  // Inspect all of the ValueType's smaller than the largest integer
540  // register to see which ones need promotion.
541  unsigned LegalIntReg = LargestIntReg;
542  for (unsigned IntReg = LargestIntReg - 1;
543       IntReg >= (unsigned)MVT::i1; --IntReg) {
544    MVT IVT = (MVT::SimpleValueType)IntReg;
545    if (isTypeLegal(IVT)) {
546      LegalIntReg = IntReg;
547    } else {
548      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
549        (MVT::SimpleValueType)LegalIntReg;
550      ValueTypeActions.setTypeAction(IVT, Promote);
551    }
552  }
553
554  // ppcf128 type is really two f64's.
555  if (!isTypeLegal(MVT::ppcf128)) {
556    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
557    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
558    TransformToType[MVT::ppcf128] = MVT::f64;
559    ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
560  }
561
562  // Decide how to handle f64. If the target does not have native f64 support,
563  // expand it to i64 and we will be generating soft float library calls.
564  if (!isTypeLegal(MVT::f64)) {
565    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
566    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
567    TransformToType[MVT::f64] = MVT::i64;
568    ValueTypeActions.setTypeAction(MVT::f64, Expand);
569  }
570
571  // Decide how to handle f32. If the target does not have native support for
572  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
573  if (!isTypeLegal(MVT::f32)) {
574    if (isTypeLegal(MVT::f64)) {
575      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
576      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
577      TransformToType[MVT::f32] = MVT::f64;
578      ValueTypeActions.setTypeAction(MVT::f32, Promote);
579    } else {
580      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
581      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
582      TransformToType[MVT::f32] = MVT::i32;
583      ValueTypeActions.setTypeAction(MVT::f32, Expand);
584    }
585  }
586
587  // Loop over all of the vector value types to see which need transformations.
588  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
589       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
590    MVT VT = (MVT::SimpleValueType)i;
591    if (!isTypeLegal(VT)) {
592      MVT IntermediateVT, RegisterVT;
593      unsigned NumIntermediates;
594      NumRegistersForVT[i] =
595        getVectorTypeBreakdown(VT,
596                               IntermediateVT, NumIntermediates,
597                               RegisterVT);
598      RegisterTypeForVT[i] = RegisterVT;
599
600      // Determine if there is a legal wider type.
601      bool IsLegalWiderType = false;
602      MVT EltVT = VT.getVectorElementType();
603      unsigned NElts = VT.getVectorNumElements();
604      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
605        MVT SVT = (MVT::SimpleValueType)nVT;
606        if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
607            SVT.getVectorNumElements() > NElts) {
608          TransformToType[i] = SVT;
609          ValueTypeActions.setTypeAction(VT, Promote);
610          IsLegalWiderType = true;
611          break;
612        }
613      }
614      if (!IsLegalWiderType) {
615        MVT NVT = VT.getPow2VectorType();
616        if (NVT == VT) {
617          // Type is already a power of 2.  The default action is to split.
618          TransformToType[i] = MVT::Other;
619          ValueTypeActions.setTypeAction(VT, Expand);
620        } else {
621          TransformToType[i] = NVT;
622          ValueTypeActions.setTypeAction(VT, Promote);
623        }
624      }
625    }
626  }
627}
628
629const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
630  return NULL;
631}
632
633
634MVT TargetLowering::getSetCCResultType(MVT VT) const {
635  return getValueType(TD->getIntPtrType());
636}
637
638
639/// getVectorTypeBreakdown - Vector types are broken down into some number of
640/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
641/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
642/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
643///
644/// This method returns the number of registers needed, and the VT for each
645/// register.  It also returns the VT and quantity of the intermediate values
646/// before they are promoted/expanded.
647///
648unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
649                                                MVT &IntermediateVT,
650                                                unsigned &NumIntermediates,
651                                      MVT &RegisterVT) const {
652  // Figure out the right, legal destination reg to copy into.
653  unsigned NumElts = VT.getVectorNumElements();
654  MVT EltTy = VT.getVectorElementType();
655
656  unsigned NumVectorRegs = 1;
657
658  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
659  // could break down into LHS/RHS like LegalizeDAG does.
660  if (!isPowerOf2_32(NumElts)) {
661    NumVectorRegs = NumElts;
662    NumElts = 1;
663  }
664
665  // Divide the input until we get to a supported size.  This will always
666  // end with a scalar if the target doesn't support vectors.
667  while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
668    NumElts >>= 1;
669    NumVectorRegs <<= 1;
670  }
671
672  NumIntermediates = NumVectorRegs;
673
674  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675  if (!isTypeLegal(NewVT))
676    NewVT = EltTy;
677  IntermediateVT = NewVT;
678
679  MVT DestVT = getTypeToTransformTo(NewVT);
680  RegisterVT = DestVT;
681  if (DestVT.bitsLT(NewVT)) {
682    // Value is expanded, e.g. i64 -> i16.
683    return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
684  } else {
685    // Otherwise, promotion or legal types use the same number of registers as
686    // the vector decimated to the appropriate level.
687    return NumVectorRegs;
688  }
689
690  return 1;
691}
692
693/// getWidenVectorType: given a vector type, returns the type to widen to
694/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
695/// If there is no vector type that we want to widen to, returns MVT::Other
696/// When and where to widen is target dependent based on the cost of
697/// scalarizing vs using the wider vector type.
698MVT TargetLowering::getWidenVectorType(MVT VT) const {
699  assert(VT.isVector());
700  if (isTypeLegal(VT))
701    return VT;
702
703  // Default is not to widen until moved to LegalizeTypes
704  return MVT::Other;
705}
706
707/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
708/// function arguments in the caller parameter area.  This is the actual
709/// alignment, not its logarithm.
710unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
711  return TD->getCallFrameTypeAlignment(Ty);
712}
713
714SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
715                                                 SelectionDAG &DAG) const {
716  if (usesGlobalOffsetTable())
717    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
718  return Table;
719}
720
721bool
722TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
723  // Assume that everything is safe in static mode.
724  if (getTargetMachine().getRelocationModel() == Reloc::Static)
725    return true;
726
727  // In dynamic-no-pic mode, assume that known defined values are safe.
728  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
729      GA &&
730      !GA->getGlobal()->isDeclaration() &&
731      !GA->getGlobal()->isWeakForLinker())
732    return true;
733
734  // Otherwise assume nothing is safe.
735  return false;
736}
737
738//===----------------------------------------------------------------------===//
739//  Optimization Methods
740//===----------------------------------------------------------------------===//
741
742/// ShrinkDemandedConstant - Check to see if the specified operand of the
743/// specified instruction is a constant integer.  If so, check to see if there
744/// are any bits set in the constant that are not demanded.  If so, shrink the
745/// constant and return true.
746bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
747                                                        const APInt &Demanded) {
748  DebugLoc dl = Op.getDebugLoc();
749
750  // FIXME: ISD::SELECT, ISD::SELECT_CC
751  switch (Op.getOpcode()) {
752  default: break;
753  case ISD::XOR:
754  case ISD::AND:
755  case ISD::OR: {
756    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
757    if (!C) return false;
758
759    if (Op.getOpcode() == ISD::XOR &&
760        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
761      return false;
762
763    // if we can expand it to have all bits set, do it
764    if (C->getAPIntValue().intersects(~Demanded)) {
765      MVT VT = Op.getValueType();
766      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
767                                DAG.getConstant(Demanded &
768                                                C->getAPIntValue(),
769                                                VT));
770      return CombineTo(Op, New);
771    }
772
773    break;
774  }
775  }
776
777  return false;
778}
779
780/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
781/// DemandedMask bits of the result of Op are ever used downstream.  If we can
782/// use this information to simplify Op, create a new simplified DAG node and
783/// return true, returning the original and new nodes in Old and New. Otherwise,
784/// analyze the expression and return a mask of KnownOne and KnownZero bits for
785/// the expression (used to simplify the caller).  The KnownZero/One bits may
786/// only be accurate for those bits in the DemandedMask.
787bool TargetLowering::SimplifyDemandedBits(SDValue Op,
788                                          const APInt &DemandedMask,
789                                          APInt &KnownZero,
790                                          APInt &KnownOne,
791                                          TargetLoweringOpt &TLO,
792                                          unsigned Depth) const {
793  unsigned BitWidth = DemandedMask.getBitWidth();
794  assert(Op.getValueSizeInBits() == BitWidth &&
795         "Mask size mismatches value type size!");
796  APInt NewMask = DemandedMask;
797  DebugLoc dl = Op.getDebugLoc();
798
799  // Don't know anything.
800  KnownZero = KnownOne = APInt(BitWidth, 0);
801
802  // Other users may use these bits.
803  if (!Op.getNode()->hasOneUse()) {
804    if (Depth != 0) {
805      // If not at the root, Just compute the KnownZero/KnownOne bits to
806      // simplify things downstream.
807      TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
808      return false;
809    }
810    // If this is the root being simplified, allow it to have multiple uses,
811    // just set the NewMask to all bits.
812    NewMask = APInt::getAllOnesValue(BitWidth);
813  } else if (DemandedMask == 0) {
814    // Not demanding any bits from Op.
815    if (Op.getOpcode() != ISD::UNDEF)
816      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
817    return false;
818  } else if (Depth == 6) {        // Limit search depth.
819    return false;
820  }
821
822  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
823  switch (Op.getOpcode()) {
824  case ISD::Constant:
825    // We know all of the bits for a constant!
826    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
827    KnownZero = ~KnownOne & NewMask;
828    return false;   // Don't fall through, will infinitely loop.
829  case ISD::AND:
830    // If the RHS is a constant, check to see if the LHS would be zero without
831    // using the bits from the RHS.  Below, we use knowledge about the RHS to
832    // simplify the LHS, here we're using information from the LHS to simplify
833    // the RHS.
834    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
835      APInt LHSZero, LHSOne;
836      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
837                                LHSZero, LHSOne, Depth+1);
838      // If the LHS already has zeros where RHSC does, this and is dead.
839      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
840        return TLO.CombineTo(Op, Op.getOperand(0));
841      // If any of the set bits in the RHS are known zero on the LHS, shrink
842      // the constant.
843      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
844        return true;
845    }
846
847    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
848                             KnownOne, TLO, Depth+1))
849      return true;
850    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
851    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
852                             KnownZero2, KnownOne2, TLO, Depth+1))
853      return true;
854    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
855
856    // If all of the demanded bits are known one on one side, return the other.
857    // These bits cannot contribute to the result of the 'and'.
858    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
859      return TLO.CombineTo(Op, Op.getOperand(0));
860    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
861      return TLO.CombineTo(Op, Op.getOperand(1));
862    // If all of the demanded bits in the inputs are known zeros, return zero.
863    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
864      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
865    // If the RHS is a constant, see if we can simplify it.
866    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
867      return true;
868
869    // Output known-1 bits are only known if set in both the LHS & RHS.
870    KnownOne &= KnownOne2;
871    // Output known-0 are known to be clear if zero in either the LHS | RHS.
872    KnownZero |= KnownZero2;
873    break;
874  case ISD::OR:
875    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
876                             KnownOne, TLO, Depth+1))
877      return true;
878    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
879    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
880                             KnownZero2, KnownOne2, TLO, Depth+1))
881      return true;
882    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
883
884    // If all of the demanded bits are known zero on one side, return the other.
885    // These bits cannot contribute to the result of the 'or'.
886    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
887      return TLO.CombineTo(Op, Op.getOperand(0));
888    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
889      return TLO.CombineTo(Op, Op.getOperand(1));
890    // If all of the potentially set bits on one side are known to be set on
891    // the other side, just use the 'other' side.
892    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
893      return TLO.CombineTo(Op, Op.getOperand(0));
894    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
895      return TLO.CombineTo(Op, Op.getOperand(1));
896    // If the RHS is a constant, see if we can simplify it.
897    if (TLO.ShrinkDemandedConstant(Op, NewMask))
898      return true;
899
900    // Output known-0 bits are only known if clear in both the LHS & RHS.
901    KnownZero &= KnownZero2;
902    // Output known-1 are known to be set if set in either the LHS | RHS.
903    KnownOne |= KnownOne2;
904    break;
905  case ISD::XOR:
906    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
907                             KnownOne, TLO, Depth+1))
908      return true;
909    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
910    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
911                             KnownOne2, TLO, Depth+1))
912      return true;
913    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
914
915    // If all of the demanded bits are known zero on one side, return the other.
916    // These bits cannot contribute to the result of the 'xor'.
917    if ((KnownZero & NewMask) == NewMask)
918      return TLO.CombineTo(Op, Op.getOperand(0));
919    if ((KnownZero2 & NewMask) == NewMask)
920      return TLO.CombineTo(Op, Op.getOperand(1));
921
922    // If all of the unknown bits are known to be zero on one side or the other
923    // (but not both) turn this into an *inclusive* or.
924    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
925    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
926      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
927                                               Op.getOperand(0),
928                                               Op.getOperand(1)));
929
930    // Output known-0 bits are known if clear or set in both the LHS & RHS.
931    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
932    // Output known-1 are known to be set if set in only one of the LHS, RHS.
933    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
934
935    // If all of the demanded bits on one side are known, and all of the set
936    // bits on that side are also known to be set on the other side, turn this
937    // into an AND, as we know the bits will be cleared.
938    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
939    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
940      if ((KnownOne & KnownOne2) == KnownOne) {
941        MVT VT = Op.getValueType();
942        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
943        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
944                                                 Op.getOperand(0), ANDC));
945      }
946    }
947
948    // If the RHS is a constant, see if we can simplify it.
949    // for XOR, we prefer to force bits to 1 if they will make a -1.
950    // if we can't force bits, try to shrink constant
951    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
952      APInt Expanded = C->getAPIntValue() | (~NewMask);
953      // if we can expand it to have all bits set, do it
954      if (Expanded.isAllOnesValue()) {
955        if (Expanded != C->getAPIntValue()) {
956          MVT VT = Op.getValueType();
957          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
958                                          TLO.DAG.getConstant(Expanded, VT));
959          return TLO.CombineTo(Op, New);
960        }
961        // if it already has all the bits set, nothing to change
962        // but don't shrink either!
963      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
964        return true;
965      }
966    }
967
968    KnownZero = KnownZeroOut;
969    KnownOne  = KnownOneOut;
970    break;
971  case ISD::SELECT:
972    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
973                             KnownOne, TLO, Depth+1))
974      return true;
975    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
976                             KnownOne2, TLO, Depth+1))
977      return true;
978    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
979    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
980
981    // If the operands are constants, see if we can simplify them.
982    if (TLO.ShrinkDemandedConstant(Op, NewMask))
983      return true;
984
985    // Only known if known in both the LHS and RHS.
986    KnownOne &= KnownOne2;
987    KnownZero &= KnownZero2;
988    break;
989  case ISD::SELECT_CC:
990    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
991                             KnownOne, TLO, Depth+1))
992      return true;
993    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
994                             KnownOne2, TLO, Depth+1))
995      return true;
996    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
997    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
998
999    // If the operands are constants, see if we can simplify them.
1000    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1001      return true;
1002
1003    // Only known if known in both the LHS and RHS.
1004    KnownOne &= KnownOne2;
1005    KnownZero &= KnownZero2;
1006    break;
1007  case ISD::SHL:
1008    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1009      unsigned ShAmt = SA->getZExtValue();
1010      SDValue InOp = Op.getOperand(0);
1011
1012      // If the shift count is an invalid immediate, don't do anything.
1013      if (ShAmt >= BitWidth)
1014        break;
1015
1016      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1017      // single shift.  We can do this if the bottom bits (which are shifted
1018      // out) are never demanded.
1019      if (InOp.getOpcode() == ISD::SRL &&
1020          isa<ConstantSDNode>(InOp.getOperand(1))) {
1021        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1022          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1023          unsigned Opc = ISD::SHL;
1024          int Diff = ShAmt-C1;
1025          if (Diff < 0) {
1026            Diff = -Diff;
1027            Opc = ISD::SRL;
1028          }
1029
1030          SDValue NewSA =
1031            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1032          MVT VT = Op.getValueType();
1033          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1034                                                   InOp.getOperand(0), NewSA));
1035        }
1036      }
1037
1038      if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1039                               KnownZero, KnownOne, TLO, Depth+1))
1040        return true;
1041      KnownZero <<= SA->getZExtValue();
1042      KnownOne  <<= SA->getZExtValue();
1043      // low bits known zero.
1044      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1045    }
1046    break;
1047  case ISD::SRL:
1048    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1049      MVT VT = Op.getValueType();
1050      unsigned ShAmt = SA->getZExtValue();
1051      unsigned VTSize = VT.getSizeInBits();
1052      SDValue InOp = Op.getOperand(0);
1053
1054      // If the shift count is an invalid immediate, don't do anything.
1055      if (ShAmt >= BitWidth)
1056        break;
1057
1058      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1059      // single shift.  We can do this if the top bits (which are shifted out)
1060      // are never demanded.
1061      if (InOp.getOpcode() == ISD::SHL &&
1062          isa<ConstantSDNode>(InOp.getOperand(1))) {
1063        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1064          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1065          unsigned Opc = ISD::SRL;
1066          int Diff = ShAmt-C1;
1067          if (Diff < 0) {
1068            Diff = -Diff;
1069            Opc = ISD::SHL;
1070          }
1071
1072          SDValue NewSA =
1073            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1074          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1075                                                   InOp.getOperand(0), NewSA));
1076        }
1077      }
1078
1079      // Compute the new bits that are at the top now.
1080      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1081                               KnownZero, KnownOne, TLO, Depth+1))
1082        return true;
1083      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1084      KnownZero = KnownZero.lshr(ShAmt);
1085      KnownOne  = KnownOne.lshr(ShAmt);
1086
1087      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1088      KnownZero |= HighBits;  // High bits known zero.
1089    }
1090    break;
1091  case ISD::SRA:
1092    // If this is an arithmetic shift right and only the low-bit is set, we can
1093    // always convert this into a logical shr, even if the shift amount is
1094    // variable.  The low bit of the shift cannot be an input sign bit unless
1095    // the shift amount is >= the size of the datatype, which is undefined.
1096    if (DemandedMask == 1)
1097      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1098                                               Op.getOperand(0), Op.getOperand(1)));
1099
1100    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1101      MVT VT = Op.getValueType();
1102      unsigned ShAmt = SA->getZExtValue();
1103
1104      // If the shift count is an invalid immediate, don't do anything.
1105      if (ShAmt >= BitWidth)
1106        break;
1107
1108      APInt InDemandedMask = (NewMask << ShAmt);
1109
1110      // If any of the demanded bits are produced by the sign extension, we also
1111      // demand the input sign bit.
1112      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1113      if (HighBits.intersects(NewMask))
1114        InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1115
1116      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1117                               KnownZero, KnownOne, TLO, Depth+1))
1118        return true;
1119      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1120      KnownZero = KnownZero.lshr(ShAmt);
1121      KnownOne  = KnownOne.lshr(ShAmt);
1122
1123      // Handle the sign bit, adjusted to where it is now in the mask.
1124      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1125
1126      // If the input sign bit is known to be zero, or if none of the top bits
1127      // are demanded, turn this into an unsigned shift right.
1128      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1129        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1130                                                 Op.getOperand(0),
1131                                                 Op.getOperand(1)));
1132      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1133        KnownOne |= HighBits;
1134      }
1135    }
1136    break;
1137  case ISD::SIGN_EXTEND_INREG: {
1138    MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1139
1140    // Sign extension.  Compute the demanded bits in the result that are not
1141    // present in the input.
1142    APInt NewBits = APInt::getHighBitsSet(BitWidth,
1143                                          BitWidth - EVT.getSizeInBits()) &
1144                    NewMask;
1145
1146    // If none of the extended bits are demanded, eliminate the sextinreg.
1147    if (NewBits == 0)
1148      return TLO.CombineTo(Op, Op.getOperand(0));
1149
1150    APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1151    InSignBit.zext(BitWidth);
1152    APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1153                                                   EVT.getSizeInBits()) &
1154                              NewMask;
1155
1156    // Since the sign extended bits are demanded, we know that the sign
1157    // bit is demanded.
1158    InputDemandedBits |= InSignBit;
1159
1160    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1161                             KnownZero, KnownOne, TLO, Depth+1))
1162      return true;
1163    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1164
1165    // If the sign bit of the input is known set or clear, then we know the
1166    // top bits of the result.
1167
1168    // If the input sign bit is known zero, convert this into a zero extension.
1169    if (KnownZero.intersects(InSignBit))
1170      return TLO.CombineTo(Op,
1171                           TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1172
1173    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1174      KnownOne |= NewBits;
1175      KnownZero &= ~NewBits;
1176    } else {                       // Input sign bit unknown
1177      KnownZero &= ~NewBits;
1178      KnownOne &= ~NewBits;
1179    }
1180    break;
1181  }
1182  case ISD::ZERO_EXTEND: {
1183    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1184    APInt InMask = NewMask;
1185    InMask.trunc(OperandBitWidth);
1186
1187    // If none of the top bits are demanded, convert this into an any_extend.
1188    APInt NewBits =
1189      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1190    if (!NewBits.intersects(NewMask))
1191      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1192                                               Op.getValueType(),
1193                                               Op.getOperand(0)));
1194
1195    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1196                             KnownZero, KnownOne, TLO, Depth+1))
1197      return true;
1198    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1199    KnownZero.zext(BitWidth);
1200    KnownOne.zext(BitWidth);
1201    KnownZero |= NewBits;
1202    break;
1203  }
1204  case ISD::SIGN_EXTEND: {
1205    MVT InVT = Op.getOperand(0).getValueType();
1206    unsigned InBits = InVT.getSizeInBits();
1207    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1208    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1209    APInt NewBits   = ~InMask & NewMask;
1210
1211    // If none of the top bits are demanded, convert this into an any_extend.
1212    if (NewBits == 0)
1213      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1214                                              Op.getValueType(),
1215                                              Op.getOperand(0)));
1216
1217    // Since some of the sign extended bits are demanded, we know that the sign
1218    // bit is demanded.
1219    APInt InDemandedBits = InMask & NewMask;
1220    InDemandedBits |= InSignBit;
1221    InDemandedBits.trunc(InBits);
1222
1223    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1224                             KnownOne, TLO, Depth+1))
1225      return true;
1226    KnownZero.zext(BitWidth);
1227    KnownOne.zext(BitWidth);
1228
1229    // If the sign bit is known zero, convert this to a zero extend.
1230    if (KnownZero.intersects(InSignBit))
1231      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1232                                               Op.getValueType(),
1233                                               Op.getOperand(0)));
1234
1235    // If the sign bit is known one, the top bits match.
1236    if (KnownOne.intersects(InSignBit)) {
1237      KnownOne  |= NewBits;
1238      KnownZero &= ~NewBits;
1239    } else {   // Otherwise, top bits aren't known.
1240      KnownOne  &= ~NewBits;
1241      KnownZero &= ~NewBits;
1242    }
1243    break;
1244  }
1245  case ISD::ANY_EXTEND: {
1246    unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1247    APInt InMask = NewMask;
1248    InMask.trunc(OperandBitWidth);
1249    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1250                             KnownZero, KnownOne, TLO, Depth+1))
1251      return true;
1252    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1253    KnownZero.zext(BitWidth);
1254    KnownOne.zext(BitWidth);
1255    break;
1256  }
1257  case ISD::TRUNCATE: {
1258    // Simplify the input, using demanded bit information, and compute the known
1259    // zero/one bits live out.
1260    APInt TruncMask = NewMask;
1261    TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1262    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1263                             KnownZero, KnownOne, TLO, Depth+1))
1264      return true;
1265    KnownZero.trunc(BitWidth);
1266    KnownOne.trunc(BitWidth);
1267
1268    // If the input is only used by this truncate, see if we can shrink it based
1269    // on the known demanded bits.
1270    if (Op.getOperand(0).getNode()->hasOneUse()) {
1271      SDValue In = Op.getOperand(0);
1272      unsigned InBitWidth = In.getValueSizeInBits();
1273      switch (In.getOpcode()) {
1274      default: break;
1275      case ISD::SRL:
1276        // Shrink SRL by a constant if none of the high bits shifted in are
1277        // demanded.
1278        if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1279          APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1280                                                 InBitWidth - BitWidth);
1281          HighBits = HighBits.lshr(ShAmt->getZExtValue());
1282          HighBits.trunc(BitWidth);
1283
1284          if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1285            // None of the shifted in bits are needed.  Add a truncate of the
1286            // shift input, then shift it.
1287            SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1288                                                 Op.getValueType(),
1289                                                 In.getOperand(0));
1290            return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1291                                                     Op.getValueType(),
1292                                                     NewTrunc,
1293                                                     In.getOperand(1)));
1294          }
1295        }
1296        break;
1297      }
1298    }
1299
1300    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1301    break;
1302  }
1303  case ISD::AssertZext: {
1304    MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1305    APInt InMask = APInt::getLowBitsSet(BitWidth,
1306                                        VT.getSizeInBits());
1307    if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1308                             KnownZero, KnownOne, TLO, Depth+1))
1309      return true;
1310    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1311    KnownZero |= ~InMask & NewMask;
1312    break;
1313  }
1314  case ISD::BIT_CONVERT:
1315#if 0
1316    // If this is an FP->Int bitcast and if the sign bit is the only thing that
1317    // is demanded, turn this into a FGETSIGN.
1318    if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
1319        MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1320        !MVT::isVector(Op.getOperand(0).getValueType())) {
1321      // Only do this xform if FGETSIGN is valid or if before legalize.
1322      if (!TLO.AfterLegalize ||
1323          isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1324        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1325        // place.  We expect the SHL to be eliminated by other optimizations.
1326        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1327                                         Op.getOperand(0));
1328        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1329        SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1330        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1331                                                 Sign, ShAmt));
1332      }
1333    }
1334#endif
1335    break;
1336  default:
1337    // Just use ComputeMaskedBits to compute output bits.
1338    TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1339    break;
1340  }
1341
1342  // If we know the value of all of the demanded bits, return this as a
1343  // constant.
1344  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1345    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1346
1347  return false;
1348}
1349
1350/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1351/// in Mask are known to be either zero or one and return them in the
1352/// KnownZero/KnownOne bitsets.
1353void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1354                                                    const APInt &Mask,
1355                                                    APInt &KnownZero,
1356                                                    APInt &KnownOne,
1357                                                    const SelectionDAG &DAG,
1358                                                    unsigned Depth) const {
1359  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1360          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1361          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1362          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1363         "Should use MaskedValueIsZero if you don't know whether Op"
1364         " is a target node!");
1365  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1366}
1367
1368/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1369/// targets that want to expose additional information about sign bits to the
1370/// DAG Combiner.
1371unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1372                                                         unsigned Depth) const {
1373  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1374          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1375          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1376          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1377         "Should use ComputeNumSignBits if you don't know whether Op"
1378         " is a target node!");
1379  return 1;
1380}
1381
1382/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1383/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1384/// determine which bit is set.
1385///
1386static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1387  // A left-shift of a constant one will have exactly one bit set, because
1388  // shifting the bit off the end is undefined.
1389  if (Val.getOpcode() == ISD::SHL)
1390    if (ConstantSDNode *C =
1391         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1392      if (C->getAPIntValue() == 1)
1393        return true;
1394
1395  // Similarly, a right-shift of a constant sign-bit will have exactly
1396  // one bit set.
1397  if (Val.getOpcode() == ISD::SRL)
1398    if (ConstantSDNode *C =
1399         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1400      if (C->getAPIntValue().isSignBit())
1401        return true;
1402
1403  // More could be done here, though the above checks are enough
1404  // to handle some common cases.
1405
1406  // Fall back to ComputeMaskedBits to catch other known cases.
1407  MVT OpVT = Val.getValueType();
1408  unsigned BitWidth = OpVT.getSizeInBits();
1409  APInt Mask = APInt::getAllOnesValue(BitWidth);
1410  APInt KnownZero, KnownOne;
1411  DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1412  return (KnownZero.countPopulation() == BitWidth - 1) &&
1413         (KnownOne.countPopulation() == 1);
1414}
1415
1416/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1417/// and cc. If it is unable to simplify it, return a null SDValue.
1418SDValue
1419TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
1420                              ISD::CondCode Cond, bool foldBooleans,
1421                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1422  SelectionDAG &DAG = DCI.DAG;
1423
1424  // These setcc operations always fold.
1425  switch (Cond) {
1426  default: break;
1427  case ISD::SETFALSE:
1428  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1429  case ISD::SETTRUE:
1430  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1431  }
1432
1433  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1434    const APInt &C1 = N1C->getAPIntValue();
1435    if (isa<ConstantSDNode>(N0.getNode())) {
1436      return DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1437    } else {
1438      // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1439      // equality comparison, then we're just comparing whether X itself is
1440      // zero.
1441      if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1442          N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1443          N0.getOperand(1).getOpcode() == ISD::Constant) {
1444        unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1445        if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1446            ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1447          if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1448            // (srl (ctlz x), 5) == 0  -> X != 0
1449            // (srl (ctlz x), 5) != 1  -> X != 0
1450            Cond = ISD::SETNE;
1451          } else {
1452            // (srl (ctlz x), 5) != 0  -> X == 0
1453            // (srl (ctlz x), 5) == 1  -> X == 0
1454            Cond = ISD::SETEQ;
1455          }
1456          SDValue Zero = DAG.getConstant(0, N0.getValueType());
1457          return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1458                              Zero, Cond);
1459        }
1460      }
1461
1462      // If the LHS is '(and load, const)', the RHS is 0,
1463      // the test is for equality or unsigned, and all 1 bits of the const are
1464      // in the same partial word, see if we can shorten the load.
1465      if (DCI.isBeforeLegalize() &&
1466          N0.getOpcode() == ISD::AND && C1 == 0 &&
1467          isa<LoadSDNode>(N0.getOperand(0)) &&
1468          N0.getOperand(0).getNode()->hasOneUse() &&
1469          isa<ConstantSDNode>(N0.getOperand(1))) {
1470        LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1471        uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1472        uint64_t bestMask = 0;
1473        unsigned bestWidth = 0, bestOffset = 0;
1474        if (!Lod->isVolatile() && Lod->isUnindexed()) {
1475          unsigned origWidth = N0.getValueType().getSizeInBits();
1476          // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1477          // 8 bits, but have to be careful...
1478          if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1479            origWidth = Lod->getMemoryVT().getSizeInBits();
1480          for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1481            uint64_t newMask = (1ULL << width) - 1;
1482            for (unsigned offset=0; offset<origWidth/width; offset++) {
1483              if ((newMask & Mask)==Mask) {
1484                if (!TD->isLittleEndian())
1485                  bestOffset = (origWidth/width - offset - 1) * (width/8);
1486                else
1487                  bestOffset = (uint64_t)offset * (width/8);
1488                bestMask = Mask >> (offset * (width/8) * 8);
1489                bestWidth = width;
1490                break;
1491              }
1492              newMask = newMask << width;
1493            }
1494          }
1495        }
1496        if (bestWidth) {
1497          MVT newVT = MVT::getIntegerVT(bestWidth);
1498          if (newVT.isRound()) {
1499            MVT PtrType = Lod->getOperand(1).getValueType();
1500            SDValue Ptr = Lod->getBasePtr();
1501            if (bestOffset != 0)
1502              Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1503                                DAG.getConstant(bestOffset, PtrType));
1504            unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1505            SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1506                                          Lod->getSrcValue(),
1507                                          Lod->getSrcValueOffset() + bestOffset,
1508                                          false, NewAlign);
1509            return DAG.getSetCC(dl, VT,
1510                                DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1511                                            DAG.getConstant(bestMask, newVT)),
1512                                DAG.getConstant(0LL, newVT), Cond);
1513          }
1514        }
1515      }
1516
1517      // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1518      if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1519        unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1520
1521        // If the comparison constant has bits in the upper part, the
1522        // zero-extended value could never match.
1523        if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1524                                                C1.getBitWidth() - InSize))) {
1525          switch (Cond) {
1526          case ISD::SETUGT:
1527          case ISD::SETUGE:
1528          case ISD::SETEQ: return DAG.getConstant(0, VT);
1529          case ISD::SETULT:
1530          case ISD::SETULE:
1531          case ISD::SETNE: return DAG.getConstant(1, VT);
1532          case ISD::SETGT:
1533          case ISD::SETGE:
1534            // True if the sign bit of C1 is set.
1535            return DAG.getConstant(C1.isNegative(), VT);
1536          case ISD::SETLT:
1537          case ISD::SETLE:
1538            // True if the sign bit of C1 isn't set.
1539            return DAG.getConstant(C1.isNonNegative(), VT);
1540          default:
1541            break;
1542          }
1543        }
1544
1545        // Otherwise, we can perform the comparison with the low bits.
1546        switch (Cond) {
1547        case ISD::SETEQ:
1548        case ISD::SETNE:
1549        case ISD::SETUGT:
1550        case ISD::SETUGE:
1551        case ISD::SETULT:
1552        case ISD::SETULE:
1553          return DAG.getSetCC(dl, VT, N0.getOperand(0),
1554                          DAG.getConstant(APInt(C1).trunc(InSize),
1555                                          N0.getOperand(0).getValueType()),
1556                          Cond);
1557        default:
1558          break;   // todo, be more careful with signed comparisons
1559        }
1560      } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1561                 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1562        MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1563        unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1564        MVT ExtDstTy = N0.getValueType();
1565        unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1566
1567        // If the extended part has any inconsistent bits, it cannot ever
1568        // compare equal.  In other words, they have to be all ones or all
1569        // zeros.
1570        APInt ExtBits =
1571          APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1572        if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1573          return DAG.getConstant(Cond == ISD::SETNE, VT);
1574
1575        SDValue ZextOp;
1576        MVT Op0Ty = N0.getOperand(0).getValueType();
1577        if (Op0Ty == ExtSrcTy) {
1578          ZextOp = N0.getOperand(0);
1579        } else {
1580          APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1581          ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1582                               DAG.getConstant(Imm, Op0Ty));
1583        }
1584        if (!DCI.isCalledByLegalizer())
1585          DCI.AddToWorklist(ZextOp.getNode());
1586        // Otherwise, make this a use of a zext.
1587        return DAG.getSetCC(dl, VT, ZextOp,
1588                            DAG.getConstant(C1 & APInt::getLowBitsSet(
1589                                                               ExtDstTyBits,
1590                                                               ExtSrcTyBits),
1591                                            ExtDstTy),
1592                            Cond);
1593      } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1594                 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1595
1596        // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
1597        if (N0.getOpcode() == ISD::SETCC) {
1598          bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1599          if (TrueWhenTrue)
1600            return N0;
1601
1602          // Invert the condition.
1603          ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1604          CC = ISD::getSetCCInverse(CC,
1605                                   N0.getOperand(0).getValueType().isInteger());
1606          return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1607        }
1608
1609        if ((N0.getOpcode() == ISD::XOR ||
1610             (N0.getOpcode() == ISD::AND &&
1611              N0.getOperand(0).getOpcode() == ISD::XOR &&
1612              N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1613            isa<ConstantSDNode>(N0.getOperand(1)) &&
1614            cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1615          // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
1616          // can only do this if the top bits are known zero.
1617          unsigned BitWidth = N0.getValueSizeInBits();
1618          if (DAG.MaskedValueIsZero(N0,
1619                                    APInt::getHighBitsSet(BitWidth,
1620                                                          BitWidth-1))) {
1621            // Okay, get the un-inverted input value.
1622            SDValue Val;
1623            if (N0.getOpcode() == ISD::XOR)
1624              Val = N0.getOperand(0);
1625            else {
1626              assert(N0.getOpcode() == ISD::AND &&
1627                     N0.getOperand(0).getOpcode() == ISD::XOR);
1628              // ((X^1)&1)^1 -> X & 1
1629              Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1630                                N0.getOperand(0).getOperand(0),
1631                                N0.getOperand(1));
1632            }
1633            return DAG.getSetCC(dl, VT, Val, N1,
1634                                Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1635          }
1636        }
1637      }
1638
1639      APInt MinVal, MaxVal;
1640      unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1641      if (ISD::isSignedIntSetCC(Cond)) {
1642        MinVal = APInt::getSignedMinValue(OperandBitSize);
1643        MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1644      } else {
1645        MinVal = APInt::getMinValue(OperandBitSize);
1646        MaxVal = APInt::getMaxValue(OperandBitSize);
1647      }
1648
1649      // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1650      if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1651        if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
1652        // X >= C0 --> X > (C0-1)
1653        return DAG.getSetCC(dl, VT, N0,
1654                            DAG.getConstant(C1-1, N1.getValueType()),
1655                            (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1656      }
1657
1658      if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1659        if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
1660        // X <= C0 --> X < (C0+1)
1661        return DAG.getSetCC(dl, VT, N0,
1662                            DAG.getConstant(C1+1, N1.getValueType()),
1663                            (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1664      }
1665
1666      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1667        return DAG.getConstant(0, VT);      // X < MIN --> false
1668      if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1669        return DAG.getConstant(1, VT);      // X >= MIN --> true
1670      if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1671        return DAG.getConstant(0, VT);      // X > MAX --> false
1672      if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1673        return DAG.getConstant(1, VT);      // X <= MAX --> true
1674
1675      // Canonicalize setgt X, Min --> setne X, Min
1676      if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1677        return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1678      // Canonicalize setlt X, Max --> setne X, Max
1679      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1680        return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1681
1682      // If we have setult X, 1, turn it into seteq X, 0
1683      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1684        return DAG.getSetCC(dl, VT, N0,
1685                            DAG.getConstant(MinVal, N0.getValueType()),
1686                            ISD::SETEQ);
1687      // If we have setugt X, Max-1, turn it into seteq X, Max
1688      else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1689        return DAG.getSetCC(dl, VT, N0,
1690                            DAG.getConstant(MaxVal, N0.getValueType()),
1691                            ISD::SETEQ);
1692
1693      // If we have "setcc X, C0", check to see if we can shrink the immediate
1694      // by changing cc.
1695
1696      // SETUGT X, SINTMAX  -> SETLT X, 0
1697      if (Cond == ISD::SETUGT &&
1698          C1 == APInt::getSignedMaxValue(OperandBitSize))
1699        return DAG.getSetCC(dl, VT, N0,
1700                            DAG.getConstant(0, N1.getValueType()),
1701                            ISD::SETLT);
1702
1703      // SETULT X, SINTMIN  -> SETGT X, -1
1704      if (Cond == ISD::SETULT &&
1705          C1 == APInt::getSignedMinValue(OperandBitSize)) {
1706        SDValue ConstMinusOne =
1707            DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1708                            N1.getValueType());
1709        return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1710      }
1711
1712      // Fold bit comparisons when we can.
1713      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1714          VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1715        if (ConstantSDNode *AndRHS =
1716                    dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1717          MVT ShiftTy = DCI.isBeforeLegalize() ?
1718            getPointerTy() : getShiftAmountTy();
1719          if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
1720            // Perform the xform if the AND RHS is a single bit.
1721            if (isPowerOf2_64(AndRHS->getZExtValue())) {
1722              return DAG.getNode(ISD::SRL, dl, VT, N0,
1723                                 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1724                                                 ShiftTy));
1725            }
1726          } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1727            // (X & 8) == 8  -->  (X & 8) >> 3
1728            // Perform the xform if C1 is a single bit.
1729            if (C1.isPowerOf2()) {
1730              return DAG.getNode(ISD::SRL, dl, VT, N0,
1731                                 DAG.getConstant(C1.logBase2(), ShiftTy));
1732            }
1733          }
1734        }
1735    }
1736  } else if (isa<ConstantSDNode>(N0.getNode())) {
1737      // Ensure that the constant occurs on the RHS.
1738    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1739  }
1740
1741  if (isa<ConstantFPSDNode>(N0.getNode())) {
1742    // Constant fold or commute setcc.
1743    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1744    if (O.getNode()) return O;
1745  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1746    // If the RHS of an FP comparison is a constant, simplify it away in
1747    // some cases.
1748    if (CFP->getValueAPF().isNaN()) {
1749      // If an operand is known to be a nan, we can fold it.
1750      switch (ISD::getUnorderedFlavor(Cond)) {
1751      default: assert(0 && "Unknown flavor!");
1752      case 0:  // Known false.
1753        return DAG.getConstant(0, VT);
1754      case 1:  // Known true.
1755        return DAG.getConstant(1, VT);
1756      case 2:  // Undefined.
1757        return DAG.getUNDEF(VT);
1758      }
1759    }
1760
1761    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
1762    // constant if knowing that the operand is non-nan is enough.  We prefer to
1763    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1764    // materialize 0.0.
1765    if (Cond == ISD::SETO || Cond == ISD::SETUO)
1766      return DAG.getSetCC(dl, VT, N0, N0, Cond);
1767  }
1768
1769  if (N0 == N1) {
1770    // We can always fold X == X for integer setcc's.
1771    if (N0.getValueType().isInteger())
1772      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1773    unsigned UOF = ISD::getUnorderedFlavor(Cond);
1774    if (UOF == 2)   // FP operators that are undefined on NaNs.
1775      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1776    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1777      return DAG.getConstant(UOF, VT);
1778    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
1779    // if it is not already.
1780    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1781    if (NewCond != Cond)
1782      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1783  }
1784
1785  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1786      N0.getValueType().isInteger()) {
1787    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1788        N0.getOpcode() == ISD::XOR) {
1789      // Simplify (X+Y) == (X+Z) -->  Y == Z
1790      if (N0.getOpcode() == N1.getOpcode()) {
1791        if (N0.getOperand(0) == N1.getOperand(0))
1792          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1793        if (N0.getOperand(1) == N1.getOperand(1))
1794          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1795        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1796          // If X op Y == Y op X, try other combinations.
1797          if (N0.getOperand(0) == N1.getOperand(1))
1798            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1799                                Cond);
1800          if (N0.getOperand(1) == N1.getOperand(0))
1801            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1802                                Cond);
1803        }
1804      }
1805
1806      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1807        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1808          // Turn (X+C1) == C2 --> X == C2-C1
1809          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1810            return DAG.getSetCC(dl, VT, N0.getOperand(0),
1811                                DAG.getConstant(RHSC->getAPIntValue()-
1812                                                LHSR->getAPIntValue(),
1813                                N0.getValueType()), Cond);
1814          }
1815
1816          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1817          if (N0.getOpcode() == ISD::XOR)
1818            // If we know that all of the inverted bits are zero, don't bother
1819            // performing the inversion.
1820            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1821              return
1822                DAG.getSetCC(dl, VT, N0.getOperand(0),
1823                             DAG.getConstant(LHSR->getAPIntValue() ^
1824                                               RHSC->getAPIntValue(),
1825                                             N0.getValueType()),
1826                             Cond);
1827        }
1828
1829        // Turn (C1-X) == C2 --> X == C1-C2
1830        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1831          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1832            return
1833              DAG.getSetCC(dl, VT, N0.getOperand(1),
1834                           DAG.getConstant(SUBC->getAPIntValue() -
1835                                             RHSC->getAPIntValue(),
1836                                           N0.getValueType()),
1837                           Cond);
1838          }
1839        }
1840      }
1841
1842      // Simplify (X+Z) == X -->  Z == 0
1843      if (N0.getOperand(0) == N1)
1844        return DAG.getSetCC(dl, VT, N0.getOperand(1),
1845                        DAG.getConstant(0, N0.getValueType()), Cond);
1846      if (N0.getOperand(1) == N1) {
1847        if (DAG.isCommutativeBinOp(N0.getOpcode()))
1848          return DAG.getSetCC(dl, VT, N0.getOperand(0),
1849                          DAG.getConstant(0, N0.getValueType()), Cond);
1850        else if (N0.getNode()->hasOneUse()) {
1851          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1852          // (Z-X) == X  --> Z == X<<1
1853          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
1854                                     N1,
1855                                     DAG.getConstant(1, getShiftAmountTy()));
1856          if (!DCI.isCalledByLegalizer())
1857            DCI.AddToWorklist(SH.getNode());
1858          return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1859        }
1860      }
1861    }
1862
1863    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1864        N1.getOpcode() == ISD::XOR) {
1865      // Simplify  X == (X+Z) -->  Z == 0
1866      if (N1.getOperand(0) == N0) {
1867        return DAG.getSetCC(dl, VT, N1.getOperand(1),
1868                        DAG.getConstant(0, N1.getValueType()), Cond);
1869      } else if (N1.getOperand(1) == N0) {
1870        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1871          return DAG.getSetCC(dl, VT, N1.getOperand(0),
1872                          DAG.getConstant(0, N1.getValueType()), Cond);
1873        } else if (N1.getNode()->hasOneUse()) {
1874          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1875          // X == (Z-X)  --> X<<1 == Z
1876          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1877                                     DAG.getConstant(1, getShiftAmountTy()));
1878          if (!DCI.isCalledByLegalizer())
1879            DCI.AddToWorklist(SH.getNode());
1880          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1881        }
1882      }
1883    }
1884
1885    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1886    // Note that where y is variable and is known to have at most
1887    // one bit set (for example, if it is z&1) we cannot do this;
1888    // the expressions are not equivalent when y==0.
1889    if (N0.getOpcode() == ISD::AND)
1890      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1891        if (ValueHasExactlyOneBitSet(N1, DAG)) {
1892          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1893          SDValue Zero = DAG.getConstant(0, N1.getValueType());
1894          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1895        }
1896      }
1897    if (N1.getOpcode() == ISD::AND)
1898      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1899        if (ValueHasExactlyOneBitSet(N0, DAG)) {
1900          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1901          SDValue Zero = DAG.getConstant(0, N0.getValueType());
1902          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1903        }
1904      }
1905  }
1906
1907  // Fold away ALL boolean setcc's.
1908  SDValue Temp;
1909  if (N0.getValueType() == MVT::i1 && foldBooleans) {
1910    switch (Cond) {
1911    default: assert(0 && "Unknown integer setcc!");
1912    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
1913      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1914      N0 = DAG.getNOT(dl, Temp, MVT::i1);
1915      if (!DCI.isCalledByLegalizer())
1916        DCI.AddToWorklist(Temp.getNode());
1917      break;
1918    case ISD::SETNE:  // X != Y   -->  (X^Y)
1919      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1920      break;
1921    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
1922    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
1923      Temp = DAG.getNOT(dl, N0, MVT::i1);
1924      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1925      if (!DCI.isCalledByLegalizer())
1926        DCI.AddToWorklist(Temp.getNode());
1927      break;
1928    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
1929    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
1930      Temp = DAG.getNOT(dl, N1, MVT::i1);
1931      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1932      if (!DCI.isCalledByLegalizer())
1933        DCI.AddToWorklist(Temp.getNode());
1934      break;
1935    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
1936    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
1937      Temp = DAG.getNOT(dl, N0, MVT::i1);
1938      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1939      if (!DCI.isCalledByLegalizer())
1940        DCI.AddToWorklist(Temp.getNode());
1941      break;
1942    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
1943    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
1944      Temp = DAG.getNOT(dl, N1, MVT::i1);
1945      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1946      break;
1947    }
1948    if (VT != MVT::i1) {
1949      if (!DCI.isCalledByLegalizer())
1950        DCI.AddToWorklist(N0.getNode());
1951      // FIXME: If running after legalize, we probably can't do this.
1952      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1953    }
1954    return N0;
1955  }
1956
1957  // Could not fold it.
1958  return SDValue();
1959}
1960
1961/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1962/// node is a GlobalAddress + offset.
1963bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
1964                                    int64_t &Offset) const {
1965  if (isa<GlobalAddressSDNode>(N)) {
1966    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
1967    GA = GASD->getGlobal();
1968    Offset += GASD->getOffset();
1969    return true;
1970  }
1971
1972  if (N->getOpcode() == ISD::ADD) {
1973    SDValue N1 = N->getOperand(0);
1974    SDValue N2 = N->getOperand(1);
1975    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
1976      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
1977      if (V) {
1978        Offset += V->getSExtValue();
1979        return true;
1980      }
1981    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
1982      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
1983      if (V) {
1984        Offset += V->getSExtValue();
1985        return true;
1986      }
1987    }
1988  }
1989  return false;
1990}
1991
1992
1993/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
1994/// loading 'Bytes' bytes from a location that is 'Dist' units away from the
1995/// location that the 'Base' load is loading from.
1996bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
1997                                       unsigned Bytes, int Dist,
1998                                       const MachineFrameInfo *MFI) const {
1999  if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
2000    return false;
2001  MVT VT = LD->getValueType(0);
2002  if (VT.getSizeInBits() / 8 != Bytes)
2003    return false;
2004
2005  SDValue Loc = LD->getOperand(1);
2006  SDValue BaseLoc = Base->getOperand(1);
2007  if (Loc.getOpcode() == ISD::FrameIndex) {
2008    if (BaseLoc.getOpcode() != ISD::FrameIndex)
2009      return false;
2010    int FI  = cast<FrameIndexSDNode>(Loc)->getIndex();
2011    int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2012    int FS  = MFI->getObjectSize(FI);
2013    int BFS = MFI->getObjectSize(BFI);
2014    if (FS != BFS || FS != (int)Bytes) return false;
2015    return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2016  }
2017
2018  GlobalValue *GV1 = NULL;
2019  GlobalValue *GV2 = NULL;
2020  int64_t Offset1 = 0;
2021  int64_t Offset2 = 0;
2022  bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2023  bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2024  if (isGA1 && isGA2 && GV1 == GV2)
2025    return Offset1 == (Offset2 + Dist*Bytes);
2026  return false;
2027}
2028
2029
2030SDValue TargetLowering::
2031PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2032  // Default implementation: no optimization.
2033  return SDValue();
2034}
2035
2036//===----------------------------------------------------------------------===//
2037//  Inline Assembler Implementation Methods
2038//===----------------------------------------------------------------------===//
2039
2040
2041TargetLowering::ConstraintType
2042TargetLowering::getConstraintType(const std::string &Constraint) const {
2043  // FIXME: lots more standard ones to handle.
2044  if (Constraint.size() == 1) {
2045    switch (Constraint[0]) {
2046    default: break;
2047    case 'r': return C_RegisterClass;
2048    case 'm':    // memory
2049    case 'o':    // offsetable
2050    case 'V':    // not offsetable
2051      return C_Memory;
2052    case 'i':    // Simple Integer or Relocatable Constant
2053    case 'n':    // Simple Integer
2054    case 's':    // Relocatable Constant
2055    case 'X':    // Allow ANY value.
2056    case 'I':    // Target registers.
2057    case 'J':
2058    case 'K':
2059    case 'L':
2060    case 'M':
2061    case 'N':
2062    case 'O':
2063    case 'P':
2064      return C_Other;
2065    }
2066  }
2067
2068  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2069      Constraint[Constraint.size()-1] == '}')
2070    return C_Register;
2071  return C_Unknown;
2072}
2073
2074/// LowerXConstraint - try to replace an X constraint, which matches anything,
2075/// with another that has more specific requirements based on the type of the
2076/// corresponding operand.
2077const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
2078  if (ConstraintVT.isInteger())
2079    return "r";
2080  if (ConstraintVT.isFloatingPoint())
2081    return "f";      // works for many targets
2082  return 0;
2083}
2084
2085/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2086/// vector.  If it is invalid, don't add anything to Ops.
2087void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2088                                                  char ConstraintLetter,
2089                                                  bool hasMemory,
2090                                                  std::vector<SDValue> &Ops,
2091                                                  SelectionDAG &DAG) const {
2092  switch (ConstraintLetter) {
2093  default: break;
2094  case 'X':     // Allows any operand; labels (basic block) use this.
2095    if (Op.getOpcode() == ISD::BasicBlock) {
2096      Ops.push_back(Op);
2097      return;
2098    }
2099    // fall through
2100  case 'i':    // Simple Integer or Relocatable Constant
2101  case 'n':    // Simple Integer
2102  case 's': {  // Relocatable Constant
2103    // These operands are interested in values of the form (GV+C), where C may
2104    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2105    // is possible and fine if either GV or C are missing.
2106    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2107    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2108
2109    // If we have "(add GV, C)", pull out GV/C
2110    if (Op.getOpcode() == ISD::ADD) {
2111      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2112      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2113      if (C == 0 || GA == 0) {
2114        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2115        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2116      }
2117      if (C == 0 || GA == 0)
2118        C = 0, GA = 0;
2119    }
2120
2121    // If we find a valid operand, map to the TargetXXX version so that the
2122    // value itself doesn't get selected.
2123    if (GA) {   // Either &GV   or   &GV+C
2124      if (ConstraintLetter != 'n') {
2125        int64_t Offs = GA->getOffset();
2126        if (C) Offs += C->getZExtValue();
2127        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2128                                                 Op.getValueType(), Offs));
2129        return;
2130      }
2131    }
2132    if (C) {   // just C, no GV.
2133      // Simple constants are not allowed for 's'.
2134      if (ConstraintLetter != 's') {
2135        // gcc prints these as sign extended.  Sign extend value to 64 bits
2136        // now; without this it would get ZExt'd later in
2137        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2138        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2139                                            MVT::i64));
2140        return;
2141      }
2142    }
2143    break;
2144  }
2145  }
2146}
2147
2148std::vector<unsigned> TargetLowering::
2149getRegClassForInlineAsmConstraint(const std::string &Constraint,
2150                                  MVT VT) const {
2151  return std::vector<unsigned>();
2152}
2153
2154
2155std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2156getRegForInlineAsmConstraint(const std::string &Constraint,
2157                             MVT VT) const {
2158  if (Constraint[0] != '{')
2159    return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2160  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2161
2162  // Remove the braces from around the name.
2163  std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2164
2165  // Figure out which register class contains this reg.
2166  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2167  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2168       E = RI->regclass_end(); RCI != E; ++RCI) {
2169    const TargetRegisterClass *RC = *RCI;
2170
2171    // If none of the the value types for this register class are valid, we
2172    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2173    bool isLegal = false;
2174    for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2175         I != E; ++I) {
2176      if (isTypeLegal(*I)) {
2177        isLegal = true;
2178        break;
2179      }
2180    }
2181
2182    if (!isLegal) continue;
2183
2184    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2185         I != E; ++I) {
2186      if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
2187        return std::make_pair(*I, RC);
2188    }
2189  }
2190
2191  return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2192}
2193
2194//===----------------------------------------------------------------------===//
2195// Constraint Selection.
2196
2197/// isMatchingInputConstraint - Return true of this is an input operand that is
2198/// a matching constraint like "4".
2199bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2200  assert(!ConstraintCode.empty() && "No known constraint!");
2201  return isdigit(ConstraintCode[0]);
2202}
2203
2204/// getMatchedOperand - If this is an input matching constraint, this method
2205/// returns the output operand it matches.
2206unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2207  assert(!ConstraintCode.empty() && "No known constraint!");
2208  return atoi(ConstraintCode.c_str());
2209}
2210
2211
2212/// getConstraintGenerality - Return an integer indicating how general CT
2213/// is.
2214static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2215  switch (CT) {
2216  default: assert(0 && "Unknown constraint type!");
2217  case TargetLowering::C_Other:
2218  case TargetLowering::C_Unknown:
2219    return 0;
2220  case TargetLowering::C_Register:
2221    return 1;
2222  case TargetLowering::C_RegisterClass:
2223    return 2;
2224  case TargetLowering::C_Memory:
2225    return 3;
2226  }
2227}
2228
2229/// ChooseConstraint - If there are multiple different constraints that we
2230/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2231/// This is somewhat tricky: constraints fall into four classes:
2232///    Other         -> immediates and magic values
2233///    Register      -> one specific register
2234///    RegisterClass -> a group of regs
2235///    Memory        -> memory
2236/// Ideally, we would pick the most specific constraint possible: if we have
2237/// something that fits into a register, we would pick it.  The problem here
2238/// is that if we have something that could either be in a register or in
2239/// memory that use of the register could cause selection of *other*
2240/// operands to fail: they might only succeed if we pick memory.  Because of
2241/// this the heuristic we use is:
2242///
2243///  1) If there is an 'other' constraint, and if the operand is valid for
2244///     that constraint, use it.  This makes us take advantage of 'i'
2245///     constraints when available.
2246///  2) Otherwise, pick the most general constraint present.  This prefers
2247///     'm' over 'r', for example.
2248///
2249static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2250                             bool hasMemory,  const TargetLowering &TLI,
2251                             SDValue Op, SelectionDAG *DAG) {
2252  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2253  unsigned BestIdx = 0;
2254  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2255  int BestGenerality = -1;
2256
2257  // Loop over the options, keeping track of the most general one.
2258  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2259    TargetLowering::ConstraintType CType =
2260      TLI.getConstraintType(OpInfo.Codes[i]);
2261
2262    // If this is an 'other' constraint, see if the operand is valid for it.
2263    // For example, on X86 we might have an 'rI' constraint.  If the operand
2264    // is an integer in the range [0..31] we want to use I (saving a load
2265    // of a register), otherwise we must use 'r'.
2266    if (CType == TargetLowering::C_Other && Op.getNode()) {
2267      assert(OpInfo.Codes[i].size() == 1 &&
2268             "Unhandled multi-letter 'other' constraint");
2269      std::vector<SDValue> ResultOps;
2270      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2271                                       ResultOps, *DAG);
2272      if (!ResultOps.empty()) {
2273        BestType = CType;
2274        BestIdx = i;
2275        break;
2276      }
2277    }
2278
2279    // This constraint letter is more general than the previous one, use it.
2280    int Generality = getConstraintGenerality(CType);
2281    if (Generality > BestGenerality) {
2282      BestType = CType;
2283      BestIdx = i;
2284      BestGenerality = Generality;
2285    }
2286  }
2287
2288  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2289  OpInfo.ConstraintType = BestType;
2290}
2291
2292/// ComputeConstraintToUse - Determines the constraint code and constraint
2293/// type to use for the specific AsmOperandInfo, setting
2294/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2295void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2296                                            SDValue Op,
2297                                            bool hasMemory,
2298                                            SelectionDAG *DAG) const {
2299  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2300
2301  // Single-letter constraints ('r') are very common.
2302  if (OpInfo.Codes.size() == 1) {
2303    OpInfo.ConstraintCode = OpInfo.Codes[0];
2304    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2305  } else {
2306    ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2307  }
2308
2309  // 'X' matches anything.
2310  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2311    // Labels and constants are handled elsewhere ('X' is the only thing
2312    // that matches labels).
2313    if (isa<BasicBlock>(OpInfo.CallOperandVal) ||
2314        isa<ConstantInt>(OpInfo.CallOperandVal))
2315      return;
2316
2317    // Otherwise, try to resolve it to something we know about by looking at
2318    // the actual operand type.
2319    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2320      OpInfo.ConstraintCode = Repl;
2321      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2322    }
2323  }
2324}
2325
2326//===----------------------------------------------------------------------===//
2327//  Loop Strength Reduction hooks
2328//===----------------------------------------------------------------------===//
2329
2330/// isLegalAddressingMode - Return true if the addressing mode represented
2331/// by AM is legal for this target, for a load/store of the specified type.
2332bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2333                                           const Type *Ty) const {
2334  // The default implementation of this implements a conservative RISCy, r+r and
2335  // r+i addr mode.
2336
2337  // Allows a sign-extended 16-bit immediate field.
2338  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2339    return false;
2340
2341  // No global is ever allowed as a base.
2342  if (AM.BaseGV)
2343    return false;
2344
2345  // Only support r+r,
2346  switch (AM.Scale) {
2347  case 0:  // "r+i" or just "i", depending on HasBaseReg.
2348    break;
2349  case 1:
2350    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
2351      return false;
2352    // Otherwise we have r+r or r+i.
2353    break;
2354  case 2:
2355    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
2356      return false;
2357    // Allow 2*r as r+r.
2358    break;
2359  }
2360
2361  return true;
2362}
2363
2364struct mu {
2365  APInt m;     // magic number
2366  bool a;      // add indicator
2367  unsigned s;  // shift amount
2368};
2369
2370/// magicu - calculate the magic numbers required to codegen an integer udiv as
2371/// a sequence of multiply, add and shifts.  Requires that the divisor not be 0.
2372static mu magicu(const APInt& d) {
2373  unsigned p;
2374  APInt nc, delta, q1, r1, q2, r2;
2375  struct mu magu;
2376  magu.a = 0;               // initialize "add" indicator
2377  APInt allOnes = APInt::getAllOnesValue(d.getBitWidth());
2378  APInt signedMin = APInt::getSignedMinValue(d.getBitWidth());
2379  APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth());
2380
2381  nc = allOnes - (-d).urem(d);
2382  p = d.getBitWidth() - 1;  // initialize p
2383  q1 = signedMin.udiv(nc);  // initialize q1 = 2p/nc
2384  r1 = signedMin - q1*nc;   // initialize r1 = rem(2p,nc)
2385  q2 = signedMax.udiv(d);   // initialize q2 = (2p-1)/d
2386  r2 = signedMax - q2*d;    // initialize r2 = rem((2p-1),d)
2387  do {
2388    p = p + 1;
2389    if (r1.uge(nc - r1)) {
2390      q1 = q1 + q1 + 1;  // update q1
2391      r1 = r1 + r1 - nc; // update r1
2392    }
2393    else {
2394      q1 = q1+q1; // update q1
2395      r1 = r1+r1; // update r1
2396    }
2397    if ((r2 + 1).uge(d - r2)) {
2398      if (q2.uge(signedMax)) magu.a = 1;
2399      q2 = q2+q2 + 1;     // update q2
2400      r2 = r2+r2 + 1 - d; // update r2
2401    }
2402    else {
2403      if (q2.uge(signedMin)) magu.a = 1;
2404      q2 = q2+q2;     // update q2
2405      r2 = r2+r2 + 1; // update r2
2406    }
2407    delta = d - 1 - r2;
2408  } while (p < d.getBitWidth()*2 &&
2409           (q1.ult(delta) || (q1 == delta && r1 == 0)));
2410  magu.m = q2 + 1; // resulting magic number
2411  magu.s = p - d.getBitWidth();  // resulting shift
2412  return magu;
2413}
2414
2415// Magic for divide replacement
2416struct ms {
2417  APInt m;  // magic number
2418  unsigned s;  // shift amount
2419};
2420
2421/// magic - calculate the magic numbers required to codegen an integer sdiv as
2422/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
2423/// or -1.
2424static ms magic(const APInt& d) {
2425  unsigned p;
2426  APInt ad, anc, delta, q1, r1, q2, r2, t;
2427  APInt allOnes = APInt::getAllOnesValue(d.getBitWidth());
2428  APInt signedMin = APInt::getSignedMinValue(d.getBitWidth());
2429  APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth());
2430  struct ms mag;
2431
2432  ad = d.abs();
2433  t = signedMin + (d.lshr(d.getBitWidth() - 1));
2434  anc = t - 1 - t.urem(ad);   // absolute value of nc
2435  p = d.getBitWidth() - 1;    // initialize p
2436  q1 = signedMin.udiv(anc);   // initialize q1 = 2p/abs(nc)
2437  r1 = signedMin - q1*anc;    // initialize r1 = rem(2p,abs(nc))
2438  q2 = signedMin.udiv(ad);    // initialize q2 = 2p/abs(d)
2439  r2 = signedMin - q2*ad;     // initialize r2 = rem(2p,abs(d))
2440  do {
2441    p = p + 1;
2442    q1 = q1<<1;          // update q1 = 2p/abs(nc)
2443    r1 = r1<<1;          // update r1 = rem(2p/abs(nc))
2444    if (r1.uge(anc)) {  // must be unsigned comparison
2445      q1 = q1 + 1;
2446      r1 = r1 - anc;
2447    }
2448    q2 = q2<<1;          // update q2 = 2p/abs(d)
2449    r2 = r2<<1;          // update r2 = rem(2p/abs(d))
2450    if (r2.uge(ad)) {   // must be unsigned comparison
2451      q2 = q2 + 1;
2452      r2 = r2 - ad;
2453    }
2454    delta = ad - r2;
2455  } while (q1.ule(delta) || (q1 == delta && r1 == 0));
2456
2457  mag.m = q2 + 1;
2458  if (d.isNegative()) mag.m = -mag.m;   // resulting magic number
2459  mag.s = p - d.getBitWidth();          // resulting shift
2460  return mag;
2461}
2462
2463/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2464/// return a DAG expression to select that will generate the same value by
2465/// multiplying by a magic number.  See:
2466/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2467SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2468                                  std::vector<SDNode*>* Created) const {
2469  MVT VT = N->getValueType(0);
2470  DebugLoc dl= N->getDebugLoc();
2471
2472  // Check to see if we can do this.
2473  // FIXME: We should be more aggressive here.
2474  if (!isTypeLegal(VT))
2475    return SDValue();
2476
2477  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2478  ms magics = magic(d);
2479
2480  // Multiply the numerator (operand 0) by the magic value
2481  // FIXME: We should support doing a MUL in a wider type
2482  SDValue Q;
2483  if (isOperationLegalOrCustom(ISD::MULHS, VT))
2484    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2485                    DAG.getConstant(magics.m, VT));
2486  else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2487    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2488                              N->getOperand(0),
2489                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2490  else
2491    return SDValue();       // No mulhs or equvialent
2492  // If d > 0 and m < 0, add the numerator
2493  if (d.isStrictlyPositive() && magics.m.isNegative()) {
2494    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2495    if (Created)
2496      Created->push_back(Q.getNode());
2497  }
2498  // If d < 0 and m > 0, subtract the numerator.
2499  if (d.isNegative() && magics.m.isStrictlyPositive()) {
2500    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2501    if (Created)
2502      Created->push_back(Q.getNode());
2503  }
2504  // Shift right algebraic if shift value is nonzero
2505  if (magics.s > 0) {
2506    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2507                    DAG.getConstant(magics.s, getShiftAmountTy()));
2508    if (Created)
2509      Created->push_back(Q.getNode());
2510  }
2511  // Extract the sign bit and add it to the quotient
2512  SDValue T =
2513    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2514                                                 getShiftAmountTy()));
2515  if (Created)
2516    Created->push_back(T.getNode());
2517  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2518}
2519
2520/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2521/// return a DAG expression to select that will generate the same value by
2522/// multiplying by a magic number.  See:
2523/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2524SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2525                                  std::vector<SDNode*>* Created) const {
2526  MVT VT = N->getValueType(0);
2527  DebugLoc dl = N->getDebugLoc();
2528
2529  // Check to see if we can do this.
2530  // FIXME: We should be more aggressive here.
2531  if (!isTypeLegal(VT))
2532    return SDValue();
2533
2534  // FIXME: We should use a narrower constant when the upper
2535  // bits are known to be zero.
2536  ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2537  mu magics = magicu(N1C->getAPIntValue());
2538
2539  // Multiply the numerator (operand 0) by the magic value
2540  // FIXME: We should support doing a MUL in a wider type
2541  SDValue Q;
2542  if (isOperationLegalOrCustom(ISD::MULHU, VT))
2543    Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2544                    DAG.getConstant(magics.m, VT));
2545  else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2546    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2547                              N->getOperand(0),
2548                              DAG.getConstant(magics.m, VT)).getNode(), 1);
2549  else
2550    return SDValue();       // No mulhu or equvialent
2551  if (Created)
2552    Created->push_back(Q.getNode());
2553
2554  if (magics.a == 0) {
2555    assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2556           "We shouldn't generate an undefined shift!");
2557    return DAG.getNode(ISD::SRL, dl, VT, Q,
2558                       DAG.getConstant(magics.s, getShiftAmountTy()));
2559  } else {
2560    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2561    if (Created)
2562      Created->push_back(NPQ.getNode());
2563    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2564                      DAG.getConstant(1, getShiftAmountTy()));
2565    if (Created)
2566      Created->push_back(NPQ.getNode());
2567    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2568    if (Created)
2569      Created->push_back(NPQ.getNode());
2570    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2571                       DAG.getConstant(magics.s-1, getShiftAmountTy()));
2572  }
2573}
2574
2575/// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET
2576/// node that don't prevent tail call optimization.
2577static SDValue IgnoreHarmlessInstructions(SDValue node) {
2578  // Found call return.
2579  if (node.getOpcode() == ISD::CALL) return node;
2580  // Ignore MERGE_VALUES. Will have at least one operand.
2581  if (node.getOpcode() == ISD::MERGE_VALUES)
2582    return IgnoreHarmlessInstructions(node.getOperand(0));
2583  // Ignore ANY_EXTEND node.
2584  if (node.getOpcode() == ISD::ANY_EXTEND)
2585    return IgnoreHarmlessInstructions(node.getOperand(0));
2586  if (node.getOpcode() == ISD::TRUNCATE)
2587    return IgnoreHarmlessInstructions(node.getOperand(0));
2588  // Any other node type.
2589  return node;
2590}
2591
2592bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall,
2593                                                    SDValue Ret) {
2594  unsigned NumOps = Ret.getNumOperands();
2595  // ISD::CALL results:(value0, ..., valuen, chain)
2596  // ISD::RET  operands:(chain, value0, flag0, ..., valuen, flagn)
2597  // Value return:
2598  // Check that operand of the RET node sources from the CALL node. The RET node
2599  // has at least two operands. Operand 0 holds the chain. Operand 1 holds the
2600  // value.
2601  if (NumOps > 1 &&
2602      IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0))
2603    return true;
2604  // void return: The RET node  has the chain result value of the CALL node as
2605  // input.
2606  if (NumOps == 1 &&
2607      Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1))
2608    return true;
2609
2610  return false;
2611}
2612