TargetLowering.cpp revision e853d2e2508e21b5c3156c7d8b6e6902a7d2604a 
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/Target/TargetData.h"
18#include "llvm/Target/TargetLoweringObjectFile.h"
19#include "llvm/Target/TargetMachine.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/CodeGen/Analysis.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineJumpTableInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/ADT/BitVector.h"
29#include "llvm/ADT/STLExtras.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/MathExtras.h"
33#include <cctype>
34using namespace llvm;
35
36/// InitLibcallNames - Set default libcall names.
37///
38static void InitLibcallNames(const char **Names) {
39  Names[RTLIB::SHL_I16] = "__ashlhi3";
40  Names[RTLIB::SHL_I32] = "__ashlsi3";
41  Names[RTLIB::SHL_I64] = "__ashldi3";
42  Names[RTLIB::SHL_I128] = "__ashlti3";
43  Names[RTLIB::SRL_I16] = "__lshrhi3";
44  Names[RTLIB::SRL_I32] = "__lshrsi3";
45  Names[RTLIB::SRL_I64] = "__lshrdi3";
46  Names[RTLIB::SRL_I128] = "__lshrti3";
47  Names[RTLIB::SRA_I16] = "__ashrhi3";
48  Names[RTLIB::SRA_I32] = "__ashrsi3";
49  Names[RTLIB::SRA_I64] = "__ashrdi3";
50  Names[RTLIB::SRA_I128] = "__ashrti3";
51  Names[RTLIB::MUL_I8] = "__mulqi3";
52  Names[RTLIB::MUL_I16] = "__mulhi3";
53  Names[RTLIB::MUL_I32] = "__mulsi3";
54  Names[RTLIB::MUL_I64] = "__muldi3";
55  Names[RTLIB::MUL_I128] = "__multi3";
56  Names[RTLIB::MULO_I32] = "__mulosi4";
57  Names[RTLIB::MULO_I64] = "__mulodi4";
58  Names[RTLIB::MULO_I128] = "__muloti4";
59  Names[RTLIB::SDIV_I8] = "__divqi3";
60  Names[RTLIB::SDIV_I16] = "__divhi3";
61  Names[RTLIB::SDIV_I32] = "__divsi3";
62  Names[RTLIB::SDIV_I64] = "__divdi3";
63  Names[RTLIB::SDIV_I128] = "__divti3";
64  Names[RTLIB::UDIV_I8] = "__udivqi3";
65  Names[RTLIB::UDIV_I16] = "__udivhi3";
66  Names[RTLIB::UDIV_I32] = "__udivsi3";
67  Names[RTLIB::UDIV_I64] = "__udivdi3";
68  Names[RTLIB::UDIV_I128] = "__udivti3";
69  Names[RTLIB::SREM_I8] = "__modqi3";
70  Names[RTLIB::SREM_I16] = "__modhi3";
71  Names[RTLIB::SREM_I32] = "__modsi3";
72  Names[RTLIB::SREM_I64] = "__moddi3";
73  Names[RTLIB::SREM_I128] = "__modti3";
74  Names[RTLIB::UREM_I8] = "__umodqi3";
75  Names[RTLIB::UREM_I16] = "__umodhi3";
76  Names[RTLIB::UREM_I32] = "__umodsi3";
77  Names[RTLIB::UREM_I64] = "__umoddi3";
78  Names[RTLIB::UREM_I128] = "__umodti3";
79
80  // These are generally not available.
81  Names[RTLIB::SDIVREM_I8] = 0;
82  Names[RTLIB::SDIVREM_I16] = 0;
83  Names[RTLIB::SDIVREM_I32] = 0;
84  Names[RTLIB::SDIVREM_I64] = 0;
85  Names[RTLIB::SDIVREM_I128] = 0;
86  Names[RTLIB::UDIVREM_I8] = 0;
87  Names[RTLIB::UDIVREM_I16] = 0;
88  Names[RTLIB::UDIVREM_I32] = 0;
89  Names[RTLIB::UDIVREM_I64] = 0;
90  Names[RTLIB::UDIVREM_I128] = 0;
91
92  Names[RTLIB::NEG_I32] = "__negsi2";
93  Names[RTLIB::NEG_I64] = "__negdi2";
94  Names[RTLIB::ADD_F32] = "__addsf3";
95  Names[RTLIB::ADD_F64] = "__adddf3";
96  Names[RTLIB::ADD_F80] = "__addxf3";
97  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98  Names[RTLIB::SUB_F32] = "__subsf3";
99  Names[RTLIB::SUB_F64] = "__subdf3";
100  Names[RTLIB::SUB_F80] = "__subxf3";
101  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102  Names[RTLIB::MUL_F32] = "__mulsf3";
103  Names[RTLIB::MUL_F64] = "__muldf3";
104  Names[RTLIB::MUL_F80] = "__mulxf3";
105  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106  Names[RTLIB::DIV_F32] = "__divsf3";
107  Names[RTLIB::DIV_F64] = "__divdf3";
108  Names[RTLIB::DIV_F80] = "__divxf3";
109  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110  Names[RTLIB::REM_F32] = "fmodf";
111  Names[RTLIB::REM_F64] = "fmod";
112  Names[RTLIB::REM_F80] = "fmodl";
113  Names[RTLIB::REM_PPCF128] = "fmodl";
114  Names[RTLIB::FMA_F32] = "fmaf";
115  Names[RTLIB::FMA_F64] = "fma";
116  Names[RTLIB::FMA_F80] = "fmal";
117  Names[RTLIB::FMA_PPCF128] = "fmal";
118  Names[RTLIB::POWI_F32] = "__powisf2";
119  Names[RTLIB::POWI_F64] = "__powidf2";
120  Names[RTLIB::POWI_F80] = "__powixf2";
121  Names[RTLIB::POWI_PPCF128] = "__powitf2";
122  Names[RTLIB::SQRT_F32] = "sqrtf";
123  Names[RTLIB::SQRT_F64] = "sqrt";
124  Names[RTLIB::SQRT_F80] = "sqrtl";
125  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126  Names[RTLIB::LOG_F32] = "logf";
127  Names[RTLIB::LOG_F64] = "log";
128  Names[RTLIB::LOG_F80] = "logl";
129  Names[RTLIB::LOG_PPCF128] = "logl";
130  Names[RTLIB::LOG2_F32] = "log2f";
131  Names[RTLIB::LOG2_F64] = "log2";
132  Names[RTLIB::LOG2_F80] = "log2l";
133  Names[RTLIB::LOG2_PPCF128] = "log2l";
134  Names[RTLIB::LOG10_F32] = "log10f";
135  Names[RTLIB::LOG10_F64] = "log10";
136  Names[RTLIB::LOG10_F80] = "log10l";
137  Names[RTLIB::LOG10_PPCF128] = "log10l";
138  Names[RTLIB::EXP_F32] = "expf";
139  Names[RTLIB::EXP_F64] = "exp";
140  Names[RTLIB::EXP_F80] = "expl";
141  Names[RTLIB::EXP_PPCF128] = "expl";
142  Names[RTLIB::EXP2_F32] = "exp2f";
143  Names[RTLIB::EXP2_F64] = "exp2";
144  Names[RTLIB::EXP2_F80] = "exp2l";
145  Names[RTLIB::EXP2_PPCF128] = "exp2l";
146  Names[RTLIB::SIN_F32] = "sinf";
147  Names[RTLIB::SIN_F64] = "sin";
148  Names[RTLIB::SIN_F80] = "sinl";
149  Names[RTLIB::SIN_PPCF128] = "sinl";
150  Names[RTLIB::COS_F32] = "cosf";
151  Names[RTLIB::COS_F64] = "cos";
152  Names[RTLIB::COS_F80] = "cosl";
153  Names[RTLIB::COS_PPCF128] = "cosl";
154  Names[RTLIB::POW_F32] = "powf";
155  Names[RTLIB::POW_F64] = "pow";
156  Names[RTLIB::POW_F80] = "powl";
157  Names[RTLIB::POW_PPCF128] = "powl";
158  Names[RTLIB::CEIL_F32] = "ceilf";
159  Names[RTLIB::CEIL_F64] = "ceil";
160  Names[RTLIB::CEIL_F80] = "ceill";
161  Names[RTLIB::CEIL_PPCF128] = "ceill";
162  Names[RTLIB::TRUNC_F32] = "truncf";
163  Names[RTLIB::TRUNC_F64] = "trunc";
164  Names[RTLIB::TRUNC_F80] = "truncl";
165  Names[RTLIB::TRUNC_PPCF128] = "truncl";
166  Names[RTLIB::RINT_F32] = "rintf";
167  Names[RTLIB::RINT_F64] = "rint";
168  Names[RTLIB::RINT_F80] = "rintl";
169  Names[RTLIB::RINT_PPCF128] = "rintl";
170  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174  Names[RTLIB::FLOOR_F32] = "floorf";
175  Names[RTLIB::FLOOR_F64] = "floor";
176  Names[RTLIB::FLOOR_F80] = "floorl";
177  Names[RTLIB::FLOOR_PPCF128] = "floorl";
178  Names[RTLIB::COPYSIGN_F32] = "copysignf";
179  Names[RTLIB::COPYSIGN_F64] = "copysign";
180  Names[RTLIB::COPYSIGN_F80] = "copysignl";
181  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246  Names[RTLIB::OEQ_F32] = "__eqsf2";
247  Names[RTLIB::OEQ_F64] = "__eqdf2";
248  Names[RTLIB::UNE_F32] = "__nesf2";
249  Names[RTLIB::UNE_F64] = "__nedf2";
250  Names[RTLIB::OGE_F32] = "__gesf2";
251  Names[RTLIB::OGE_F64] = "__gedf2";
252  Names[RTLIB::OLT_F32] = "__ltsf2";
253  Names[RTLIB::OLT_F64] = "__ltdf2";
254  Names[RTLIB::OLE_F32] = "__lesf2";
255  Names[RTLIB::OLE_F64] = "__ledf2";
256  Names[RTLIB::OGT_F32] = "__gtsf2";
257  Names[RTLIB::OGT_F64] = "__gtdf2";
258  Names[RTLIB::UO_F32] = "__unordsf2";
259  Names[RTLIB::UO_F64] = "__unorddf2";
260  Names[RTLIB::O_F32] = "__unordsf2";
261  Names[RTLIB::O_F64] = "__unorddf2";
262  Names[RTLIB::MEMCPY] = "memcpy";
263  Names[RTLIB::MEMMOVE] = "memmove";
264  Names[RTLIB::MEMSET] = "memset";
265  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
293  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
298}
299
300/// InitLibcallCallingConvs - Set default libcall CallingConvs.
301///
302static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304    CCs[i] = CallingConv::C;
305  }
306}
307
308/// getFPEXT - Return the FPEXT_*_* value for the given types, or
309/// UNKNOWN_LIBCALL if there is none.
310RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311  if (OpVT == MVT::f32) {
312    if (RetVT == MVT::f64)
313      return FPEXT_F32_F64;
314  }
315
316  return UNKNOWN_LIBCALL;
317}
318
319/// getFPROUND - Return the FPROUND_*_* value for the given types, or
320/// UNKNOWN_LIBCALL if there is none.
321RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322  if (RetVT == MVT::f32) {
323    if (OpVT == MVT::f64)
324      return FPROUND_F64_F32;
325    if (OpVT == MVT::f80)
326      return FPROUND_F80_F32;
327    if (OpVT == MVT::ppcf128)
328      return FPROUND_PPCF128_F32;
329  } else if (RetVT == MVT::f64) {
330    if (OpVT == MVT::f80)
331      return FPROUND_F80_F64;
332    if (OpVT == MVT::ppcf128)
333      return FPROUND_PPCF128_F64;
334  }
335
336  return UNKNOWN_LIBCALL;
337}
338
339/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340/// UNKNOWN_LIBCALL if there is none.
341RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342  if (OpVT == MVT::f32) {
343    if (RetVT == MVT::i8)
344      return FPTOSINT_F32_I8;
345    if (RetVT == MVT::i16)
346      return FPTOSINT_F32_I16;
347    if (RetVT == MVT::i32)
348      return FPTOSINT_F32_I32;
349    if (RetVT == MVT::i64)
350      return FPTOSINT_F32_I64;
351    if (RetVT == MVT::i128)
352      return FPTOSINT_F32_I128;
353  } else if (OpVT == MVT::f64) {
354    if (RetVT == MVT::i8)
355      return FPTOSINT_F64_I8;
356    if (RetVT == MVT::i16)
357      return FPTOSINT_F64_I16;
358    if (RetVT == MVT::i32)
359      return FPTOSINT_F64_I32;
360    if (RetVT == MVT::i64)
361      return FPTOSINT_F64_I64;
362    if (RetVT == MVT::i128)
363      return FPTOSINT_F64_I128;
364  } else if (OpVT == MVT::f80) {
365    if (RetVT == MVT::i32)
366      return FPTOSINT_F80_I32;
367    if (RetVT == MVT::i64)
368      return FPTOSINT_F80_I64;
369    if (RetVT == MVT::i128)
370      return FPTOSINT_F80_I128;
371  } else if (OpVT == MVT::ppcf128) {
372    if (RetVT == MVT::i32)
373      return FPTOSINT_PPCF128_I32;
374    if (RetVT == MVT::i64)
375      return FPTOSINT_PPCF128_I64;
376    if (RetVT == MVT::i128)
377      return FPTOSINT_PPCF128_I128;
378  }
379  return UNKNOWN_LIBCALL;
380}
381
382/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383/// UNKNOWN_LIBCALL if there is none.
384RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385  if (OpVT == MVT::f32) {
386    if (RetVT == MVT::i8)
387      return FPTOUINT_F32_I8;
388    if (RetVT == MVT::i16)
389      return FPTOUINT_F32_I16;
390    if (RetVT == MVT::i32)
391      return FPTOUINT_F32_I32;
392    if (RetVT == MVT::i64)
393      return FPTOUINT_F32_I64;
394    if (RetVT == MVT::i128)
395      return FPTOUINT_F32_I128;
396  } else if (OpVT == MVT::f64) {
397    if (RetVT == MVT::i8)
398      return FPTOUINT_F64_I8;
399    if (RetVT == MVT::i16)
400      return FPTOUINT_F64_I16;
401    if (RetVT == MVT::i32)
402      return FPTOUINT_F64_I32;
403    if (RetVT == MVT::i64)
404      return FPTOUINT_F64_I64;
405    if (RetVT == MVT::i128)
406      return FPTOUINT_F64_I128;
407  } else if (OpVT == MVT::f80) {
408    if (RetVT == MVT::i32)
409      return FPTOUINT_F80_I32;
410    if (RetVT == MVT::i64)
411      return FPTOUINT_F80_I64;
412    if (RetVT == MVT::i128)
413      return FPTOUINT_F80_I128;
414  } else if (OpVT == MVT::ppcf128) {
415    if (RetVT == MVT::i32)
416      return FPTOUINT_PPCF128_I32;
417    if (RetVT == MVT::i64)
418      return FPTOUINT_PPCF128_I64;
419    if (RetVT == MVT::i128)
420      return FPTOUINT_PPCF128_I128;
421  }
422  return UNKNOWN_LIBCALL;
423}
424
425/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426/// UNKNOWN_LIBCALL if there is none.
427RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428  if (OpVT == MVT::i32) {
429    if (RetVT == MVT::f32)
430      return SINTTOFP_I32_F32;
431    else if (RetVT == MVT::f64)
432      return SINTTOFP_I32_F64;
433    else if (RetVT == MVT::f80)
434      return SINTTOFP_I32_F80;
435    else if (RetVT == MVT::ppcf128)
436      return SINTTOFP_I32_PPCF128;
437  } else if (OpVT == MVT::i64) {
438    if (RetVT == MVT::f32)
439      return SINTTOFP_I64_F32;
440    else if (RetVT == MVT::f64)
441      return SINTTOFP_I64_F64;
442    else if (RetVT == MVT::f80)
443      return SINTTOFP_I64_F80;
444    else if (RetVT == MVT::ppcf128)
445      return SINTTOFP_I64_PPCF128;
446  } else if (OpVT == MVT::i128) {
447    if (RetVT == MVT::f32)
448      return SINTTOFP_I128_F32;
449    else if (RetVT == MVT::f64)
450      return SINTTOFP_I128_F64;
451    else if (RetVT == MVT::f80)
452      return SINTTOFP_I128_F80;
453    else if (RetVT == MVT::ppcf128)
454      return SINTTOFP_I128_PPCF128;
455  }
456  return UNKNOWN_LIBCALL;
457}
458
459/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460/// UNKNOWN_LIBCALL if there is none.
461RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462  if (OpVT == MVT::i32) {
463    if (RetVT == MVT::f32)
464      return UINTTOFP_I32_F32;
465    else if (RetVT == MVT::f64)
466      return UINTTOFP_I32_F64;
467    else if (RetVT == MVT::f80)
468      return UINTTOFP_I32_F80;
469    else if (RetVT == MVT::ppcf128)
470      return UINTTOFP_I32_PPCF128;
471  } else if (OpVT == MVT::i64) {
472    if (RetVT == MVT::f32)
473      return UINTTOFP_I64_F32;
474    else if (RetVT == MVT::f64)
475      return UINTTOFP_I64_F64;
476    else if (RetVT == MVT::f80)
477      return UINTTOFP_I64_F80;
478    else if (RetVT == MVT::ppcf128)
479      return UINTTOFP_I64_PPCF128;
480  } else if (OpVT == MVT::i128) {
481    if (RetVT == MVT::f32)
482      return UINTTOFP_I128_F32;
483    else if (RetVT == MVT::f64)
484      return UINTTOFP_I128_F64;
485    else if (RetVT == MVT::f80)
486      return UINTTOFP_I128_F80;
487    else if (RetVT == MVT::ppcf128)
488      return UINTTOFP_I128_PPCF128;
489  }
490  return UNKNOWN_LIBCALL;
491}
492
493/// InitCmpLibcallCCs - Set default comparison libcall CC.
494///
495static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499  CCs[RTLIB::UNE_F32] = ISD::SETNE;
500  CCs[RTLIB::UNE_F64] = ISD::SETNE;
501  CCs[RTLIB::OGE_F32] = ISD::SETGE;
502  CCs[RTLIB::OGE_F64] = ISD::SETGE;
503  CCs[RTLIB::OLT_F32] = ISD::SETLT;
504  CCs[RTLIB::OLT_F64] = ISD::SETLT;
505  CCs[RTLIB::OLE_F32] = ISD::SETLE;
506  CCs[RTLIB::OLE_F64] = ISD::SETLE;
507  CCs[RTLIB::OGT_F32] = ISD::SETGT;
508  CCs[RTLIB::OGT_F64] = ISD::SETGT;
509  CCs[RTLIB::UO_F32] = ISD::SETNE;
510  CCs[RTLIB::UO_F64] = ISD::SETNE;
511  CCs[RTLIB::O_F32] = ISD::SETEQ;
512  CCs[RTLIB::O_F64] = ISD::SETEQ;
513}
514
515/// NOTE: The constructor takes ownership of TLOF.
516TargetLowering::TargetLowering(const TargetMachine &tm,
517                               const TargetLoweringObjectFile *tlof)
518  : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
519  // All operations default to being supported.
520  memset(OpActions, 0, sizeof(OpActions));
521  memset(LoadExtActions, 0, sizeof(LoadExtActions));
522  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524  memset(CondCodeActions, 0, sizeof(CondCodeActions));
525
526  // Set default actions for various operations.
527  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528    // Default all indexed load / store to expand.
529    for (unsigned IM = (unsigned)ISD::PRE_INC;
530         IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531      setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532      setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
533    }
534
535    // These operations default to expand.
536    setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537    setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
538  }
539
540  // Most targets ignore the @llvm.prefetch intrinsic.
541  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
542
543  // ConstantFP nodes default to expand.  Targets can either change this to
544  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545  // to optimize expansions for certain constants.
546  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
547  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
550
551  // These library functions default to expand.
552  setOperationAction(ISD::FLOG ,  MVT::f16, Expand);
553  setOperationAction(ISD::FLOG2,  MVT::f16, Expand);
554  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555  setOperationAction(ISD::FEXP ,  MVT::f16, Expand);
556  setOperationAction(ISD::FEXP2,  MVT::f16, Expand);
557  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559  setOperationAction(ISD::FCEIL,  MVT::f16, Expand);
560  setOperationAction(ISD::FRINT,  MVT::f16, Expand);
561  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
562  setOperationAction(ISD::FLOG ,  MVT::f32, Expand);
563  setOperationAction(ISD::FLOG2,  MVT::f32, Expand);
564  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565  setOperationAction(ISD::FEXP ,  MVT::f32, Expand);
566  setOperationAction(ISD::FEXP2,  MVT::f32, Expand);
567  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569  setOperationAction(ISD::FCEIL,  MVT::f32, Expand);
570  setOperationAction(ISD::FRINT,  MVT::f32, Expand);
571  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
572  setOperationAction(ISD::FLOG ,  MVT::f64, Expand);
573  setOperationAction(ISD::FLOG2,  MVT::f64, Expand);
574  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575  setOperationAction(ISD::FEXP ,  MVT::f64, Expand);
576  setOperationAction(ISD::FEXP2,  MVT::f64, Expand);
577  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579  setOperationAction(ISD::FCEIL,  MVT::f64, Expand);
580  setOperationAction(ISD::FRINT,  MVT::f64, Expand);
581  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
582
583  // Default ISD::TRAP to expand (which turns it into abort).
584  setOperationAction(ISD::TRAP, MVT::Other, Expand);
585
586  IsLittleEndian = TD->isLittleEndian();
587  PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
588  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
589  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
590  maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
591  maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
592    = maxStoresPerMemmoveOptSize = 4;
593  benefitFromCodePlacementOpt = false;
594  UseUnderscoreSetJmp = false;
595  UseUnderscoreLongJmp = false;
596  SelectIsExpensive = false;
597  IntDivIsCheap = false;
598  Pow2DivIsCheap = false;
599  JumpIsExpensive = false;
600  predictableSelectIsExpensive = false;
601  StackPointerRegisterToSaveRestore = 0;
602  ExceptionPointerRegister = 0;
603  ExceptionSelectorRegister = 0;
604  BooleanContents = UndefinedBooleanContent;
605  BooleanVectorContents = UndefinedBooleanContent;
606  SchedPreferenceInfo = Sched::ILP;
607  JumpBufSize = 0;
608  JumpBufAlignment = 0;
609  MinFunctionAlignment = 0;
610  PrefFunctionAlignment = 0;
611  PrefLoopAlignment = 0;
612  MinStackArgumentAlignment = 1;
613  ShouldFoldAtomicFences = false;
614  InsertFencesForAtomic = false;
615  SupportJumpTables = true;
616
617  InitLibcallNames(LibcallRoutineNames);
618  InitCmpLibcallCCs(CmpLibcallCCs);
619  InitLibcallCallingConvs(LibcallCallingConvs);
620}
621
622TargetLowering::~TargetLowering() {
623  delete &TLOF;
624}
625
626MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
627  return MVT::getIntegerVT(8*TD->getPointerSize());
628}
629
630/// canOpTrap - Returns true if the operation can trap for the value type.
631/// VT must be a legal type.
632bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
633  assert(isTypeLegal(VT));
634  switch (Op) {
635  default:
636    return false;
637  case ISD::FDIV:
638  case ISD::FREM:
639  case ISD::SDIV:
640  case ISD::UDIV:
641  case ISD::SREM:
642  case ISD::UREM:
643    return true;
644  }
645}
646
647
648static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
649                                          unsigned &NumIntermediates,
650                                          EVT &RegisterVT,
651                                          TargetLowering *TLI) {
652  // Figure out the right, legal destination reg to copy into.
653  unsigned NumElts = VT.getVectorNumElements();
654  MVT EltTy = VT.getVectorElementType();
655
656  unsigned NumVectorRegs = 1;
657
658  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
659  // could break down into LHS/RHS like LegalizeDAG does.
660  if (!isPowerOf2_32(NumElts)) {
661    NumVectorRegs = NumElts;
662    NumElts = 1;
663  }
664
665  // Divide the input until we get to a supported size.  This will always
666  // end with a scalar if the target doesn't support vectors.
667  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
668    NumElts >>= 1;
669    NumVectorRegs <<= 1;
670  }
671
672  NumIntermediates = NumVectorRegs;
673
674  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675  if (!TLI->isTypeLegal(NewVT))
676    NewVT = EltTy;
677  IntermediateVT = NewVT;
678
679  unsigned NewVTSize = NewVT.getSizeInBits();
680
681  // Convert sizes such as i33 to i64.
682  if (!isPowerOf2_32(NewVTSize))
683    NewVTSize = NextPowerOf2(NewVTSize);
684
685  EVT DestVT = TLI->getRegisterType(NewVT);
686  RegisterVT = DestVT;
687  if (EVT(DestVT).bitsLT(NewVT))    // Value is expanded, e.g. i64 -> i16.
688    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
689
690  // Otherwise, promotion or legal types use the same number of registers as
691  // the vector decimated to the appropriate level.
692  return NumVectorRegs;
693}
694
695/// isLegalRC - Return true if the value types that can be represented by the
696/// specified register class are all legal.
697bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
698  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
699       I != E; ++I) {
700    if (isTypeLegal(*I))
701      return true;
702  }
703  return false;
704}
705
706/// findRepresentativeClass - Return the largest legal super-reg register class
707/// of the register class for the specified type and its associated "cost".
708std::pair<const TargetRegisterClass*, uint8_t>
709TargetLowering::findRepresentativeClass(EVT VT) const {
710  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
711  const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
712  if (!RC)
713    return std::make_pair(RC, 0);
714
715  // Compute the set of all super-register classes.
716  BitVector SuperRegRC(TRI->getNumRegClasses());
717  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
718    SuperRegRC.setBitsInMask(RCI.getMask());
719
720  // Find the first legal register class with the largest spill size.
721  const TargetRegisterClass *BestRC = RC;
722  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
723    const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
724    // We want the largest possible spill size.
725    if (SuperRC->getSize() <= BestRC->getSize())
726      continue;
727    if (!isLegalRC(SuperRC))
728      continue;
729    BestRC = SuperRC;
730  }
731  return std::make_pair(BestRC, 1);
732}
733
734/// computeRegisterProperties - Once all of the register classes are added,
735/// this allows us to compute derived properties we expose.
736void TargetLowering::computeRegisterProperties() {
737  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
738         "Too many value types for ValueTypeActions to hold!");
739
740  // Everything defaults to needing one register.
741  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
742    NumRegistersForVT[i] = 1;
743    RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
744  }
745  // ...except isVoid, which doesn't need any registers.
746  NumRegistersForVT[MVT::isVoid] = 0;
747
748  // Find the largest integer register class.
749  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
750  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
751    assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
752
753  // Every integer value type larger than this largest register takes twice as
754  // many registers to represent as the previous ValueType.
755  for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
756    EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
757    if (!ExpandedVT.isInteger())
758      break;
759    NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
760    RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
761    TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
762    ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
763  }
764
765  // Inspect all of the ValueType's smaller than the largest integer
766  // register to see which ones need promotion.
767  unsigned LegalIntReg = LargestIntReg;
768  for (unsigned IntReg = LargestIntReg - 1;
769       IntReg >= (unsigned)MVT::i1; --IntReg) {
770    EVT IVT = (MVT::SimpleValueType)IntReg;
771    if (isTypeLegal(IVT)) {
772      LegalIntReg = IntReg;
773    } else {
774      RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
775        (const MVT::SimpleValueType)LegalIntReg;
776      ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
777    }
778  }
779
780  // ppcf128 type is really two f64's.
781  if (!isTypeLegal(MVT::ppcf128)) {
782    NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
783    RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
784    TransformToType[MVT::ppcf128] = MVT::f64;
785    ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
786  }
787
788  // Decide how to handle f64. If the target does not have native f64 support,
789  // expand it to i64 and we will be generating soft float library calls.
790  if (!isTypeLegal(MVT::f64)) {
791    NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
792    RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
793    TransformToType[MVT::f64] = MVT::i64;
794    ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
795  }
796
797  // Decide how to handle f32. If the target does not have native support for
798  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
799  if (!isTypeLegal(MVT::f32)) {
800    if (isTypeLegal(MVT::f64)) {
801      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
802      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
803      TransformToType[MVT::f32] = MVT::f64;
804      ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
805    } else {
806      NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
807      RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
808      TransformToType[MVT::f32] = MVT::i32;
809      ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
810    }
811  }
812
813  // Loop over all of the vector value types to see which need transformations.
814  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
815       i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
816    MVT VT = (MVT::SimpleValueType)i;
817    if (isTypeLegal(VT)) continue;
818
819    // Determine if there is a legal wider type.  If so, we should promote to
820    // that wider vector type.
821    EVT EltVT = VT.getVectorElementType();
822    unsigned NElts = VT.getVectorNumElements();
823    if (NElts != 1) {
824      bool IsLegalWiderType = false;
825      // First try to promote the elements of integer vectors. If no legal
826      // promotion was found, fallback to the widen-vector method.
827      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
828        EVT SVT = (MVT::SimpleValueType)nVT;
829        // Promote vectors of integers to vectors with the same number
830        // of elements, with a wider element type.
831        if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
832            && SVT.getVectorNumElements() == NElts &&
833            isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
834          TransformToType[i] = SVT;
835          RegisterTypeForVT[i] = SVT;
836          NumRegistersForVT[i] = 1;
837          ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
838          IsLegalWiderType = true;
839          break;
840        }
841      }
842
843      if (IsLegalWiderType) continue;
844
845      // Try to widen the vector.
846      for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
847        EVT SVT = (MVT::SimpleValueType)nVT;
848        if (SVT.getVectorElementType() == EltVT &&
849            SVT.getVectorNumElements() > NElts &&
850            isTypeLegal(SVT)) {
851          TransformToType[i] = SVT;
852          RegisterTypeForVT[i] = SVT;
853          NumRegistersForVT[i] = 1;
854          ValueTypeActions.setTypeAction(VT, TypeWidenVector);
855          IsLegalWiderType = true;
856          break;
857        }
858      }
859      if (IsLegalWiderType) continue;
860    }
861
862    MVT IntermediateVT;
863    EVT RegisterVT;
864    unsigned NumIntermediates;
865    NumRegistersForVT[i] =
866      getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
867                                RegisterVT, this);
868    RegisterTypeForVT[i] = RegisterVT;
869
870    EVT NVT = VT.getPow2VectorType();
871    if (NVT == VT) {
872      // Type is already a power of 2.  The default action is to split.
873      TransformToType[i] = MVT::Other;
874      unsigned NumElts = VT.getVectorNumElements();
875      ValueTypeActions.setTypeAction(VT,
876            NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
877    } else {
878      TransformToType[i] = NVT;
879      ValueTypeActions.setTypeAction(VT, TypeWidenVector);
880    }
881  }
882
883  // Determine the 'representative' register class for each value type.
884  // An representative register class is the largest (meaning one which is
885  // not a sub-register class / subreg register class) legal register class for
886  // a group of value types. For example, on i386, i8, i16, and i32
887  // representative would be GR32; while on x86_64 it's GR64.
888  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
889    const TargetRegisterClass* RRC;
890    uint8_t Cost;
891    tie(RRC, Cost) =  findRepresentativeClass((MVT::SimpleValueType)i);
892    RepRegClassForVT[i] = RRC;
893    RepRegClassCostForVT[i] = Cost;
894  }
895}
896
897const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
898  return NULL;
899}
900
901EVT TargetLowering::getSetCCResultType(EVT VT) const {
902  assert(!VT.isVector() && "No default SetCC type for vectors!");
903  return PointerTy.SimpleTy;
904}
905
906MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
907  return MVT::i32; // return the default value
908}
909
910/// getVectorTypeBreakdown - Vector types are broken down into some number of
911/// legal first class types.  For example, MVT::v8f32 maps to 2 MVT::v4f32
912/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
913/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
914///
915/// This method returns the number of registers needed, and the VT for each
916/// register.  It also returns the VT and quantity of the intermediate values
917/// before they are promoted/expanded.
918///
919unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
920                                                EVT &IntermediateVT,
921                                                unsigned &NumIntermediates,
922                                                EVT &RegisterVT) const {
923  unsigned NumElts = VT.getVectorNumElements();
924
925  // If there is a wider vector type with the same element type as this one,
926  // or a promoted vector type that has the same number of elements which
927  // are wider, then we should convert to that legal vector type.
928  // This handles things like <2 x float> -> <4 x float> and
929  // <4 x i1> -> <4 x i32>.
930  LegalizeTypeAction TA = getTypeAction(Context, VT);
931  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
932    RegisterVT = getTypeToTransformTo(Context, VT);
933    if (isTypeLegal(RegisterVT)) {
934      IntermediateVT = RegisterVT;
935      NumIntermediates = 1;
936      return 1;
937    }
938  }
939
940  // Figure out the right, legal destination reg to copy into.
941  EVT EltTy = VT.getVectorElementType();
942
943  unsigned NumVectorRegs = 1;
944
945  // FIXME: We don't support non-power-of-2-sized vectors for now.  Ideally we
946  // could break down into LHS/RHS like LegalizeDAG does.
947  if (!isPowerOf2_32(NumElts)) {
948    NumVectorRegs = NumElts;
949    NumElts = 1;
950  }
951
952  // Divide the input until we get to a supported size.  This will always
953  // end with a scalar if the target doesn't support vectors.
954  while (NumElts > 1 && !isTypeLegal(
955                                   EVT::getVectorVT(Context, EltTy, NumElts))) {
956    NumElts >>= 1;
957    NumVectorRegs <<= 1;
958  }
959
960  NumIntermediates = NumVectorRegs;
961
962  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
963  if (!isTypeLegal(NewVT))
964    NewVT = EltTy;
965  IntermediateVT = NewVT;
966
967  EVT DestVT = getRegisterType(Context, NewVT);
968  RegisterVT = DestVT;
969  unsigned NewVTSize = NewVT.getSizeInBits();
970
971  // Convert sizes such as i33 to i64.
972  if (!isPowerOf2_32(NewVTSize))
973    NewVTSize = NextPowerOf2(NewVTSize);
974
975  if (DestVT.bitsLT(NewVT))   // Value is expanded, e.g. i64 -> i16.
976    return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
977
978  // Otherwise, promotion or legal types use the same number of registers as
979  // the vector decimated to the appropriate level.
980  return NumVectorRegs;
981}
982
983/// Get the EVTs and ArgFlags collections that represent the legalized return
984/// type of the given function.  This does not require a DAG or a return value,
985/// and is suitable for use before any DAGs for the function are constructed.
986/// TODO: Move this out of TargetLowering.cpp.
987void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
988                         SmallVectorImpl<ISD::OutputArg> &Outs,
989                         const TargetLowering &TLI) {
990  SmallVector<EVT, 4> ValueVTs;
991  ComputeValueVTs(TLI, ReturnType, ValueVTs);
992  unsigned NumValues = ValueVTs.size();
993  if (NumValues == 0) return;
994
995  for (unsigned j = 0, f = NumValues; j != f; ++j) {
996    EVT VT = ValueVTs[j];
997    ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
998
999    if (attr.hasSExtAttr())
1000      ExtendKind = ISD::SIGN_EXTEND;
1001    else if (attr.hasZExtAttr())
1002      ExtendKind = ISD::ZERO_EXTEND;
1003
1004    // FIXME: C calling convention requires the return type to be promoted to
1005    // at least 32-bit. But this is not necessary for non-C calling
1006    // conventions. The frontend should mark functions whose return values
1007    // require promoting with signext or zeroext attributes.
1008    if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1009      EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1010      if (VT.bitsLT(MinVT))
1011        VT = MinVT;
1012    }
1013
1014    unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1015    EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1016
1017    // 'inreg' on function refers to return value
1018    ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1019    if (attr.hasInRegAttr())
1020      Flags.setInReg();
1021
1022    // Propagate extension type if any
1023    if (attr.hasSExtAttr())
1024      Flags.setSExt();
1025    else if (attr.hasZExtAttr())
1026      Flags.setZExt();
1027
1028    for (unsigned i = 0; i < NumParts; ++i)
1029      Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1030  }
1031}
1032
1033/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1034/// function arguments in the caller parameter area.  This is the actual
1035/// alignment, not its logarithm.
1036unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1037  return TD->getCallFrameTypeAlignment(Ty);
1038}
1039
1040/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1041/// current function.  The returned value is a member of the
1042/// MachineJumpTableInfo::JTEntryKind enum.
1043unsigned TargetLowering::getJumpTableEncoding() const {
1044  // In non-pic modes, just use the address of a block.
1045  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1046    return MachineJumpTableInfo::EK_BlockAddress;
1047
1048  // In PIC mode, if the target supports a GPRel32 directive, use it.
1049  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1050    return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1051
1052  // Otherwise, use a label difference.
1053  return MachineJumpTableInfo::EK_LabelDifference32;
1054}
1055
1056SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1057                                                 SelectionDAG &DAG) const {
1058  // If our PIC model is GP relative, use the global offset table as the base.
1059  unsigned JTEncoding = getJumpTableEncoding();
1060
1061  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1062      (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1063    return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1064
1065  return Table;
1066}
1067
1068/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1069/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1070/// MCExpr.
1071const MCExpr *
1072TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1073                                             unsigned JTI,MCContext &Ctx) const{
1074  // The normal PIC reloc base is the label at the start of the jump table.
1075  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1076}
1077
1078bool
1079TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1080  // Assume that everything is safe in static mode.
1081  if (getTargetMachine().getRelocationModel() == Reloc::Static)
1082    return true;
1083
1084  // In dynamic-no-pic mode, assume that known defined values are safe.
1085  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1086      GA &&
1087      !GA->getGlobal()->isDeclaration() &&
1088      !GA->getGlobal()->isWeakForLinker())
1089    return true;
1090
1091  // Otherwise assume nothing is safe.
1092  return false;
1093}
1094
1095//===----------------------------------------------------------------------===//
1096//  Optimization Methods
1097//===----------------------------------------------------------------------===//
1098
1099/// ShrinkDemandedConstant - Check to see if the specified operand of the
1100/// specified instruction is a constant integer.  If so, check to see if there
1101/// are any bits set in the constant that are not demanded.  If so, shrink the
1102/// constant and return true.
1103bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1104                                                        const APInt &Demanded) {
1105  DebugLoc dl = Op.getDebugLoc();
1106
1107  // FIXME: ISD::SELECT, ISD::SELECT_CC
1108  switch (Op.getOpcode()) {
1109  default: break;
1110  case ISD::XOR:
1111  case ISD::AND:
1112  case ISD::OR: {
1113    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1114    if (!C) return false;
1115
1116    if (Op.getOpcode() == ISD::XOR &&
1117        (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1118      return false;
1119
1120    // if we can expand it to have all bits set, do it
1121    if (C->getAPIntValue().intersects(~Demanded)) {
1122      EVT VT = Op.getValueType();
1123      SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1124                                DAG.getConstant(Demanded &
1125                                                C->getAPIntValue(),
1126                                                VT));
1127      return CombineTo(Op, New);
1128    }
1129
1130    break;
1131  }
1132  }
1133
1134  return false;
1135}
1136
1137/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1138/// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
1139/// cast, but it could be generalized for targets with other types of
1140/// implicit widening casts.
1141bool
1142TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1143                                                    unsigned BitWidth,
1144                                                    const APInt &Demanded,
1145                                                    DebugLoc dl) {
1146  assert(Op.getNumOperands() == 2 &&
1147         "ShrinkDemandedOp only supports binary operators!");
1148  assert(Op.getNode()->getNumValues() == 1 &&
1149         "ShrinkDemandedOp only supports nodes with one result!");
1150
1151  // Don't do this if the node has another user, which may require the
1152  // full value.
1153  if (!Op.getNode()->hasOneUse())
1154    return false;
1155
1156  // Search for the smallest integer type with free casts to and from
1157  // Op's type. For expedience, just check power-of-2 integer types.
1158  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1159  unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1160  if (!isPowerOf2_32(SmallVTBits))
1161    SmallVTBits = NextPowerOf2(SmallVTBits);
1162  for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1163    EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1164    if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1165        TLI.isZExtFree(SmallVT, Op.getValueType())) {
1166      // We found a type with free casts.
1167      SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1168                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1169                                          Op.getNode()->getOperand(0)),
1170                              DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1171                                          Op.getNode()->getOperand(1)));
1172      SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1173      return CombineTo(Op, Z);
1174    }
1175  }
1176  return false;
1177}
1178
1179/// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
1180/// DemandedMask bits of the result of Op are ever used downstream.  If we can
1181/// use this information to simplify Op, create a new simplified DAG node and
1182/// return true, returning the original and new nodes in Old and New. Otherwise,
1183/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1184/// the expression (used to simplify the caller).  The KnownZero/One bits may
1185/// only be accurate for those bits in the DemandedMask.
1186bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1187                                          const APInt &DemandedMask,
1188                                          APInt &KnownZero,
1189                                          APInt &KnownOne,
1190                                          TargetLoweringOpt &TLO,
1191                                          unsigned Depth) const {
1192  unsigned BitWidth = DemandedMask.getBitWidth();
1193  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1194         "Mask size mismatches value type size!");
1195  APInt NewMask = DemandedMask;
1196  DebugLoc dl = Op.getDebugLoc();
1197
1198  // Don't know anything.
1199  KnownZero = KnownOne = APInt(BitWidth, 0);
1200
1201  // Other users may use these bits.
1202  if (!Op.getNode()->hasOneUse()) {
1203    if (Depth != 0) {
1204      // If not at the root, Just compute the KnownZero/KnownOne bits to
1205      // simplify things downstream.
1206      TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1207      return false;
1208    }
1209    // If this is the root being simplified, allow it to have multiple uses,
1210    // just set the NewMask to all bits.
1211    NewMask = APInt::getAllOnesValue(BitWidth);
1212  } else if (DemandedMask == 0) {
1213    // Not demanding any bits from Op.
1214    if (Op.getOpcode() != ISD::UNDEF)
1215      return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1216    return false;
1217  } else if (Depth == 6) {        // Limit search depth.
1218    return false;
1219  }
1220
1221  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1222  switch (Op.getOpcode()) {
1223  case ISD::Constant:
1224    // We know all of the bits for a constant!
1225    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1226    KnownZero = ~KnownOne;
1227    return false;   // Don't fall through, will infinitely loop.
1228  case ISD::AND:
1229    // If the RHS is a constant, check to see if the LHS would be zero without
1230    // using the bits from the RHS.  Below, we use knowledge about the RHS to
1231    // simplify the LHS, here we're using information from the LHS to simplify
1232    // the RHS.
1233    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1234      APInt LHSZero, LHSOne;
1235      // Do not increment Depth here; that can cause an infinite loop.
1236      TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1237      // If the LHS already has zeros where RHSC does, this and is dead.
1238      if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1239        return TLO.CombineTo(Op, Op.getOperand(0));
1240      // If any of the set bits in the RHS are known zero on the LHS, shrink
1241      // the constant.
1242      if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1243        return true;
1244    }
1245
1246    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1247                             KnownOne, TLO, Depth+1))
1248      return true;
1249    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1250    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1251                             KnownZero2, KnownOne2, TLO, Depth+1))
1252      return true;
1253    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1254
1255    // If all of the demanded bits are known one on one side, return the other.
1256    // These bits cannot contribute to the result of the 'and'.
1257    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1258      return TLO.CombineTo(Op, Op.getOperand(0));
1259    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1260      return TLO.CombineTo(Op, Op.getOperand(1));
1261    // If all of the demanded bits in the inputs are known zeros, return zero.
1262    if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1263      return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1264    // If the RHS is a constant, see if we can simplify it.
1265    if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1266      return true;
1267    // If the operation can be done in a smaller type, do so.
1268    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1269      return true;
1270
1271    // Output known-1 bits are only known if set in both the LHS & RHS.
1272    KnownOne &= KnownOne2;
1273    // Output known-0 are known to be clear if zero in either the LHS | RHS.
1274    KnownZero |= KnownZero2;
1275    break;
1276  case ISD::OR:
1277    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1278                             KnownOne, TLO, Depth+1))
1279      return true;
1280    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1281    if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1282                             KnownZero2, KnownOne2, TLO, Depth+1))
1283      return true;
1284    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1285
1286    // If all of the demanded bits are known zero on one side, return the other.
1287    // These bits cannot contribute to the result of the 'or'.
1288    if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1289      return TLO.CombineTo(Op, Op.getOperand(0));
1290    if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1291      return TLO.CombineTo(Op, Op.getOperand(1));
1292    // If all of the potentially set bits on one side are known to be set on
1293    // the other side, just use the 'other' side.
1294    if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1295      return TLO.CombineTo(Op, Op.getOperand(0));
1296    if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1297      return TLO.CombineTo(Op, Op.getOperand(1));
1298    // If the RHS is a constant, see if we can simplify it.
1299    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1300      return true;
1301    // If the operation can be done in a smaller type, do so.
1302    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1303      return true;
1304
1305    // Output known-0 bits are only known if clear in both the LHS & RHS.
1306    KnownZero &= KnownZero2;
1307    // Output known-1 are known to be set if set in either the LHS | RHS.
1308    KnownOne |= KnownOne2;
1309    break;
1310  case ISD::XOR:
1311    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1312                             KnownOne, TLO, Depth+1))
1313      return true;
1314    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1315    if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1316                             KnownOne2, TLO, Depth+1))
1317      return true;
1318    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1319
1320    // If all of the demanded bits are known zero on one side, return the other.
1321    // These bits cannot contribute to the result of the 'xor'.
1322    if ((KnownZero & NewMask) == NewMask)
1323      return TLO.CombineTo(Op, Op.getOperand(0));
1324    if ((KnownZero2 & NewMask) == NewMask)
1325      return TLO.CombineTo(Op, Op.getOperand(1));
1326    // If the operation can be done in a smaller type, do so.
1327    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1328      return true;
1329
1330    // If all of the unknown bits are known to be zero on one side or the other
1331    // (but not both) turn this into an *inclusive* or.
1332    //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1333    if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1334      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1335                                               Op.getOperand(0),
1336                                               Op.getOperand(1)));
1337
1338    // Output known-0 bits are known if clear or set in both the LHS & RHS.
1339    KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1340    // Output known-1 are known to be set if set in only one of the LHS, RHS.
1341    KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1342
1343    // If all of the demanded bits on one side are known, and all of the set
1344    // bits on that side are also known to be set on the other side, turn this
1345    // into an AND, as we know the bits will be cleared.
1346    //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1347    // NB: it is okay if more bits are known than are requested
1348    if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1349      if (KnownOne == KnownOne2) { // set bits are the same on both sides
1350        EVT VT = Op.getValueType();
1351        SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1352        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1353                                                 Op.getOperand(0), ANDC));
1354      }
1355    }
1356
1357    // If the RHS is a constant, see if we can simplify it.
1358    // for XOR, we prefer to force bits to 1 if they will make a -1.
1359    // if we can't force bits, try to shrink constant
1360    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1361      APInt Expanded = C->getAPIntValue() | (~NewMask);
1362      // if we can expand it to have all bits set, do it
1363      if (Expanded.isAllOnesValue()) {
1364        if (Expanded != C->getAPIntValue()) {
1365          EVT VT = Op.getValueType();
1366          SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1367                                          TLO.DAG.getConstant(Expanded, VT));
1368          return TLO.CombineTo(Op, New);
1369        }
1370        // if it already has all the bits set, nothing to change
1371        // but don't shrink either!
1372      } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1373        return true;
1374      }
1375    }
1376
1377    KnownZero = KnownZeroOut;
1378    KnownOne  = KnownOneOut;
1379    break;
1380  case ISD::SELECT:
1381    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1382                             KnownOne, TLO, Depth+1))
1383      return true;
1384    if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1385                             KnownOne2, TLO, Depth+1))
1386      return true;
1387    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1388    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1389
1390    // If the operands are constants, see if we can simplify them.
1391    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1392      return true;
1393
1394    // Only known if known in both the LHS and RHS.
1395    KnownOne &= KnownOne2;
1396    KnownZero &= KnownZero2;
1397    break;
1398  case ISD::SELECT_CC:
1399    if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1400                             KnownOne, TLO, Depth+1))
1401      return true;
1402    if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1403                             KnownOne2, TLO, Depth+1))
1404      return true;
1405    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1406    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1407
1408    // If the operands are constants, see if we can simplify them.
1409    if (TLO.ShrinkDemandedConstant(Op, NewMask))
1410      return true;
1411
1412    // Only known if known in both the LHS and RHS.
1413    KnownOne &= KnownOne2;
1414    KnownZero &= KnownZero2;
1415    break;
1416  case ISD::SHL:
1417    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1418      unsigned ShAmt = SA->getZExtValue();
1419      SDValue InOp = Op.getOperand(0);
1420
1421      // If the shift count is an invalid immediate, don't do anything.
1422      if (ShAmt >= BitWidth)
1423        break;
1424
1425      // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1426      // single shift.  We can do this if the bottom bits (which are shifted
1427      // out) are never demanded.
1428      if (InOp.getOpcode() == ISD::SRL &&
1429          isa<ConstantSDNode>(InOp.getOperand(1))) {
1430        if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1431          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1432          unsigned Opc = ISD::SHL;
1433          int Diff = ShAmt-C1;
1434          if (Diff < 0) {
1435            Diff = -Diff;
1436            Opc = ISD::SRL;
1437          }
1438
1439          SDValue NewSA =
1440            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1441          EVT VT = Op.getValueType();
1442          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1443                                                   InOp.getOperand(0), NewSA));
1444        }
1445      }
1446
1447      if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1448                               KnownZero, KnownOne, TLO, Depth+1))
1449        return true;
1450
1451      // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1452      // are not demanded. This will likely allow the anyext to be folded away.
1453      if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1454        SDValue InnerOp = InOp.getNode()->getOperand(0);
1455        EVT InnerVT = InnerOp.getValueType();
1456        unsigned InnerBits = InnerVT.getSizeInBits();
1457        if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1458            isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1459          EVT ShTy = getShiftAmountTy(InnerVT);
1460          if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1461            ShTy = InnerVT;
1462          SDValue NarrowShl =
1463            TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1464                            TLO.DAG.getConstant(ShAmt, ShTy));
1465          return
1466            TLO.CombineTo(Op,
1467                          TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1468                                          NarrowShl));
1469        }
1470      }
1471
1472      KnownZero <<= SA->getZExtValue();
1473      KnownOne  <<= SA->getZExtValue();
1474      // low bits known zero.
1475      KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1476    }
1477    break;
1478  case ISD::SRL:
1479    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1480      EVT VT = Op.getValueType();
1481      unsigned ShAmt = SA->getZExtValue();
1482      unsigned VTSize = VT.getSizeInBits();
1483      SDValue InOp = Op.getOperand(0);
1484
1485      // If the shift count is an invalid immediate, don't do anything.
1486      if (ShAmt >= BitWidth)
1487        break;
1488
1489      // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1490      // single shift.  We can do this if the top bits (which are shifted out)
1491      // are never demanded.
1492      if (InOp.getOpcode() == ISD::SHL &&
1493          isa<ConstantSDNode>(InOp.getOperand(1))) {
1494        if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1495          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1496          unsigned Opc = ISD::SRL;
1497          int Diff = ShAmt-C1;
1498          if (Diff < 0) {
1499            Diff = -Diff;
1500            Opc = ISD::SHL;
1501          }
1502
1503          SDValue NewSA =
1504            TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1505          return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1506                                                   InOp.getOperand(0), NewSA));
1507        }
1508      }
1509
1510      // Compute the new bits that are at the top now.
1511      if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1512                               KnownZero, KnownOne, TLO, Depth+1))
1513        return true;
1514      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1515      KnownZero = KnownZero.lshr(ShAmt);
1516      KnownOne  = KnownOne.lshr(ShAmt);
1517
1518      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1519      KnownZero |= HighBits;  // High bits known zero.
1520    }
1521    break;
1522  case ISD::SRA:
1523    // If this is an arithmetic shift right and only the low-bit is set, we can
1524    // always convert this into a logical shr, even if the shift amount is
1525    // variable.  The low bit of the shift cannot be an input sign bit unless
1526    // the shift amount is >= the size of the datatype, which is undefined.
1527    if (NewMask == 1)
1528      return TLO.CombineTo(Op,
1529                           TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1530                                           Op.getOperand(0), Op.getOperand(1)));
1531
1532    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1533      EVT VT = Op.getValueType();
1534      unsigned ShAmt = SA->getZExtValue();
1535
1536      // If the shift count is an invalid immediate, don't do anything.
1537      if (ShAmt >= BitWidth)
1538        break;
1539
1540      APInt InDemandedMask = (NewMask << ShAmt);
1541
1542      // If any of the demanded bits are produced by the sign extension, we also
1543      // demand the input sign bit.
1544      APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1545      if (HighBits.intersects(NewMask))
1546        InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1547
1548      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1549                               KnownZero, KnownOne, TLO, Depth+1))
1550        return true;
1551      assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1552      KnownZero = KnownZero.lshr(ShAmt);
1553      KnownOne  = KnownOne.lshr(ShAmt);
1554
1555      // Handle the sign bit, adjusted to where it is now in the mask.
1556      APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1557
1558      // If the input sign bit is known to be zero, or if none of the top bits
1559      // are demanded, turn this into an unsigned shift right.
1560      if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1561        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1562                                                 Op.getOperand(0),
1563                                                 Op.getOperand(1)));
1564      } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1565        KnownOne |= HighBits;
1566      }
1567    }
1568    break;
1569  case ISD::SIGN_EXTEND_INREG: {
1570    EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1571
1572    APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1573    // If we only care about the highest bit, don't bother shifting right.
1574    if (MsbMask == DemandedMask) {
1575      unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1576      SDValue InOp = Op.getOperand(0);
1577
1578      // Compute the correct shift amount type, which must be getShiftAmountTy
1579      // for scalar types after legalization.
1580      EVT ShiftAmtTy = Op.getValueType();
1581      if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1582        ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1583
1584      SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1585      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1586                                            Op.getValueType(), InOp, ShiftAmt));
1587    }
1588
1589    // Sign extension.  Compute the demanded bits in the result that are not
1590    // present in the input.
1591    APInt NewBits =
1592      APInt::getHighBitsSet(BitWidth,
1593                            BitWidth - ExVT.getScalarType().getSizeInBits());
1594
1595    // If none of the extended bits are demanded, eliminate the sextinreg.
1596    if ((NewBits & NewMask) == 0)
1597      return TLO.CombineTo(Op, Op.getOperand(0));
1598
1599    APInt InSignBit =
1600      APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1601    APInt InputDemandedBits =
1602      APInt::getLowBitsSet(BitWidth,
1603                           ExVT.getScalarType().getSizeInBits()) &
1604      NewMask;
1605
1606    // Since the sign extended bits are demanded, we know that the sign
1607    // bit is demanded.
1608    InputDemandedBits |= InSignBit;
1609
1610    if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1611                             KnownZero, KnownOne, TLO, Depth+1))
1612      return true;
1613    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1614
1615    // If the sign bit of the input is known set or clear, then we know the
1616    // top bits of the result.
1617
1618    // If the input sign bit is known zero, convert this into a zero extension.
1619    if (KnownZero.intersects(InSignBit))
1620      return TLO.CombineTo(Op,
1621                          TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1622
1623    if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
1624      KnownOne |= NewBits;
1625      KnownZero &= ~NewBits;
1626    } else {                       // Input sign bit unknown
1627      KnownZero &= ~NewBits;
1628      KnownOne &= ~NewBits;
1629    }
1630    break;
1631  }
1632  case ISD::ZERO_EXTEND: {
1633    unsigned OperandBitWidth =
1634      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1635    APInt InMask = NewMask.trunc(OperandBitWidth);
1636
1637    // If none of the top bits are demanded, convert this into an any_extend.
1638    APInt NewBits =
1639      APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1640    if (!NewBits.intersects(NewMask))
1641      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1642                                               Op.getValueType(),
1643                                               Op.getOperand(0)));
1644
1645    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1646                             KnownZero, KnownOne, TLO, Depth+1))
1647      return true;
1648    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1649    KnownZero = KnownZero.zext(BitWidth);
1650    KnownOne = KnownOne.zext(BitWidth);
1651    KnownZero |= NewBits;
1652    break;
1653  }
1654  case ISD::SIGN_EXTEND: {
1655    EVT InVT = Op.getOperand(0).getValueType();
1656    unsigned InBits = InVT.getScalarType().getSizeInBits();
1657    APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
1658    APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1659    APInt NewBits   = ~InMask & NewMask;
1660
1661    // If none of the top bits are demanded, convert this into an any_extend.
1662    if (NewBits == 0)
1663      return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1664                                              Op.getValueType(),
1665                                              Op.getOperand(0)));
1666
1667    // Since some of the sign extended bits are demanded, we know that the sign
1668    // bit is demanded.
1669    APInt InDemandedBits = InMask & NewMask;
1670    InDemandedBits |= InSignBit;
1671    InDemandedBits = InDemandedBits.trunc(InBits);
1672
1673    if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1674                             KnownOne, TLO, Depth+1))
1675      return true;
1676    KnownZero = KnownZero.zext(BitWidth);
1677    KnownOne = KnownOne.zext(BitWidth);
1678
1679    // If the sign bit is known zero, convert this to a zero extend.
1680    if (KnownZero.intersects(InSignBit))
1681      return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1682                                               Op.getValueType(),
1683                                               Op.getOperand(0)));
1684
1685    // If the sign bit is known one, the top bits match.
1686    if (KnownOne.intersects(InSignBit)) {
1687      KnownOne |= NewBits;
1688      assert((KnownZero & NewBits) == 0);
1689    } else {   // Otherwise, top bits aren't known.
1690      assert((KnownOne & NewBits) == 0);
1691      assert((KnownZero & NewBits) == 0);
1692    }
1693    break;
1694  }
1695  case ISD::ANY_EXTEND: {
1696    unsigned OperandBitWidth =
1697      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1698    APInt InMask = NewMask.trunc(OperandBitWidth);
1699    if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1700                             KnownZero, KnownOne, TLO, Depth+1))
1701      return true;
1702    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1703    KnownZero = KnownZero.zext(BitWidth);
1704    KnownOne = KnownOne.zext(BitWidth);
1705    break;
1706  }
1707  case ISD::TRUNCATE: {
1708    // Simplify the input, using demanded bit information, and compute the known
1709    // zero/one bits live out.
1710    unsigned OperandBitWidth =
1711      Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1712    APInt TruncMask = NewMask.zext(OperandBitWidth);
1713    if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1714                             KnownZero, KnownOne, TLO, Depth+1))
1715      return true;
1716    KnownZero = KnownZero.trunc(BitWidth);
1717    KnownOne = KnownOne.trunc(BitWidth);
1718
1719    // If the input is only used by this truncate, see if we can shrink it based
1720    // on the known demanded bits.
1721    if (Op.getOperand(0).getNode()->hasOneUse()) {
1722      SDValue In = Op.getOperand(0);
1723      switch (In.getOpcode()) {
1724      default: break;
1725      case ISD::SRL:
1726        // Shrink SRL by a constant if none of the high bits shifted in are
1727        // demanded.
1728        if (TLO.LegalTypes() &&
1729            !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1730          // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1731          // undesirable.
1732          break;
1733        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1734        if (!ShAmt)
1735          break;
1736        SDValue Shift = In.getOperand(1);
1737        if (TLO.LegalTypes()) {
1738          uint64_t ShVal = ShAmt->getZExtValue();
1739          Shift =
1740            TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1741        }
1742
1743        APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1744                                               OperandBitWidth - BitWidth);
1745        HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1746
1747        if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1748          // None of the shifted in bits are needed.  Add a truncate of the
1749          // shift input, then shift it.
1750          SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1751                                             Op.getValueType(),
1752                                             In.getOperand(0));
1753          return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1754                                                   Op.getValueType(),
1755                                                   NewTrunc,
1756                                                   Shift));
1757        }
1758        break;
1759      }
1760    }
1761
1762    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1763    break;
1764  }
1765  case ISD::AssertZext: {
1766    // AssertZext demands all of the high bits, plus any of the low bits
1767    // demanded by its users.
1768    EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1769    APInt InMask = APInt::getLowBitsSet(BitWidth,
1770                                        VT.getSizeInBits());
1771    if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1772                             KnownZero, KnownOne, TLO, Depth+1))
1773      return true;
1774    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1775
1776    KnownZero |= ~InMask & NewMask;
1777    break;
1778  }
1779  case ISD::BITCAST:
1780    // If this is an FP->Int bitcast and if the sign bit is the only
1781    // thing demanded, turn this into a FGETSIGN.
1782    if (!TLO.LegalOperations() &&
1783        !Op.getValueType().isVector() &&
1784        !Op.getOperand(0).getValueType().isVector() &&
1785        NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1786        Op.getOperand(0).getValueType().isFloatingPoint()) {
1787      bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1788      bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1789      if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1790        EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1791        // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1792        // place.  We expect the SHL to be eliminated by other optimizations.
1793        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1794        unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1795        if (!OpVTLegal && OpVTSizeInBits > 32)
1796          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1797        unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1798        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1799        return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1800                                                 Op.getValueType(),
1801                                                 Sign, ShAmt));
1802      }
1803    }
1804    break;
1805  case ISD::ADD:
1806  case ISD::MUL:
1807  case ISD::SUB: {
1808    // Add, Sub, and Mul don't demand any bits in positions beyond that
1809    // of the highest bit demanded of them.
1810    APInt LoMask = APInt::getLowBitsSet(BitWidth,
1811                                        BitWidth - NewMask.countLeadingZeros());
1812    if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1813                             KnownOne2, TLO, Depth+1))
1814      return true;
1815    if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1816                             KnownOne2, TLO, Depth+1))
1817      return true;
1818    // See if the operation should be performed at a smaller bit width.
1819    if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1820      return true;
1821  }
1822  // FALL THROUGH
1823  default:
1824    // Just use ComputeMaskedBits to compute output bits.
1825    TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1826    break;
1827  }
1828
1829  // If we know the value of all of the demanded bits, return this as a
1830  // constant.
1831  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1832    return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1833
1834  return false;
1835}
1836
1837/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1838/// in Mask are known to be either zero or one and return them in the
1839/// KnownZero/KnownOne bitsets.
1840void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1841                                                    APInt &KnownZero,
1842                                                    APInt &KnownOne,
1843                                                    const SelectionDAG &DAG,
1844                                                    unsigned Depth) const {
1845  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1846          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1847          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1848          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1849         "Should use MaskedValueIsZero if you don't know whether Op"
1850         " is a target node!");
1851  KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1852}
1853
1854/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1855/// targets that want to expose additional information about sign bits to the
1856/// DAG Combiner.
1857unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1858                                                         unsigned Depth) const {
1859  assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1860          Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1861          Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1862          Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1863         "Should use ComputeNumSignBits if you don't know whether Op"
1864         " is a target node!");
1865  return 1;
1866}
1867
1868/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1869/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1870/// determine which bit is set.
1871///
1872static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1873  // A left-shift of a constant one will have exactly one bit set, because
1874  // shifting the bit off the end is undefined.
1875  if (Val.getOpcode() == ISD::SHL)
1876    if (ConstantSDNode *C =
1877         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1878      if (C->getAPIntValue() == 1)
1879        return true;
1880
1881  // Similarly, a right-shift of a constant sign-bit will have exactly
1882  // one bit set.
1883  if (Val.getOpcode() == ISD::SRL)
1884    if (ConstantSDNode *C =
1885         dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1886      if (C->getAPIntValue().isSignBit())
1887        return true;
1888
1889  // More could be done here, though the above checks are enough
1890  // to handle some common cases.
1891
1892  // Fall back to ComputeMaskedBits to catch other known cases.
1893  EVT OpVT = Val.getValueType();
1894  unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1895  APInt KnownZero, KnownOne;
1896  DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1897  return (KnownZero.countPopulation() == BitWidth - 1) &&
1898         (KnownOne.countPopulation() == 1);
1899}
1900
1901/// SimplifySetCC - Try to simplify a setcc built with the specified operands
1902/// and cc. If it is unable to simplify it, return a null SDValue.
1903SDValue
1904TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1905                              ISD::CondCode Cond, bool foldBooleans,
1906                              DAGCombinerInfo &DCI, DebugLoc dl) const {
1907  SelectionDAG &DAG = DCI.DAG;
1908
1909  // These setcc operations always fold.
1910  switch (Cond) {
1911  default: break;
1912  case ISD::SETFALSE:
1913  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1914  case ISD::SETTRUE:
1915  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1916  }
1917
1918  // Ensure that the constant occurs on the RHS, and fold constant
1919  // comparisons.
1920  if (isa<ConstantSDNode>(N0.getNode()))
1921    return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1922
1923  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1924    const APInt &C1 = N1C->getAPIntValue();
1925
1926    // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1927    // equality comparison, then we're just comparing whether X itself is
1928    // zero.
1929    if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1930        N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1931        N0.getOperand(1).getOpcode() == ISD::Constant) {
1932      const APInt &ShAmt
1933        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1934      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1935          ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1936        if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1937          // (srl (ctlz x), 5) == 0  -> X != 0
1938          // (srl (ctlz x), 5) != 1  -> X != 0
1939          Cond = ISD::SETNE;
1940        } else {
1941          // (srl (ctlz x), 5) != 0  -> X == 0
1942          // (srl (ctlz x), 5) == 1  -> X == 0
1943          Cond = ISD::SETEQ;
1944        }
1945        SDValue Zero = DAG.getConstant(0, N0.getValueType());
1946        return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1947                            Zero, Cond);
1948      }
1949    }
1950
1951    SDValue CTPOP = N0;
1952    // Look through truncs that don't change the value of a ctpop.
1953    if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1954      CTPOP = N0.getOperand(0);
1955
1956    if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1957        (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1958                        Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1959      EVT CTVT = CTPOP.getValueType();
1960      SDValue CTOp = CTPOP.getOperand(0);
1961
1962      // (ctpop x) u< 2 -> (x & x-1) == 0
1963      // (ctpop x) u> 1 -> (x & x-1) != 0
1964      if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1965        SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1966                                  DAG.getConstant(1, CTVT));
1967        SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1968        ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1969        return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1970      }
1971
1972      // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1973    }
1974
1975    // (zext x) == C --> x == (trunc C)
1976    if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1977        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1978      unsigned MinBits = N0.getValueSizeInBits();
1979      SDValue PreZExt;
1980      if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1981        // ZExt
1982        MinBits = N0->getOperand(0).getValueSizeInBits();
1983        PreZExt = N0->getOperand(0);
1984      } else if (N0->getOpcode() == ISD::AND) {
1985        // DAGCombine turns costly ZExts into ANDs
1986        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1987          if ((C->getAPIntValue()+1).isPowerOf2()) {
1988            MinBits = C->getAPIntValue().countTrailingOnes();
1989            PreZExt = N0->getOperand(0);
1990          }
1991      } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1992        // ZEXTLOAD
1993        if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1994          MinBits = LN0->getMemoryVT().getSizeInBits();
1995          PreZExt = N0;
1996        }
1997      }
1998
1999      // Make sure we're not losing bits from the constant.
2000      if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2001        EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2002        if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2003          // Will get folded away.
2004          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2005          SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2006          return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2007        }
2008      }
2009    }
2010
2011    // If the LHS is '(and load, const)', the RHS is 0,
2012    // the test is for equality or unsigned, and all 1 bits of the const are
2013    // in the same partial word, see if we can shorten the load.
2014    if (DCI.isBeforeLegalize() &&
2015        N0.getOpcode() == ISD::AND && C1 == 0 &&
2016        N0.getNode()->hasOneUse() &&
2017        isa<LoadSDNode>(N0.getOperand(0)) &&
2018        N0.getOperand(0).getNode()->hasOneUse() &&
2019        isa<ConstantSDNode>(N0.getOperand(1))) {
2020      LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2021      APInt bestMask;
2022      unsigned bestWidth = 0, bestOffset = 0;
2023      if (!Lod->isVolatile() && Lod->isUnindexed()) {
2024        unsigned origWidth = N0.getValueType().getSizeInBits();
2025        unsigned maskWidth = origWidth;
2026        // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2027        // 8 bits, but have to be careful...
2028        if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2029          origWidth = Lod->getMemoryVT().getSizeInBits();
2030        const APInt &Mask =
2031          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2032        for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2033          APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2034          for (unsigned offset=0; offset<origWidth/width; offset++) {
2035            if ((newMask & Mask) == Mask) {
2036              if (!TD->isLittleEndian())
2037                bestOffset = (origWidth/width - offset - 1) * (width/8);
2038              else
2039                bestOffset = (uint64_t)offset * (width/8);
2040              bestMask = Mask.lshr(offset * (width/8) * 8);
2041              bestWidth = width;
2042              break;
2043            }
2044            newMask = newMask << width;
2045          }
2046        }
2047      }
2048      if (bestWidth) {
2049        EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2050        if (newVT.isRound()) {
2051          EVT PtrType = Lod->getOperand(1).getValueType();
2052          SDValue Ptr = Lod->getBasePtr();
2053          if (bestOffset != 0)
2054            Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2055                              DAG.getConstant(bestOffset, PtrType));
2056          unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2057          SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2058                                Lod->getPointerInfo().getWithOffset(bestOffset),
2059                                        false, false, false, NewAlign);
2060          return DAG.getSetCC(dl, VT,
2061                              DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2062                                      DAG.getConstant(bestMask.trunc(bestWidth),
2063                                                      newVT)),
2064                              DAG.getConstant(0LL, newVT), Cond);
2065        }
2066      }
2067    }
2068
2069    // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2070    if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2071      unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2072
2073      // If the comparison constant has bits in the upper part, the
2074      // zero-extended value could never match.
2075      if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2076                                              C1.getBitWidth() - InSize))) {
2077        switch (Cond) {
2078        case ISD::SETUGT:
2079        case ISD::SETUGE:
2080        case ISD::SETEQ: return DAG.getConstant(0, VT);
2081        case ISD::SETULT:
2082        case ISD::SETULE:
2083        case ISD::SETNE: return DAG.getConstant(1, VT);
2084        case ISD::SETGT:
2085        case ISD::SETGE:
2086          // True if the sign bit of C1 is set.
2087          return DAG.getConstant(C1.isNegative(), VT);
2088        case ISD::SETLT:
2089        case ISD::SETLE:
2090          // True if the sign bit of C1 isn't set.
2091          return DAG.getConstant(C1.isNonNegative(), VT);
2092        default:
2093          break;
2094        }
2095      }
2096
2097      // Otherwise, we can perform the comparison with the low bits.
2098      switch (Cond) {
2099      case ISD::SETEQ:
2100      case ISD::SETNE:
2101      case ISD::SETUGT:
2102      case ISD::SETUGE:
2103      case ISD::SETULT:
2104      case ISD::SETULE: {
2105        EVT newVT = N0.getOperand(0).getValueType();
2106        if (DCI.isBeforeLegalizeOps() ||
2107            (isOperationLegal(ISD::SETCC, newVT) &&
2108              getCondCodeAction(Cond, newVT)==Legal))
2109          return DAG.getSetCC(dl, VT, N0.getOperand(0),
2110                              DAG.getConstant(C1.trunc(InSize), newVT),
2111                              Cond);
2112        break;
2113      }
2114      default:
2115        break;   // todo, be more careful with signed comparisons
2116      }
2117    } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2118               (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2119      EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2120      unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2121      EVT ExtDstTy = N0.getValueType();
2122      unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2123
2124      // If the constant doesn't fit into the number of bits for the source of
2125      // the sign extension, it is impossible for both sides to be equal.
2126      if (C1.getMinSignedBits() > ExtSrcTyBits)
2127        return DAG.getConstant(Cond == ISD::SETNE, VT);
2128
2129      SDValue ZextOp;
2130      EVT Op0Ty = N0.getOperand(0).getValueType();
2131      if (Op0Ty == ExtSrcTy) {
2132        ZextOp = N0.getOperand(0);
2133      } else {
2134        APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2135        ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2136                              DAG.getConstant(Imm, Op0Ty));
2137      }
2138      if (!DCI.isCalledByLegalizer())
2139        DCI.AddToWorklist(ZextOp.getNode());
2140      // Otherwise, make this a use of a zext.
2141      return DAG.getSetCC(dl, VT, ZextOp,
2142                          DAG.getConstant(C1 & APInt::getLowBitsSet(
2143                                                              ExtDstTyBits,
2144                                                              ExtSrcTyBits),
2145                                          ExtDstTy),
2146                          Cond);
2147    } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2148                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2149      // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
2150      if (N0.getOpcode() == ISD::SETCC &&
2151          isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2152        bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2153        if (TrueWhenTrue)
2154          return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2155        // Invert the condition.
2156        ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2157        CC = ISD::getSetCCInverse(CC,
2158                                  N0.getOperand(0).getValueType().isInteger());
2159        return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2160      }
2161
2162      if ((N0.getOpcode() == ISD::XOR ||
2163           (N0.getOpcode() == ISD::AND &&
2164            N0.getOperand(0).getOpcode() == ISD::XOR &&
2165            N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2166          isa<ConstantSDNode>(N0.getOperand(1)) &&
2167          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2168        // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
2169        // can only do this if the top bits are known zero.
2170        unsigned BitWidth = N0.getValueSizeInBits();
2171        if (DAG.MaskedValueIsZero(N0,
2172                                  APInt::getHighBitsSet(BitWidth,
2173                                                        BitWidth-1))) {
2174          // Okay, get the un-inverted input value.
2175          SDValue Val;
2176          if (N0.getOpcode() == ISD::XOR)
2177            Val = N0.getOperand(0);
2178          else {
2179            assert(N0.getOpcode() == ISD::AND &&
2180                    N0.getOperand(0).getOpcode() == ISD::XOR);
2181            // ((X^1)&1)^1 -> X & 1
2182            Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2183                              N0.getOperand(0).getOperand(0),
2184                              N0.getOperand(1));
2185          }
2186
2187          return DAG.getSetCC(dl, VT, Val, N1,
2188                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2189        }
2190      } else if (N1C->getAPIntValue() == 1 &&
2191                 (VT == MVT::i1 ||
2192                  getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2193        SDValue Op0 = N0;
2194        if (Op0.getOpcode() == ISD::TRUNCATE)
2195          Op0 = Op0.getOperand(0);
2196
2197        if ((Op0.getOpcode() == ISD::XOR) &&
2198            Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2199            Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2200          // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2201          Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2202          return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2203                              Cond);
2204        } else if (Op0.getOpcode() == ISD::AND &&
2205                isa<ConstantSDNode>(Op0.getOperand(1)) &&
2206                cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2207          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2208          if (Op0.getValueType().bitsGT(VT))
2209            Op0 = DAG.getNode(ISD::AND, dl, VT,
2210                          DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2211                          DAG.getConstant(1, VT));
2212          else if (Op0.getValueType().bitsLT(VT))
2213            Op0 = DAG.getNode(ISD::AND, dl, VT,
2214                        DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2215                        DAG.getConstant(1, VT));
2216
2217          return DAG.getSetCC(dl, VT, Op0,
2218                              DAG.getConstant(0, Op0.getValueType()),
2219                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2220        }
2221      }
2222    }
2223
2224    APInt MinVal, MaxVal;
2225    unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2226    if (ISD::isSignedIntSetCC(Cond)) {
2227      MinVal = APInt::getSignedMinValue(OperandBitSize);
2228      MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2229    } else {
2230      MinVal = APInt::getMinValue(OperandBitSize);
2231      MaxVal = APInt::getMaxValue(OperandBitSize);
2232    }
2233
2234    // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2235    if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2236      if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2237      // X >= C0 --> X > (C0-1)
2238      return DAG.getSetCC(dl, VT, N0,
2239                          DAG.getConstant(C1-1, N1.getValueType()),
2240                          (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2241    }
2242
2243    if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2244      if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2245      // X <= C0 --> X < (C0+1)
2246      return DAG.getSetCC(dl, VT, N0,
2247                          DAG.getConstant(C1+1, N1.getValueType()),
2248                          (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2249    }
2250
2251    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2252      return DAG.getConstant(0, VT);      // X < MIN --> false
2253    if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2254      return DAG.getConstant(1, VT);      // X >= MIN --> true
2255    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2256      return DAG.getConstant(0, VT);      // X > MAX --> false
2257    if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2258      return DAG.getConstant(1, VT);      // X <= MAX --> true
2259
2260    // Canonicalize setgt X, Min --> setne X, Min
2261    if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2262      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2263    // Canonicalize setlt X, Max --> setne X, Max
2264    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2265      return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2266
2267    // If we have setult X, 1, turn it into seteq X, 0
2268    if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2269      return DAG.getSetCC(dl, VT, N0,
2270                          DAG.getConstant(MinVal, N0.getValueType()),
2271                          ISD::SETEQ);
2272    // If we have setugt X, Max-1, turn it into seteq X, Max
2273    else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2274      return DAG.getSetCC(dl, VT, N0,
2275                          DAG.getConstant(MaxVal, N0.getValueType()),
2276                          ISD::SETEQ);
2277
2278    // If we have "setcc X, C0", check to see if we can shrink the immediate
2279    // by changing cc.
2280
2281    // SETUGT X, SINTMAX  -> SETLT X, 0
2282    if (Cond == ISD::SETUGT &&
2283        C1 == APInt::getSignedMaxValue(OperandBitSize))
2284      return DAG.getSetCC(dl, VT, N0,
2285                          DAG.getConstant(0, N1.getValueType()),
2286                          ISD::SETLT);
2287
2288    // SETULT X, SINTMIN  -> SETGT X, -1
2289    if (Cond == ISD::SETULT &&
2290        C1 == APInt::getSignedMinValue(OperandBitSize)) {
2291      SDValue ConstMinusOne =
2292          DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2293                          N1.getValueType());
2294      return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2295    }
2296
2297    // Fold bit comparisons when we can.
2298    if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2299        (VT == N0.getValueType() ||
2300         (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2301        N0.getOpcode() == ISD::AND)
2302      if (ConstantSDNode *AndRHS =
2303                  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2304        EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2305          getPointerTy() : getShiftAmountTy(N0.getValueType());
2306        if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2307          // Perform the xform if the AND RHS is a single bit.
2308          if (AndRHS->getAPIntValue().isPowerOf2()) {
2309            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2310                              DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2311                   DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2312          }
2313        } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2314          // (X & 8) == 8  -->  (X & 8) >> 3
2315          // Perform the xform if C1 is a single bit.
2316          if (C1.isPowerOf2()) {
2317            return DAG.getNode(ISD::TRUNCATE, dl, VT,
2318                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2319                                      DAG.getConstant(C1.logBase2(), ShiftTy)));
2320          }
2321        }
2322      }
2323
2324    if (C1.getMinSignedBits() <= 64 &&
2325        !isLegalICmpImmediate(C1.getSExtValue())) {
2326      // (X & -256) == 256 -> (X >> 8) == 1
2327      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2328          N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
2329        if (ConstantSDNode *AndRHS =
2330            dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2331          const APInt &AndRHSC = AndRHS->getAPIntValue();
2332          if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
2333            unsigned ShiftBits = AndRHSC.countTrailingZeros();
2334            EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2335              getPointerTy() : getShiftAmountTy(N0.getValueType());
2336            EVT CmpTy = N0.getValueType();
2337            SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
2338                                        DAG.getConstant(ShiftBits, ShiftTy));
2339            SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
2340            return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
2341          }
2342        }
2343      } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
2344                 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
2345        bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
2346        // X <  0x100000000 -> (X >> 32) <  1
2347        // X >= 0x100000000 -> (X >> 32) >= 1
2348        // X <= 0x0ffffffff -> (X >> 32) <  1
2349        // X >  0x0ffffffff -> (X >> 32) >= 1
2350        unsigned ShiftBits;
2351        APInt NewC = C1;
2352        ISD::CondCode NewCond = Cond;
2353        if (AdjOne) {
2354          ShiftBits = C1.countTrailingOnes();
2355          NewC = NewC + 1;
2356          NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2357        } else {
2358          ShiftBits = C1.countTrailingZeros();
2359        }
2360        NewC = NewC.lshr(ShiftBits);
2361        if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
2362          EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
2363            getPointerTy() : getShiftAmountTy(N0.getValueType());
2364          EVT CmpTy = N0.getValueType();
2365          SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
2366                                      DAG.getConstant(ShiftBits, ShiftTy));
2367          SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
2368          return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2369        }
2370      }
2371    }
2372  }
2373
2374  if (isa<ConstantFPSDNode>(N0.getNode())) {
2375    // Constant fold or commute setcc.
2376    SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2377    if (O.getNode()) return O;
2378  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2379    // If the RHS of an FP comparison is a constant, simplify it away in
2380    // some cases.
2381    if (CFP->getValueAPF().isNaN()) {
2382      // If an operand is known to be a nan, we can fold it.
2383      switch (ISD::getUnorderedFlavor(Cond)) {
2384      default: llvm_unreachable("Unknown flavor!");
2385      case 0:  // Known false.
2386        return DAG.getConstant(0, VT);
2387      case 1:  // Known true.
2388        return DAG.getConstant(1, VT);
2389      case 2:  // Undefined.
2390        return DAG.getUNDEF(VT);
2391      }
2392    }
2393
2394    // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
2395    // constant if knowing that the operand is non-nan is enough.  We prefer to
2396    // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2397    // materialize 0.0.
2398    if (Cond == ISD::SETO || Cond == ISD::SETUO)
2399      return DAG.getSetCC(dl, VT, N0, N0, Cond);
2400
2401    // If the condition is not legal, see if we can find an equivalent one
2402    // which is legal.
2403    if (!isCondCodeLegal(Cond, N0.getValueType())) {
2404      // If the comparison was an awkward floating-point == or != and one of
2405      // the comparison operands is infinity or negative infinity, convert the
2406      // condition to a less-awkward <= or >=.
2407      if (CFP->getValueAPF().isInfinity()) {
2408        if (CFP->getValueAPF().isNegative()) {
2409          if (Cond == ISD::SETOEQ &&
2410              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2411            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2412          if (Cond == ISD::SETUEQ &&
2413              isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2414            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2415          if (Cond == ISD::SETUNE &&
2416              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2417            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2418          if (Cond == ISD::SETONE &&
2419              isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2420            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2421        } else {
2422          if (Cond == ISD::SETOEQ &&
2423              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2424            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2425          if (Cond == ISD::SETUEQ &&
2426              isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2427            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2428          if (Cond == ISD::SETUNE &&
2429              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2430            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2431          if (Cond == ISD::SETONE &&
2432              isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2433            return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2434        }
2435      }
2436    }
2437  }
2438
2439  if (N0 == N1) {
2440    // The sext(setcc()) => setcc() optimization relies on the appropriate
2441    // constant being emitted.
2442    uint64_t EqVal = 0;
2443    switch (getBooleanContents(N0.getValueType().isVector())) {
2444    case UndefinedBooleanContent:
2445    case ZeroOrOneBooleanContent:
2446      EqVal = ISD::isTrueWhenEqual(Cond);
2447      break;
2448    case ZeroOrNegativeOneBooleanContent:
2449      EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
2450      break;
2451    }
2452
2453    // We can always fold X == X for integer setcc's.
2454    if (N0.getValueType().isInteger()) {
2455      return DAG.getConstant(EqVal, VT);
2456    }
2457    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2458    if (UOF == 2)   // FP operators that are undefined on NaNs.
2459      return DAG.getConstant(EqVal, VT);
2460    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2461      return DAG.getConstant(EqVal, VT);
2462    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2463    // if it is not already.
2464    ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2465    if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
2466          getCondCodeAction(NewCond, N0.getValueType()) == Legal))
2467      return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2468  }
2469
2470  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2471      N0.getValueType().isInteger()) {
2472    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2473        N0.getOpcode() == ISD::XOR) {
2474      // Simplify (X+Y) == (X+Z) -->  Y == Z
2475      if (N0.getOpcode() == N1.getOpcode()) {
2476        if (N0.getOperand(0) == N1.getOperand(0))
2477          return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2478        if (N0.getOperand(1) == N1.getOperand(1))
2479          return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2480        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2481          // If X op Y == Y op X, try other combinations.
2482          if (N0.getOperand(0) == N1.getOperand(1))
2483            return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2484                                Cond);
2485          if (N0.getOperand(1) == N1.getOperand(0))
2486            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2487                                Cond);
2488        }
2489      }
2490
2491      // If RHS is a legal immediate value for a compare instruction, we need
2492      // to be careful about increasing register pressure needlessly.
2493      bool LegalRHSImm = false;
2494
2495      if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2496        if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2497          // Turn (X+C1) == C2 --> X == C2-C1
2498          if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2499            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2500                                DAG.getConstant(RHSC->getAPIntValue()-
2501                                                LHSR->getAPIntValue(),
2502                                N0.getValueType()), Cond);
2503          }
2504
2505          // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2506          if (N0.getOpcode() == ISD::XOR)
2507            // If we know that all of the inverted bits are zero, don't bother
2508            // performing the inversion.
2509            if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2510              return
2511                DAG.getSetCC(dl, VT, N0.getOperand(0),
2512                             DAG.getConstant(LHSR->getAPIntValue() ^
2513                                               RHSC->getAPIntValue(),
2514                                             N0.getValueType()),
2515                             Cond);
2516        }
2517
2518        // Turn (C1-X) == C2 --> X == C1-C2
2519        if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2520          if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2521            return
2522              DAG.getSetCC(dl, VT, N0.getOperand(1),
2523                           DAG.getConstant(SUBC->getAPIntValue() -
2524                                             RHSC->getAPIntValue(),
2525                                           N0.getValueType()),
2526                           Cond);
2527          }
2528        }
2529
2530        // Could RHSC fold directly into a compare?
2531        if (RHSC->getValueType(0).getSizeInBits() <= 64)
2532          LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2533      }
2534
2535      // Simplify (X+Z) == X -->  Z == 0
2536      // Don't do this if X is an immediate that can fold into a cmp
2537      // instruction and X+Z has other uses. It could be an induction variable
2538      // chain, and the transform would increase register pressure.
2539      if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2540        if (N0.getOperand(0) == N1)
2541          return DAG.getSetCC(dl, VT, N0.getOperand(1),
2542                              DAG.getConstant(0, N0.getValueType()), Cond);
2543        if (N0.getOperand(1) == N1) {
2544          if (DAG.isCommutativeBinOp(N0.getOpcode()))
2545            return DAG.getSetCC(dl, VT, N0.getOperand(0),
2546                                DAG.getConstant(0, N0.getValueType()), Cond);
2547          else if (N0.getNode()->hasOneUse()) {
2548            assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2549            // (Z-X) == X  --> Z == X<<1
2550            SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2551                       DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2552            if (!DCI.isCalledByLegalizer())
2553              DCI.AddToWorklist(SH.getNode());
2554            return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2555          }
2556        }
2557      }
2558    }
2559
2560    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2561        N1.getOpcode() == ISD::XOR) {
2562      // Simplify  X == (X+Z) -->  Z == 0
2563      if (N1.getOperand(0) == N0) {
2564        return DAG.getSetCC(dl, VT, N1.getOperand(1),
2565                        DAG.getConstant(0, N1.getValueType()), Cond);
2566      } else if (N1.getOperand(1) == N0) {
2567        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2568          return DAG.getSetCC(dl, VT, N1.getOperand(0),
2569                          DAG.getConstant(0, N1.getValueType()), Cond);
2570        } else if (N1.getNode()->hasOneUse()) {
2571          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2572          // X == (Z-X)  --> X<<1 == Z
2573          SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2574                       DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2575          if (!DCI.isCalledByLegalizer())
2576            DCI.AddToWorklist(SH.getNode());
2577          return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2578        }
2579      }
2580    }
2581
2582    // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2583    // Note that where y is variable and is known to have at most
2584    // one bit set (for example, if it is z&1) we cannot do this;
2585    // the expressions are not equivalent when y==0.
2586    if (N0.getOpcode() == ISD::AND)
2587      if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2588        if (ValueHasExactlyOneBitSet(N1, DAG)) {
2589          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2590          SDValue Zero = DAG.getConstant(0, N1.getValueType());
2591          return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2592        }
2593      }
2594    if (N1.getOpcode() == ISD::AND)
2595      if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2596        if (ValueHasExactlyOneBitSet(N0, DAG)) {
2597          Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2598          SDValue Zero = DAG.getConstant(0, N0.getValueType());
2599          return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2600        }
2601      }
2602  }
2603
2604  // Fold away ALL boolean setcc's.
2605  SDValue Temp;
2606  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2607    switch (Cond) {
2608    default: llvm_unreachable("Unknown integer setcc!");
2609    case ISD::SETEQ:  // X == Y  -> ~(X^Y)
2610      Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2611      N0 = DAG.getNOT(dl, Temp, MVT::i1);
2612      if (!DCI.isCalledByLegalizer())
2613        DCI.AddToWorklist(Temp.getNode());
2614      break;
2615    case ISD::SETNE:  // X != Y   -->  (X^Y)
2616      N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2617      break;
2618    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
2619    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
2620      Temp = DAG.getNOT(dl, N0, MVT::i1);
2621      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2622      if (!DCI.isCalledByLegalizer())
2623        DCI.AddToWorklist(Temp.getNode());
2624      break;
2625    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
2626    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
2627      Temp = DAG.getNOT(dl, N1, MVT::i1);
2628      N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2629      if (!DCI.isCalledByLegalizer())
2630        DCI.AddToWorklist(Temp.getNode());
2631      break;
2632    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
2633    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
2634      Temp = DAG.getNOT(dl, N0, MVT::i1);
2635      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2636      if (!DCI.isCalledByLegalizer())
2637        DCI.AddToWorklist(Temp.getNode());
2638      break;
2639    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
2640    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
2641      Temp = DAG.getNOT(dl, N1, MVT::i1);
2642      N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2643      break;
2644    }
2645    if (VT != MVT::i1) {
2646      if (!DCI.isCalledByLegalizer())
2647        DCI.AddToWorklist(N0.getNode());
2648      // FIXME: If running after legalize, we probably can't do this.
2649      N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2650    }
2651    return N0;
2652  }
2653
2654  // Could not fold it.
2655  return SDValue();
2656}
2657
2658/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2659/// node is a GlobalAddress + offset.
2660bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2661                                    int64_t &Offset) const {
2662  if (isa<GlobalAddressSDNode>(N)) {
2663    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2664    GA = GASD->getGlobal();
2665    Offset += GASD->getOffset();
2666    return true;
2667  }
2668
2669  if (N->getOpcode() == ISD::ADD) {
2670    SDValue N1 = N->getOperand(0);
2671    SDValue N2 = N->getOperand(1);
2672    if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2673      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2674      if (V) {
2675        Offset += V->getSExtValue();
2676        return true;
2677      }
2678    } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2679      ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2680      if (V) {
2681        Offset += V->getSExtValue();
2682        return true;
2683      }
2684    }
2685  }
2686
2687  return false;
2688}
2689
2690
2691SDValue TargetLowering::
2692PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2693  // Default implementation: no optimization.
2694  return SDValue();
2695}
2696
2697//===----------------------------------------------------------------------===//
2698//  Inline Assembler Implementation Methods
2699//===----------------------------------------------------------------------===//
2700
2701
2702TargetLowering::ConstraintType
2703TargetLowering::getConstraintType(const std::string &Constraint) const {
2704  if (Constraint.size() == 1) {
2705    switch (Constraint[0]) {
2706    default: break;
2707    case 'r': return C_RegisterClass;
2708    case 'm':    // memory
2709    case 'o':    // offsetable
2710    case 'V':    // not offsetable
2711      return C_Memory;
2712    case 'i':    // Simple Integer or Relocatable Constant
2713    case 'n':    // Simple Integer
2714    case 'E':    // Floating Point Constant
2715    case 'F':    // Floating Point Constant
2716    case 's':    // Relocatable Constant
2717    case 'p':    // Address.
2718    case 'X':    // Allow ANY value.
2719    case 'I':    // Target registers.
2720    case 'J':
2721    case 'K':
2722    case 'L':
2723    case 'M':
2724    case 'N':
2725    case 'O':
2726    case 'P':
2727    case '<':
2728    case '>':
2729      return C_Other;
2730    }
2731  }
2732
2733  if (Constraint.size() > 1 && Constraint[0] == '{' &&
2734      Constraint[Constraint.size()-1] == '}')
2735    return C_Register;
2736  return C_Unknown;
2737}
2738
2739/// LowerXConstraint - try to replace an X constraint, which matches anything,
2740/// with another that has more specific requirements based on the type of the
2741/// corresponding operand.
2742const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2743  if (ConstraintVT.isInteger())
2744    return "r";
2745  if (ConstraintVT.isFloatingPoint())
2746    return "f";      // works for many targets
2747  return 0;
2748}
2749
2750/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2751/// vector.  If it is invalid, don't add anything to Ops.
2752void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2753                                                  std::string &Constraint,
2754                                                  std::vector<SDValue> &Ops,
2755                                                  SelectionDAG &DAG) const {
2756
2757  if (Constraint.length() > 1) return;
2758
2759  char ConstraintLetter = Constraint[0];
2760  switch (ConstraintLetter) {
2761  default: break;
2762  case 'X':     // Allows any operand; labels (basic block) use this.
2763    if (Op.getOpcode() == ISD::BasicBlock) {
2764      Ops.push_back(Op);
2765      return;
2766    }
2767    // fall through
2768  case 'i':    // Simple Integer or Relocatable Constant
2769  case 'n':    // Simple Integer
2770  case 's': {  // Relocatable Constant
2771    // These operands are interested in values of the form (GV+C), where C may
2772    // be folded in as an offset of GV, or it may be explicitly added.  Also, it
2773    // is possible and fine if either GV or C are missing.
2774    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2775    GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2776
2777    // If we have "(add GV, C)", pull out GV/C
2778    if (Op.getOpcode() == ISD::ADD) {
2779      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2780      GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2781      if (C == 0 || GA == 0) {
2782        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2783        GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2784      }
2785      if (C == 0 || GA == 0)
2786        C = 0, GA = 0;
2787    }
2788
2789    // If we find a valid operand, map to the TargetXXX version so that the
2790    // value itself doesn't get selected.
2791    if (GA) {   // Either &GV   or   &GV+C
2792      if (ConstraintLetter != 'n') {
2793        int64_t Offs = GA->getOffset();
2794        if (C) Offs += C->getZExtValue();
2795        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2796                                                 C ? C->getDebugLoc() : DebugLoc(),
2797                                                 Op.getValueType(), Offs));
2798        return;
2799      }
2800    }
2801    if (C) {   // just C, no GV.
2802      // Simple constants are not allowed for 's'.
2803      if (ConstraintLetter != 's') {
2804        // gcc prints these as sign extended.  Sign extend value to 64 bits
2805        // now; without this it would get ZExt'd later in
2806        // ScheduleDAGSDNodes::EmitNode, which is very generic.
2807        Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2808                                            MVT::i64));
2809        return;
2810      }
2811    }
2812    break;
2813  }
2814  }
2815}
2816
2817std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2818getRegForInlineAsmConstraint(const std::string &Constraint,
2819                             EVT VT) const {
2820  if (Constraint[0] != '{')
2821    return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2822  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2823
2824  // Remove the braces from around the name.
2825  StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2826
2827  // Figure out which register class contains this reg.
2828  const TargetRegisterInfo *RI = TM.getRegisterInfo();
2829  for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2830       E = RI->regclass_end(); RCI != E; ++RCI) {
2831    const TargetRegisterClass *RC = *RCI;
2832
2833    // If none of the value types for this register class are valid, we
2834    // can't use it.  For example, 64-bit reg classes on 32-bit targets.
2835    if (!isLegalRC(RC))
2836      continue;
2837
2838    for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2839         I != E; ++I) {
2840      if (RegName.equals_lower(RI->getName(*I)))
2841        return std::make_pair(*I, RC);
2842    }
2843  }
2844
2845  return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2846}
2847
2848//===----------------------------------------------------------------------===//
2849// Constraint Selection.
2850
2851/// isMatchingInputConstraint - Return true of this is an input operand that is
2852/// a matching constraint like "4".
2853bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2854  assert(!ConstraintCode.empty() && "No known constraint!");
2855  return isdigit(ConstraintCode[0]);
2856}
2857
2858/// getMatchedOperand - If this is an input matching constraint, this method
2859/// returns the output operand it matches.
2860unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2861  assert(!ConstraintCode.empty() && "No known constraint!");
2862  return atoi(ConstraintCode.c_str());
2863}
2864
2865
2866/// ParseConstraints - Split up the constraint string from the inline
2867/// assembly value into the specific constraints and their prefixes,
2868/// and also tie in the associated operand values.
2869/// If this returns an empty vector, and if the constraint string itself
2870/// isn't empty, there was an error parsing.
2871TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2872    ImmutableCallSite CS) const {
2873  /// ConstraintOperands - Information about all of the constraints.
2874  AsmOperandInfoVector ConstraintOperands;
2875  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2876  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2877
2878  // Do a prepass over the constraints, canonicalizing them, and building up the
2879  // ConstraintOperands list.
2880  InlineAsm::ConstraintInfoVector
2881    ConstraintInfos = IA->ParseConstraints();
2882
2883  unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
2884  unsigned ResNo = 0;   // ResNo - The result number of the next output.
2885
2886  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2887    ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2888    AsmOperandInfo &OpInfo = ConstraintOperands.back();
2889
2890    // Update multiple alternative constraint count.
2891    if (OpInfo.multipleAlternatives.size() > maCount)
2892      maCount = OpInfo.multipleAlternatives.size();
2893
2894    OpInfo.ConstraintVT = MVT::Other;
2895
2896    // Compute the value type for each operand.
2897    switch (OpInfo.Type) {
2898    case InlineAsm::isOutput:
2899      // Indirect outputs just consume an argument.
2900      if (OpInfo.isIndirect) {
2901        OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2902        break;
2903      }
2904
2905      // The return value of the call is this value.  As such, there is no
2906      // corresponding argument.
2907      assert(!CS.getType()->isVoidTy() &&
2908             "Bad inline asm!");
2909      if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2910        OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2911      } else {
2912        assert(ResNo == 0 && "Asm only has one result!");
2913        OpInfo.ConstraintVT = getValueType(CS.getType());
2914      }
2915      ++ResNo;
2916      break;
2917    case InlineAsm::isInput:
2918      OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2919      break;
2920    case InlineAsm::isClobber:
2921      // Nothing to do.
2922      break;
2923    }
2924
2925    if (OpInfo.CallOperandVal) {
2926      llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2927      if (OpInfo.isIndirect) {
2928        llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2929        if (!PtrTy)
2930          report_fatal_error("Indirect operand for inline asm not a pointer!");
2931        OpTy = PtrTy->getElementType();
2932      }
2933
2934      // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2935      if (StructType *STy = dyn_cast<StructType>(OpTy))
2936        if (STy->getNumElements() == 1)
2937          OpTy = STy->getElementType(0);
2938
2939      // If OpTy is not a single value, it may be a struct/union that we
2940      // can tile with integers.
2941      if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2942        unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2943        switch (BitSize) {
2944        default: break;
2945        case 1:
2946        case 8:
2947        case 16:
2948        case 32:
2949        case 64:
2950        case 128:
2951          OpInfo.ConstraintVT =
2952              EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2953          break;
2954        }
2955      } else if (dyn_cast<PointerType>(OpTy)) {
2956        OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2957      } else {
2958        OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2959      }
2960    }
2961  }
2962
2963  // If we have multiple alternative constraints, select the best alternative.
2964  if (ConstraintInfos.size()) {
2965    if (maCount) {
2966      unsigned bestMAIndex = 0;
2967      int bestWeight = -1;
2968      // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
2969      int weight = -1;
2970      unsigned maIndex;
2971      // Compute the sums of the weights for each alternative, keeping track
2972      // of the best (highest weight) one so far.
2973      for (maIndex = 0; maIndex < maCount; ++maIndex) {
2974        int weightSum = 0;
2975        for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2976            cIndex != eIndex; ++cIndex) {
2977          AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2978          if (OpInfo.Type == InlineAsm::isClobber)
2979            continue;
2980
2981          // If this is an output operand with a matching input operand,
2982          // look up the matching input. If their types mismatch, e.g. one
2983          // is an integer, the other is floating point, or their sizes are
2984          // different, flag it as an maCantMatch.
2985          if (OpInfo.hasMatchingInput()) {
2986            AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2987            if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2988              if ((OpInfo.ConstraintVT.isInteger() !=
2989                   Input.ConstraintVT.isInteger()) ||
2990                  (OpInfo.ConstraintVT.getSizeInBits() !=
2991                   Input.ConstraintVT.getSizeInBits())) {
2992                weightSum = -1;  // Can't match.
2993                break;
2994              }
2995            }
2996          }
2997          weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2998          if (weight == -1) {
2999            weightSum = -1;
3000            break;
3001          }
3002          weightSum += weight;
3003        }
3004        // Update best.
3005        if (weightSum > bestWeight) {
3006          bestWeight = weightSum;
3007          bestMAIndex = maIndex;
3008        }
3009      }
3010
3011      // Now select chosen alternative in each constraint.
3012      for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3013          cIndex != eIndex; ++cIndex) {
3014        AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
3015        if (cInfo.Type == InlineAsm::isClobber)
3016          continue;
3017        cInfo.selectAlternative(bestMAIndex);
3018      }
3019    }
3020  }
3021
3022  // Check and hook up tied operands, choose constraint code to use.
3023  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3024      cIndex != eIndex; ++cIndex) {
3025    AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3026
3027    // If this is an output operand with a matching input operand, look up the
3028    // matching input. If their types mismatch, e.g. one is an integer, the
3029    // other is floating point, or their sizes are different, flag it as an
3030    // error.
3031    if (OpInfo.hasMatchingInput()) {
3032      AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3033
3034      if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3035        std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3036          getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3037                                       OpInfo.ConstraintVT);
3038        std::pair<unsigned, const TargetRegisterClass*> InputRC =
3039          getRegForInlineAsmConstraint(Input.ConstraintCode,
3040                                       Input.ConstraintVT);
3041        if ((OpInfo.ConstraintVT.isInteger() !=
3042             Input.ConstraintVT.isInteger()) ||
3043            (MatchRC.second != InputRC.second)) {
3044          report_fatal_error("Unsupported asm: input constraint"
3045                             " with a matching output constraint of"
3046                             " incompatible type!");
3047        }
3048      }
3049
3050    }
3051  }
3052
3053  return ConstraintOperands;
3054}
3055
3056
3057/// getConstraintGenerality - Return an integer indicating how general CT
3058/// is.
3059static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3060  switch (CT) {
3061  case TargetLowering::C_Other:
3062  case TargetLowering::C_Unknown:
3063    return 0;
3064  case TargetLowering::C_Register:
3065    return 1;
3066  case TargetLowering::C_RegisterClass:
3067    return 2;
3068  case TargetLowering::C_Memory:
3069    return 3;
3070  }
3071  llvm_unreachable("Invalid constraint type");
3072}
3073
3074/// Examine constraint type and operand type and determine a weight value.
3075/// This object must already have been set up with the operand type
3076/// and the current alternative constraint selected.
3077TargetLowering::ConstraintWeight
3078  TargetLowering::getMultipleConstraintMatchWeight(
3079    AsmOperandInfo &info, int maIndex) const {
3080  InlineAsm::ConstraintCodeVector *rCodes;
3081  if (maIndex >= (int)info.multipleAlternatives.size())
3082    rCodes = &info.Codes;
3083  else
3084    rCodes = &info.multipleAlternatives[maIndex].Codes;
3085  ConstraintWeight BestWeight = CW_Invalid;
3086
3087  // Loop over the options, keeping track of the most general one.
3088  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3089    ConstraintWeight weight =
3090      getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3091    if (weight > BestWeight)
3092      BestWeight = weight;
3093  }
3094
3095  return BestWeight;
3096}
3097
3098/// Examine constraint type and operand type and determine a weight value.
3099/// This object must already have been set up with the operand type
3100/// and the current alternative constraint selected.
3101TargetLowering::ConstraintWeight
3102  TargetLowering::getSingleConstraintMatchWeight(
3103    AsmOperandInfo &info, const char *constraint) const {
3104  ConstraintWeight weight = CW_Invalid;
3105  Value *CallOperandVal = info.CallOperandVal;
3106    // If we don't have a value, we can't do a match,
3107    // but allow it at the lowest weight.
3108  if (CallOperandVal == NULL)
3109    return CW_Default;
3110  // Look at the constraint type.
3111  switch (*constraint) {
3112    case 'i': // immediate integer.
3113    case 'n': // immediate integer with a known value.
3114      if (isa<ConstantInt>(CallOperandVal))
3115        weight = CW_Constant;
3116      break;
3117    case 's': // non-explicit intregal immediate.
3118      if (isa<GlobalValue>(CallOperandVal))
3119        weight = CW_Constant;
3120      break;
3121    case 'E': // immediate float if host format.
3122    case 'F': // immediate float.
3123      if (isa<ConstantFP>(CallOperandVal))
3124        weight = CW_Constant;
3125      break;
3126    case '<': // memory operand with autodecrement.
3127    case '>': // memory operand with autoincrement.
3128    case 'm': // memory operand.
3129    case 'o': // offsettable memory operand
3130    case 'V': // non-offsettable memory operand
3131      weight = CW_Memory;
3132      break;
3133    case 'r': // general register.
3134    case 'g': // general register, memory operand or immediate integer.
3135              // note: Clang converts "g" to "imr".
3136      if (CallOperandVal->getType()->isIntegerTy())
3137        weight = CW_Register;
3138      break;
3139    case 'X': // any operand.
3140    default:
3141      weight = CW_Default;
3142      break;
3143  }
3144  return weight;
3145}
3146
3147/// ChooseConstraint - If there are multiple different constraints that we
3148/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3149/// This is somewhat tricky: constraints fall into four classes:
3150///    Other         -> immediates and magic values
3151///    Register      -> one specific register
3152///    RegisterClass -> a group of regs
3153///    Memory        -> memory
3154/// Ideally, we would pick the most specific constraint possible: if we have
3155/// something that fits into a register, we would pick it.  The problem here
3156/// is that if we have something that could either be in a register or in
3157/// memory that use of the register could cause selection of *other*
3158/// operands to fail: they might only succeed if we pick memory.  Because of
3159/// this the heuristic we use is:
3160///
3161///  1) If there is an 'other' constraint, and if the operand is valid for
3162///     that constraint, use it.  This makes us take advantage of 'i'
3163///     constraints when available.
3164///  2) Otherwise, pick the most general constraint present.  This prefers
3165///     'm' over 'r', for example.
3166///
3167static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3168                             const TargetLowering &TLI,
3169                             SDValue Op, SelectionDAG *DAG) {
3170  assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3171  unsigned BestIdx = 0;
3172  TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3173  int BestGenerality = -1;
3174
3175  // Loop over the options, keeping track of the most general one.
3176  for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3177    TargetLowering::ConstraintType CType =
3178      TLI.getConstraintType(OpInfo.Codes[i]);
3179
3180    // If this is an 'other' constraint, see if the operand is valid for it.
3181    // For example, on X86 we might have an 'rI' constraint.  If the operand
3182    // is an integer in the range [0..31] we want to use I (saving a load
3183    // of a register), otherwise we must use 'r'.
3184    if (CType == TargetLowering::C_Other && Op.getNode()) {
3185      assert(OpInfo.Codes[i].size() == 1 &&
3186             "Unhandled multi-letter 'other' constraint");
3187      std::vector<SDValue> ResultOps;
3188      TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3189                                       ResultOps, *DAG);
3190      if (!ResultOps.empty()) {
3191        BestType = CType;
3192        BestIdx = i;
3193        break;
3194      }
3195    }
3196
3197    // Things with matching constraints can only be registers, per gcc
3198    // documentation.  This mainly affects "g" constraints.
3199    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3200      continue;
3201
3202    // This constraint letter is more general than the previous one, use it.
3203    int Generality = getConstraintGenerality(CType);
3204    if (Generality > BestGenerality) {
3205      BestType = CType;
3206      BestIdx = i;
3207      BestGenerality = Generality;
3208    }
3209  }
3210
3211  OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3212  OpInfo.ConstraintType = BestType;
3213}
3214
3215/// ComputeConstraintToUse - Determines the constraint code and constraint
3216/// type to use for the specific AsmOperandInfo, setting
3217/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3218void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3219                                            SDValue Op,
3220                                            SelectionDAG *DAG) const {
3221  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3222
3223  // Single-letter constraints ('r') are very common.
3224  if (OpInfo.Codes.size() == 1) {
3225    OpInfo.ConstraintCode = OpInfo.Codes[0];
3226    OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3227  } else {
3228    ChooseConstraint(OpInfo, *this, Op, DAG);
3229  }
3230
3231  // 'X' matches anything.
3232  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3233    // Labels and constants are handled elsewhere ('X' is the only thing
3234    // that matches labels).  For Functions, the type here is the type of
3235    // the result, which is not what we want to look at; leave them alone.
3236    Value *v = OpInfo.CallOperandVal;
3237    if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3238      OpInfo.CallOperandVal = v;
3239      return;
3240    }
3241
3242    // Otherwise, try to resolve it to something we know about by looking at
3243    // the actual operand type.
3244    if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3245      OpInfo.ConstraintCode = Repl;
3246      OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3247    }
3248  }
3249}
3250
3251//===----------------------------------------------------------------------===//
3252//  Loop Strength Reduction hooks
3253//===----------------------------------------------------------------------===//
3254
3255/// isLegalAddressingMode - Return true if the addressing mode represented
3256/// by AM is legal for this target, for a load/store of the specified type.
3257bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3258                                           Type *Ty) const {
3259  // The default implementation of this implements a conservative RISCy, r+r and
3260  // r+i addr mode.
3261
3262  // Allows a sign-extended 16-bit immediate field.
3263  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3264    return false;
3265
3266  // No global is ever allowed as a base.
3267  if (AM.BaseGV)
3268    return false;
3269
3270  // Only support r+r,
3271  switch (AM.Scale) {
3272  case 0:  // "r+i" or just "i", depending on HasBaseReg.
3273    break;
3274  case 1:
3275    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
3276      return false;
3277    // Otherwise we have r+r or r+i.
3278    break;
3279  case 2:
3280    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
3281      return false;
3282    // Allow 2*r as r+r.
3283    break;
3284  }
3285
3286  return true;
3287}
3288
3289/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3290/// with the multiplicative inverse of the constant.
3291SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3292                                       SelectionDAG &DAG) const {
3293  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3294  APInt d = C->getAPIntValue();
3295  assert(d != 0 && "Division by zero!");
3296
3297  // Shift the value upfront if it is even, so the LSB is one.
3298  unsigned ShAmt = d.countTrailingZeros();
3299  if (ShAmt) {
3300    // TODO: For UDIV use SRL instead of SRA.
3301    SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3302    Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3303    d = d.ashr(ShAmt);
3304  }
3305
3306  // Calculate the multiplicative inverse, using Newton's method.
3307  APInt t, xn = d;
3308  while ((t = d*xn) != 1)
3309    xn *= APInt(d.getBitWidth(), 2) - t;
3310
3311  Op2 = DAG.getConstant(xn, Op1.getValueType());
3312  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3313}
3314
3315/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3316/// return a DAG expression to select that will generate the same value by
3317/// multiplying by a magic number.  See:
3318/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3319SDValue TargetLowering::
3320BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3321          std::vector<SDNode*>* Created) const {
3322  EVT VT = N->getValueType(0);
3323  DebugLoc dl= N->getDebugLoc();
3324
3325  // Check to see if we can do this.
3326  // FIXME: We should be more aggressive here.
3327  if (!isTypeLegal(VT))
3328    return SDValue();
3329
3330  APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3331  APInt::ms magics = d.magic();
3332
3333  // Multiply the numerator (operand 0) by the magic value
3334  // FIXME: We should support doing a MUL in a wider type
3335  SDValue Q;
3336  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3337                            isOperationLegalOrCustom(ISD::MULHS, VT))
3338    Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3339                    DAG.getConstant(magics.m, VT));
3340  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3341                                 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3342    Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3343                              N->getOperand(0),
3344                              DAG.getConstant(magics.m, VT)).getNode(), 1);
3345  else
3346    return SDValue();       // No mulhs or equvialent
3347  // If d > 0 and m < 0, add the numerator
3348  if (d.isStrictlyPositive() && magics.m.isNegative()) {
3349    Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3350    if (Created)
3351      Created->push_back(Q.getNode());
3352  }
3353  // If d < 0 and m > 0, subtract the numerator.
3354  if (d.isNegative() && magics.m.isStrictlyPositive()) {
3355    Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3356    if (Created)
3357      Created->push_back(Q.getNode());
3358  }
3359  // Shift right algebraic if shift value is nonzero
3360  if (magics.s > 0) {
3361    Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3362                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3363    if (Created)
3364      Created->push_back(Q.getNode());
3365  }
3366  // Extract the sign bit and add it to the quotient
3367  SDValue T =
3368    DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3369                                           getShiftAmountTy(Q.getValueType())));
3370  if (Created)
3371    Created->push_back(T.getNode());
3372  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3373}
3374
3375/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3376/// return a DAG expression to select that will generate the same value by
3377/// multiplying by a magic number.  See:
3378/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3379SDValue TargetLowering::
3380BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3381          std::vector<SDNode*>* Created) const {
3382  EVT VT = N->getValueType(0);
3383  DebugLoc dl = N->getDebugLoc();
3384
3385  // Check to see if we can do this.
3386  // FIXME: We should be more aggressive here.
3387  if (!isTypeLegal(VT))
3388    return SDValue();
3389
3390  // FIXME: We should use a narrower constant when the upper
3391  // bits are known to be zero.
3392  const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3393  APInt::mu magics = N1C.magicu();
3394
3395  SDValue Q = N->getOperand(0);
3396
3397  // If the divisor is even, we can avoid using the expensive fixup by shifting
3398  // the divided value upfront.
3399  if (magics.a != 0 && !N1C[0]) {
3400    unsigned Shift = N1C.countTrailingZeros();
3401    Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3402                    DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3403    if (Created)
3404      Created->push_back(Q.getNode());
3405
3406    // Get magic number for the shifted divisor.
3407    magics = N1C.lshr(Shift).magicu(Shift);
3408    assert(magics.a == 0 && "Should use cheap fixup now");
3409  }
3410
3411  // Multiply the numerator (operand 0) by the magic value
3412  // FIXME: We should support doing a MUL in a wider type
3413  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3414                            isOperationLegalOrCustom(ISD::MULHU, VT))
3415    Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3416  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3417                                 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3418    Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3419                            DAG.getConstant(magics.m, VT)).getNode(), 1);
3420  else
3421    return SDValue();       // No mulhu or equvialent
3422  if (Created)
3423    Created->push_back(Q.getNode());
3424
3425  if (magics.a == 0) {
3426    assert(magics.s < N1C.getBitWidth() &&
3427           "We shouldn't generate an undefined shift!");
3428    return DAG.getNode(ISD::SRL, dl, VT, Q,
3429                 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3430  } else {
3431    SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3432    if (Created)
3433      Created->push_back(NPQ.getNode());
3434    NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3435                      DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3436    if (Created)
3437      Created->push_back(NPQ.getNode());
3438    NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3439    if (Created)
3440      Created->push_back(NPQ.getNode());
3441    return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3442             DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
3443  }
3444}
3445