TargetLowering.cpp revision ec880283b3682982c750c9b78f6a9b4777e21883
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/MathExtras.h" 32#include <cctype> 33using namespace llvm; 34 35/// We are in the process of implementing a new TypeLegalization action 36/// - the promotion of vector elements. This feature is disabled by default 37/// and only enabled using this flag. 38static cl::opt<bool> 39AllowPromoteIntElem("promote-elements", cl::Hidden, 40 cl::desc("Allow promotion of integer vector element types")); 41 42namespace llvm { 43TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 44 bool isLocal = GV->hasLocalLinkage(); 45 bool isDeclaration = GV->isDeclaration(); 46 // FIXME: what should we do for protected and internal visibility? 47 // For variables, is internal different from hidden? 48 bool isHidden = GV->hasHiddenVisibility(); 49 50 if (reloc == Reloc::PIC_) { 51 if (isLocal || isHidden) 52 return TLSModel::LocalDynamic; 53 else 54 return TLSModel::GeneralDynamic; 55 } else { 56 if (!isDeclaration || isHidden) 57 return TLSModel::LocalExec; 58 else 59 return TLSModel::InitialExec; 60 } 61} 62} 63 64/// InitLibcallNames - Set default libcall names. 65/// 66static void InitLibcallNames(const char **Names) { 67 Names[RTLIB::SHL_I16] = "__ashlhi3"; 68 Names[RTLIB::SHL_I32] = "__ashlsi3"; 69 Names[RTLIB::SHL_I64] = "__ashldi3"; 70 Names[RTLIB::SHL_I128] = "__ashlti3"; 71 Names[RTLIB::SRL_I16] = "__lshrhi3"; 72 Names[RTLIB::SRL_I32] = "__lshrsi3"; 73 Names[RTLIB::SRL_I64] = "__lshrdi3"; 74 Names[RTLIB::SRL_I128] = "__lshrti3"; 75 Names[RTLIB::SRA_I16] = "__ashrhi3"; 76 Names[RTLIB::SRA_I32] = "__ashrsi3"; 77 Names[RTLIB::SRA_I64] = "__ashrdi3"; 78 Names[RTLIB::SRA_I128] = "__ashrti3"; 79 Names[RTLIB::MUL_I8] = "__mulqi3"; 80 Names[RTLIB::MUL_I16] = "__mulhi3"; 81 Names[RTLIB::MUL_I32] = "__mulsi3"; 82 Names[RTLIB::MUL_I64] = "__muldi3"; 83 Names[RTLIB::MUL_I128] = "__multi3"; 84 Names[RTLIB::SDIV_I8] = "__divqi3"; 85 Names[RTLIB::SDIV_I16] = "__divhi3"; 86 Names[RTLIB::SDIV_I32] = "__divsi3"; 87 Names[RTLIB::SDIV_I64] = "__divdi3"; 88 Names[RTLIB::SDIV_I128] = "__divti3"; 89 Names[RTLIB::UDIV_I8] = "__udivqi3"; 90 Names[RTLIB::UDIV_I16] = "__udivhi3"; 91 Names[RTLIB::UDIV_I32] = "__udivsi3"; 92 Names[RTLIB::UDIV_I64] = "__udivdi3"; 93 Names[RTLIB::UDIV_I128] = "__udivti3"; 94 Names[RTLIB::SREM_I8] = "__modqi3"; 95 Names[RTLIB::SREM_I16] = "__modhi3"; 96 Names[RTLIB::SREM_I32] = "__modsi3"; 97 Names[RTLIB::SREM_I64] = "__moddi3"; 98 Names[RTLIB::SREM_I128] = "__modti3"; 99 Names[RTLIB::UREM_I8] = "__umodqi3"; 100 Names[RTLIB::UREM_I16] = "__umodhi3"; 101 Names[RTLIB::UREM_I32] = "__umodsi3"; 102 Names[RTLIB::UREM_I64] = "__umoddi3"; 103 Names[RTLIB::UREM_I128] = "__umodti3"; 104 105 // These are generally not available. 106 Names[RTLIB::SDIVREM_I8] = 0; 107 Names[RTLIB::SDIVREM_I16] = 0; 108 Names[RTLIB::SDIVREM_I32] = 0; 109 Names[RTLIB::SDIVREM_I64] = 0; 110 Names[RTLIB::SDIVREM_I128] = 0; 111 Names[RTLIB::UDIVREM_I8] = 0; 112 Names[RTLIB::UDIVREM_I16] = 0; 113 Names[RTLIB::UDIVREM_I32] = 0; 114 Names[RTLIB::UDIVREM_I64] = 0; 115 Names[RTLIB::UDIVREM_I128] = 0; 116 117 Names[RTLIB::NEG_I32] = "__negsi2"; 118 Names[RTLIB::NEG_I64] = "__negdi2"; 119 Names[RTLIB::ADD_F32] = "__addsf3"; 120 Names[RTLIB::ADD_F64] = "__adddf3"; 121 Names[RTLIB::ADD_F80] = "__addxf3"; 122 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 123 Names[RTLIB::SUB_F32] = "__subsf3"; 124 Names[RTLIB::SUB_F64] = "__subdf3"; 125 Names[RTLIB::SUB_F80] = "__subxf3"; 126 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 127 Names[RTLIB::MUL_F32] = "__mulsf3"; 128 Names[RTLIB::MUL_F64] = "__muldf3"; 129 Names[RTLIB::MUL_F80] = "__mulxf3"; 130 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 131 Names[RTLIB::DIV_F32] = "__divsf3"; 132 Names[RTLIB::DIV_F64] = "__divdf3"; 133 Names[RTLIB::DIV_F80] = "__divxf3"; 134 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 135 Names[RTLIB::REM_F32] = "fmodf"; 136 Names[RTLIB::REM_F64] = "fmod"; 137 Names[RTLIB::REM_F80] = "fmodl"; 138 Names[RTLIB::REM_PPCF128] = "fmodl"; 139 Names[RTLIB::POWI_F32] = "__powisf2"; 140 Names[RTLIB::POWI_F64] = "__powidf2"; 141 Names[RTLIB::POWI_F80] = "__powixf2"; 142 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 143 Names[RTLIB::SQRT_F32] = "sqrtf"; 144 Names[RTLIB::SQRT_F64] = "sqrt"; 145 Names[RTLIB::SQRT_F80] = "sqrtl"; 146 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 147 Names[RTLIB::LOG_F32] = "logf"; 148 Names[RTLIB::LOG_F64] = "log"; 149 Names[RTLIB::LOG_F80] = "logl"; 150 Names[RTLIB::LOG_PPCF128] = "logl"; 151 Names[RTLIB::LOG2_F32] = "log2f"; 152 Names[RTLIB::LOG2_F64] = "log2"; 153 Names[RTLIB::LOG2_F80] = "log2l"; 154 Names[RTLIB::LOG2_PPCF128] = "log2l"; 155 Names[RTLIB::LOG10_F32] = "log10f"; 156 Names[RTLIB::LOG10_F64] = "log10"; 157 Names[RTLIB::LOG10_F80] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_PPCF128] = "expl"; 163 Names[RTLIB::EXP2_F32] = "exp2f"; 164 Names[RTLIB::EXP2_F64] = "exp2"; 165 Names[RTLIB::EXP2_F80] = "exp2l"; 166 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 167 Names[RTLIB::SIN_F32] = "sinf"; 168 Names[RTLIB::SIN_F64] = "sin"; 169 Names[RTLIB::SIN_F80] = "sinl"; 170 Names[RTLIB::SIN_PPCF128] = "sinl"; 171 Names[RTLIB::COS_F32] = "cosf"; 172 Names[RTLIB::COS_F64] = "cos"; 173 Names[RTLIB::COS_F80] = "cosl"; 174 Names[RTLIB::COS_PPCF128] = "cosl"; 175 Names[RTLIB::POW_F32] = "powf"; 176 Names[RTLIB::POW_F64] = "pow"; 177 Names[RTLIB::POW_F80] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_PPCF128] = "ceill"; 183 Names[RTLIB::TRUNC_F32] = "truncf"; 184 Names[RTLIB::TRUNC_F64] = "trunc"; 185 Names[RTLIB::TRUNC_F80] = "truncl"; 186 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 187 Names[RTLIB::RINT_F32] = "rintf"; 188 Names[RTLIB::RINT_F64] = "rint"; 189 Names[RTLIB::RINT_F80] = "rintl"; 190 Names[RTLIB::RINT_PPCF128] = "rintl"; 191 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 192 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 193 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 194 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 195 Names[RTLIB::FLOOR_F32] = "floorf"; 196 Names[RTLIB::FLOOR_F64] = "floor"; 197 Names[RTLIB::FLOOR_F80] = "floorl"; 198 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 199 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 200 Names[RTLIB::COPYSIGN_F64] = "copysign"; 201 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 202 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 203 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 204 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 205 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 206 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 207 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 208 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 209 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 210 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 211 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 212 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 213 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 214 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 215 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 216 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 217 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 218 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 219 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 220 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 221 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 222 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 223 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 224 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 225 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 226 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 227 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 228 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 229 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 230 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 231 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 232 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 233 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 234 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 235 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 236 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 237 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 238 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 239 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 240 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 241 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 242 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 243 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 244 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 245 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 246 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 247 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 248 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 249 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 250 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 251 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 252 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 253 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 254 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 255 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 256 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 257 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 258 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 259 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 260 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 261 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 262 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 263 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 264 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 265 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 266 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 267 Names[RTLIB::OEQ_F32] = "__eqsf2"; 268 Names[RTLIB::OEQ_F64] = "__eqdf2"; 269 Names[RTLIB::UNE_F32] = "__nesf2"; 270 Names[RTLIB::UNE_F64] = "__nedf2"; 271 Names[RTLIB::OGE_F32] = "__gesf2"; 272 Names[RTLIB::OGE_F64] = "__gedf2"; 273 Names[RTLIB::OLT_F32] = "__ltsf2"; 274 Names[RTLIB::OLT_F64] = "__ltdf2"; 275 Names[RTLIB::OLE_F32] = "__lesf2"; 276 Names[RTLIB::OLE_F64] = "__ledf2"; 277 Names[RTLIB::OGT_F32] = "__gtsf2"; 278 Names[RTLIB::OGT_F64] = "__gtdf2"; 279 Names[RTLIB::UO_F32] = "__unordsf2"; 280 Names[RTLIB::UO_F64] = "__unorddf2"; 281 Names[RTLIB::O_F32] = "__unordsf2"; 282 Names[RTLIB::O_F64] = "__unorddf2"; 283 Names[RTLIB::MEMCPY] = "memcpy"; 284 Names[RTLIB::MEMMOVE] = "memmove"; 285 Names[RTLIB::MEMSET] = "memset"; 286 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 287 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 288 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 289 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 290 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 291 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 292 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 293 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 294 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 295 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 296 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 297 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 298 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 299 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 300 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 301 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 302 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 303 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 304 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 305 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 306 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 307 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 308 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 309 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 310 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 311 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 312 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 313 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 314 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 315 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 316 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 317 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 318 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 319} 320 321/// InitLibcallCallingConvs - Set default libcall CallingConvs. 322/// 323static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 324 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 325 CCs[i] = CallingConv::C; 326 } 327} 328 329/// getFPEXT - Return the FPEXT_*_* value for the given types, or 330/// UNKNOWN_LIBCALL if there is none. 331RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 332 if (OpVT == MVT::f32) { 333 if (RetVT == MVT::f64) 334 return FPEXT_F32_F64; 335 } 336 337 return UNKNOWN_LIBCALL; 338} 339 340/// getFPROUND - Return the FPROUND_*_* value for the given types, or 341/// UNKNOWN_LIBCALL if there is none. 342RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 343 if (RetVT == MVT::f32) { 344 if (OpVT == MVT::f64) 345 return FPROUND_F64_F32; 346 if (OpVT == MVT::f80) 347 return FPROUND_F80_F32; 348 if (OpVT == MVT::ppcf128) 349 return FPROUND_PPCF128_F32; 350 } else if (RetVT == MVT::f64) { 351 if (OpVT == MVT::f80) 352 return FPROUND_F80_F64; 353 if (OpVT == MVT::ppcf128) 354 return FPROUND_PPCF128_F64; 355 } 356 357 return UNKNOWN_LIBCALL; 358} 359 360/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 361/// UNKNOWN_LIBCALL if there is none. 362RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 363 if (OpVT == MVT::f32) { 364 if (RetVT == MVT::i8) 365 return FPTOSINT_F32_I8; 366 if (RetVT == MVT::i16) 367 return FPTOSINT_F32_I16; 368 if (RetVT == MVT::i32) 369 return FPTOSINT_F32_I32; 370 if (RetVT == MVT::i64) 371 return FPTOSINT_F32_I64; 372 if (RetVT == MVT::i128) 373 return FPTOSINT_F32_I128; 374 } else if (OpVT == MVT::f64) { 375 if (RetVT == MVT::i8) 376 return FPTOSINT_F64_I8; 377 if (RetVT == MVT::i16) 378 return FPTOSINT_F64_I16; 379 if (RetVT == MVT::i32) 380 return FPTOSINT_F64_I32; 381 if (RetVT == MVT::i64) 382 return FPTOSINT_F64_I64; 383 if (RetVT == MVT::i128) 384 return FPTOSINT_F64_I128; 385 } else if (OpVT == MVT::f80) { 386 if (RetVT == MVT::i32) 387 return FPTOSINT_F80_I32; 388 if (RetVT == MVT::i64) 389 return FPTOSINT_F80_I64; 390 if (RetVT == MVT::i128) 391 return FPTOSINT_F80_I128; 392 } else if (OpVT == MVT::ppcf128) { 393 if (RetVT == MVT::i32) 394 return FPTOSINT_PPCF128_I32; 395 if (RetVT == MVT::i64) 396 return FPTOSINT_PPCF128_I64; 397 if (RetVT == MVT::i128) 398 return FPTOSINT_PPCF128_I128; 399 } 400 return UNKNOWN_LIBCALL; 401} 402 403/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 404/// UNKNOWN_LIBCALL if there is none. 405RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 406 if (OpVT == MVT::f32) { 407 if (RetVT == MVT::i8) 408 return FPTOUINT_F32_I8; 409 if (RetVT == MVT::i16) 410 return FPTOUINT_F32_I16; 411 if (RetVT == MVT::i32) 412 return FPTOUINT_F32_I32; 413 if (RetVT == MVT::i64) 414 return FPTOUINT_F32_I64; 415 if (RetVT == MVT::i128) 416 return FPTOUINT_F32_I128; 417 } else if (OpVT == MVT::f64) { 418 if (RetVT == MVT::i8) 419 return FPTOUINT_F64_I8; 420 if (RetVT == MVT::i16) 421 return FPTOUINT_F64_I16; 422 if (RetVT == MVT::i32) 423 return FPTOUINT_F64_I32; 424 if (RetVT == MVT::i64) 425 return FPTOUINT_F64_I64; 426 if (RetVT == MVT::i128) 427 return FPTOUINT_F64_I128; 428 } else if (OpVT == MVT::f80) { 429 if (RetVT == MVT::i32) 430 return FPTOUINT_F80_I32; 431 if (RetVT == MVT::i64) 432 return FPTOUINT_F80_I64; 433 if (RetVT == MVT::i128) 434 return FPTOUINT_F80_I128; 435 } else if (OpVT == MVT::ppcf128) { 436 if (RetVT == MVT::i32) 437 return FPTOUINT_PPCF128_I32; 438 if (RetVT == MVT::i64) 439 return FPTOUINT_PPCF128_I64; 440 if (RetVT == MVT::i128) 441 return FPTOUINT_PPCF128_I128; 442 } 443 return UNKNOWN_LIBCALL; 444} 445 446/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 447/// UNKNOWN_LIBCALL if there is none. 448RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 449 if (OpVT == MVT::i32) { 450 if (RetVT == MVT::f32) 451 return SINTTOFP_I32_F32; 452 else if (RetVT == MVT::f64) 453 return SINTTOFP_I32_F64; 454 else if (RetVT == MVT::f80) 455 return SINTTOFP_I32_F80; 456 else if (RetVT == MVT::ppcf128) 457 return SINTTOFP_I32_PPCF128; 458 } else if (OpVT == MVT::i64) { 459 if (RetVT == MVT::f32) 460 return SINTTOFP_I64_F32; 461 else if (RetVT == MVT::f64) 462 return SINTTOFP_I64_F64; 463 else if (RetVT == MVT::f80) 464 return SINTTOFP_I64_F80; 465 else if (RetVT == MVT::ppcf128) 466 return SINTTOFP_I64_PPCF128; 467 } else if (OpVT == MVT::i128) { 468 if (RetVT == MVT::f32) 469 return SINTTOFP_I128_F32; 470 else if (RetVT == MVT::f64) 471 return SINTTOFP_I128_F64; 472 else if (RetVT == MVT::f80) 473 return SINTTOFP_I128_F80; 474 else if (RetVT == MVT::ppcf128) 475 return SINTTOFP_I128_PPCF128; 476 } 477 return UNKNOWN_LIBCALL; 478} 479 480/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 481/// UNKNOWN_LIBCALL if there is none. 482RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 483 if (OpVT == MVT::i32) { 484 if (RetVT == MVT::f32) 485 return UINTTOFP_I32_F32; 486 else if (RetVT == MVT::f64) 487 return UINTTOFP_I32_F64; 488 else if (RetVT == MVT::f80) 489 return UINTTOFP_I32_F80; 490 else if (RetVT == MVT::ppcf128) 491 return UINTTOFP_I32_PPCF128; 492 } else if (OpVT == MVT::i64) { 493 if (RetVT == MVT::f32) 494 return UINTTOFP_I64_F32; 495 else if (RetVT == MVT::f64) 496 return UINTTOFP_I64_F64; 497 else if (RetVT == MVT::f80) 498 return UINTTOFP_I64_F80; 499 else if (RetVT == MVT::ppcf128) 500 return UINTTOFP_I64_PPCF128; 501 } else if (OpVT == MVT::i128) { 502 if (RetVT == MVT::f32) 503 return UINTTOFP_I128_F32; 504 else if (RetVT == MVT::f64) 505 return UINTTOFP_I128_F64; 506 else if (RetVT == MVT::f80) 507 return UINTTOFP_I128_F80; 508 else if (RetVT == MVT::ppcf128) 509 return UINTTOFP_I128_PPCF128; 510 } 511 return UNKNOWN_LIBCALL; 512} 513 514/// InitCmpLibcallCCs - Set default comparison libcall CC. 515/// 516static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 517 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 518 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 519 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 520 CCs[RTLIB::UNE_F32] = ISD::SETNE; 521 CCs[RTLIB::UNE_F64] = ISD::SETNE; 522 CCs[RTLIB::OGE_F32] = ISD::SETGE; 523 CCs[RTLIB::OGE_F64] = ISD::SETGE; 524 CCs[RTLIB::OLT_F32] = ISD::SETLT; 525 CCs[RTLIB::OLT_F64] = ISD::SETLT; 526 CCs[RTLIB::OLE_F32] = ISD::SETLE; 527 CCs[RTLIB::OLE_F64] = ISD::SETLE; 528 CCs[RTLIB::OGT_F32] = ISD::SETGT; 529 CCs[RTLIB::OGT_F64] = ISD::SETGT; 530 CCs[RTLIB::UO_F32] = ISD::SETNE; 531 CCs[RTLIB::UO_F64] = ISD::SETNE; 532 CCs[RTLIB::O_F32] = ISD::SETEQ; 533 CCs[RTLIB::O_F64] = ISD::SETEQ; 534} 535 536/// NOTE: The constructor takes ownership of TLOF. 537TargetLowering::TargetLowering(const TargetMachine &tm, 538 const TargetLoweringObjectFile *tlof) 539 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), 540 mayPromoteElements(AllowPromoteIntElem) { 541 // All operations default to being supported. 542 memset(OpActions, 0, sizeof(OpActions)); 543 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 544 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 545 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 546 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 547 548 // Set default actions for various operations. 549 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 550 // Default all indexed load / store to expand. 551 for (unsigned IM = (unsigned)ISD::PRE_INC; 552 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 553 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 554 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 555 } 556 557 // These operations default to expand. 558 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 559 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 560 } 561 562 // Most targets ignore the @llvm.prefetch intrinsic. 563 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 564 565 // ConstantFP nodes default to expand. Targets can either change this to 566 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 567 // to optimize expansions for certain constants. 568 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 569 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 570 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 571 572 // These library functions default to expand. 573 setOperationAction(ISD::FLOG , MVT::f64, Expand); 574 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 575 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 576 setOperationAction(ISD::FEXP , MVT::f64, Expand); 577 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 578 setOperationAction(ISD::FLOG , MVT::f32, Expand); 579 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 580 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 581 setOperationAction(ISD::FEXP , MVT::f32, Expand); 582 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 583 584 // Default ISD::TRAP to expand (which turns it into abort). 585 setOperationAction(ISD::TRAP, MVT::Other, Expand); 586 587 IsLittleEndian = TD->isLittleEndian(); 588 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 589 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 590 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 591 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 592 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 593 = maxStoresPerMemmoveOptSize = 4; 594 benefitFromCodePlacementOpt = false; 595 UseUnderscoreSetJmp = false; 596 UseUnderscoreLongJmp = false; 597 SelectIsExpensive = false; 598 IntDivIsCheap = false; 599 Pow2DivIsCheap = false; 600 JumpIsExpensive = false; 601 StackPointerRegisterToSaveRestore = 0; 602 ExceptionPointerRegister = 0; 603 ExceptionSelectorRegister = 0; 604 BooleanContents = UndefinedBooleanContent; 605 SchedPreferenceInfo = Sched::Latency; 606 JumpBufSize = 0; 607 JumpBufAlignment = 0; 608 MinFunctionAlignment = 0; 609 PrefFunctionAlignment = 0; 610 PrefLoopAlignment = 0; 611 MinStackArgumentAlignment = 1; 612 ShouldFoldAtomicFences = false; 613 614 InitLibcallNames(LibcallRoutineNames); 615 InitCmpLibcallCCs(CmpLibcallCCs); 616 InitLibcallCallingConvs(LibcallCallingConvs); 617} 618 619TargetLowering::~TargetLowering() { 620 delete &TLOF; 621} 622 623MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const { 624 return MVT::getIntegerVT(8*TD->getPointerSize()); 625} 626 627/// canOpTrap - Returns true if the operation can trap for the value type. 628/// VT must be a legal type. 629bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 630 assert(isTypeLegal(VT)); 631 switch (Op) { 632 default: 633 return false; 634 case ISD::FDIV: 635 case ISD::FREM: 636 case ISD::SDIV: 637 case ISD::UDIV: 638 case ISD::SREM: 639 case ISD::UREM: 640 return true; 641 } 642} 643 644 645static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 646 unsigned &NumIntermediates, 647 EVT &RegisterVT, 648 TargetLowering *TLI) { 649 // Figure out the right, legal destination reg to copy into. 650 unsigned NumElts = VT.getVectorNumElements(); 651 MVT EltTy = VT.getVectorElementType(); 652 653 unsigned NumVectorRegs = 1; 654 655 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 656 // could break down into LHS/RHS like LegalizeDAG does. 657 if (!isPowerOf2_32(NumElts)) { 658 NumVectorRegs = NumElts; 659 NumElts = 1; 660 } 661 662 // Divide the input until we get to a supported size. This will always 663 // end with a scalar if the target doesn't support vectors. 664 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 665 NumElts >>= 1; 666 NumVectorRegs <<= 1; 667 } 668 669 NumIntermediates = NumVectorRegs; 670 671 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 672 if (!TLI->isTypeLegal(NewVT)) 673 NewVT = EltTy; 674 IntermediateVT = NewVT; 675 676 EVT DestVT = TLI->getRegisterType(NewVT); 677 RegisterVT = DestVT; 678 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 679 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 680 681 // Otherwise, promotion or legal types use the same number of registers as 682 // the vector decimated to the appropriate level. 683 return NumVectorRegs; 684} 685 686/// isLegalRC - Return true if the value types that can be represented by the 687/// specified register class are all legal. 688bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const { 689 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 690 I != E; ++I) { 691 if (isTypeLegal(*I)) 692 return true; 693 } 694 return false; 695} 696 697/// hasLegalSuperRegRegClasses - Return true if the specified register class 698/// has one or more super-reg register classes that are legal. 699bool 700TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{ 701 if (*RC->superregclasses_begin() == 0) 702 return false; 703 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 704 E = RC->superregclasses_end(); I != E; ++I) { 705 const TargetRegisterClass *RRC = *I; 706 if (isLegalRC(RRC)) 707 return true; 708 } 709 return false; 710} 711 712/// findRepresentativeClass - Return the largest legal super-reg register class 713/// of the register class for the specified type and its associated "cost". 714std::pair<const TargetRegisterClass*, uint8_t> 715TargetLowering::findRepresentativeClass(EVT VT) const { 716 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 717 if (!RC) 718 return std::make_pair(RC, 0); 719 const TargetRegisterClass *BestRC = RC; 720 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(), 721 E = RC->superregclasses_end(); I != E; ++I) { 722 const TargetRegisterClass *RRC = *I; 723 if (RRC->isASubClass() || !isLegalRC(RRC)) 724 continue; 725 if (!hasLegalSuperRegRegClasses(RRC)) 726 return std::make_pair(RRC, 1); 727 BestRC = RRC; 728 } 729 return std::make_pair(BestRC, 1); 730} 731 732 733/// computeRegisterProperties - Once all of the register classes are added, 734/// this allows us to compute derived properties we expose. 735void TargetLowering::computeRegisterProperties() { 736 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 737 "Too many value types for ValueTypeActions to hold!"); 738 739 // Everything defaults to needing one register. 740 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 741 NumRegistersForVT[i] = 1; 742 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 743 } 744 // ...except isVoid, which doesn't need any registers. 745 NumRegistersForVT[MVT::isVoid] = 0; 746 747 // Find the largest integer register class. 748 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 749 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 750 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 751 752 // Every integer value type larger than this largest register takes twice as 753 // many registers to represent as the previous ValueType. 754 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 755 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 756 if (!ExpandedVT.isInteger()) 757 break; 758 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 759 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 760 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 761 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger); 762 } 763 764 // Inspect all of the ValueType's smaller than the largest integer 765 // register to see which ones need promotion. 766 unsigned LegalIntReg = LargestIntReg; 767 for (unsigned IntReg = LargestIntReg - 1; 768 IntReg >= (unsigned)MVT::i1; --IntReg) { 769 EVT IVT = (MVT::SimpleValueType)IntReg; 770 if (isTypeLegal(IVT)) { 771 LegalIntReg = IntReg; 772 } else { 773 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 774 (MVT::SimpleValueType)LegalIntReg; 775 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 776 } 777 } 778 779 // ppcf128 type is really two f64's. 780 if (!isTypeLegal(MVT::ppcf128)) { 781 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 782 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 783 TransformToType[MVT::ppcf128] = MVT::f64; 784 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 785 } 786 787 // Decide how to handle f64. If the target does not have native f64 support, 788 // expand it to i64 and we will be generating soft float library calls. 789 if (!isTypeLegal(MVT::f64)) { 790 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 791 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 792 TransformToType[MVT::f64] = MVT::i64; 793 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 794 } 795 796 // Decide how to handle f32. If the target does not have native support for 797 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 798 if (!isTypeLegal(MVT::f32)) { 799 if (isTypeLegal(MVT::f64)) { 800 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 801 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 802 TransformToType[MVT::f32] = MVT::f64; 803 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 804 } else { 805 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 806 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 807 TransformToType[MVT::f32] = MVT::i32; 808 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 809 } 810 } 811 812 // Loop over all of the vector value types to see which need transformations. 813 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 814 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 815 MVT VT = (MVT::SimpleValueType)i; 816 if (isTypeLegal(VT)) continue; 817 818 // Determine if there is a legal wider type. If so, we should promote to 819 // that wider vector type. 820 EVT EltVT = VT.getVectorElementType(); 821 unsigned NElts = VT.getVectorNumElements(); 822 if (NElts != 1) { 823 bool IsLegalWiderType = false; 824 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 825 EVT SVT = (MVT::SimpleValueType)nVT; 826 827 // If we allow the promotion of vector elements using a flag, 828 // then return TypePromoteInteger on vector elements. 829 if (mayPromoteElements) { 830 // Promote vectors of integers to vectors with the same number 831 // of elements, with a wider element type. 832 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 833 && SVT.getVectorNumElements() == NElts && 834 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 835 TransformToType[i] = SVT; 836 RegisterTypeForVT[i] = SVT; 837 NumRegistersForVT[i] = 1; 838 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 839 IsLegalWiderType = true; 840 break; 841 } 842 } 843 844 if (SVT.getVectorElementType() == EltVT && 845 SVT.getVectorNumElements() > NElts && 846 isTypeLegal(SVT)) { 847 TransformToType[i] = SVT; 848 RegisterTypeForVT[i] = SVT; 849 NumRegistersForVT[i] = 1; 850 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 851 IsLegalWiderType = true; 852 break; 853 } 854 } 855 if (IsLegalWiderType) continue; 856 } 857 858 MVT IntermediateVT; 859 EVT RegisterVT; 860 unsigned NumIntermediates; 861 NumRegistersForVT[i] = 862 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 863 RegisterVT, this); 864 RegisterTypeForVT[i] = RegisterVT; 865 866 EVT NVT = VT.getPow2VectorType(); 867 if (NVT == VT) { 868 // Type is already a power of 2. The default action is to split. 869 TransformToType[i] = MVT::Other; 870 unsigned NumElts = VT.getVectorNumElements(); 871 ValueTypeActions.setTypeAction(VT, 872 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 873 } else { 874 TransformToType[i] = NVT; 875 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 876 } 877 } 878 879 // Determine the 'representative' register class for each value type. 880 // An representative register class is the largest (meaning one which is 881 // not a sub-register class / subreg register class) legal register class for 882 // a group of value types. For example, on i386, i8, i16, and i32 883 // representative would be GR32; while on x86_64 it's GR64. 884 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 885 const TargetRegisterClass* RRC; 886 uint8_t Cost; 887 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 888 RepRegClassForVT[i] = RRC; 889 RepRegClassCostForVT[i] = Cost; 890 } 891} 892 893const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 894 return NULL; 895} 896 897 898MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 899 return PointerTy.SimpleTy; 900} 901 902MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 903 return MVT::i32; // return the default value 904} 905 906/// getVectorTypeBreakdown - Vector types are broken down into some number of 907/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 908/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 909/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 910/// 911/// This method returns the number of registers needed, and the VT for each 912/// register. It also returns the VT and quantity of the intermediate values 913/// before they are promoted/expanded. 914/// 915unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 916 EVT &IntermediateVT, 917 unsigned &NumIntermediates, 918 EVT &RegisterVT) const { 919 unsigned NumElts = VT.getVectorNumElements(); 920 921 // If there is a wider vector type with the same element type as this one, 922 // we should widen to that legal vector type. This handles things like 923 // <2 x float> -> <4 x float>. 924 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) { 925 RegisterVT = getTypeToTransformTo(Context, VT); 926 if (isTypeLegal(RegisterVT)) { 927 IntermediateVT = RegisterVT; 928 NumIntermediates = 1; 929 return 1; 930 } 931 } 932 933 // Figure out the right, legal destination reg to copy into. 934 EVT EltTy = VT.getVectorElementType(); 935 936 unsigned NumVectorRegs = 1; 937 938 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 939 // could break down into LHS/RHS like LegalizeDAG does. 940 if (!isPowerOf2_32(NumElts)) { 941 NumVectorRegs = NumElts; 942 NumElts = 1; 943 } 944 945 // Divide the input until we get to a supported size. This will always 946 // end with a scalar if the target doesn't support vectors. 947 while (NumElts > 1 && !isTypeLegal( 948 EVT::getVectorVT(Context, EltTy, NumElts))) { 949 NumElts >>= 1; 950 NumVectorRegs <<= 1; 951 } 952 953 NumIntermediates = NumVectorRegs; 954 955 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 956 if (!isTypeLegal(NewVT)) 957 NewVT = EltTy; 958 IntermediateVT = NewVT; 959 960 EVT DestVT = getRegisterType(Context, NewVT); 961 RegisterVT = DestVT; 962 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 963 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 964 965 // Otherwise, promotion or legal types use the same number of registers as 966 // the vector decimated to the appropriate level. 967 return NumVectorRegs; 968} 969 970/// Get the EVTs and ArgFlags collections that represent the legalized return 971/// type of the given function. This does not require a DAG or a return value, 972/// and is suitable for use before any DAGs for the function are constructed. 973/// TODO: Move this out of TargetLowering.cpp. 974void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 975 SmallVectorImpl<ISD::OutputArg> &Outs, 976 const TargetLowering &TLI, 977 SmallVectorImpl<uint64_t> *Offsets) { 978 SmallVector<EVT, 4> ValueVTs; 979 ComputeValueVTs(TLI, ReturnType, ValueVTs); 980 unsigned NumValues = ValueVTs.size(); 981 if (NumValues == 0) return; 982 unsigned Offset = 0; 983 984 for (unsigned j = 0, f = NumValues; j != f; ++j) { 985 EVT VT = ValueVTs[j]; 986 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 987 988 if (attr & Attribute::SExt) 989 ExtendKind = ISD::SIGN_EXTEND; 990 else if (attr & Attribute::ZExt) 991 ExtendKind = ISD::ZERO_EXTEND; 992 993 // FIXME: C calling convention requires the return type to be promoted to 994 // at least 32-bit. But this is not necessary for non-C calling 995 // conventions. The frontend should mark functions whose return values 996 // require promoting with signext or zeroext attributes. 997 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 998 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 999 if (VT.bitsLT(MinVT)) 1000 VT = MinVT; 1001 } 1002 1003 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1004 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1005 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 1006 PartVT.getTypeForEVT(ReturnType->getContext())); 1007 1008 // 'inreg' on function refers to return value 1009 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1010 if (attr & Attribute::InReg) 1011 Flags.setInReg(); 1012 1013 // Propagate extension type if any 1014 if (attr & Attribute::SExt) 1015 Flags.setSExt(); 1016 else if (attr & Attribute::ZExt) 1017 Flags.setZExt(); 1018 1019 for (unsigned i = 0; i < NumParts; ++i) { 1020 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 1021 if (Offsets) { 1022 Offsets->push_back(Offset); 1023 Offset += PartSize; 1024 } 1025 } 1026 } 1027} 1028 1029/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1030/// function arguments in the caller parameter area. This is the actual 1031/// alignment, not its logarithm. 1032unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 1033 return TD->getCallFrameTypeAlignment(Ty); 1034} 1035 1036/// getJumpTableEncoding - Return the entry encoding for a jump table in the 1037/// current function. The returned value is a member of the 1038/// MachineJumpTableInfo::JTEntryKind enum. 1039unsigned TargetLowering::getJumpTableEncoding() const { 1040 // In non-pic modes, just use the address of a block. 1041 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 1042 return MachineJumpTableInfo::EK_BlockAddress; 1043 1044 // In PIC mode, if the target supports a GPRel32 directive, use it. 1045 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 1046 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 1047 1048 // Otherwise, use a label difference. 1049 return MachineJumpTableInfo::EK_LabelDifference32; 1050} 1051 1052SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1053 SelectionDAG &DAG) const { 1054 // If our PIC model is GP relative, use the global offset table as the base. 1055 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 1056 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 1057 return Table; 1058} 1059 1060/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1061/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1062/// MCExpr. 1063const MCExpr * 1064TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 1065 unsigned JTI,MCContext &Ctx) const{ 1066 // The normal PIC reloc base is the label at the start of the jump table. 1067 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 1068} 1069 1070bool 1071TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1072 // Assume that everything is safe in static mode. 1073 if (getTargetMachine().getRelocationModel() == Reloc::Static) 1074 return true; 1075 1076 // In dynamic-no-pic mode, assume that known defined values are safe. 1077 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 1078 GA && 1079 !GA->getGlobal()->isDeclaration() && 1080 !GA->getGlobal()->isWeakForLinker()) 1081 return true; 1082 1083 // Otherwise assume nothing is safe. 1084 return false; 1085} 1086 1087//===----------------------------------------------------------------------===// 1088// Optimization Methods 1089//===----------------------------------------------------------------------===// 1090 1091/// ShrinkDemandedConstant - Check to see if the specified operand of the 1092/// specified instruction is a constant integer. If so, check to see if there 1093/// are any bits set in the constant that are not demanded. If so, shrink the 1094/// constant and return true. 1095bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 1096 const APInt &Demanded) { 1097 DebugLoc dl = Op.getDebugLoc(); 1098 1099 // FIXME: ISD::SELECT, ISD::SELECT_CC 1100 switch (Op.getOpcode()) { 1101 default: break; 1102 case ISD::XOR: 1103 case ISD::AND: 1104 case ISD::OR: { 1105 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 1106 if (!C) return false; 1107 1108 if (Op.getOpcode() == ISD::XOR && 1109 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 1110 return false; 1111 1112 // if we can expand it to have all bits set, do it 1113 if (C->getAPIntValue().intersects(~Demanded)) { 1114 EVT VT = Op.getValueType(); 1115 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 1116 DAG.getConstant(Demanded & 1117 C->getAPIntValue(), 1118 VT)); 1119 return CombineTo(Op, New); 1120 } 1121 1122 break; 1123 } 1124 } 1125 1126 return false; 1127} 1128 1129/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1130/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1131/// cast, but it could be generalized for targets with other types of 1132/// implicit widening casts. 1133bool 1134TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1135 unsigned BitWidth, 1136 const APInt &Demanded, 1137 DebugLoc dl) { 1138 assert(Op.getNumOperands() == 2 && 1139 "ShrinkDemandedOp only supports binary operators!"); 1140 assert(Op.getNode()->getNumValues() == 1 && 1141 "ShrinkDemandedOp only supports nodes with one result!"); 1142 1143 // Don't do this if the node has another user, which may require the 1144 // full value. 1145 if (!Op.getNode()->hasOneUse()) 1146 return false; 1147 1148 // Search for the smallest integer type with free casts to and from 1149 // Op's type. For expedience, just check power-of-2 integer types. 1150 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1151 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1152 if (!isPowerOf2_32(SmallVTBits)) 1153 SmallVTBits = NextPowerOf2(SmallVTBits); 1154 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1155 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1156 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1157 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1158 // We found a type with free casts. 1159 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1160 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1161 Op.getNode()->getOperand(0)), 1162 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1163 Op.getNode()->getOperand(1))); 1164 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1165 return CombineTo(Op, Z); 1166 } 1167 } 1168 return false; 1169} 1170 1171/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1172/// DemandedMask bits of the result of Op are ever used downstream. If we can 1173/// use this information to simplify Op, create a new simplified DAG node and 1174/// return true, returning the original and new nodes in Old and New. Otherwise, 1175/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1176/// the expression (used to simplify the caller). The KnownZero/One bits may 1177/// only be accurate for those bits in the DemandedMask. 1178bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1179 const APInt &DemandedMask, 1180 APInt &KnownZero, 1181 APInt &KnownOne, 1182 TargetLoweringOpt &TLO, 1183 unsigned Depth) const { 1184 unsigned BitWidth = DemandedMask.getBitWidth(); 1185 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1186 "Mask size mismatches value type size!"); 1187 APInt NewMask = DemandedMask; 1188 DebugLoc dl = Op.getDebugLoc(); 1189 1190 // Don't know anything. 1191 KnownZero = KnownOne = APInt(BitWidth, 0); 1192 1193 // Other users may use these bits. 1194 if (!Op.getNode()->hasOneUse()) { 1195 if (Depth != 0) { 1196 // If not at the root, Just compute the KnownZero/KnownOne bits to 1197 // simplify things downstream. 1198 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1199 return false; 1200 } 1201 // If this is the root being simplified, allow it to have multiple uses, 1202 // just set the NewMask to all bits. 1203 NewMask = APInt::getAllOnesValue(BitWidth); 1204 } else if (DemandedMask == 0) { 1205 // Not demanding any bits from Op. 1206 if (Op.getOpcode() != ISD::UNDEF) 1207 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1208 return false; 1209 } else if (Depth == 6) { // Limit search depth. 1210 return false; 1211 } 1212 1213 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1214 switch (Op.getOpcode()) { 1215 case ISD::Constant: 1216 // We know all of the bits for a constant! 1217 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1218 KnownZero = ~KnownOne & NewMask; 1219 return false; // Don't fall through, will infinitely loop. 1220 case ISD::AND: 1221 // If the RHS is a constant, check to see if the LHS would be zero without 1222 // using the bits from the RHS. Below, we use knowledge about the RHS to 1223 // simplify the LHS, here we're using information from the LHS to simplify 1224 // the RHS. 1225 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1226 APInt LHSZero, LHSOne; 1227 // Do not increment Depth here; that can cause an infinite loop. 1228 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1229 LHSZero, LHSOne, Depth); 1230 // If the LHS already has zeros where RHSC does, this and is dead. 1231 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1232 return TLO.CombineTo(Op, Op.getOperand(0)); 1233 // If any of the set bits in the RHS are known zero on the LHS, shrink 1234 // the constant. 1235 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1236 return true; 1237 } 1238 1239 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1240 KnownOne, TLO, Depth+1)) 1241 return true; 1242 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1243 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1244 KnownZero2, KnownOne2, TLO, Depth+1)) 1245 return true; 1246 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1247 1248 // If all of the demanded bits are known one on one side, return the other. 1249 // These bits cannot contribute to the result of the 'and'. 1250 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1251 return TLO.CombineTo(Op, Op.getOperand(0)); 1252 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1253 return TLO.CombineTo(Op, Op.getOperand(1)); 1254 // If all of the demanded bits in the inputs are known zeros, return zero. 1255 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1256 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1257 // If the RHS is a constant, see if we can simplify it. 1258 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1259 return true; 1260 // If the operation can be done in a smaller type, do so. 1261 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1262 return true; 1263 1264 // Output known-1 bits are only known if set in both the LHS & RHS. 1265 KnownOne &= KnownOne2; 1266 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1267 KnownZero |= KnownZero2; 1268 break; 1269 case ISD::OR: 1270 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1271 KnownOne, TLO, Depth+1)) 1272 return true; 1273 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1274 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1275 KnownZero2, KnownOne2, TLO, Depth+1)) 1276 return true; 1277 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1278 1279 // If all of the demanded bits are known zero on one side, return the other. 1280 // These bits cannot contribute to the result of the 'or'. 1281 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1282 return TLO.CombineTo(Op, Op.getOperand(0)); 1283 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1284 return TLO.CombineTo(Op, Op.getOperand(1)); 1285 // If all of the potentially set bits on one side are known to be set on 1286 // the other side, just use the 'other' side. 1287 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1288 return TLO.CombineTo(Op, Op.getOperand(0)); 1289 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1290 return TLO.CombineTo(Op, Op.getOperand(1)); 1291 // If the RHS is a constant, see if we can simplify it. 1292 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1293 return true; 1294 // If the operation can be done in a smaller type, do so. 1295 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1296 return true; 1297 1298 // Output known-0 bits are only known if clear in both the LHS & RHS. 1299 KnownZero &= KnownZero2; 1300 // Output known-1 are known to be set if set in either the LHS | RHS. 1301 KnownOne |= KnownOne2; 1302 break; 1303 case ISD::XOR: 1304 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1305 KnownOne, TLO, Depth+1)) 1306 return true; 1307 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1308 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1309 KnownOne2, TLO, Depth+1)) 1310 return true; 1311 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1312 1313 // If all of the demanded bits are known zero on one side, return the other. 1314 // These bits cannot contribute to the result of the 'xor'. 1315 if ((KnownZero & NewMask) == NewMask) 1316 return TLO.CombineTo(Op, Op.getOperand(0)); 1317 if ((KnownZero2 & NewMask) == NewMask) 1318 return TLO.CombineTo(Op, Op.getOperand(1)); 1319 // If the operation can be done in a smaller type, do so. 1320 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1321 return true; 1322 1323 // If all of the unknown bits are known to be zero on one side or the other 1324 // (but not both) turn this into an *inclusive* or. 1325 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1326 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1327 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1328 Op.getOperand(0), 1329 Op.getOperand(1))); 1330 1331 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1332 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1333 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1334 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1335 1336 // If all of the demanded bits on one side are known, and all of the set 1337 // bits on that side are also known to be set on the other side, turn this 1338 // into an AND, as we know the bits will be cleared. 1339 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1340 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1341 if ((KnownOne & KnownOne2) == KnownOne) { 1342 EVT VT = Op.getValueType(); 1343 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1344 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1345 Op.getOperand(0), ANDC)); 1346 } 1347 } 1348 1349 // If the RHS is a constant, see if we can simplify it. 1350 // for XOR, we prefer to force bits to 1 if they will make a -1. 1351 // if we can't force bits, try to shrink constant 1352 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1353 APInt Expanded = C->getAPIntValue() | (~NewMask); 1354 // if we can expand it to have all bits set, do it 1355 if (Expanded.isAllOnesValue()) { 1356 if (Expanded != C->getAPIntValue()) { 1357 EVT VT = Op.getValueType(); 1358 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1359 TLO.DAG.getConstant(Expanded, VT)); 1360 return TLO.CombineTo(Op, New); 1361 } 1362 // if it already has all the bits set, nothing to change 1363 // but don't shrink either! 1364 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1365 return true; 1366 } 1367 } 1368 1369 KnownZero = KnownZeroOut; 1370 KnownOne = KnownOneOut; 1371 break; 1372 case ISD::SELECT: 1373 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1374 KnownOne, TLO, Depth+1)) 1375 return true; 1376 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1377 KnownOne2, TLO, Depth+1)) 1378 return true; 1379 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1380 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1381 1382 // If the operands are constants, see if we can simplify them. 1383 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1384 return true; 1385 1386 // Only known if known in both the LHS and RHS. 1387 KnownOne &= KnownOne2; 1388 KnownZero &= KnownZero2; 1389 break; 1390 case ISD::SELECT_CC: 1391 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1392 KnownOne, TLO, Depth+1)) 1393 return true; 1394 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1395 KnownOne2, TLO, Depth+1)) 1396 return true; 1397 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1398 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1399 1400 // If the operands are constants, see if we can simplify them. 1401 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1402 return true; 1403 1404 // Only known if known in both the LHS and RHS. 1405 KnownOne &= KnownOne2; 1406 KnownZero &= KnownZero2; 1407 break; 1408 case ISD::SHL: 1409 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1410 unsigned ShAmt = SA->getZExtValue(); 1411 SDValue InOp = Op.getOperand(0); 1412 1413 // If the shift count is an invalid immediate, don't do anything. 1414 if (ShAmt >= BitWidth) 1415 break; 1416 1417 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1418 // single shift. We can do this if the bottom bits (which are shifted 1419 // out) are never demanded. 1420 if (InOp.getOpcode() == ISD::SRL && 1421 isa<ConstantSDNode>(InOp.getOperand(1))) { 1422 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1423 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1424 unsigned Opc = ISD::SHL; 1425 int Diff = ShAmt-C1; 1426 if (Diff < 0) { 1427 Diff = -Diff; 1428 Opc = ISD::SRL; 1429 } 1430 1431 SDValue NewSA = 1432 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1433 EVT VT = Op.getValueType(); 1434 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1435 InOp.getOperand(0), NewSA)); 1436 } 1437 } 1438 1439 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 1440 KnownZero, KnownOne, TLO, Depth+1)) 1441 return true; 1442 1443 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 1444 // are not demanded. This will likely allow the anyext to be folded away. 1445 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 1446 SDValue InnerOp = InOp.getNode()->getOperand(0); 1447 EVT InnerVT = InnerOp.getValueType(); 1448 if ((APInt::getHighBitsSet(BitWidth, 1449 BitWidth - InnerVT.getSizeInBits()) & 1450 DemandedMask) == 0 && 1451 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 1452 EVT ShTy = getShiftAmountTy(InnerVT); 1453 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 1454 ShTy = InnerVT; 1455 SDValue NarrowShl = 1456 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 1457 TLO.DAG.getConstant(ShAmt, ShTy)); 1458 return 1459 TLO.CombineTo(Op, 1460 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 1461 NarrowShl)); 1462 } 1463 } 1464 1465 KnownZero <<= SA->getZExtValue(); 1466 KnownOne <<= SA->getZExtValue(); 1467 // low bits known zero. 1468 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1469 } 1470 break; 1471 case ISD::SRL: 1472 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1473 EVT VT = Op.getValueType(); 1474 unsigned ShAmt = SA->getZExtValue(); 1475 unsigned VTSize = VT.getSizeInBits(); 1476 SDValue InOp = Op.getOperand(0); 1477 1478 // If the shift count is an invalid immediate, don't do anything. 1479 if (ShAmt >= BitWidth) 1480 break; 1481 1482 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1483 // single shift. We can do this if the top bits (which are shifted out) 1484 // are never demanded. 1485 if (InOp.getOpcode() == ISD::SHL && 1486 isa<ConstantSDNode>(InOp.getOperand(1))) { 1487 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1488 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1489 unsigned Opc = ISD::SRL; 1490 int Diff = ShAmt-C1; 1491 if (Diff < 0) { 1492 Diff = -Diff; 1493 Opc = ISD::SHL; 1494 } 1495 1496 SDValue NewSA = 1497 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1498 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1499 InOp.getOperand(0), NewSA)); 1500 } 1501 } 1502 1503 // Compute the new bits that are at the top now. 1504 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1505 KnownZero, KnownOne, TLO, Depth+1)) 1506 return true; 1507 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1508 KnownZero = KnownZero.lshr(ShAmt); 1509 KnownOne = KnownOne.lshr(ShAmt); 1510 1511 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1512 KnownZero |= HighBits; // High bits known zero. 1513 } 1514 break; 1515 case ISD::SRA: 1516 // If this is an arithmetic shift right and only the low-bit is set, we can 1517 // always convert this into a logical shr, even if the shift amount is 1518 // variable. The low bit of the shift cannot be an input sign bit unless 1519 // the shift amount is >= the size of the datatype, which is undefined. 1520 if (DemandedMask == 1) 1521 return TLO.CombineTo(Op, 1522 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1523 Op.getOperand(0), Op.getOperand(1))); 1524 1525 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1526 EVT VT = Op.getValueType(); 1527 unsigned ShAmt = SA->getZExtValue(); 1528 1529 // If the shift count is an invalid immediate, don't do anything. 1530 if (ShAmt >= BitWidth) 1531 break; 1532 1533 APInt InDemandedMask = (NewMask << ShAmt); 1534 1535 // If any of the demanded bits are produced by the sign extension, we also 1536 // demand the input sign bit. 1537 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1538 if (HighBits.intersects(NewMask)) 1539 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1540 1541 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1542 KnownZero, KnownOne, TLO, Depth+1)) 1543 return true; 1544 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1545 KnownZero = KnownZero.lshr(ShAmt); 1546 KnownOne = KnownOne.lshr(ShAmt); 1547 1548 // Handle the sign bit, adjusted to where it is now in the mask. 1549 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1550 1551 // If the input sign bit is known to be zero, or if none of the top bits 1552 // are demanded, turn this into an unsigned shift right. 1553 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1554 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1555 Op.getOperand(0), 1556 Op.getOperand(1))); 1557 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1558 KnownOne |= HighBits; 1559 } 1560 } 1561 break; 1562 case ISD::SIGN_EXTEND_INREG: { 1563 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1564 1565 // Sign extension. Compute the demanded bits in the result that are not 1566 // present in the input. 1567 APInt NewBits = 1568 APInt::getHighBitsSet(BitWidth, 1569 BitWidth - EVT.getScalarType().getSizeInBits()); 1570 1571 // If none of the extended bits are demanded, eliminate the sextinreg. 1572 if ((NewBits & NewMask) == 0) 1573 return TLO.CombineTo(Op, Op.getOperand(0)); 1574 1575 APInt InSignBit = 1576 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth); 1577 APInt InputDemandedBits = 1578 APInt::getLowBitsSet(BitWidth, 1579 EVT.getScalarType().getSizeInBits()) & 1580 NewMask; 1581 1582 // Since the sign extended bits are demanded, we know that the sign 1583 // bit is demanded. 1584 InputDemandedBits |= InSignBit; 1585 1586 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1587 KnownZero, KnownOne, TLO, Depth+1)) 1588 return true; 1589 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1590 1591 // If the sign bit of the input is known set or clear, then we know the 1592 // top bits of the result. 1593 1594 // If the input sign bit is known zero, convert this into a zero extension. 1595 if (KnownZero.intersects(InSignBit)) 1596 return TLO.CombineTo(Op, 1597 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1598 1599 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1600 KnownOne |= NewBits; 1601 KnownZero &= ~NewBits; 1602 } else { // Input sign bit unknown 1603 KnownZero &= ~NewBits; 1604 KnownOne &= ~NewBits; 1605 } 1606 break; 1607 } 1608 case ISD::ZERO_EXTEND: { 1609 unsigned OperandBitWidth = 1610 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1611 APInt InMask = NewMask.trunc(OperandBitWidth); 1612 1613 // If none of the top bits are demanded, convert this into an any_extend. 1614 APInt NewBits = 1615 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1616 if (!NewBits.intersects(NewMask)) 1617 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1618 Op.getValueType(), 1619 Op.getOperand(0))); 1620 1621 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1622 KnownZero, KnownOne, TLO, Depth+1)) 1623 return true; 1624 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1625 KnownZero = KnownZero.zext(BitWidth); 1626 KnownOne = KnownOne.zext(BitWidth); 1627 KnownZero |= NewBits; 1628 break; 1629 } 1630 case ISD::SIGN_EXTEND: { 1631 EVT InVT = Op.getOperand(0).getValueType(); 1632 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1633 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1634 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1635 APInt NewBits = ~InMask & NewMask; 1636 1637 // If none of the top bits are demanded, convert this into an any_extend. 1638 if (NewBits == 0) 1639 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1640 Op.getValueType(), 1641 Op.getOperand(0))); 1642 1643 // Since some of the sign extended bits are demanded, we know that the sign 1644 // bit is demanded. 1645 APInt InDemandedBits = InMask & NewMask; 1646 InDemandedBits |= InSignBit; 1647 InDemandedBits = InDemandedBits.trunc(InBits); 1648 1649 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1650 KnownOne, TLO, Depth+1)) 1651 return true; 1652 KnownZero = KnownZero.zext(BitWidth); 1653 KnownOne = KnownOne.zext(BitWidth); 1654 1655 // If the sign bit is known zero, convert this to a zero extend. 1656 if (KnownZero.intersects(InSignBit)) 1657 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1658 Op.getValueType(), 1659 Op.getOperand(0))); 1660 1661 // If the sign bit is known one, the top bits match. 1662 if (KnownOne.intersects(InSignBit)) { 1663 KnownOne |= NewBits; 1664 KnownZero &= ~NewBits; 1665 } else { // Otherwise, top bits aren't known. 1666 KnownOne &= ~NewBits; 1667 KnownZero &= ~NewBits; 1668 } 1669 break; 1670 } 1671 case ISD::ANY_EXTEND: { 1672 unsigned OperandBitWidth = 1673 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1674 APInt InMask = NewMask.trunc(OperandBitWidth); 1675 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1676 KnownZero, KnownOne, TLO, Depth+1)) 1677 return true; 1678 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1679 KnownZero = KnownZero.zext(BitWidth); 1680 KnownOne = KnownOne.zext(BitWidth); 1681 break; 1682 } 1683 case ISD::TRUNCATE: { 1684 // Simplify the input, using demanded bit information, and compute the known 1685 // zero/one bits live out. 1686 unsigned OperandBitWidth = 1687 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1688 APInt TruncMask = NewMask.zext(OperandBitWidth); 1689 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1690 KnownZero, KnownOne, TLO, Depth+1)) 1691 return true; 1692 KnownZero = KnownZero.trunc(BitWidth); 1693 KnownOne = KnownOne.trunc(BitWidth); 1694 1695 // If the input is only used by this truncate, see if we can shrink it based 1696 // on the known demanded bits. 1697 if (Op.getOperand(0).getNode()->hasOneUse()) { 1698 SDValue In = Op.getOperand(0); 1699 switch (In.getOpcode()) { 1700 default: break; 1701 case ISD::SRL: 1702 // Shrink SRL by a constant if none of the high bits shifted in are 1703 // demanded. 1704 if (TLO.LegalTypes() && 1705 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1706 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1707 // undesirable. 1708 break; 1709 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1710 if (!ShAmt) 1711 break; 1712 SDValue Shift = In.getOperand(1); 1713 if (TLO.LegalTypes()) { 1714 uint64_t ShVal = ShAmt->getZExtValue(); 1715 Shift = 1716 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 1717 } 1718 1719 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1720 OperandBitWidth - BitWidth); 1721 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 1722 1723 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1724 // None of the shifted in bits are needed. Add a truncate of the 1725 // shift input, then shift it. 1726 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1727 Op.getValueType(), 1728 In.getOperand(0)); 1729 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1730 Op.getValueType(), 1731 NewTrunc, 1732 Shift)); 1733 } 1734 break; 1735 } 1736 } 1737 1738 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1739 break; 1740 } 1741 case ISD::AssertZext: { 1742 // Demand all the bits of the input that are demanded in the output. 1743 // The low bits are obvious; the high bits are demanded because we're 1744 // asserting that they're zero here. 1745 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1746 KnownZero, KnownOne, TLO, Depth+1)) 1747 return true; 1748 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1749 1750 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1751 APInt InMask = APInt::getLowBitsSet(BitWidth, 1752 VT.getSizeInBits()); 1753 KnownZero |= ~InMask & NewMask; 1754 break; 1755 } 1756 case ISD::BITCAST: 1757 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1758 // is demanded, turn this into a FGETSIGN. 1759 if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 1760 Op.getOperand(0).getValueType().isFloatingPoint() && 1761 !Op.getOperand(0).getValueType().isVector()) { 1762 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 1763 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 1764 if (OpVTLegal || i32Legal) { 1765 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 1766 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1767 // place. We expect the SHL to be eliminated by other optimizations. 1768 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 1769 if (!OpVTLegal) 1770 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1771 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1772 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1773 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1774 Op.getValueType(), 1775 Sign, ShAmt)); 1776 } 1777 } 1778 break; 1779 case ISD::ADD: 1780 case ISD::MUL: 1781 case ISD::SUB: { 1782 // Add, Sub, and Mul don't demand any bits in positions beyond that 1783 // of the highest bit demanded of them. 1784 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1785 BitWidth - NewMask.countLeadingZeros()); 1786 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1787 KnownOne2, TLO, Depth+1)) 1788 return true; 1789 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1790 KnownOne2, TLO, Depth+1)) 1791 return true; 1792 // See if the operation should be performed at a smaller bit width. 1793 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1794 return true; 1795 } 1796 // FALL THROUGH 1797 default: 1798 // Just use ComputeMaskedBits to compute output bits. 1799 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1800 break; 1801 } 1802 1803 // If we know the value of all of the demanded bits, return this as a 1804 // constant. 1805 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1806 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1807 1808 return false; 1809} 1810 1811/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1812/// in Mask are known to be either zero or one and return them in the 1813/// KnownZero/KnownOne bitsets. 1814void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1815 const APInt &Mask, 1816 APInt &KnownZero, 1817 APInt &KnownOne, 1818 const SelectionDAG &DAG, 1819 unsigned Depth) const { 1820 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1821 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1822 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1823 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1824 "Should use MaskedValueIsZero if you don't know whether Op" 1825 " is a target node!"); 1826 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1827} 1828 1829/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1830/// targets that want to expose additional information about sign bits to the 1831/// DAG Combiner. 1832unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1833 unsigned Depth) const { 1834 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1835 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1836 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1837 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1838 "Should use ComputeNumSignBits if you don't know whether Op" 1839 " is a target node!"); 1840 return 1; 1841} 1842 1843/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1844/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1845/// determine which bit is set. 1846/// 1847static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1848 // A left-shift of a constant one will have exactly one bit set, because 1849 // shifting the bit off the end is undefined. 1850 if (Val.getOpcode() == ISD::SHL) 1851 if (ConstantSDNode *C = 1852 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1853 if (C->getAPIntValue() == 1) 1854 return true; 1855 1856 // Similarly, a right-shift of a constant sign-bit will have exactly 1857 // one bit set. 1858 if (Val.getOpcode() == ISD::SRL) 1859 if (ConstantSDNode *C = 1860 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1861 if (C->getAPIntValue().isSignBit()) 1862 return true; 1863 1864 // More could be done here, though the above checks are enough 1865 // to handle some common cases. 1866 1867 // Fall back to ComputeMaskedBits to catch other known cases. 1868 EVT OpVT = Val.getValueType(); 1869 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1870 APInt Mask = APInt::getAllOnesValue(BitWidth); 1871 APInt KnownZero, KnownOne; 1872 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1873 return (KnownZero.countPopulation() == BitWidth - 1) && 1874 (KnownOne.countPopulation() == 1); 1875} 1876 1877/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1878/// and cc. If it is unable to simplify it, return a null SDValue. 1879SDValue 1880TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1881 ISD::CondCode Cond, bool foldBooleans, 1882 DAGCombinerInfo &DCI, DebugLoc dl) const { 1883 SelectionDAG &DAG = DCI.DAG; 1884 1885 // These setcc operations always fold. 1886 switch (Cond) { 1887 default: break; 1888 case ISD::SETFALSE: 1889 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1890 case ISD::SETTRUE: 1891 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1892 } 1893 1894 // Ensure that the constant occurs on the RHS, and fold constant 1895 // comparisons. 1896 if (isa<ConstantSDNode>(N0.getNode())) 1897 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1898 1899 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1900 const APInt &C1 = N1C->getAPIntValue(); 1901 1902 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1903 // equality comparison, then we're just comparing whether X itself is 1904 // zero. 1905 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1906 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1907 N0.getOperand(1).getOpcode() == ISD::Constant) { 1908 const APInt &ShAmt 1909 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1910 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1911 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1912 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1913 // (srl (ctlz x), 5) == 0 -> X != 0 1914 // (srl (ctlz x), 5) != 1 -> X != 0 1915 Cond = ISD::SETNE; 1916 } else { 1917 // (srl (ctlz x), 5) != 0 -> X == 0 1918 // (srl (ctlz x), 5) == 1 -> X == 0 1919 Cond = ISD::SETEQ; 1920 } 1921 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1922 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1923 Zero, Cond); 1924 } 1925 } 1926 1927 SDValue CTPOP = N0; 1928 // Look through truncs that don't change the value of a ctpop. 1929 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1930 CTPOP = N0.getOperand(0); 1931 1932 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1933 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1934 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1935 EVT CTVT = CTPOP.getValueType(); 1936 SDValue CTOp = CTPOP.getOperand(0); 1937 1938 // (ctpop x) u< 2 -> (x & x-1) == 0 1939 // (ctpop x) u> 1 -> (x & x-1) != 0 1940 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1941 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1942 DAG.getConstant(1, CTVT)); 1943 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1944 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1945 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1946 } 1947 1948 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1949 } 1950 1951 // (zext x) == C --> x == (trunc C) 1952 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1953 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1954 unsigned MinBits = N0.getValueSizeInBits(); 1955 SDValue PreZExt; 1956 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1957 // ZExt 1958 MinBits = N0->getOperand(0).getValueSizeInBits(); 1959 PreZExt = N0->getOperand(0); 1960 } else if (N0->getOpcode() == ISD::AND) { 1961 // DAGCombine turns costly ZExts into ANDs 1962 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1963 if ((C->getAPIntValue()+1).isPowerOf2()) { 1964 MinBits = C->getAPIntValue().countTrailingOnes(); 1965 PreZExt = N0->getOperand(0); 1966 } 1967 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1968 // ZEXTLOAD 1969 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1970 MinBits = LN0->getMemoryVT().getSizeInBits(); 1971 PreZExt = N0; 1972 } 1973 } 1974 1975 // Make sure we're not loosing bits from the constant. 1976 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) { 1977 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1978 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1979 // Will get folded away. 1980 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1981 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1982 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1983 } 1984 } 1985 } 1986 1987 // If the LHS is '(and load, const)', the RHS is 0, 1988 // the test is for equality or unsigned, and all 1 bits of the const are 1989 // in the same partial word, see if we can shorten the load. 1990 if (DCI.isBeforeLegalize() && 1991 N0.getOpcode() == ISD::AND && C1 == 0 && 1992 N0.getNode()->hasOneUse() && 1993 isa<LoadSDNode>(N0.getOperand(0)) && 1994 N0.getOperand(0).getNode()->hasOneUse() && 1995 isa<ConstantSDNode>(N0.getOperand(1))) { 1996 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1997 APInt bestMask; 1998 unsigned bestWidth = 0, bestOffset = 0; 1999 if (!Lod->isVolatile() && Lod->isUnindexed()) { 2000 unsigned origWidth = N0.getValueType().getSizeInBits(); 2001 unsigned maskWidth = origWidth; 2002 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 2003 // 8 bits, but have to be careful... 2004 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 2005 origWidth = Lod->getMemoryVT().getSizeInBits(); 2006 const APInt &Mask = 2007 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2008 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 2009 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 2010 for (unsigned offset=0; offset<origWidth/width; offset++) { 2011 if ((newMask & Mask) == Mask) { 2012 if (!TD->isLittleEndian()) 2013 bestOffset = (origWidth/width - offset - 1) * (width/8); 2014 else 2015 bestOffset = (uint64_t)offset * (width/8); 2016 bestMask = Mask.lshr(offset * (width/8) * 8); 2017 bestWidth = width; 2018 break; 2019 } 2020 newMask = newMask << width; 2021 } 2022 } 2023 } 2024 if (bestWidth) { 2025 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 2026 if (newVT.isRound()) { 2027 EVT PtrType = Lod->getOperand(1).getValueType(); 2028 SDValue Ptr = Lod->getBasePtr(); 2029 if (bestOffset != 0) 2030 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 2031 DAG.getConstant(bestOffset, PtrType)); 2032 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 2033 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 2034 Lod->getPointerInfo().getWithOffset(bestOffset), 2035 false, false, NewAlign); 2036 return DAG.getSetCC(dl, VT, 2037 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 2038 DAG.getConstant(bestMask.trunc(bestWidth), 2039 newVT)), 2040 DAG.getConstant(0LL, newVT), Cond); 2041 } 2042 } 2043 } 2044 2045 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2046 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2047 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 2048 2049 // If the comparison constant has bits in the upper part, the 2050 // zero-extended value could never match. 2051 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 2052 C1.getBitWidth() - InSize))) { 2053 switch (Cond) { 2054 case ISD::SETUGT: 2055 case ISD::SETUGE: 2056 case ISD::SETEQ: return DAG.getConstant(0, VT); 2057 case ISD::SETULT: 2058 case ISD::SETULE: 2059 case ISD::SETNE: return DAG.getConstant(1, VT); 2060 case ISD::SETGT: 2061 case ISD::SETGE: 2062 // True if the sign bit of C1 is set. 2063 return DAG.getConstant(C1.isNegative(), VT); 2064 case ISD::SETLT: 2065 case ISD::SETLE: 2066 // True if the sign bit of C1 isn't set. 2067 return DAG.getConstant(C1.isNonNegative(), VT); 2068 default: 2069 break; 2070 } 2071 } 2072 2073 // Otherwise, we can perform the comparison with the low bits. 2074 switch (Cond) { 2075 case ISD::SETEQ: 2076 case ISD::SETNE: 2077 case ISD::SETUGT: 2078 case ISD::SETUGE: 2079 case ISD::SETULT: 2080 case ISD::SETULE: { 2081 EVT newVT = N0.getOperand(0).getValueType(); 2082 if (DCI.isBeforeLegalizeOps() || 2083 (isOperationLegal(ISD::SETCC, newVT) && 2084 getCondCodeAction(Cond, newVT)==Legal)) 2085 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2086 DAG.getConstant(C1.trunc(InSize), newVT), 2087 Cond); 2088 break; 2089 } 2090 default: 2091 break; // todo, be more careful with signed comparisons 2092 } 2093 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2094 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2095 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2096 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 2097 EVT ExtDstTy = N0.getValueType(); 2098 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 2099 2100 // If the constant doesn't fit into the number of bits for the source of 2101 // the sign extension, it is impossible for both sides to be equal. 2102 if (C1.getMinSignedBits() > ExtSrcTyBits) 2103 return DAG.getConstant(Cond == ISD::SETNE, VT); 2104 2105 SDValue ZextOp; 2106 EVT Op0Ty = N0.getOperand(0).getValueType(); 2107 if (Op0Ty == ExtSrcTy) { 2108 ZextOp = N0.getOperand(0); 2109 } else { 2110 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 2111 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 2112 DAG.getConstant(Imm, Op0Ty)); 2113 } 2114 if (!DCI.isCalledByLegalizer()) 2115 DCI.AddToWorklist(ZextOp.getNode()); 2116 // Otherwise, make this a use of a zext. 2117 return DAG.getSetCC(dl, VT, ZextOp, 2118 DAG.getConstant(C1 & APInt::getLowBitsSet( 2119 ExtDstTyBits, 2120 ExtSrcTyBits), 2121 ExtDstTy), 2122 Cond); 2123 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 2124 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2125 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 2126 if (N0.getOpcode() == ISD::SETCC && 2127 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 2128 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 2129 if (TrueWhenTrue) 2130 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 2131 // Invert the condition. 2132 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 2133 CC = ISD::getSetCCInverse(CC, 2134 N0.getOperand(0).getValueType().isInteger()); 2135 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 2136 } 2137 2138 if ((N0.getOpcode() == ISD::XOR || 2139 (N0.getOpcode() == ISD::AND && 2140 N0.getOperand(0).getOpcode() == ISD::XOR && 2141 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 2142 isa<ConstantSDNode>(N0.getOperand(1)) && 2143 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 2144 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 2145 // can only do this if the top bits are known zero. 2146 unsigned BitWidth = N0.getValueSizeInBits(); 2147 if (DAG.MaskedValueIsZero(N0, 2148 APInt::getHighBitsSet(BitWidth, 2149 BitWidth-1))) { 2150 // Okay, get the un-inverted input value. 2151 SDValue Val; 2152 if (N0.getOpcode() == ISD::XOR) 2153 Val = N0.getOperand(0); 2154 else { 2155 assert(N0.getOpcode() == ISD::AND && 2156 N0.getOperand(0).getOpcode() == ISD::XOR); 2157 // ((X^1)&1)^1 -> X & 1 2158 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 2159 N0.getOperand(0).getOperand(0), 2160 N0.getOperand(1)); 2161 } 2162 2163 return DAG.getSetCC(dl, VT, Val, N1, 2164 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2165 } 2166 } else if (N1C->getAPIntValue() == 1 && 2167 (VT == MVT::i1 || 2168 getBooleanContents() == ZeroOrOneBooleanContent)) { 2169 SDValue Op0 = N0; 2170 if (Op0.getOpcode() == ISD::TRUNCATE) 2171 Op0 = Op0.getOperand(0); 2172 2173 if ((Op0.getOpcode() == ISD::XOR) && 2174 Op0.getOperand(0).getOpcode() == ISD::SETCC && 2175 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 2176 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 2177 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 2178 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 2179 Cond); 2180 } else if (Op0.getOpcode() == ISD::AND && 2181 isa<ConstantSDNode>(Op0.getOperand(1)) && 2182 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 2183 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 2184 if (Op0.getValueType().bitsGT(VT)) 2185 Op0 = DAG.getNode(ISD::AND, dl, VT, 2186 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 2187 DAG.getConstant(1, VT)); 2188 else if (Op0.getValueType().bitsLT(VT)) 2189 Op0 = DAG.getNode(ISD::AND, dl, VT, 2190 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 2191 DAG.getConstant(1, VT)); 2192 2193 return DAG.getSetCC(dl, VT, Op0, 2194 DAG.getConstant(0, Op0.getValueType()), 2195 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 2196 } 2197 } 2198 } 2199 2200 APInt MinVal, MaxVal; 2201 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 2202 if (ISD::isSignedIntSetCC(Cond)) { 2203 MinVal = APInt::getSignedMinValue(OperandBitSize); 2204 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 2205 } else { 2206 MinVal = APInt::getMinValue(OperandBitSize); 2207 MaxVal = APInt::getMaxValue(OperandBitSize); 2208 } 2209 2210 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2211 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2212 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2213 // X >= C0 --> X > (C0-1) 2214 return DAG.getSetCC(dl, VT, N0, 2215 DAG.getConstant(C1-1, N1.getValueType()), 2216 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2217 } 2218 2219 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2220 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2221 // X <= C0 --> X < (C0+1) 2222 return DAG.getSetCC(dl, VT, N0, 2223 DAG.getConstant(C1+1, N1.getValueType()), 2224 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2225 } 2226 2227 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2228 return DAG.getConstant(0, VT); // X < MIN --> false 2229 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2230 return DAG.getConstant(1, VT); // X >= MIN --> true 2231 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2232 return DAG.getConstant(0, VT); // X > MAX --> false 2233 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2234 return DAG.getConstant(1, VT); // X <= MAX --> true 2235 2236 // Canonicalize setgt X, Min --> setne X, Min 2237 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2238 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2239 // Canonicalize setlt X, Max --> setne X, Max 2240 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2241 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2242 2243 // If we have setult X, 1, turn it into seteq X, 0 2244 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2245 return DAG.getSetCC(dl, VT, N0, 2246 DAG.getConstant(MinVal, N0.getValueType()), 2247 ISD::SETEQ); 2248 // If we have setugt X, Max-1, turn it into seteq X, Max 2249 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2250 return DAG.getSetCC(dl, VT, N0, 2251 DAG.getConstant(MaxVal, N0.getValueType()), 2252 ISD::SETEQ); 2253 2254 // If we have "setcc X, C0", check to see if we can shrink the immediate 2255 // by changing cc. 2256 2257 // SETUGT X, SINTMAX -> SETLT X, 0 2258 if (Cond == ISD::SETUGT && 2259 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2260 return DAG.getSetCC(dl, VT, N0, 2261 DAG.getConstant(0, N1.getValueType()), 2262 ISD::SETLT); 2263 2264 // SETULT X, SINTMIN -> SETGT X, -1 2265 if (Cond == ISD::SETULT && 2266 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2267 SDValue ConstMinusOne = 2268 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2269 N1.getValueType()); 2270 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2271 } 2272 2273 // Fold bit comparisons when we can. 2274 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2275 (VT == N0.getValueType() || 2276 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2277 N0.getOpcode() == ISD::AND) 2278 if (ConstantSDNode *AndRHS = 2279 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2280 EVT ShiftTy = DCI.isBeforeLegalize() ? 2281 getPointerTy() : getShiftAmountTy(N0.getValueType()); 2282 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2283 // Perform the xform if the AND RHS is a single bit. 2284 if (AndRHS->getAPIntValue().isPowerOf2()) { 2285 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2286 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2287 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2288 } 2289 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2290 // (X & 8) == 8 --> (X & 8) >> 3 2291 // Perform the xform if C1 is a single bit. 2292 if (C1.isPowerOf2()) { 2293 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2294 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2295 DAG.getConstant(C1.logBase2(), ShiftTy))); 2296 } 2297 } 2298 } 2299 } 2300 2301 if (isa<ConstantFPSDNode>(N0.getNode())) { 2302 // Constant fold or commute setcc. 2303 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2304 if (O.getNode()) return O; 2305 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2306 // If the RHS of an FP comparison is a constant, simplify it away in 2307 // some cases. 2308 if (CFP->getValueAPF().isNaN()) { 2309 // If an operand is known to be a nan, we can fold it. 2310 switch (ISD::getUnorderedFlavor(Cond)) { 2311 default: llvm_unreachable("Unknown flavor!"); 2312 case 0: // Known false. 2313 return DAG.getConstant(0, VT); 2314 case 1: // Known true. 2315 return DAG.getConstant(1, VT); 2316 case 2: // Undefined. 2317 return DAG.getUNDEF(VT); 2318 } 2319 } 2320 2321 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2322 // constant if knowing that the operand is non-nan is enough. We prefer to 2323 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2324 // materialize 0.0. 2325 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2326 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2327 2328 // If the condition is not legal, see if we can find an equivalent one 2329 // which is legal. 2330 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2331 // If the comparison was an awkward floating-point == or != and one of 2332 // the comparison operands is infinity or negative infinity, convert the 2333 // condition to a less-awkward <= or >=. 2334 if (CFP->getValueAPF().isInfinity()) { 2335 if (CFP->getValueAPF().isNegative()) { 2336 if (Cond == ISD::SETOEQ && 2337 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2338 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2339 if (Cond == ISD::SETUEQ && 2340 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2341 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2342 if (Cond == ISD::SETUNE && 2343 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2344 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2345 if (Cond == ISD::SETONE && 2346 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2347 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2348 } else { 2349 if (Cond == ISD::SETOEQ && 2350 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2351 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2352 if (Cond == ISD::SETUEQ && 2353 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2354 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2355 if (Cond == ISD::SETUNE && 2356 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2357 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2358 if (Cond == ISD::SETONE && 2359 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2360 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2361 } 2362 } 2363 } 2364 } 2365 2366 if (N0 == N1) { 2367 // We can always fold X == X for integer setcc's. 2368 if (N0.getValueType().isInteger()) 2369 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2370 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2371 if (UOF == 2) // FP operators that are undefined on NaNs. 2372 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2373 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2374 return DAG.getConstant(UOF, VT); 2375 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2376 // if it is not already. 2377 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2378 if (NewCond != Cond) 2379 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2380 } 2381 2382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2383 N0.getValueType().isInteger()) { 2384 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2385 N0.getOpcode() == ISD::XOR) { 2386 // Simplify (X+Y) == (X+Z) --> Y == Z 2387 if (N0.getOpcode() == N1.getOpcode()) { 2388 if (N0.getOperand(0) == N1.getOperand(0)) 2389 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2390 if (N0.getOperand(1) == N1.getOperand(1)) 2391 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2392 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2393 // If X op Y == Y op X, try other combinations. 2394 if (N0.getOperand(0) == N1.getOperand(1)) 2395 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2396 Cond); 2397 if (N0.getOperand(1) == N1.getOperand(0)) 2398 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2399 Cond); 2400 } 2401 } 2402 2403 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2404 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2405 // Turn (X+C1) == C2 --> X == C2-C1 2406 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2407 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2408 DAG.getConstant(RHSC->getAPIntValue()- 2409 LHSR->getAPIntValue(), 2410 N0.getValueType()), Cond); 2411 } 2412 2413 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2414 if (N0.getOpcode() == ISD::XOR) 2415 // If we know that all of the inverted bits are zero, don't bother 2416 // performing the inversion. 2417 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2418 return 2419 DAG.getSetCC(dl, VT, N0.getOperand(0), 2420 DAG.getConstant(LHSR->getAPIntValue() ^ 2421 RHSC->getAPIntValue(), 2422 N0.getValueType()), 2423 Cond); 2424 } 2425 2426 // Turn (C1-X) == C2 --> X == C1-C2 2427 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2428 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2429 return 2430 DAG.getSetCC(dl, VT, N0.getOperand(1), 2431 DAG.getConstant(SUBC->getAPIntValue() - 2432 RHSC->getAPIntValue(), 2433 N0.getValueType()), 2434 Cond); 2435 } 2436 } 2437 } 2438 2439 // Simplify (X+Z) == X --> Z == 0 2440 if (N0.getOperand(0) == N1) 2441 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2442 DAG.getConstant(0, N0.getValueType()), Cond); 2443 if (N0.getOperand(1) == N1) { 2444 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2445 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2446 DAG.getConstant(0, N0.getValueType()), Cond); 2447 else if (N0.getNode()->hasOneUse()) { 2448 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2449 // (Z-X) == X --> Z == X<<1 2450 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2451 N1, 2452 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 2453 if (!DCI.isCalledByLegalizer()) 2454 DCI.AddToWorklist(SH.getNode()); 2455 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2456 } 2457 } 2458 } 2459 2460 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2461 N1.getOpcode() == ISD::XOR) { 2462 // Simplify X == (X+Z) --> Z == 0 2463 if (N1.getOperand(0) == N0) { 2464 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2465 DAG.getConstant(0, N1.getValueType()), Cond); 2466 } else if (N1.getOperand(1) == N0) { 2467 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2468 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2469 DAG.getConstant(0, N1.getValueType()), Cond); 2470 } else if (N1.getNode()->hasOneUse()) { 2471 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2472 // X == (Z-X) --> X<<1 == Z 2473 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2474 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 2475 if (!DCI.isCalledByLegalizer()) 2476 DCI.AddToWorklist(SH.getNode()); 2477 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2478 } 2479 } 2480 } 2481 2482 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2483 // Note that where y is variable and is known to have at most 2484 // one bit set (for example, if it is z&1) we cannot do this; 2485 // the expressions are not equivalent when y==0. 2486 if (N0.getOpcode() == ISD::AND) 2487 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2488 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2489 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2490 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2491 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2492 } 2493 } 2494 if (N1.getOpcode() == ISD::AND) 2495 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2496 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2497 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2498 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2499 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2500 } 2501 } 2502 } 2503 2504 // Fold away ALL boolean setcc's. 2505 SDValue Temp; 2506 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2507 switch (Cond) { 2508 default: llvm_unreachable("Unknown integer setcc!"); 2509 case ISD::SETEQ: // X == Y -> ~(X^Y) 2510 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2511 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2512 if (!DCI.isCalledByLegalizer()) 2513 DCI.AddToWorklist(Temp.getNode()); 2514 break; 2515 case ISD::SETNE: // X != Y --> (X^Y) 2516 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2517 break; 2518 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2519 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2520 Temp = DAG.getNOT(dl, N0, MVT::i1); 2521 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2522 if (!DCI.isCalledByLegalizer()) 2523 DCI.AddToWorklist(Temp.getNode()); 2524 break; 2525 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2526 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2527 Temp = DAG.getNOT(dl, N1, MVT::i1); 2528 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2529 if (!DCI.isCalledByLegalizer()) 2530 DCI.AddToWorklist(Temp.getNode()); 2531 break; 2532 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2533 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2534 Temp = DAG.getNOT(dl, N0, MVT::i1); 2535 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2536 if (!DCI.isCalledByLegalizer()) 2537 DCI.AddToWorklist(Temp.getNode()); 2538 break; 2539 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2540 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2541 Temp = DAG.getNOT(dl, N1, MVT::i1); 2542 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2543 break; 2544 } 2545 if (VT != MVT::i1) { 2546 if (!DCI.isCalledByLegalizer()) 2547 DCI.AddToWorklist(N0.getNode()); 2548 // FIXME: If running after legalize, we probably can't do this. 2549 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2550 } 2551 return N0; 2552 } 2553 2554 // Could not fold it. 2555 return SDValue(); 2556} 2557 2558/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2559/// node is a GlobalAddress + offset. 2560bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 2561 int64_t &Offset) const { 2562 if (isa<GlobalAddressSDNode>(N)) { 2563 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2564 GA = GASD->getGlobal(); 2565 Offset += GASD->getOffset(); 2566 return true; 2567 } 2568 2569 if (N->getOpcode() == ISD::ADD) { 2570 SDValue N1 = N->getOperand(0); 2571 SDValue N2 = N->getOperand(1); 2572 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2573 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2574 if (V) { 2575 Offset += V->getSExtValue(); 2576 return true; 2577 } 2578 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2579 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2580 if (V) { 2581 Offset += V->getSExtValue(); 2582 return true; 2583 } 2584 } 2585 } 2586 2587 return false; 2588} 2589 2590 2591SDValue TargetLowering:: 2592PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2593 // Default implementation: no optimization. 2594 return SDValue(); 2595} 2596 2597//===----------------------------------------------------------------------===// 2598// Inline Assembler Implementation Methods 2599//===----------------------------------------------------------------------===// 2600 2601 2602TargetLowering::ConstraintType 2603TargetLowering::getConstraintType(const std::string &Constraint) const { 2604 // FIXME: lots more standard ones to handle. 2605 if (Constraint.size() == 1) { 2606 switch (Constraint[0]) { 2607 default: break; 2608 case 'r': return C_RegisterClass; 2609 case 'm': // memory 2610 case 'o': // offsetable 2611 case 'V': // not offsetable 2612 return C_Memory; 2613 case 'i': // Simple Integer or Relocatable Constant 2614 case 'n': // Simple Integer 2615 case 'E': // Floating Point Constant 2616 case 'F': // Floating Point Constant 2617 case 's': // Relocatable Constant 2618 case 'p': // Address. 2619 case 'X': // Allow ANY value. 2620 case 'I': // Target registers. 2621 case 'J': 2622 case 'K': 2623 case 'L': 2624 case 'M': 2625 case 'N': 2626 case 'O': 2627 case 'P': 2628 case '<': 2629 case '>': 2630 return C_Other; 2631 } 2632 } 2633 2634 if (Constraint.size() > 1 && Constraint[0] == '{' && 2635 Constraint[Constraint.size()-1] == '}') 2636 return C_Register; 2637 return C_Unknown; 2638} 2639 2640/// LowerXConstraint - try to replace an X constraint, which matches anything, 2641/// with another that has more specific requirements based on the type of the 2642/// corresponding operand. 2643const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2644 if (ConstraintVT.isInteger()) 2645 return "r"; 2646 if (ConstraintVT.isFloatingPoint()) 2647 return "f"; // works for many targets 2648 return 0; 2649} 2650 2651/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2652/// vector. If it is invalid, don't add anything to Ops. 2653void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2654 char ConstraintLetter, 2655 std::vector<SDValue> &Ops, 2656 SelectionDAG &DAG) const { 2657 switch (ConstraintLetter) { 2658 default: break; 2659 case 'X': // Allows any operand; labels (basic block) use this. 2660 if (Op.getOpcode() == ISD::BasicBlock) { 2661 Ops.push_back(Op); 2662 return; 2663 } 2664 // fall through 2665 case 'i': // Simple Integer or Relocatable Constant 2666 case 'n': // Simple Integer 2667 case 's': { // Relocatable Constant 2668 // These operands are interested in values of the form (GV+C), where C may 2669 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2670 // is possible and fine if either GV or C are missing. 2671 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2672 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2673 2674 // If we have "(add GV, C)", pull out GV/C 2675 if (Op.getOpcode() == ISD::ADD) { 2676 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2677 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2678 if (C == 0 || GA == 0) { 2679 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2680 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2681 } 2682 if (C == 0 || GA == 0) 2683 C = 0, GA = 0; 2684 } 2685 2686 // If we find a valid operand, map to the TargetXXX version so that the 2687 // value itself doesn't get selected. 2688 if (GA) { // Either &GV or &GV+C 2689 if (ConstraintLetter != 'n') { 2690 int64_t Offs = GA->getOffset(); 2691 if (C) Offs += C->getZExtValue(); 2692 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2693 C ? C->getDebugLoc() : DebugLoc(), 2694 Op.getValueType(), Offs)); 2695 return; 2696 } 2697 } 2698 if (C) { // just C, no GV. 2699 // Simple constants are not allowed for 's'. 2700 if (ConstraintLetter != 's') { 2701 // gcc prints these as sign extended. Sign extend value to 64 bits 2702 // now; without this it would get ZExt'd later in 2703 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2704 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2705 MVT::i64)); 2706 return; 2707 } 2708 } 2709 break; 2710 } 2711 } 2712} 2713 2714std::vector<unsigned> TargetLowering:: 2715getRegClassForInlineAsmConstraint(const std::string &Constraint, 2716 EVT VT) const { 2717 return std::vector<unsigned>(); 2718} 2719 2720 2721std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2722getRegForInlineAsmConstraint(const std::string &Constraint, 2723 EVT VT) const { 2724 if (Constraint[0] != '{') 2725 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2726 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2727 2728 // Remove the braces from around the name. 2729 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2730 2731 // Figure out which register class contains this reg. 2732 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2733 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2734 E = RI->regclass_end(); RCI != E; ++RCI) { 2735 const TargetRegisterClass *RC = *RCI; 2736 2737 // If none of the value types for this register class are valid, we 2738 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2739 bool isLegal = false; 2740 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2741 I != E; ++I) { 2742 if (isTypeLegal(*I)) { 2743 isLegal = true; 2744 break; 2745 } 2746 } 2747 2748 if (!isLegal) continue; 2749 2750 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2751 I != E; ++I) { 2752 if (RegName.equals_lower(RI->getName(*I))) 2753 return std::make_pair(*I, RC); 2754 } 2755 } 2756 2757 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2758} 2759 2760//===----------------------------------------------------------------------===// 2761// Constraint Selection. 2762 2763/// isMatchingInputConstraint - Return true of this is an input operand that is 2764/// a matching constraint like "4". 2765bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2766 assert(!ConstraintCode.empty() && "No known constraint!"); 2767 return isdigit(ConstraintCode[0]); 2768} 2769 2770/// getMatchedOperand - If this is an input matching constraint, this method 2771/// returns the output operand it matches. 2772unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2773 assert(!ConstraintCode.empty() && "No known constraint!"); 2774 return atoi(ConstraintCode.c_str()); 2775} 2776 2777 2778/// ParseConstraints - Split up the constraint string from the inline 2779/// assembly value into the specific constraints and their prefixes, 2780/// and also tie in the associated operand values. 2781/// If this returns an empty vector, and if the constraint string itself 2782/// isn't empty, there was an error parsing. 2783TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2784 ImmutableCallSite CS) const { 2785 /// ConstraintOperands - Information about all of the constraints. 2786 AsmOperandInfoVector ConstraintOperands; 2787 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2788 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2789 2790 // Do a prepass over the constraints, canonicalizing them, and building up the 2791 // ConstraintOperands list. 2792 InlineAsm::ConstraintInfoVector 2793 ConstraintInfos = IA->ParseConstraints(); 2794 2795 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2796 unsigned ResNo = 0; // ResNo - The result number of the next output. 2797 2798 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2799 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2800 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2801 2802 // Update multiple alternative constraint count. 2803 if (OpInfo.multipleAlternatives.size() > maCount) 2804 maCount = OpInfo.multipleAlternatives.size(); 2805 2806 OpInfo.ConstraintVT = MVT::Other; 2807 2808 // Compute the value type for each operand. 2809 switch (OpInfo.Type) { 2810 case InlineAsm::isOutput: 2811 // Indirect outputs just consume an argument. 2812 if (OpInfo.isIndirect) { 2813 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2814 break; 2815 } 2816 2817 // The return value of the call is this value. As such, there is no 2818 // corresponding argument. 2819 assert(!CS.getType()->isVoidTy() && 2820 "Bad inline asm!"); 2821 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 2822 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo)); 2823 } else { 2824 assert(ResNo == 0 && "Asm only has one result!"); 2825 OpInfo.ConstraintVT = getValueType(CS.getType()); 2826 } 2827 ++ResNo; 2828 break; 2829 case InlineAsm::isInput: 2830 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2831 break; 2832 case InlineAsm::isClobber: 2833 // Nothing to do. 2834 break; 2835 } 2836 2837 if (OpInfo.CallOperandVal) { 2838 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2839 if (OpInfo.isIndirect) { 2840 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2841 if (!PtrTy) 2842 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2843 OpTy = PtrTy->getElementType(); 2844 } 2845 2846 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2847 if (const StructType *STy = dyn_cast<StructType>(OpTy)) 2848 if (STy->getNumElements() == 1) 2849 OpTy = STy->getElementType(0); 2850 2851 // If OpTy is not a single value, it may be a struct/union that we 2852 // can tile with integers. 2853 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2854 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 2855 switch (BitSize) { 2856 default: break; 2857 case 1: 2858 case 8: 2859 case 16: 2860 case 32: 2861 case 64: 2862 case 128: 2863 OpInfo.ConstraintVT = 2864 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2865 break; 2866 } 2867 } else if (dyn_cast<PointerType>(OpTy)) { 2868 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize()); 2869 } else { 2870 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true); 2871 } 2872 } 2873 } 2874 2875 // If we have multiple alternative constraints, select the best alternative. 2876 if (ConstraintInfos.size()) { 2877 if (maCount) { 2878 unsigned bestMAIndex = 0; 2879 int bestWeight = -1; 2880 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2881 int weight = -1; 2882 unsigned maIndex; 2883 // Compute the sums of the weights for each alternative, keeping track 2884 // of the best (highest weight) one so far. 2885 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2886 int weightSum = 0; 2887 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2888 cIndex != eIndex; ++cIndex) { 2889 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2890 if (OpInfo.Type == InlineAsm::isClobber) 2891 continue; 2892 2893 // If this is an output operand with a matching input operand, 2894 // look up the matching input. If their types mismatch, e.g. one 2895 // is an integer, the other is floating point, or their sizes are 2896 // different, flag it as an maCantMatch. 2897 if (OpInfo.hasMatchingInput()) { 2898 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2899 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2900 if ((OpInfo.ConstraintVT.isInteger() != 2901 Input.ConstraintVT.isInteger()) || 2902 (OpInfo.ConstraintVT.getSizeInBits() != 2903 Input.ConstraintVT.getSizeInBits())) { 2904 weightSum = -1; // Can't match. 2905 break; 2906 } 2907 } 2908 } 2909 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2910 if (weight == -1) { 2911 weightSum = -1; 2912 break; 2913 } 2914 weightSum += weight; 2915 } 2916 // Update best. 2917 if (weightSum > bestWeight) { 2918 bestWeight = weightSum; 2919 bestMAIndex = maIndex; 2920 } 2921 } 2922 2923 // Now select chosen alternative in each constraint. 2924 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2925 cIndex != eIndex; ++cIndex) { 2926 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2927 if (cInfo.Type == InlineAsm::isClobber) 2928 continue; 2929 cInfo.selectAlternative(bestMAIndex); 2930 } 2931 } 2932 } 2933 2934 // Check and hook up tied operands, choose constraint code to use. 2935 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2936 cIndex != eIndex; ++cIndex) { 2937 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2938 2939 // If this is an output operand with a matching input operand, look up the 2940 // matching input. If their types mismatch, e.g. one is an integer, the 2941 // other is floating point, or their sizes are different, flag it as an 2942 // error. 2943 if (OpInfo.hasMatchingInput()) { 2944 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2945 2946 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2947 if ((OpInfo.ConstraintVT.isInteger() != 2948 Input.ConstraintVT.isInteger()) || 2949 (OpInfo.ConstraintVT.getSizeInBits() != 2950 Input.ConstraintVT.getSizeInBits())) { 2951 report_fatal_error("Unsupported asm: input constraint" 2952 " with a matching output constraint of" 2953 " incompatible type!"); 2954 } 2955 } 2956 2957 } 2958 } 2959 2960 return ConstraintOperands; 2961} 2962 2963 2964/// getConstraintGenerality - Return an integer indicating how general CT 2965/// is. 2966static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2967 switch (CT) { 2968 default: llvm_unreachable("Unknown constraint type!"); 2969 case TargetLowering::C_Other: 2970 case TargetLowering::C_Unknown: 2971 return 0; 2972 case TargetLowering::C_Register: 2973 return 1; 2974 case TargetLowering::C_RegisterClass: 2975 return 2; 2976 case TargetLowering::C_Memory: 2977 return 3; 2978 } 2979} 2980 2981/// Examine constraint type and operand type and determine a weight value. 2982/// This object must already have been set up with the operand type 2983/// and the current alternative constraint selected. 2984TargetLowering::ConstraintWeight 2985 TargetLowering::getMultipleConstraintMatchWeight( 2986 AsmOperandInfo &info, int maIndex) const { 2987 InlineAsm::ConstraintCodeVector *rCodes; 2988 if (maIndex >= (int)info.multipleAlternatives.size()) 2989 rCodes = &info.Codes; 2990 else 2991 rCodes = &info.multipleAlternatives[maIndex].Codes; 2992 ConstraintWeight BestWeight = CW_Invalid; 2993 2994 // Loop over the options, keeping track of the most general one. 2995 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2996 ConstraintWeight weight = 2997 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2998 if (weight > BestWeight) 2999 BestWeight = weight; 3000 } 3001 3002 return BestWeight; 3003} 3004 3005/// Examine constraint type and operand type and determine a weight value. 3006/// This object must already have been set up with the operand type 3007/// and the current alternative constraint selected. 3008TargetLowering::ConstraintWeight 3009 TargetLowering::getSingleConstraintMatchWeight( 3010 AsmOperandInfo &info, const char *constraint) const { 3011 ConstraintWeight weight = CW_Invalid; 3012 Value *CallOperandVal = info.CallOperandVal; 3013 // If we don't have a value, we can't do a match, 3014 // but allow it at the lowest weight. 3015 if (CallOperandVal == NULL) 3016 return CW_Default; 3017 // Look at the constraint type. 3018 switch (*constraint) { 3019 case 'i': // immediate integer. 3020 case 'n': // immediate integer with a known value. 3021 if (isa<ConstantInt>(CallOperandVal)) 3022 weight = CW_Constant; 3023 break; 3024 case 's': // non-explicit intregal immediate. 3025 if (isa<GlobalValue>(CallOperandVal)) 3026 weight = CW_Constant; 3027 break; 3028 case 'E': // immediate float if host format. 3029 case 'F': // immediate float. 3030 if (isa<ConstantFP>(CallOperandVal)) 3031 weight = CW_Constant; 3032 break; 3033 case '<': // memory operand with autodecrement. 3034 case '>': // memory operand with autoincrement. 3035 case 'm': // memory operand. 3036 case 'o': // offsettable memory operand 3037 case 'V': // non-offsettable memory operand 3038 weight = CW_Memory; 3039 break; 3040 case 'r': // general register. 3041 case 'g': // general register, memory operand or immediate integer. 3042 // note: Clang converts "g" to "imr". 3043 if (CallOperandVal->getType()->isIntegerTy()) 3044 weight = CW_Register; 3045 break; 3046 case 'X': // any operand. 3047 default: 3048 weight = CW_Default; 3049 break; 3050 } 3051 return weight; 3052} 3053 3054/// ChooseConstraint - If there are multiple different constraints that we 3055/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 3056/// This is somewhat tricky: constraints fall into four classes: 3057/// Other -> immediates and magic values 3058/// Register -> one specific register 3059/// RegisterClass -> a group of regs 3060/// Memory -> memory 3061/// Ideally, we would pick the most specific constraint possible: if we have 3062/// something that fits into a register, we would pick it. The problem here 3063/// is that if we have something that could either be in a register or in 3064/// memory that use of the register could cause selection of *other* 3065/// operands to fail: they might only succeed if we pick memory. Because of 3066/// this the heuristic we use is: 3067/// 3068/// 1) If there is an 'other' constraint, and if the operand is valid for 3069/// that constraint, use it. This makes us take advantage of 'i' 3070/// constraints when available. 3071/// 2) Otherwise, pick the most general constraint present. This prefers 3072/// 'm' over 'r', for example. 3073/// 3074static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 3075 const TargetLowering &TLI, 3076 SDValue Op, SelectionDAG *DAG) { 3077 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 3078 unsigned BestIdx = 0; 3079 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 3080 int BestGenerality = -1; 3081 3082 // Loop over the options, keeping track of the most general one. 3083 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 3084 TargetLowering::ConstraintType CType = 3085 TLI.getConstraintType(OpInfo.Codes[i]); 3086 3087 // If this is an 'other' constraint, see if the operand is valid for it. 3088 // For example, on X86 we might have an 'rI' constraint. If the operand 3089 // is an integer in the range [0..31] we want to use I (saving a load 3090 // of a register), otherwise we must use 'r'. 3091 if (CType == TargetLowering::C_Other && Op.getNode()) { 3092 assert(OpInfo.Codes[i].size() == 1 && 3093 "Unhandled multi-letter 'other' constraint"); 3094 std::vector<SDValue> ResultOps; 3095 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 3096 ResultOps, *DAG); 3097 if (!ResultOps.empty()) { 3098 BestType = CType; 3099 BestIdx = i; 3100 break; 3101 } 3102 } 3103 3104 // Things with matching constraints can only be registers, per gcc 3105 // documentation. This mainly affects "g" constraints. 3106 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 3107 continue; 3108 3109 // This constraint letter is more general than the previous one, use it. 3110 int Generality = getConstraintGenerality(CType); 3111 if (Generality > BestGenerality) { 3112 BestType = CType; 3113 BestIdx = i; 3114 BestGenerality = Generality; 3115 } 3116 } 3117 3118 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 3119 OpInfo.ConstraintType = BestType; 3120} 3121 3122/// ComputeConstraintToUse - Determines the constraint code and constraint 3123/// type to use for the specific AsmOperandInfo, setting 3124/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 3125void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 3126 SDValue Op, 3127 SelectionDAG *DAG) const { 3128 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 3129 3130 // Single-letter constraints ('r') are very common. 3131 if (OpInfo.Codes.size() == 1) { 3132 OpInfo.ConstraintCode = OpInfo.Codes[0]; 3133 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3134 } else { 3135 ChooseConstraint(OpInfo, *this, Op, DAG); 3136 } 3137 3138 // 'X' matches anything. 3139 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 3140 // Labels and constants are handled elsewhere ('X' is the only thing 3141 // that matches labels). For Functions, the type here is the type of 3142 // the result, which is not what we want to look at; leave them alone. 3143 Value *v = OpInfo.CallOperandVal; 3144 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 3145 OpInfo.CallOperandVal = v; 3146 return; 3147 } 3148 3149 // Otherwise, try to resolve it to something we know about by looking at 3150 // the actual operand type. 3151 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 3152 OpInfo.ConstraintCode = Repl; 3153 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 3154 } 3155 } 3156} 3157 3158//===----------------------------------------------------------------------===// 3159// Loop Strength Reduction hooks 3160//===----------------------------------------------------------------------===// 3161 3162/// isLegalAddressingMode - Return true if the addressing mode represented 3163/// by AM is legal for this target, for a load/store of the specified type. 3164bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 3165 const Type *Ty) const { 3166 // The default implementation of this implements a conservative RISCy, r+r and 3167 // r+i addr mode. 3168 3169 // Allows a sign-extended 16-bit immediate field. 3170 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3171 return false; 3172 3173 // No global is ever allowed as a base. 3174 if (AM.BaseGV) 3175 return false; 3176 3177 // Only support r+r, 3178 switch (AM.Scale) { 3179 case 0: // "r+i" or just "i", depending on HasBaseReg. 3180 break; 3181 case 1: 3182 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3183 return false; 3184 // Otherwise we have r+r or r+i. 3185 break; 3186 case 2: 3187 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3188 return false; 3189 // Allow 2*r as r+r. 3190 break; 3191 } 3192 3193 return true; 3194} 3195 3196/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3197/// return a DAG expression to select that will generate the same value by 3198/// multiplying by a magic number. See: 3199/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3200SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 3201 std::vector<SDNode*>* Created) const { 3202 EVT VT = N->getValueType(0); 3203 DebugLoc dl= N->getDebugLoc(); 3204 3205 // Check to see if we can do this. 3206 // FIXME: We should be more aggressive here. 3207 if (!isTypeLegal(VT)) 3208 return SDValue(); 3209 3210 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3211 APInt::ms magics = d.magic(); 3212 3213 // Multiply the numerator (operand 0) by the magic value 3214 // FIXME: We should support doing a MUL in a wider type 3215 SDValue Q; 3216 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 3217 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 3218 DAG.getConstant(magics.m, VT)); 3219 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 3220 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 3221 N->getOperand(0), 3222 DAG.getConstant(magics.m, VT)).getNode(), 1); 3223 else 3224 return SDValue(); // No mulhs or equvialent 3225 // If d > 0 and m < 0, add the numerator 3226 if (d.isStrictlyPositive() && magics.m.isNegative()) { 3227 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 3228 if (Created) 3229 Created->push_back(Q.getNode()); 3230 } 3231 // If d < 0 and m > 0, subtract the numerator. 3232 if (d.isNegative() && magics.m.isStrictlyPositive()) { 3233 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3234 if (Created) 3235 Created->push_back(Q.getNode()); 3236 } 3237 // Shift right algebraic if shift value is nonzero 3238 if (magics.s > 0) { 3239 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 3240 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3241 if (Created) 3242 Created->push_back(Q.getNode()); 3243 } 3244 // Extract the sign bit and add it to the quotient 3245 SDValue T = 3246 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 3247 getShiftAmountTy(Q.getValueType()))); 3248 if (Created) 3249 Created->push_back(T.getNode()); 3250 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 3251} 3252 3253/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3254/// return a DAG expression to select that will generate the same value by 3255/// multiplying by a magic number. See: 3256/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3257SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 3258 std::vector<SDNode*>* Created) const { 3259 EVT VT = N->getValueType(0); 3260 DebugLoc dl = N->getDebugLoc(); 3261 3262 // Check to see if we can do this. 3263 // FIXME: We should be more aggressive here. 3264 if (!isTypeLegal(VT)) 3265 return SDValue(); 3266 3267 // FIXME: We should use a narrower constant when the upper 3268 // bits are known to be zero. 3269 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 3270 APInt::mu magics = N1C.magicu(); 3271 3272 SDValue Q = N->getOperand(0); 3273 3274 // If the divisor is even, we can avoid using the expensive fixup by shifting 3275 // the divided value upfront. 3276 if (magics.a != 0 && !N1C[0]) { 3277 unsigned Shift = N1C.countTrailingZeros(); 3278 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 3279 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 3280 if (Created) 3281 Created->push_back(Q.getNode()); 3282 3283 // Get magic number for the shifted divisor. 3284 magics = N1C.lshr(Shift).magicu(Shift); 3285 assert(magics.a == 0 && "Should use cheap fixup now"); 3286 } 3287 3288 // Multiply the numerator (operand 0) by the magic value 3289 // FIXME: We should support doing a MUL in a wider type 3290 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 3291 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 3292 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 3293 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 3294 DAG.getConstant(magics.m, VT)).getNode(), 1); 3295 else 3296 return SDValue(); // No mulhu or equvialent 3297 if (Created) 3298 Created->push_back(Q.getNode()); 3299 3300 if (magics.a == 0) { 3301 assert(magics.s < N1C.getBitWidth() && 3302 "We shouldn't generate an undefined shift!"); 3303 return DAG.getNode(ISD::SRL, dl, VT, Q, 3304 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 3305 } else { 3306 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3307 if (Created) 3308 Created->push_back(NPQ.getNode()); 3309 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 3310 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 3311 if (Created) 3312 Created->push_back(NPQ.getNode()); 3313 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 3314 if (Created) 3315 Created->push_back(NPQ.getNode()); 3316 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 3317 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 3318 } 3319} 3320