TargetLowering.cpp revision f0144127b98425d214e59e4a1a4b342b78e3642b
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/Target/TargetAsmInfo.h" 16#include "llvm/Target/TargetData.h" 17#include "llvm/Target/TargetLoweringObjectFile.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "llvm/Target/TargetSubtarget.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/ADT/StringExtras.h" 26#include "llvm/ADT/STLExtras.h" 27#include "llvm/Support/ErrorHandling.h" 28#include "llvm/Support/MathExtras.h" 29using namespace llvm; 30 31namespace llvm { 32TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 33 bool isLocal = GV->hasLocalLinkage(); 34 bool isDeclaration = GV->isDeclaration(); 35 // FIXME: what should we do for protected and internal visibility? 36 // For variables, is internal different from hidden? 37 bool isHidden = GV->hasHiddenVisibility(); 38 39 if (reloc == Reloc::PIC_) { 40 if (isLocal || isHidden) 41 return TLSModel::LocalDynamic; 42 else 43 return TLSModel::GeneralDynamic; 44 } else { 45 if (!isDeclaration || isHidden) 46 return TLSModel::LocalExec; 47 else 48 return TLSModel::InitialExec; 49 } 50} 51} 52 53/// InitLibcallNames - Set default libcall names. 54/// 55static void InitLibcallNames(const char **Names) { 56 Names[RTLIB::SHL_I16] = "__ashlhi3"; 57 Names[RTLIB::SHL_I32] = "__ashlsi3"; 58 Names[RTLIB::SHL_I64] = "__ashldi3"; 59 Names[RTLIB::SHL_I128] = "__ashlti3"; 60 Names[RTLIB::SRL_I16] = "__lshrhi3"; 61 Names[RTLIB::SRL_I32] = "__lshrsi3"; 62 Names[RTLIB::SRL_I64] = "__lshrdi3"; 63 Names[RTLIB::SRL_I128] = "__lshrti3"; 64 Names[RTLIB::SRA_I16] = "__ashrhi3"; 65 Names[RTLIB::SRA_I32] = "__ashrsi3"; 66 Names[RTLIB::SRA_I64] = "__ashrdi3"; 67 Names[RTLIB::SRA_I128] = "__ashrti3"; 68 Names[RTLIB::MUL_I16] = "__mulhi3"; 69 Names[RTLIB::MUL_I32] = "__mulsi3"; 70 Names[RTLIB::MUL_I64] = "__muldi3"; 71 Names[RTLIB::MUL_I128] = "__multi3"; 72 Names[RTLIB::SDIV_I16] = "__divhi3"; 73 Names[RTLIB::SDIV_I32] = "__divsi3"; 74 Names[RTLIB::SDIV_I64] = "__divdi3"; 75 Names[RTLIB::SDIV_I128] = "__divti3"; 76 Names[RTLIB::UDIV_I16] = "__udivhi3"; 77 Names[RTLIB::UDIV_I32] = "__udivsi3"; 78 Names[RTLIB::UDIV_I64] = "__udivdi3"; 79 Names[RTLIB::UDIV_I128] = "__udivti3"; 80 Names[RTLIB::SREM_I16] = "__modhi3"; 81 Names[RTLIB::SREM_I32] = "__modsi3"; 82 Names[RTLIB::SREM_I64] = "__moddi3"; 83 Names[RTLIB::SREM_I128] = "__modti3"; 84 Names[RTLIB::UREM_I16] = "__umodhi3"; 85 Names[RTLIB::UREM_I32] = "__umodsi3"; 86 Names[RTLIB::UREM_I64] = "__umoddi3"; 87 Names[RTLIB::UREM_I128] = "__umodti3"; 88 Names[RTLIB::NEG_I32] = "__negsi2"; 89 Names[RTLIB::NEG_I64] = "__negdi2"; 90 Names[RTLIB::ADD_F32] = "__addsf3"; 91 Names[RTLIB::ADD_F64] = "__adddf3"; 92 Names[RTLIB::ADD_F80] = "__addxf3"; 93 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 94 Names[RTLIB::SUB_F32] = "__subsf3"; 95 Names[RTLIB::SUB_F64] = "__subdf3"; 96 Names[RTLIB::SUB_F80] = "__subxf3"; 97 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 98 Names[RTLIB::MUL_F32] = "__mulsf3"; 99 Names[RTLIB::MUL_F64] = "__muldf3"; 100 Names[RTLIB::MUL_F80] = "__mulxf3"; 101 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 102 Names[RTLIB::DIV_F32] = "__divsf3"; 103 Names[RTLIB::DIV_F64] = "__divdf3"; 104 Names[RTLIB::DIV_F80] = "__divxf3"; 105 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 106 Names[RTLIB::REM_F32] = "fmodf"; 107 Names[RTLIB::REM_F64] = "fmod"; 108 Names[RTLIB::REM_F80] = "fmodl"; 109 Names[RTLIB::REM_PPCF128] = "fmodl"; 110 Names[RTLIB::POWI_F32] = "__powisf2"; 111 Names[RTLIB::POWI_F64] = "__powidf2"; 112 Names[RTLIB::POWI_F80] = "__powixf2"; 113 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 114 Names[RTLIB::SQRT_F32] = "sqrtf"; 115 Names[RTLIB::SQRT_F64] = "sqrt"; 116 Names[RTLIB::SQRT_F80] = "sqrtl"; 117 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 118 Names[RTLIB::LOG_F32] = "logf"; 119 Names[RTLIB::LOG_F64] = "log"; 120 Names[RTLIB::LOG_F80] = "logl"; 121 Names[RTLIB::LOG_PPCF128] = "logl"; 122 Names[RTLIB::LOG2_F32] = "log2f"; 123 Names[RTLIB::LOG2_F64] = "log2"; 124 Names[RTLIB::LOG2_F80] = "log2l"; 125 Names[RTLIB::LOG2_PPCF128] = "log2l"; 126 Names[RTLIB::LOG10_F32] = "log10f"; 127 Names[RTLIB::LOG10_F64] = "log10"; 128 Names[RTLIB::LOG10_F80] = "log10l"; 129 Names[RTLIB::LOG10_PPCF128] = "log10l"; 130 Names[RTLIB::EXP_F32] = "expf"; 131 Names[RTLIB::EXP_F64] = "exp"; 132 Names[RTLIB::EXP_F80] = "expl"; 133 Names[RTLIB::EXP_PPCF128] = "expl"; 134 Names[RTLIB::EXP2_F32] = "exp2f"; 135 Names[RTLIB::EXP2_F64] = "exp2"; 136 Names[RTLIB::EXP2_F80] = "exp2l"; 137 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 138 Names[RTLIB::SIN_F32] = "sinf"; 139 Names[RTLIB::SIN_F64] = "sin"; 140 Names[RTLIB::SIN_F80] = "sinl"; 141 Names[RTLIB::SIN_PPCF128] = "sinl"; 142 Names[RTLIB::COS_F32] = "cosf"; 143 Names[RTLIB::COS_F64] = "cos"; 144 Names[RTLIB::COS_F80] = "cosl"; 145 Names[RTLIB::COS_PPCF128] = "cosl"; 146 Names[RTLIB::POW_F32] = "powf"; 147 Names[RTLIB::POW_F64] = "pow"; 148 Names[RTLIB::POW_F80] = "powl"; 149 Names[RTLIB::POW_PPCF128] = "powl"; 150 Names[RTLIB::CEIL_F32] = "ceilf"; 151 Names[RTLIB::CEIL_F64] = "ceil"; 152 Names[RTLIB::CEIL_F80] = "ceill"; 153 Names[RTLIB::CEIL_PPCF128] = "ceill"; 154 Names[RTLIB::TRUNC_F32] = "truncf"; 155 Names[RTLIB::TRUNC_F64] = "trunc"; 156 Names[RTLIB::TRUNC_F80] = "truncl"; 157 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 158 Names[RTLIB::RINT_F32] = "rintf"; 159 Names[RTLIB::RINT_F64] = "rint"; 160 Names[RTLIB::RINT_F80] = "rintl"; 161 Names[RTLIB::RINT_PPCF128] = "rintl"; 162 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 163 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 164 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 165 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 166 Names[RTLIB::FLOOR_F32] = "floorf"; 167 Names[RTLIB::FLOOR_F64] = "floor"; 168 Names[RTLIB::FLOOR_F80] = "floorl"; 169 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 170 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 171 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 172 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 173 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 174 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 175 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 176 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8"; 177 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16"; 178 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 179 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 180 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 181 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 182 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 183 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 184 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 185 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 186 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 187 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 188 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 189 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 190 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8"; 191 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16"; 192 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 193 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 194 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 195 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 196 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 197 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 198 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 199 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 200 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 201 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 202 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 203 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 204 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 205 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 206 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 207 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 208 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 209 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 210 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 211 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 212 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 213 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 214 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 215 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 216 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 217 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 218 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 219 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 220 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 221 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 222 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 223 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 224 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 225 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 226 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 227 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 228 Names[RTLIB::OEQ_F32] = "__eqsf2"; 229 Names[RTLIB::OEQ_F64] = "__eqdf2"; 230 Names[RTLIB::UNE_F32] = "__nesf2"; 231 Names[RTLIB::UNE_F64] = "__nedf2"; 232 Names[RTLIB::OGE_F32] = "__gesf2"; 233 Names[RTLIB::OGE_F64] = "__gedf2"; 234 Names[RTLIB::OLT_F32] = "__ltsf2"; 235 Names[RTLIB::OLT_F64] = "__ltdf2"; 236 Names[RTLIB::OLE_F32] = "__lesf2"; 237 Names[RTLIB::OLE_F64] = "__ledf2"; 238 Names[RTLIB::OGT_F32] = "__gtsf2"; 239 Names[RTLIB::OGT_F64] = "__gtdf2"; 240 Names[RTLIB::UO_F32] = "__unordsf2"; 241 Names[RTLIB::UO_F64] = "__unorddf2"; 242 Names[RTLIB::O_F32] = "__unordsf2"; 243 Names[RTLIB::O_F64] = "__unorddf2"; 244 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 245} 246 247/// getFPEXT - Return the FPEXT_*_* value for the given types, or 248/// UNKNOWN_LIBCALL if there is none. 249RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { 250 if (OpVT == MVT::f32) { 251 if (RetVT == MVT::f64) 252 return FPEXT_F32_F64; 253 } 254 return UNKNOWN_LIBCALL; 255} 256 257/// getFPROUND - Return the FPROUND_*_* value for the given types, or 258/// UNKNOWN_LIBCALL if there is none. 259RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { 260 if (RetVT == MVT::f32) { 261 if (OpVT == MVT::f64) 262 return FPROUND_F64_F32; 263 if (OpVT == MVT::f80) 264 return FPROUND_F80_F32; 265 if (OpVT == MVT::ppcf128) 266 return FPROUND_PPCF128_F32; 267 } else if (RetVT == MVT::f64) { 268 if (OpVT == MVT::f80) 269 return FPROUND_F80_F64; 270 if (OpVT == MVT::ppcf128) 271 return FPROUND_PPCF128_F64; 272 } 273 return UNKNOWN_LIBCALL; 274} 275 276/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 277/// UNKNOWN_LIBCALL if there is none. 278RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { 279 if (OpVT == MVT::f32) { 280 if (RetVT == MVT::i8) 281 return FPTOSINT_F32_I8; 282 if (RetVT == MVT::i16) 283 return FPTOSINT_F32_I16; 284 if (RetVT == MVT::i32) 285 return FPTOSINT_F32_I32; 286 if (RetVT == MVT::i64) 287 return FPTOSINT_F32_I64; 288 if (RetVT == MVT::i128) 289 return FPTOSINT_F32_I128; 290 } else if (OpVT == MVT::f64) { 291 if (RetVT == MVT::i32) 292 return FPTOSINT_F64_I32; 293 if (RetVT == MVT::i64) 294 return FPTOSINT_F64_I64; 295 if (RetVT == MVT::i128) 296 return FPTOSINT_F64_I128; 297 } else if (OpVT == MVT::f80) { 298 if (RetVT == MVT::i32) 299 return FPTOSINT_F80_I32; 300 if (RetVT == MVT::i64) 301 return FPTOSINT_F80_I64; 302 if (RetVT == MVT::i128) 303 return FPTOSINT_F80_I128; 304 } else if (OpVT == MVT::ppcf128) { 305 if (RetVT == MVT::i32) 306 return FPTOSINT_PPCF128_I32; 307 if (RetVT == MVT::i64) 308 return FPTOSINT_PPCF128_I64; 309 if (RetVT == MVT::i128) 310 return FPTOSINT_PPCF128_I128; 311 } 312 return UNKNOWN_LIBCALL; 313} 314 315/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 316/// UNKNOWN_LIBCALL if there is none. 317RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { 318 if (OpVT == MVT::f32) { 319 if (RetVT == MVT::i8) 320 return FPTOUINT_F32_I8; 321 if (RetVT == MVT::i16) 322 return FPTOUINT_F32_I16; 323 if (RetVT == MVT::i32) 324 return FPTOUINT_F32_I32; 325 if (RetVT == MVT::i64) 326 return FPTOUINT_F32_I64; 327 if (RetVT == MVT::i128) 328 return FPTOUINT_F32_I128; 329 } else if (OpVT == MVT::f64) { 330 if (RetVT == MVT::i32) 331 return FPTOUINT_F64_I32; 332 if (RetVT == MVT::i64) 333 return FPTOUINT_F64_I64; 334 if (RetVT == MVT::i128) 335 return FPTOUINT_F64_I128; 336 } else if (OpVT == MVT::f80) { 337 if (RetVT == MVT::i32) 338 return FPTOUINT_F80_I32; 339 if (RetVT == MVT::i64) 340 return FPTOUINT_F80_I64; 341 if (RetVT == MVT::i128) 342 return FPTOUINT_F80_I128; 343 } else if (OpVT == MVT::ppcf128) { 344 if (RetVT == MVT::i32) 345 return FPTOUINT_PPCF128_I32; 346 if (RetVT == MVT::i64) 347 return FPTOUINT_PPCF128_I64; 348 if (RetVT == MVT::i128) 349 return FPTOUINT_PPCF128_I128; 350 } 351 return UNKNOWN_LIBCALL; 352} 353 354/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 355/// UNKNOWN_LIBCALL if there is none. 356RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { 357 if (OpVT == MVT::i32) { 358 if (RetVT == MVT::f32) 359 return SINTTOFP_I32_F32; 360 else if (RetVT == MVT::f64) 361 return SINTTOFP_I32_F64; 362 else if (RetVT == MVT::f80) 363 return SINTTOFP_I32_F80; 364 else if (RetVT == MVT::ppcf128) 365 return SINTTOFP_I32_PPCF128; 366 } else if (OpVT == MVT::i64) { 367 if (RetVT == MVT::f32) 368 return SINTTOFP_I64_F32; 369 else if (RetVT == MVT::f64) 370 return SINTTOFP_I64_F64; 371 else if (RetVT == MVT::f80) 372 return SINTTOFP_I64_F80; 373 else if (RetVT == MVT::ppcf128) 374 return SINTTOFP_I64_PPCF128; 375 } else if (OpVT == MVT::i128) { 376 if (RetVT == MVT::f32) 377 return SINTTOFP_I128_F32; 378 else if (RetVT == MVT::f64) 379 return SINTTOFP_I128_F64; 380 else if (RetVT == MVT::f80) 381 return SINTTOFP_I128_F80; 382 else if (RetVT == MVT::ppcf128) 383 return SINTTOFP_I128_PPCF128; 384 } 385 return UNKNOWN_LIBCALL; 386} 387 388/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 389/// UNKNOWN_LIBCALL if there is none. 390RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { 391 if (OpVT == MVT::i32) { 392 if (RetVT == MVT::f32) 393 return UINTTOFP_I32_F32; 394 else if (RetVT == MVT::f64) 395 return UINTTOFP_I32_F64; 396 else if (RetVT == MVT::f80) 397 return UINTTOFP_I32_F80; 398 else if (RetVT == MVT::ppcf128) 399 return UINTTOFP_I32_PPCF128; 400 } else if (OpVT == MVT::i64) { 401 if (RetVT == MVT::f32) 402 return UINTTOFP_I64_F32; 403 else if (RetVT == MVT::f64) 404 return UINTTOFP_I64_F64; 405 else if (RetVT == MVT::f80) 406 return UINTTOFP_I64_F80; 407 else if (RetVT == MVT::ppcf128) 408 return UINTTOFP_I64_PPCF128; 409 } else if (OpVT == MVT::i128) { 410 if (RetVT == MVT::f32) 411 return UINTTOFP_I128_F32; 412 else if (RetVT == MVT::f64) 413 return UINTTOFP_I128_F64; 414 else if (RetVT == MVT::f80) 415 return UINTTOFP_I128_F80; 416 else if (RetVT == MVT::ppcf128) 417 return UINTTOFP_I128_PPCF128; 418 } 419 return UNKNOWN_LIBCALL; 420} 421 422/// InitCmpLibcallCCs - Set default comparison libcall CC. 423/// 424static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 425 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 426 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 427 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 428 CCs[RTLIB::UNE_F32] = ISD::SETNE; 429 CCs[RTLIB::UNE_F64] = ISD::SETNE; 430 CCs[RTLIB::OGE_F32] = ISD::SETGE; 431 CCs[RTLIB::OGE_F64] = ISD::SETGE; 432 CCs[RTLIB::OLT_F32] = ISD::SETLT; 433 CCs[RTLIB::OLT_F64] = ISD::SETLT; 434 CCs[RTLIB::OLE_F32] = ISD::SETLE; 435 CCs[RTLIB::OLE_F64] = ISD::SETLE; 436 CCs[RTLIB::OGT_F32] = ISD::SETGT; 437 CCs[RTLIB::OGT_F64] = ISD::SETGT; 438 CCs[RTLIB::UO_F32] = ISD::SETNE; 439 CCs[RTLIB::UO_F64] = ISD::SETNE; 440 CCs[RTLIB::O_F32] = ISD::SETEQ; 441 CCs[RTLIB::O_F64] = ISD::SETEQ; 442} 443 444/// NOTE: The constructor takes ownership of TLOF. 445TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) 446 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 447 // All operations default to being supported. 448 memset(OpActions, 0, sizeof(OpActions)); 449 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 450 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 451 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 452 memset(ConvertActions, 0, sizeof(ConvertActions)); 453 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 454 455 // Set default actions for various operations. 456 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 457 // Default all indexed load / store to expand. 458 for (unsigned IM = (unsigned)ISD::PRE_INC; 459 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 460 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 461 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 462 } 463 464 // These operations default to expand. 465 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 466 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 467 } 468 469 // Most targets ignore the @llvm.prefetch intrinsic. 470 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 471 472 // ConstantFP nodes default to expand. Targets can either change this to 473 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate 474 // to optimize expansions for certain constants. 475 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 476 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 477 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 478 479 // These library functions default to expand. 480 setOperationAction(ISD::FLOG , MVT::f64, Expand); 481 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 482 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 483 setOperationAction(ISD::FEXP , MVT::f64, Expand); 484 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 485 setOperationAction(ISD::FLOG , MVT::f32, Expand); 486 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 487 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 488 setOperationAction(ISD::FEXP , MVT::f32, Expand); 489 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 490 491 // Default ISD::TRAP to expand (which turns it into abort). 492 setOperationAction(ISD::TRAP, MVT::Other, Expand); 493 494 IsLittleEndian = TD->isLittleEndian(); 495 UsesGlobalOffsetTable = false; 496 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()); 497 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 498 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 499 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 500 allowUnalignedMemoryAccesses = false; 501 benefitFromCodePlacementOpt = false; 502 UseUnderscoreSetJmp = false; 503 UseUnderscoreLongJmp = false; 504 SelectIsExpensive = false; 505 IntDivIsCheap = false; 506 Pow2DivIsCheap = false; 507 StackPointerRegisterToSaveRestore = 0; 508 ExceptionPointerRegister = 0; 509 ExceptionSelectorRegister = 0; 510 BooleanContents = UndefinedBooleanContent; 511 SchedPreferenceInfo = SchedulingForLatency; 512 JumpBufSize = 0; 513 JumpBufAlignment = 0; 514 IfCvtBlockSizeLimit = 2; 515 IfCvtDupBlockSizeLimit = 0; 516 PrefLoopAlignment = 0; 517 518 InitLibcallNames(LibcallRoutineNames); 519 InitCmpLibcallCCs(CmpLibcallCCs); 520 521 // Tell Legalize whether the assembler supports DEBUG_LOC. 522 const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); 523 if (!TASM || !TASM->hasDotLocAndDotFile()) 524 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 525} 526 527TargetLowering::~TargetLowering() { 528 delete &TLOF; 529} 530 531/// computeRegisterProperties - Once all of the register classes are added, 532/// this allows us to compute derived properties we expose. 533void TargetLowering::computeRegisterProperties() { 534 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 535 "Too many value types for ValueTypeActions to hold!"); 536 537 // Everything defaults to needing one register. 538 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 539 NumRegistersForVT[i] = 1; 540 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 541 } 542 // ...except isVoid, which doesn't need any registers. 543 NumRegistersForVT[MVT::isVoid] = 0; 544 545 // Find the largest integer register class. 546 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 547 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 548 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 549 550 // Every integer value type larger than this largest register takes twice as 551 // many registers to represent as the previous ValueType. 552 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 553 MVT EVT = (MVT::SimpleValueType)ExpandedReg; 554 if (!EVT.isInteger()) 555 break; 556 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 557 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 558 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 559 ValueTypeActions.setTypeAction(EVT, Expand); 560 } 561 562 // Inspect all of the ValueType's smaller than the largest integer 563 // register to see which ones need promotion. 564 unsigned LegalIntReg = LargestIntReg; 565 for (unsigned IntReg = LargestIntReg - 1; 566 IntReg >= (unsigned)MVT::i1; --IntReg) { 567 MVT IVT = (MVT::SimpleValueType)IntReg; 568 if (isTypeLegal(IVT)) { 569 LegalIntReg = IntReg; 570 } else { 571 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 572 (MVT::SimpleValueType)LegalIntReg; 573 ValueTypeActions.setTypeAction(IVT, Promote); 574 } 575 } 576 577 // ppcf128 type is really two f64's. 578 if (!isTypeLegal(MVT::ppcf128)) { 579 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 580 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 581 TransformToType[MVT::ppcf128] = MVT::f64; 582 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 583 } 584 585 // Decide how to handle f64. If the target does not have native f64 support, 586 // expand it to i64 and we will be generating soft float library calls. 587 if (!isTypeLegal(MVT::f64)) { 588 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 589 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 590 TransformToType[MVT::f64] = MVT::i64; 591 ValueTypeActions.setTypeAction(MVT::f64, Expand); 592 } 593 594 // Decide how to handle f32. If the target does not have native support for 595 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 596 if (!isTypeLegal(MVT::f32)) { 597 if (isTypeLegal(MVT::f64)) { 598 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 599 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 600 TransformToType[MVT::f32] = MVT::f64; 601 ValueTypeActions.setTypeAction(MVT::f32, Promote); 602 } else { 603 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 604 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 605 TransformToType[MVT::f32] = MVT::i32; 606 ValueTypeActions.setTypeAction(MVT::f32, Expand); 607 } 608 } 609 610 // Loop over all of the vector value types to see which need transformations. 611 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 612 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 613 MVT VT = (MVT::SimpleValueType)i; 614 if (!isTypeLegal(VT)) { 615 MVT IntermediateVT, RegisterVT; 616 unsigned NumIntermediates; 617 NumRegistersForVT[i] = 618 getVectorTypeBreakdown(VT, 619 IntermediateVT, NumIntermediates, 620 RegisterVT); 621 RegisterTypeForVT[i] = RegisterVT; 622 623 // Determine if there is a legal wider type. 624 bool IsLegalWiderType = false; 625 MVT EltVT = VT.getVectorElementType(); 626 unsigned NElts = VT.getVectorNumElements(); 627 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 628 MVT SVT = (MVT::SimpleValueType)nVT; 629 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && 630 SVT.getVectorNumElements() > NElts) { 631 TransformToType[i] = SVT; 632 ValueTypeActions.setTypeAction(VT, Promote); 633 IsLegalWiderType = true; 634 break; 635 } 636 } 637 if (!IsLegalWiderType) { 638 MVT NVT = VT.getPow2VectorType(); 639 if (NVT == VT) { 640 // Type is already a power of 2. The default action is to split. 641 TransformToType[i] = MVT::Other; 642 ValueTypeActions.setTypeAction(VT, Expand); 643 } else { 644 TransformToType[i] = NVT; 645 ValueTypeActions.setTypeAction(VT, Promote); 646 } 647 } 648 } 649 } 650} 651 652const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 653 return NULL; 654} 655 656 657MVT TargetLowering::getSetCCResultType(MVT VT) const { 658 return getValueType(TD->getIntPtrType()); 659} 660 661 662/// getVectorTypeBreakdown - Vector types are broken down into some number of 663/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 664/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 665/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 666/// 667/// This method returns the number of registers needed, and the VT for each 668/// register. It also returns the VT and quantity of the intermediate values 669/// before they are promoted/expanded. 670/// 671unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, 672 MVT &IntermediateVT, 673 unsigned &NumIntermediates, 674 MVT &RegisterVT) const { 675 // Figure out the right, legal destination reg to copy into. 676 unsigned NumElts = VT.getVectorNumElements(); 677 MVT EltTy = VT.getVectorElementType(); 678 679 unsigned NumVectorRegs = 1; 680 681 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 682 // could break down into LHS/RHS like LegalizeDAG does. 683 if (!isPowerOf2_32(NumElts)) { 684 NumVectorRegs = NumElts; 685 NumElts = 1; 686 } 687 688 // Divide the input until we get to a supported size. This will always 689 // end with a scalar if the target doesn't support vectors. 690 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 691 NumElts >>= 1; 692 NumVectorRegs <<= 1; 693 } 694 695 NumIntermediates = NumVectorRegs; 696 697 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 698 if (!isTypeLegal(NewVT)) 699 NewVT = EltTy; 700 IntermediateVT = NewVT; 701 702 MVT DestVT = getRegisterType(NewVT); 703 RegisterVT = DestVT; 704 if (DestVT.bitsLT(NewVT)) { 705 // Value is expanded, e.g. i64 -> i16. 706 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 707 } else { 708 // Otherwise, promotion or legal types use the same number of registers as 709 // the vector decimated to the appropriate level. 710 return NumVectorRegs; 711 } 712 713 return 1; 714} 715 716/// getWidenVectorType: given a vector type, returns the type to widen to 717/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 718/// If there is no vector type that we want to widen to, returns MVT::Other 719/// When and where to widen is target dependent based on the cost of 720/// scalarizing vs using the wider vector type. 721MVT TargetLowering::getWidenVectorType(MVT VT) const { 722 assert(VT.isVector()); 723 if (isTypeLegal(VT)) 724 return VT; 725 726 // Default is not to widen until moved to LegalizeTypes 727 return MVT::Other; 728} 729 730/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 731/// function arguments in the caller parameter area. This is the actual 732/// alignment, not its logarithm. 733unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 734 return TD->getCallFrameTypeAlignment(Ty); 735} 736 737SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 738 SelectionDAG &DAG) const { 739 if (usesGlobalOffsetTable()) 740 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 741 return Table; 742} 743 744bool 745TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 746 // Assume that everything is safe in static mode. 747 if (getTargetMachine().getRelocationModel() == Reloc::Static) 748 return true; 749 750 // In dynamic-no-pic mode, assume that known defined values are safe. 751 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 752 GA && 753 !GA->getGlobal()->isDeclaration() && 754 !GA->getGlobal()->isWeakForLinker()) 755 return true; 756 757 // Otherwise assume nothing is safe. 758 return false; 759} 760 761//===----------------------------------------------------------------------===// 762// Optimization Methods 763//===----------------------------------------------------------------------===// 764 765/// ShrinkDemandedConstant - Check to see if the specified operand of the 766/// specified instruction is a constant integer. If so, check to see if there 767/// are any bits set in the constant that are not demanded. If so, shrink the 768/// constant and return true. 769bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 770 const APInt &Demanded) { 771 DebugLoc dl = Op.getDebugLoc(); 772 773 // FIXME: ISD::SELECT, ISD::SELECT_CC 774 switch (Op.getOpcode()) { 775 default: break; 776 case ISD::XOR: 777 case ISD::AND: 778 case ISD::OR: { 779 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 780 if (!C) return false; 781 782 if (Op.getOpcode() == ISD::XOR && 783 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 784 return false; 785 786 // if we can expand it to have all bits set, do it 787 if (C->getAPIntValue().intersects(~Demanded)) { 788 MVT VT = Op.getValueType(); 789 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 790 DAG.getConstant(Demanded & 791 C->getAPIntValue(), 792 VT)); 793 return CombineTo(Op, New); 794 } 795 796 break; 797 } 798 } 799 800 return false; 801} 802 803/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 804/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 805/// cast, but it could be generalized for targets with other types of 806/// implicit widening casts. 807bool 808TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 809 unsigned BitWidth, 810 const APInt &Demanded, 811 DebugLoc dl) { 812 assert(Op.getNumOperands() == 2 && 813 "ShrinkDemandedOp only supports binary operators!"); 814 assert(Op.getNode()->getNumValues() == 1 && 815 "ShrinkDemandedOp only supports nodes with one result!"); 816 817 // Don't do this if the node has another user, which may require the 818 // full value. 819 if (!Op.getNode()->hasOneUse()) 820 return false; 821 822 // Search for the smallest integer type with free casts to and from 823 // Op's type. For expedience, just check power-of-2 integer types. 824 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 825 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 826 if (!isPowerOf2_32(SmallVTBits)) 827 SmallVTBits = NextPowerOf2(SmallVTBits); 828 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 829 MVT SmallVT = MVT::getIntegerVT(SmallVTBits); 830 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 831 TLI.isZExtFree(SmallVT, Op.getValueType())) { 832 // We found a type with free casts. 833 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 834 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 835 Op.getNode()->getOperand(0)), 836 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 837 Op.getNode()->getOperand(1))); 838 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 839 return CombineTo(Op, Z); 840 } 841 } 842 return false; 843} 844 845/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 846/// DemandedMask bits of the result of Op are ever used downstream. If we can 847/// use this information to simplify Op, create a new simplified DAG node and 848/// return true, returning the original and new nodes in Old and New. Otherwise, 849/// analyze the expression and return a mask of KnownOne and KnownZero bits for 850/// the expression (used to simplify the caller). The KnownZero/One bits may 851/// only be accurate for those bits in the DemandedMask. 852bool TargetLowering::SimplifyDemandedBits(SDValue Op, 853 const APInt &DemandedMask, 854 APInt &KnownZero, 855 APInt &KnownOne, 856 TargetLoweringOpt &TLO, 857 unsigned Depth) const { 858 unsigned BitWidth = DemandedMask.getBitWidth(); 859 assert(Op.getValueSizeInBits() == BitWidth && 860 "Mask size mismatches value type size!"); 861 APInt NewMask = DemandedMask; 862 DebugLoc dl = Op.getDebugLoc(); 863 864 // Don't know anything. 865 KnownZero = KnownOne = APInt(BitWidth, 0); 866 867 // Other users may use these bits. 868 if (!Op.getNode()->hasOneUse()) { 869 if (Depth != 0) { 870 // If not at the root, Just compute the KnownZero/KnownOne bits to 871 // simplify things downstream. 872 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 873 return false; 874 } 875 // If this is the root being simplified, allow it to have multiple uses, 876 // just set the NewMask to all bits. 877 NewMask = APInt::getAllOnesValue(BitWidth); 878 } else if (DemandedMask == 0) { 879 // Not demanding any bits from Op. 880 if (Op.getOpcode() != ISD::UNDEF) 881 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 882 return false; 883 } else if (Depth == 6) { // Limit search depth. 884 return false; 885 } 886 887 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 888 switch (Op.getOpcode()) { 889 case ISD::Constant: 890 // We know all of the bits for a constant! 891 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 892 KnownZero = ~KnownOne & NewMask; 893 return false; // Don't fall through, will infinitely loop. 894 case ISD::AND: 895 // If the RHS is a constant, check to see if the LHS would be zero without 896 // using the bits from the RHS. Below, we use knowledge about the RHS to 897 // simplify the LHS, here we're using information from the LHS to simplify 898 // the RHS. 899 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 900 APInt LHSZero, LHSOne; 901 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 902 LHSZero, LHSOne, Depth+1); 903 // If the LHS already has zeros where RHSC does, this and is dead. 904 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 905 return TLO.CombineTo(Op, Op.getOperand(0)); 906 // If any of the set bits in the RHS are known zero on the LHS, shrink 907 // the constant. 908 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 909 return true; 910 } 911 912 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 913 KnownOne, TLO, Depth+1)) 914 return true; 915 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 916 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 917 KnownZero2, KnownOne2, TLO, Depth+1)) 918 return true; 919 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 920 921 // If all of the demanded bits are known one on one side, return the other. 922 // These bits cannot contribute to the result of the 'and'. 923 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 924 return TLO.CombineTo(Op, Op.getOperand(0)); 925 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 926 return TLO.CombineTo(Op, Op.getOperand(1)); 927 // If all of the demanded bits in the inputs are known zeros, return zero. 928 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 929 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 930 // If the RHS is a constant, see if we can simplify it. 931 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 932 return true; 933 // If the operation can be done in a smaller type, do so. 934 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 935 return true; 936 937 // Output known-1 bits are only known if set in both the LHS & RHS. 938 KnownOne &= KnownOne2; 939 // Output known-0 are known to be clear if zero in either the LHS | RHS. 940 KnownZero |= KnownZero2; 941 break; 942 case ISD::OR: 943 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 944 KnownOne, TLO, Depth+1)) 945 return true; 946 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 947 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 948 KnownZero2, KnownOne2, TLO, Depth+1)) 949 return true; 950 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 951 952 // If all of the demanded bits are known zero on one side, return the other. 953 // These bits cannot contribute to the result of the 'or'. 954 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 955 return TLO.CombineTo(Op, Op.getOperand(0)); 956 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 957 return TLO.CombineTo(Op, Op.getOperand(1)); 958 // If all of the potentially set bits on one side are known to be set on 959 // the other side, just use the 'other' side. 960 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 961 return TLO.CombineTo(Op, Op.getOperand(0)); 962 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 963 return TLO.CombineTo(Op, Op.getOperand(1)); 964 // If the RHS is a constant, see if we can simplify it. 965 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 966 return true; 967 // If the operation can be done in a smaller type, do so. 968 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 969 return true; 970 971 // Output known-0 bits are only known if clear in both the LHS & RHS. 972 KnownZero &= KnownZero2; 973 // Output known-1 are known to be set if set in either the LHS | RHS. 974 KnownOne |= KnownOne2; 975 break; 976 case ISD::XOR: 977 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 978 KnownOne, TLO, Depth+1)) 979 return true; 980 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 981 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 982 KnownOne2, TLO, Depth+1)) 983 return true; 984 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 985 986 // If all of the demanded bits are known zero on one side, return the other. 987 // These bits cannot contribute to the result of the 'xor'. 988 if ((KnownZero & NewMask) == NewMask) 989 return TLO.CombineTo(Op, Op.getOperand(0)); 990 if ((KnownZero2 & NewMask) == NewMask) 991 return TLO.CombineTo(Op, Op.getOperand(1)); 992 // If the operation can be done in a smaller type, do so. 993 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 994 return true; 995 996 // If all of the unknown bits are known to be zero on one side or the other 997 // (but not both) turn this into an *inclusive* or. 998 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 999 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1000 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1001 Op.getOperand(0), 1002 Op.getOperand(1))); 1003 1004 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1005 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1006 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1007 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1008 1009 // If all of the demanded bits on one side are known, and all of the set 1010 // bits on that side are also known to be set on the other side, turn this 1011 // into an AND, as we know the bits will be cleared. 1012 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1013 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1014 if ((KnownOne & KnownOne2) == KnownOne) { 1015 MVT VT = Op.getValueType(); 1016 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1017 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1018 Op.getOperand(0), ANDC)); 1019 } 1020 } 1021 1022 // If the RHS is a constant, see if we can simplify it. 1023 // for XOR, we prefer to force bits to 1 if they will make a -1. 1024 // if we can't force bits, try to shrink constant 1025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1026 APInt Expanded = C->getAPIntValue() | (~NewMask); 1027 // if we can expand it to have all bits set, do it 1028 if (Expanded.isAllOnesValue()) { 1029 if (Expanded != C->getAPIntValue()) { 1030 MVT VT = Op.getValueType(); 1031 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1032 TLO.DAG.getConstant(Expanded, VT)); 1033 return TLO.CombineTo(Op, New); 1034 } 1035 // if it already has all the bits set, nothing to change 1036 // but don't shrink either! 1037 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1038 return true; 1039 } 1040 } 1041 1042 KnownZero = KnownZeroOut; 1043 KnownOne = KnownOneOut; 1044 break; 1045 case ISD::SELECT: 1046 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1047 KnownOne, TLO, Depth+1)) 1048 return true; 1049 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1050 KnownOne2, TLO, Depth+1)) 1051 return true; 1052 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1053 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1054 1055 // If the operands are constants, see if we can simplify them. 1056 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1057 return true; 1058 1059 // Only known if known in both the LHS and RHS. 1060 KnownOne &= KnownOne2; 1061 KnownZero &= KnownZero2; 1062 break; 1063 case ISD::SELECT_CC: 1064 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1065 KnownOne, TLO, Depth+1)) 1066 return true; 1067 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1068 KnownOne2, TLO, Depth+1)) 1069 return true; 1070 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1071 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1072 1073 // If the operands are constants, see if we can simplify them. 1074 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1075 return true; 1076 1077 // Only known if known in both the LHS and RHS. 1078 KnownOne &= KnownOne2; 1079 KnownZero &= KnownZero2; 1080 break; 1081 case ISD::SHL: 1082 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1083 unsigned ShAmt = SA->getZExtValue(); 1084 SDValue InOp = Op.getOperand(0); 1085 1086 // If the shift count is an invalid immediate, don't do anything. 1087 if (ShAmt >= BitWidth) 1088 break; 1089 1090 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1091 // single shift. We can do this if the bottom bits (which are shifted 1092 // out) are never demanded. 1093 if (InOp.getOpcode() == ISD::SRL && 1094 isa<ConstantSDNode>(InOp.getOperand(1))) { 1095 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1096 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1097 unsigned Opc = ISD::SHL; 1098 int Diff = ShAmt-C1; 1099 if (Diff < 0) { 1100 Diff = -Diff; 1101 Opc = ISD::SRL; 1102 } 1103 1104 SDValue NewSA = 1105 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1106 MVT VT = Op.getValueType(); 1107 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1108 InOp.getOperand(0), NewSA)); 1109 } 1110 } 1111 1112 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1113 KnownZero, KnownOne, TLO, Depth+1)) 1114 return true; 1115 KnownZero <<= SA->getZExtValue(); 1116 KnownOne <<= SA->getZExtValue(); 1117 // low bits known zero. 1118 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1119 } 1120 break; 1121 case ISD::SRL: 1122 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1123 MVT VT = Op.getValueType(); 1124 unsigned ShAmt = SA->getZExtValue(); 1125 unsigned VTSize = VT.getSizeInBits(); 1126 SDValue InOp = Op.getOperand(0); 1127 1128 // If the shift count is an invalid immediate, don't do anything. 1129 if (ShAmt >= BitWidth) 1130 break; 1131 1132 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1133 // single shift. We can do this if the top bits (which are shifted out) 1134 // are never demanded. 1135 if (InOp.getOpcode() == ISD::SHL && 1136 isa<ConstantSDNode>(InOp.getOperand(1))) { 1137 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1138 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1139 unsigned Opc = ISD::SRL; 1140 int Diff = ShAmt-C1; 1141 if (Diff < 0) { 1142 Diff = -Diff; 1143 Opc = ISD::SHL; 1144 } 1145 1146 SDValue NewSA = 1147 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1148 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1149 InOp.getOperand(0), NewSA)); 1150 } 1151 } 1152 1153 // Compute the new bits that are at the top now. 1154 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1155 KnownZero, KnownOne, TLO, Depth+1)) 1156 return true; 1157 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1158 KnownZero = KnownZero.lshr(ShAmt); 1159 KnownOne = KnownOne.lshr(ShAmt); 1160 1161 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1162 KnownZero |= HighBits; // High bits known zero. 1163 } 1164 break; 1165 case ISD::SRA: 1166 // If this is an arithmetic shift right and only the low-bit is set, we can 1167 // always convert this into a logical shr, even if the shift amount is 1168 // variable. The low bit of the shift cannot be an input sign bit unless 1169 // the shift amount is >= the size of the datatype, which is undefined. 1170 if (DemandedMask == 1) 1171 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1172 Op.getOperand(0), Op.getOperand(1))); 1173 1174 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1175 MVT VT = Op.getValueType(); 1176 unsigned ShAmt = SA->getZExtValue(); 1177 1178 // If the shift count is an invalid immediate, don't do anything. 1179 if (ShAmt >= BitWidth) 1180 break; 1181 1182 APInt InDemandedMask = (NewMask << ShAmt); 1183 1184 // If any of the demanded bits are produced by the sign extension, we also 1185 // demand the input sign bit. 1186 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1187 if (HighBits.intersects(NewMask)) 1188 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits()); 1189 1190 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1191 KnownZero, KnownOne, TLO, Depth+1)) 1192 return true; 1193 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1194 KnownZero = KnownZero.lshr(ShAmt); 1195 KnownOne = KnownOne.lshr(ShAmt); 1196 1197 // Handle the sign bit, adjusted to where it is now in the mask. 1198 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1199 1200 // If the input sign bit is known to be zero, or if none of the top bits 1201 // are demanded, turn this into an unsigned shift right. 1202 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1203 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1204 Op.getOperand(0), 1205 Op.getOperand(1))); 1206 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1207 KnownOne |= HighBits; 1208 } 1209 } 1210 break; 1211 case ISD::SIGN_EXTEND_INREG: { 1212 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1213 1214 // Sign extension. Compute the demanded bits in the result that are not 1215 // present in the input. 1216 APInt NewBits = APInt::getHighBitsSet(BitWidth, 1217 BitWidth - EVT.getSizeInBits()) & 1218 NewMask; 1219 1220 // If none of the extended bits are demanded, eliminate the sextinreg. 1221 if (NewBits == 0) 1222 return TLO.CombineTo(Op, Op.getOperand(0)); 1223 1224 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits()); 1225 InSignBit.zext(BitWidth); 1226 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth, 1227 EVT.getSizeInBits()) & 1228 NewMask; 1229 1230 // Since the sign extended bits are demanded, we know that the sign 1231 // bit is demanded. 1232 InputDemandedBits |= InSignBit; 1233 1234 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1235 KnownZero, KnownOne, TLO, Depth+1)) 1236 return true; 1237 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1238 1239 // If the sign bit of the input is known set or clear, then we know the 1240 // top bits of the result. 1241 1242 // If the input sign bit is known zero, convert this into a zero extension. 1243 if (KnownZero.intersects(InSignBit)) 1244 return TLO.CombineTo(Op, 1245 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1246 1247 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1248 KnownOne |= NewBits; 1249 KnownZero &= ~NewBits; 1250 } else { // Input sign bit unknown 1251 KnownZero &= ~NewBits; 1252 KnownOne &= ~NewBits; 1253 } 1254 break; 1255 } 1256 case ISD::ZERO_EXTEND: { 1257 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1258 APInt InMask = NewMask; 1259 InMask.trunc(OperandBitWidth); 1260 1261 // If none of the top bits are demanded, convert this into an any_extend. 1262 APInt NewBits = 1263 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1264 if (!NewBits.intersects(NewMask)) 1265 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1266 Op.getValueType(), 1267 Op.getOperand(0))); 1268 1269 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1270 KnownZero, KnownOne, TLO, Depth+1)) 1271 return true; 1272 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1273 KnownZero.zext(BitWidth); 1274 KnownOne.zext(BitWidth); 1275 KnownZero |= NewBits; 1276 break; 1277 } 1278 case ISD::SIGN_EXTEND: { 1279 MVT InVT = Op.getOperand(0).getValueType(); 1280 unsigned InBits = InVT.getSizeInBits(); 1281 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1282 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1283 APInt NewBits = ~InMask & NewMask; 1284 1285 // If none of the top bits are demanded, convert this into an any_extend. 1286 if (NewBits == 0) 1287 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1288 Op.getValueType(), 1289 Op.getOperand(0))); 1290 1291 // Since some of the sign extended bits are demanded, we know that the sign 1292 // bit is demanded. 1293 APInt InDemandedBits = InMask & NewMask; 1294 InDemandedBits |= InSignBit; 1295 InDemandedBits.trunc(InBits); 1296 1297 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1298 KnownOne, TLO, Depth+1)) 1299 return true; 1300 KnownZero.zext(BitWidth); 1301 KnownOne.zext(BitWidth); 1302 1303 // If the sign bit is known zero, convert this to a zero extend. 1304 if (KnownZero.intersects(InSignBit)) 1305 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1306 Op.getValueType(), 1307 Op.getOperand(0))); 1308 1309 // If the sign bit is known one, the top bits match. 1310 if (KnownOne.intersects(InSignBit)) { 1311 KnownOne |= NewBits; 1312 KnownZero &= ~NewBits; 1313 } else { // Otherwise, top bits aren't known. 1314 KnownOne &= ~NewBits; 1315 KnownZero &= ~NewBits; 1316 } 1317 break; 1318 } 1319 case ISD::ANY_EXTEND: { 1320 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits(); 1321 APInt InMask = NewMask; 1322 InMask.trunc(OperandBitWidth); 1323 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1324 KnownZero, KnownOne, TLO, Depth+1)) 1325 return true; 1326 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1327 KnownZero.zext(BitWidth); 1328 KnownOne.zext(BitWidth); 1329 break; 1330 } 1331 case ISD::TRUNCATE: { 1332 // Simplify the input, using demanded bit information, and compute the known 1333 // zero/one bits live out. 1334 APInt TruncMask = NewMask; 1335 TruncMask.zext(Op.getOperand(0).getValueSizeInBits()); 1336 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1337 KnownZero, KnownOne, TLO, Depth+1)) 1338 return true; 1339 KnownZero.trunc(BitWidth); 1340 KnownOne.trunc(BitWidth); 1341 1342 // If the input is only used by this truncate, see if we can shrink it based 1343 // on the known demanded bits. 1344 if (Op.getOperand(0).getNode()->hasOneUse()) { 1345 SDValue In = Op.getOperand(0); 1346 unsigned InBitWidth = In.getValueSizeInBits(); 1347 switch (In.getOpcode()) { 1348 default: break; 1349 case ISD::SRL: 1350 // Shrink SRL by a constant if none of the high bits shifted in are 1351 // demanded. 1352 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){ 1353 APInt HighBits = APInt::getHighBitsSet(InBitWidth, 1354 InBitWidth - BitWidth); 1355 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1356 HighBits.trunc(BitWidth); 1357 1358 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1359 // None of the shifted in bits are needed. Add a truncate of the 1360 // shift input, then shift it. 1361 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1362 Op.getValueType(), 1363 In.getOperand(0)); 1364 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1365 Op.getValueType(), 1366 NewTrunc, 1367 In.getOperand(1))); 1368 } 1369 } 1370 break; 1371 } 1372 } 1373 1374 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1375 break; 1376 } 1377 case ISD::AssertZext: { 1378 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1379 APInt InMask = APInt::getLowBitsSet(BitWidth, 1380 VT.getSizeInBits()); 1381 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, 1382 KnownZero, KnownOne, TLO, Depth+1)) 1383 return true; 1384 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1385 KnownZero |= ~InMask & NewMask; 1386 break; 1387 } 1388 case ISD::BIT_CONVERT: 1389#if 0 1390 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1391 // is demanded, turn this into a FGETSIGN. 1392 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && 1393 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1394 !MVT::isVector(Op.getOperand(0).getValueType())) { 1395 // Only do this xform if FGETSIGN is valid or if before legalize. 1396 if (!TLO.AfterLegalize || 1397 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1398 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1399 // place. We expect the SHL to be eliminated by other optimizations. 1400 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1401 Op.getOperand(0)); 1402 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1403 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1404 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1405 Sign, ShAmt)); 1406 } 1407 } 1408#endif 1409 break; 1410 case ISD::ADD: 1411 case ISD::MUL: 1412 case ISD::SUB: { 1413 // Add, Sub, and Mul don't demand any bits in positions beyond that 1414 // of the highest bit demanded of them. 1415 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1416 BitWidth - NewMask.countLeadingZeros()); 1417 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1418 KnownOne2, TLO, Depth+1)) 1419 return true; 1420 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1421 KnownOne2, TLO, Depth+1)) 1422 return true; 1423 // See if the operation should be performed at a smaller bit width. 1424 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1425 return true; 1426 } 1427 // FALL THROUGH 1428 default: 1429 // Just use ComputeMaskedBits to compute output bits. 1430 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1431 break; 1432 } 1433 1434 // If we know the value of all of the demanded bits, return this as a 1435 // constant. 1436 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1437 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1438 1439 return false; 1440} 1441 1442/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1443/// in Mask are known to be either zero or one and return them in the 1444/// KnownZero/KnownOne bitsets. 1445void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1446 const APInt &Mask, 1447 APInt &KnownZero, 1448 APInt &KnownOne, 1449 const SelectionDAG &DAG, 1450 unsigned Depth) const { 1451 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1452 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1453 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1454 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1455 "Should use MaskedValueIsZero if you don't know whether Op" 1456 " is a target node!"); 1457 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1458} 1459 1460/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1461/// targets that want to expose additional information about sign bits to the 1462/// DAG Combiner. 1463unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1464 unsigned Depth) const { 1465 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1466 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1467 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1468 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1469 "Should use ComputeNumSignBits if you don't know whether Op" 1470 " is a target node!"); 1471 return 1; 1472} 1473 1474/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1475/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1476/// determine which bit is set. 1477/// 1478static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1479 // A left-shift of a constant one will have exactly one bit set, because 1480 // shifting the bit off the end is undefined. 1481 if (Val.getOpcode() == ISD::SHL) 1482 if (ConstantSDNode *C = 1483 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1484 if (C->getAPIntValue() == 1) 1485 return true; 1486 1487 // Similarly, a right-shift of a constant sign-bit will have exactly 1488 // one bit set. 1489 if (Val.getOpcode() == ISD::SRL) 1490 if (ConstantSDNode *C = 1491 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1492 if (C->getAPIntValue().isSignBit()) 1493 return true; 1494 1495 // More could be done here, though the above checks are enough 1496 // to handle some common cases. 1497 1498 // Fall back to ComputeMaskedBits to catch other known cases. 1499 MVT OpVT = Val.getValueType(); 1500 unsigned BitWidth = OpVT.getSizeInBits(); 1501 APInt Mask = APInt::getAllOnesValue(BitWidth); 1502 APInt KnownZero, KnownOne; 1503 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1504 return (KnownZero.countPopulation() == BitWidth - 1) && 1505 (KnownOne.countPopulation() == 1); 1506} 1507 1508/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1509/// and cc. If it is unable to simplify it, return a null SDValue. 1510SDValue 1511TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 1512 ISD::CondCode Cond, bool foldBooleans, 1513 DAGCombinerInfo &DCI, DebugLoc dl) const { 1514 SelectionDAG &DAG = DCI.DAG; 1515 1516 // These setcc operations always fold. 1517 switch (Cond) { 1518 default: break; 1519 case ISD::SETFALSE: 1520 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1521 case ISD::SETTRUE: 1522 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1523 } 1524 1525 if (isa<ConstantSDNode>(N0.getNode())) { 1526 // Ensure that the constant occurs on the RHS, and fold constant 1527 // comparisons. 1528 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1529 } 1530 1531 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1532 const APInt &C1 = N1C->getAPIntValue(); 1533 1534 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1535 // equality comparison, then we're just comparing whether X itself is 1536 // zero. 1537 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1538 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1539 N0.getOperand(1).getOpcode() == ISD::Constant) { 1540 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1541 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1542 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1543 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1544 // (srl (ctlz x), 5) == 0 -> X != 0 1545 // (srl (ctlz x), 5) != 1 -> X != 0 1546 Cond = ISD::SETNE; 1547 } else { 1548 // (srl (ctlz x), 5) != 0 -> X == 0 1549 // (srl (ctlz x), 5) == 1 -> X == 0 1550 Cond = ISD::SETEQ; 1551 } 1552 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1553 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1554 Zero, Cond); 1555 } 1556 } 1557 1558 // If the LHS is '(and load, const)', the RHS is 0, 1559 // the test is for equality or unsigned, and all 1 bits of the const are 1560 // in the same partial word, see if we can shorten the load. 1561 if (DCI.isBeforeLegalize() && 1562 N0.getOpcode() == ISD::AND && C1 == 0 && 1563 N0.getNode()->hasOneUse() && 1564 isa<LoadSDNode>(N0.getOperand(0)) && 1565 N0.getOperand(0).getNode()->hasOneUse() && 1566 isa<ConstantSDNode>(N0.getOperand(1))) { 1567 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1568 uint64_t bestMask = 0; 1569 unsigned bestWidth = 0, bestOffset = 0; 1570 if (!Lod->isVolatile() && Lod->isUnindexed() && 1571 // FIXME: This uses getZExtValue() below so it only works on i64 and 1572 // below. 1573 N0.getValueType().getSizeInBits() <= 64) { 1574 unsigned origWidth = N0.getValueType().getSizeInBits(); 1575 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1576 // 8 bits, but have to be careful... 1577 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1578 origWidth = Lod->getMemoryVT().getSizeInBits(); 1579 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 1580 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1581 uint64_t newMask = (1ULL << width) - 1; 1582 for (unsigned offset=0; offset<origWidth/width; offset++) { 1583 if ((newMask & Mask) == Mask) { 1584 if (!TD->isLittleEndian()) 1585 bestOffset = (origWidth/width - offset - 1) * (width/8); 1586 else 1587 bestOffset = (uint64_t)offset * (width/8); 1588 bestMask = Mask >> (offset * (width/8) * 8); 1589 bestWidth = width; 1590 break; 1591 } 1592 newMask = newMask << width; 1593 } 1594 } 1595 } 1596 if (bestWidth) { 1597 MVT newVT = MVT::getIntegerVT(bestWidth); 1598 if (newVT.isRound()) { 1599 MVT PtrType = Lod->getOperand(1).getValueType(); 1600 SDValue Ptr = Lod->getBasePtr(); 1601 if (bestOffset != 0) 1602 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1603 DAG.getConstant(bestOffset, PtrType)); 1604 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1605 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1606 Lod->getSrcValue(), 1607 Lod->getSrcValueOffset() + bestOffset, 1608 false, NewAlign); 1609 return DAG.getSetCC(dl, VT, 1610 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1611 DAG.getConstant(bestMask, newVT)), 1612 DAG.getConstant(0LL, newVT), Cond); 1613 } 1614 } 1615 } 1616 1617 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1618 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1619 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1620 1621 // If the comparison constant has bits in the upper part, the 1622 // zero-extended value could never match. 1623 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1624 C1.getBitWidth() - InSize))) { 1625 switch (Cond) { 1626 case ISD::SETUGT: 1627 case ISD::SETUGE: 1628 case ISD::SETEQ: return DAG.getConstant(0, VT); 1629 case ISD::SETULT: 1630 case ISD::SETULE: 1631 case ISD::SETNE: return DAG.getConstant(1, VT); 1632 case ISD::SETGT: 1633 case ISD::SETGE: 1634 // True if the sign bit of C1 is set. 1635 return DAG.getConstant(C1.isNegative(), VT); 1636 case ISD::SETLT: 1637 case ISD::SETLE: 1638 // True if the sign bit of C1 isn't set. 1639 return DAG.getConstant(C1.isNonNegative(), VT); 1640 default: 1641 break; 1642 } 1643 } 1644 1645 // Otherwise, we can perform the comparison with the low bits. 1646 switch (Cond) { 1647 case ISD::SETEQ: 1648 case ISD::SETNE: 1649 case ISD::SETUGT: 1650 case ISD::SETUGE: 1651 case ISD::SETULT: 1652 case ISD::SETULE: { 1653 MVT newVT = N0.getOperand(0).getValueType(); 1654 if (DCI.isBeforeLegalizeOps() || 1655 (isOperationLegal(ISD::SETCC, newVT) && 1656 getCondCodeAction(Cond, newVT)==Legal)) 1657 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1658 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1659 Cond); 1660 break; 1661 } 1662 default: 1663 break; // todo, be more careful with signed comparisons 1664 } 1665 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1666 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1667 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1668 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1669 MVT ExtDstTy = N0.getValueType(); 1670 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1671 1672 // If the extended part has any inconsistent bits, it cannot ever 1673 // compare equal. In other words, they have to be all ones or all 1674 // zeros. 1675 APInt ExtBits = 1676 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1677 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1678 return DAG.getConstant(Cond == ISD::SETNE, VT); 1679 1680 SDValue ZextOp; 1681 MVT Op0Ty = N0.getOperand(0).getValueType(); 1682 if (Op0Ty == ExtSrcTy) { 1683 ZextOp = N0.getOperand(0); 1684 } else { 1685 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1686 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1687 DAG.getConstant(Imm, Op0Ty)); 1688 } 1689 if (!DCI.isCalledByLegalizer()) 1690 DCI.AddToWorklist(ZextOp.getNode()); 1691 // Otherwise, make this a use of a zext. 1692 return DAG.getSetCC(dl, VT, ZextOp, 1693 DAG.getConstant(C1 & APInt::getLowBitsSet( 1694 ExtDstTyBits, 1695 ExtSrcTyBits), 1696 ExtDstTy), 1697 Cond); 1698 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1699 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1700 1701 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1702 if (N0.getOpcode() == ISD::SETCC) { 1703 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); 1704 if (TrueWhenTrue) 1705 return N0; 1706 1707 // Invert the condition. 1708 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1709 CC = ISD::getSetCCInverse(CC, 1710 N0.getOperand(0).getValueType().isInteger()); 1711 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1712 } 1713 1714 if ((N0.getOpcode() == ISD::XOR || 1715 (N0.getOpcode() == ISD::AND && 1716 N0.getOperand(0).getOpcode() == ISD::XOR && 1717 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1718 isa<ConstantSDNode>(N0.getOperand(1)) && 1719 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1720 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1721 // can only do this if the top bits are known zero. 1722 unsigned BitWidth = N0.getValueSizeInBits(); 1723 if (DAG.MaskedValueIsZero(N0, 1724 APInt::getHighBitsSet(BitWidth, 1725 BitWidth-1))) { 1726 // Okay, get the un-inverted input value. 1727 SDValue Val; 1728 if (N0.getOpcode() == ISD::XOR) 1729 Val = N0.getOperand(0); 1730 else { 1731 assert(N0.getOpcode() == ISD::AND && 1732 N0.getOperand(0).getOpcode() == ISD::XOR); 1733 // ((X^1)&1)^1 -> X & 1 1734 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1735 N0.getOperand(0).getOperand(0), 1736 N0.getOperand(1)); 1737 } 1738 return DAG.getSetCC(dl, VT, Val, N1, 1739 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1740 } 1741 } 1742 } 1743 1744 APInt MinVal, MaxVal; 1745 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1746 if (ISD::isSignedIntSetCC(Cond)) { 1747 MinVal = APInt::getSignedMinValue(OperandBitSize); 1748 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1749 } else { 1750 MinVal = APInt::getMinValue(OperandBitSize); 1751 MaxVal = APInt::getMaxValue(OperandBitSize); 1752 } 1753 1754 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1755 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1756 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1757 // X >= C0 --> X > (C0-1) 1758 return DAG.getSetCC(dl, VT, N0, 1759 DAG.getConstant(C1-1, N1.getValueType()), 1760 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1761 } 1762 1763 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1764 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1765 // X <= C0 --> X < (C0+1) 1766 return DAG.getSetCC(dl, VT, N0, 1767 DAG.getConstant(C1+1, N1.getValueType()), 1768 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1769 } 1770 1771 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1772 return DAG.getConstant(0, VT); // X < MIN --> false 1773 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1774 return DAG.getConstant(1, VT); // X >= MIN --> true 1775 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1776 return DAG.getConstant(0, VT); // X > MAX --> false 1777 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1778 return DAG.getConstant(1, VT); // X <= MAX --> true 1779 1780 // Canonicalize setgt X, Min --> setne X, Min 1781 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1782 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1783 // Canonicalize setlt X, Max --> setne X, Max 1784 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1785 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1786 1787 // If we have setult X, 1, turn it into seteq X, 0 1788 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1789 return DAG.getSetCC(dl, VT, N0, 1790 DAG.getConstant(MinVal, N0.getValueType()), 1791 ISD::SETEQ); 1792 // If we have setugt X, Max-1, turn it into seteq X, Max 1793 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1794 return DAG.getSetCC(dl, VT, N0, 1795 DAG.getConstant(MaxVal, N0.getValueType()), 1796 ISD::SETEQ); 1797 1798 // If we have "setcc X, C0", check to see if we can shrink the immediate 1799 // by changing cc. 1800 1801 // SETUGT X, SINTMAX -> SETLT X, 0 1802 if (Cond == ISD::SETUGT && 1803 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1804 return DAG.getSetCC(dl, VT, N0, 1805 DAG.getConstant(0, N1.getValueType()), 1806 ISD::SETLT); 1807 1808 // SETULT X, SINTMIN -> SETGT X, -1 1809 if (Cond == ISD::SETULT && 1810 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1811 SDValue ConstMinusOne = 1812 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1813 N1.getValueType()); 1814 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1815 } 1816 1817 // Fold bit comparisons when we can. 1818 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1819 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1820 if (ConstantSDNode *AndRHS = 1821 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1822 MVT ShiftTy = DCI.isBeforeLegalize() ? 1823 getPointerTy() : getShiftAmountTy(); 1824 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1825 // Perform the xform if the AND RHS is a single bit. 1826 if (isPowerOf2_64(AndRHS->getZExtValue())) { 1827 return DAG.getNode(ISD::SRL, dl, VT, N0, 1828 DAG.getConstant(Log2_64(AndRHS->getZExtValue()), 1829 ShiftTy)); 1830 } 1831 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { 1832 // (X & 8) == 8 --> (X & 8) >> 3 1833 // Perform the xform if C1 is a single bit. 1834 if (C1.isPowerOf2()) { 1835 return DAG.getNode(ISD::SRL, dl, VT, N0, 1836 DAG.getConstant(C1.logBase2(), ShiftTy)); 1837 } 1838 } 1839 } 1840 } 1841 1842 if (isa<ConstantFPSDNode>(N0.getNode())) { 1843 // Constant fold or commute setcc. 1844 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1845 if (O.getNode()) return O; 1846 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1847 // If the RHS of an FP comparison is a constant, simplify it away in 1848 // some cases. 1849 if (CFP->getValueAPF().isNaN()) { 1850 // If an operand is known to be a nan, we can fold it. 1851 switch (ISD::getUnorderedFlavor(Cond)) { 1852 default: llvm_unreachable("Unknown flavor!"); 1853 case 0: // Known false. 1854 return DAG.getConstant(0, VT); 1855 case 1: // Known true. 1856 return DAG.getConstant(1, VT); 1857 case 2: // Undefined. 1858 return DAG.getUNDEF(VT); 1859 } 1860 } 1861 1862 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1863 // constant if knowing that the operand is non-nan is enough. We prefer to 1864 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1865 // materialize 0.0. 1866 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1867 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1868 } 1869 1870 if (N0 == N1) { 1871 // We can always fold X == X for integer setcc's. 1872 if (N0.getValueType().isInteger()) 1873 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1874 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1875 if (UOF == 2) // FP operators that are undefined on NaNs. 1876 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 1877 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1878 return DAG.getConstant(UOF, VT); 1879 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1880 // if it is not already. 1881 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1882 if (NewCond != Cond) 1883 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1884 } 1885 1886 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1887 N0.getValueType().isInteger()) { 1888 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1889 N0.getOpcode() == ISD::XOR) { 1890 // Simplify (X+Y) == (X+Z) --> Y == Z 1891 if (N0.getOpcode() == N1.getOpcode()) { 1892 if (N0.getOperand(0) == N1.getOperand(0)) 1893 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1894 if (N0.getOperand(1) == N1.getOperand(1)) 1895 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1896 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1897 // If X op Y == Y op X, try other combinations. 1898 if (N0.getOperand(0) == N1.getOperand(1)) 1899 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1900 Cond); 1901 if (N0.getOperand(1) == N1.getOperand(0)) 1902 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1903 Cond); 1904 } 1905 } 1906 1907 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1908 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1909 // Turn (X+C1) == C2 --> X == C2-C1 1910 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1911 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1912 DAG.getConstant(RHSC->getAPIntValue()- 1913 LHSR->getAPIntValue(), 1914 N0.getValueType()), Cond); 1915 } 1916 1917 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1918 if (N0.getOpcode() == ISD::XOR) 1919 // If we know that all of the inverted bits are zero, don't bother 1920 // performing the inversion. 1921 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1922 return 1923 DAG.getSetCC(dl, VT, N0.getOperand(0), 1924 DAG.getConstant(LHSR->getAPIntValue() ^ 1925 RHSC->getAPIntValue(), 1926 N0.getValueType()), 1927 Cond); 1928 } 1929 1930 // Turn (C1-X) == C2 --> X == C1-C2 1931 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1932 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1933 return 1934 DAG.getSetCC(dl, VT, N0.getOperand(1), 1935 DAG.getConstant(SUBC->getAPIntValue() - 1936 RHSC->getAPIntValue(), 1937 N0.getValueType()), 1938 Cond); 1939 } 1940 } 1941 } 1942 1943 // Simplify (X+Z) == X --> Z == 0 1944 if (N0.getOperand(0) == N1) 1945 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1946 DAG.getConstant(0, N0.getValueType()), Cond); 1947 if (N0.getOperand(1) == N1) { 1948 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1949 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1950 DAG.getConstant(0, N0.getValueType()), Cond); 1951 else if (N0.getNode()->hasOneUse()) { 1952 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1953 // (Z-X) == X --> Z == X<<1 1954 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 1955 N1, 1956 DAG.getConstant(1, getShiftAmountTy())); 1957 if (!DCI.isCalledByLegalizer()) 1958 DCI.AddToWorklist(SH.getNode()); 1959 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1960 } 1961 } 1962 } 1963 1964 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1965 N1.getOpcode() == ISD::XOR) { 1966 // Simplify X == (X+Z) --> Z == 0 1967 if (N1.getOperand(0) == N0) { 1968 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1969 DAG.getConstant(0, N1.getValueType()), Cond); 1970 } else if (N1.getOperand(1) == N0) { 1971 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 1972 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1973 DAG.getConstant(0, N1.getValueType()), Cond); 1974 } else if (N1.getNode()->hasOneUse()) { 1975 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1976 // X == (Z-X) --> X<<1 == Z 1977 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1978 DAG.getConstant(1, getShiftAmountTy())); 1979 if (!DCI.isCalledByLegalizer()) 1980 DCI.AddToWorklist(SH.getNode()); 1981 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1982 } 1983 } 1984 } 1985 1986 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1987 // Note that where y is variable and is known to have at most 1988 // one bit set (for example, if it is z&1) we cannot do this; 1989 // the expressions are not equivalent when y==0. 1990 if (N0.getOpcode() == ISD::AND) 1991 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1992 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1993 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1994 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1995 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1996 } 1997 } 1998 if (N1.getOpcode() == ISD::AND) 1999 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2000 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2001 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2002 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2003 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2004 } 2005 } 2006 } 2007 2008 // Fold away ALL boolean setcc's. 2009 SDValue Temp; 2010 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2011 switch (Cond) { 2012 default: llvm_unreachable("Unknown integer setcc!"); 2013 case ISD::SETEQ: // X == Y -> ~(X^Y) 2014 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2015 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2016 if (!DCI.isCalledByLegalizer()) 2017 DCI.AddToWorklist(Temp.getNode()); 2018 break; 2019 case ISD::SETNE: // X != Y --> (X^Y) 2020 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2021 break; 2022 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2023 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2024 Temp = DAG.getNOT(dl, N0, MVT::i1); 2025 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2026 if (!DCI.isCalledByLegalizer()) 2027 DCI.AddToWorklist(Temp.getNode()); 2028 break; 2029 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2030 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2031 Temp = DAG.getNOT(dl, N1, MVT::i1); 2032 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2033 if (!DCI.isCalledByLegalizer()) 2034 DCI.AddToWorklist(Temp.getNode()); 2035 break; 2036 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2037 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2038 Temp = DAG.getNOT(dl, N0, MVT::i1); 2039 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2040 if (!DCI.isCalledByLegalizer()) 2041 DCI.AddToWorklist(Temp.getNode()); 2042 break; 2043 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2044 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2045 Temp = DAG.getNOT(dl, N1, MVT::i1); 2046 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2047 break; 2048 } 2049 if (VT != MVT::i1) { 2050 if (!DCI.isCalledByLegalizer()) 2051 DCI.AddToWorklist(N0.getNode()); 2052 // FIXME: If running after legalize, we probably can't do this. 2053 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2054 } 2055 return N0; 2056 } 2057 2058 // Could not fold it. 2059 return SDValue(); 2060} 2061 2062/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2063/// node is a GlobalAddress + offset. 2064bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, 2065 int64_t &Offset) const { 2066 if (isa<GlobalAddressSDNode>(N)) { 2067 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2068 GA = GASD->getGlobal(); 2069 Offset += GASD->getOffset(); 2070 return true; 2071 } 2072 2073 if (N->getOpcode() == ISD::ADD) { 2074 SDValue N1 = N->getOperand(0); 2075 SDValue N2 = N->getOperand(1); 2076 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2077 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2078 if (V) { 2079 Offset += V->getSExtValue(); 2080 return true; 2081 } 2082 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2083 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2084 if (V) { 2085 Offset += V->getSExtValue(); 2086 return true; 2087 } 2088 } 2089 } 2090 return false; 2091} 2092 2093 2094/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 2095/// location that is 'Dist' units away from the location that the 'Base' load 2096/// is loading from. 2097bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, 2098 unsigned Bytes, int Dist, 2099 const MachineFrameInfo *MFI) const { 2100 if (LD->getChain() != Base->getChain()) 2101 return false; 2102 MVT VT = LD->getValueType(0); 2103 if (VT.getSizeInBits() / 8 != Bytes) 2104 return false; 2105 2106 SDValue Loc = LD->getOperand(1); 2107 SDValue BaseLoc = Base->getOperand(1); 2108 if (Loc.getOpcode() == ISD::FrameIndex) { 2109 if (BaseLoc.getOpcode() != ISD::FrameIndex) 2110 return false; 2111 int FI = cast<FrameIndexSDNode>(Loc)->getIndex(); 2112 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex(); 2113 int FS = MFI->getObjectSize(FI); 2114 int BFS = MFI->getObjectSize(BFI); 2115 if (FS != BFS || FS != (int)Bytes) return false; 2116 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes); 2117 } 2118 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) { 2119 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1)); 2120 if (V && (V->getSExtValue() == Dist*Bytes)) 2121 return true; 2122 } 2123 2124 GlobalValue *GV1 = NULL; 2125 GlobalValue *GV2 = NULL; 2126 int64_t Offset1 = 0; 2127 int64_t Offset2 = 0; 2128 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); 2129 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); 2130 if (isGA1 && isGA2 && GV1 == GV2) 2131 return Offset1 == (Offset2 + Dist*Bytes); 2132 return false; 2133} 2134 2135 2136SDValue TargetLowering:: 2137PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2138 // Default implementation: no optimization. 2139 return SDValue(); 2140} 2141 2142//===----------------------------------------------------------------------===// 2143// Inline Assembler Implementation Methods 2144//===----------------------------------------------------------------------===// 2145 2146 2147TargetLowering::ConstraintType 2148TargetLowering::getConstraintType(const std::string &Constraint) const { 2149 // FIXME: lots more standard ones to handle. 2150 if (Constraint.size() == 1) { 2151 switch (Constraint[0]) { 2152 default: break; 2153 case 'r': return C_RegisterClass; 2154 case 'm': // memory 2155 case 'o': // offsetable 2156 case 'V': // not offsetable 2157 return C_Memory; 2158 case 'i': // Simple Integer or Relocatable Constant 2159 case 'n': // Simple Integer 2160 case 's': // Relocatable Constant 2161 case 'X': // Allow ANY value. 2162 case 'I': // Target registers. 2163 case 'J': 2164 case 'K': 2165 case 'L': 2166 case 'M': 2167 case 'N': 2168 case 'O': 2169 case 'P': 2170 return C_Other; 2171 } 2172 } 2173 2174 if (Constraint.size() > 1 && Constraint[0] == '{' && 2175 Constraint[Constraint.size()-1] == '}') 2176 return C_Register; 2177 return C_Unknown; 2178} 2179 2180/// LowerXConstraint - try to replace an X constraint, which matches anything, 2181/// with another that has more specific requirements based on the type of the 2182/// corresponding operand. 2183const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ 2184 if (ConstraintVT.isInteger()) 2185 return "r"; 2186 if (ConstraintVT.isFloatingPoint()) 2187 return "f"; // works for many targets 2188 return 0; 2189} 2190 2191/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2192/// vector. If it is invalid, don't add anything to Ops. 2193void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2194 char ConstraintLetter, 2195 bool hasMemory, 2196 std::vector<SDValue> &Ops, 2197 SelectionDAG &DAG) const { 2198 switch (ConstraintLetter) { 2199 default: break; 2200 case 'X': // Allows any operand; labels (basic block) use this. 2201 if (Op.getOpcode() == ISD::BasicBlock) { 2202 Ops.push_back(Op); 2203 return; 2204 } 2205 // fall through 2206 case 'i': // Simple Integer or Relocatable Constant 2207 case 'n': // Simple Integer 2208 case 's': { // Relocatable Constant 2209 // These operands are interested in values of the form (GV+C), where C may 2210 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2211 // is possible and fine if either GV or C are missing. 2212 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2213 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2214 2215 // If we have "(add GV, C)", pull out GV/C 2216 if (Op.getOpcode() == ISD::ADD) { 2217 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2218 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2219 if (C == 0 || GA == 0) { 2220 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2221 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2222 } 2223 if (C == 0 || GA == 0) 2224 C = 0, GA = 0; 2225 } 2226 2227 // If we find a valid operand, map to the TargetXXX version so that the 2228 // value itself doesn't get selected. 2229 if (GA) { // Either &GV or &GV+C 2230 if (ConstraintLetter != 'n') { 2231 int64_t Offs = GA->getOffset(); 2232 if (C) Offs += C->getZExtValue(); 2233 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2234 Op.getValueType(), Offs)); 2235 return; 2236 } 2237 } 2238 if (C) { // just C, no GV. 2239 // Simple constants are not allowed for 's'. 2240 if (ConstraintLetter != 's') { 2241 // gcc prints these as sign extended. Sign extend value to 64 bits 2242 // now; without this it would get ZExt'd later in 2243 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2244 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2245 MVT::i64)); 2246 return; 2247 } 2248 } 2249 break; 2250 } 2251 } 2252} 2253 2254std::vector<unsigned> TargetLowering:: 2255getRegClassForInlineAsmConstraint(const std::string &Constraint, 2256 MVT VT) const { 2257 return std::vector<unsigned>(); 2258} 2259 2260 2261std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2262getRegForInlineAsmConstraint(const std::string &Constraint, 2263 MVT VT) const { 2264 if (Constraint[0] != '{') 2265 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2266 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2267 2268 // Remove the braces from around the name. 2269 std::string RegName(Constraint.begin()+1, Constraint.end()-1); 2270 2271 // Figure out which register class contains this reg. 2272 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2273 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2274 E = RI->regclass_end(); RCI != E; ++RCI) { 2275 const TargetRegisterClass *RC = *RCI; 2276 2277 // If none of the the value types for this register class are valid, we 2278 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2279 bool isLegal = false; 2280 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2281 I != E; ++I) { 2282 if (isTypeLegal(*I)) { 2283 isLegal = true; 2284 break; 2285 } 2286 } 2287 2288 if (!isLegal) continue; 2289 2290 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2291 I != E; ++I) { 2292 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName)) 2293 return std::make_pair(*I, RC); 2294 } 2295 } 2296 2297 return std::pair<unsigned, const TargetRegisterClass*>(0, 0); 2298} 2299 2300//===----------------------------------------------------------------------===// 2301// Constraint Selection. 2302 2303/// isMatchingInputConstraint - Return true of this is an input operand that is 2304/// a matching constraint like "4". 2305bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2306 assert(!ConstraintCode.empty() && "No known constraint!"); 2307 return isdigit(ConstraintCode[0]); 2308} 2309 2310/// getMatchedOperand - If this is an input matching constraint, this method 2311/// returns the output operand it matches. 2312unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2313 assert(!ConstraintCode.empty() && "No known constraint!"); 2314 return atoi(ConstraintCode.c_str()); 2315} 2316 2317 2318/// getConstraintGenerality - Return an integer indicating how general CT 2319/// is. 2320static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2321 switch (CT) { 2322 default: llvm_unreachable("Unknown constraint type!"); 2323 case TargetLowering::C_Other: 2324 case TargetLowering::C_Unknown: 2325 return 0; 2326 case TargetLowering::C_Register: 2327 return 1; 2328 case TargetLowering::C_RegisterClass: 2329 return 2; 2330 case TargetLowering::C_Memory: 2331 return 3; 2332 } 2333} 2334 2335/// ChooseConstraint - If there are multiple different constraints that we 2336/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2337/// This is somewhat tricky: constraints fall into four classes: 2338/// Other -> immediates and magic values 2339/// Register -> one specific register 2340/// RegisterClass -> a group of regs 2341/// Memory -> memory 2342/// Ideally, we would pick the most specific constraint possible: if we have 2343/// something that fits into a register, we would pick it. The problem here 2344/// is that if we have something that could either be in a register or in 2345/// memory that use of the register could cause selection of *other* 2346/// operands to fail: they might only succeed if we pick memory. Because of 2347/// this the heuristic we use is: 2348/// 2349/// 1) If there is an 'other' constraint, and if the operand is valid for 2350/// that constraint, use it. This makes us take advantage of 'i' 2351/// constraints when available. 2352/// 2) Otherwise, pick the most general constraint present. This prefers 2353/// 'm' over 'r', for example. 2354/// 2355static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2356 bool hasMemory, const TargetLowering &TLI, 2357 SDValue Op, SelectionDAG *DAG) { 2358 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2359 unsigned BestIdx = 0; 2360 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2361 int BestGenerality = -1; 2362 2363 // Loop over the options, keeping track of the most general one. 2364 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2365 TargetLowering::ConstraintType CType = 2366 TLI.getConstraintType(OpInfo.Codes[i]); 2367 2368 // If this is an 'other' constraint, see if the operand is valid for it. 2369 // For example, on X86 we might have an 'rI' constraint. If the operand 2370 // is an integer in the range [0..31] we want to use I (saving a load 2371 // of a register), otherwise we must use 'r'. 2372 if (CType == TargetLowering::C_Other && Op.getNode()) { 2373 assert(OpInfo.Codes[i].size() == 1 && 2374 "Unhandled multi-letter 'other' constraint"); 2375 std::vector<SDValue> ResultOps; 2376 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, 2377 ResultOps, *DAG); 2378 if (!ResultOps.empty()) { 2379 BestType = CType; 2380 BestIdx = i; 2381 break; 2382 } 2383 } 2384 2385 // This constraint letter is more general than the previous one, use it. 2386 int Generality = getConstraintGenerality(CType); 2387 if (Generality > BestGenerality) { 2388 BestType = CType; 2389 BestIdx = i; 2390 BestGenerality = Generality; 2391 } 2392 } 2393 2394 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2395 OpInfo.ConstraintType = BestType; 2396} 2397 2398/// ComputeConstraintToUse - Determines the constraint code and constraint 2399/// type to use for the specific AsmOperandInfo, setting 2400/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2401void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2402 SDValue Op, 2403 bool hasMemory, 2404 SelectionDAG *DAG) const { 2405 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2406 2407 // Single-letter constraints ('r') are very common. 2408 if (OpInfo.Codes.size() == 1) { 2409 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2410 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2411 } else { 2412 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); 2413 } 2414 2415 // 'X' matches anything. 2416 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2417 // Labels and constants are handled elsewhere ('X' is the only thing 2418 // that matches labels). For Functions, the type here is the type of 2419 // the result, which is not what we want to look at; leave them alone. 2420 Value *v = OpInfo.CallOperandVal; 2421 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2422 OpInfo.CallOperandVal = v; 2423 return; 2424 } 2425 2426 // Otherwise, try to resolve it to something we know about by looking at 2427 // the actual operand type. 2428 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2429 OpInfo.ConstraintCode = Repl; 2430 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2431 } 2432 } 2433} 2434 2435//===----------------------------------------------------------------------===// 2436// Loop Strength Reduction hooks 2437//===----------------------------------------------------------------------===// 2438 2439/// isLegalAddressingMode - Return true if the addressing mode represented 2440/// by AM is legal for this target, for a load/store of the specified type. 2441bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2442 const Type *Ty) const { 2443 // The default implementation of this implements a conservative RISCy, r+r and 2444 // r+i addr mode. 2445 2446 // Allows a sign-extended 16-bit immediate field. 2447 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2448 return false; 2449 2450 // No global is ever allowed as a base. 2451 if (AM.BaseGV) 2452 return false; 2453 2454 // Only support r+r, 2455 switch (AM.Scale) { 2456 case 0: // "r+i" or just "i", depending on HasBaseReg. 2457 break; 2458 case 1: 2459 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2460 return false; 2461 // Otherwise we have r+r or r+i. 2462 break; 2463 case 2: 2464 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2465 return false; 2466 // Allow 2*r as r+r. 2467 break; 2468 } 2469 2470 return true; 2471} 2472 2473/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2474/// return a DAG expression to select that will generate the same value by 2475/// multiplying by a magic number. See: 2476/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2477SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2478 std::vector<SDNode*>* Created) const { 2479 MVT VT = N->getValueType(0); 2480 DebugLoc dl= N->getDebugLoc(); 2481 2482 // Check to see if we can do this. 2483 // FIXME: We should be more aggressive here. 2484 if (!isTypeLegal(VT)) 2485 return SDValue(); 2486 2487 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2488 APInt::ms magics = d.magic(); 2489 2490 // Multiply the numerator (operand 0) by the magic value 2491 // FIXME: We should support doing a MUL in a wider type 2492 SDValue Q; 2493 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2494 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2495 DAG.getConstant(magics.m, VT)); 2496 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2497 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2498 N->getOperand(0), 2499 DAG.getConstant(magics.m, VT)).getNode(), 1); 2500 else 2501 return SDValue(); // No mulhs or equvialent 2502 // If d > 0 and m < 0, add the numerator 2503 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2504 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2505 if (Created) 2506 Created->push_back(Q.getNode()); 2507 } 2508 // If d < 0 and m > 0, subtract the numerator. 2509 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2510 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2511 if (Created) 2512 Created->push_back(Q.getNode()); 2513 } 2514 // Shift right algebraic if shift value is nonzero 2515 if (magics.s > 0) { 2516 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2517 DAG.getConstant(magics.s, getShiftAmountTy())); 2518 if (Created) 2519 Created->push_back(Q.getNode()); 2520 } 2521 // Extract the sign bit and add it to the quotient 2522 SDValue T = 2523 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2524 getShiftAmountTy())); 2525 if (Created) 2526 Created->push_back(T.getNode()); 2527 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2528} 2529 2530/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2531/// return a DAG expression to select that will generate the same value by 2532/// multiplying by a magic number. See: 2533/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2534SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2535 std::vector<SDNode*>* Created) const { 2536 MVT VT = N->getValueType(0); 2537 DebugLoc dl = N->getDebugLoc(); 2538 2539 // Check to see if we can do this. 2540 // FIXME: We should be more aggressive here. 2541 if (!isTypeLegal(VT)) 2542 return SDValue(); 2543 2544 // FIXME: We should use a narrower constant when the upper 2545 // bits are known to be zero. 2546 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2547 APInt::mu magics = N1C->getAPIntValue().magicu(); 2548 2549 // Multiply the numerator (operand 0) by the magic value 2550 // FIXME: We should support doing a MUL in a wider type 2551 SDValue Q; 2552 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2553 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2554 DAG.getConstant(magics.m, VT)); 2555 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2556 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2557 N->getOperand(0), 2558 DAG.getConstant(magics.m, VT)).getNode(), 1); 2559 else 2560 return SDValue(); // No mulhu or equvialent 2561 if (Created) 2562 Created->push_back(Q.getNode()); 2563 2564 if (magics.a == 0) { 2565 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2566 "We shouldn't generate an undefined shift!"); 2567 return DAG.getNode(ISD::SRL, dl, VT, Q, 2568 DAG.getConstant(magics.s, getShiftAmountTy())); 2569 } else { 2570 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2571 if (Created) 2572 Created->push_back(NPQ.getNode()); 2573 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2574 DAG.getConstant(1, getShiftAmountTy())); 2575 if (Created) 2576 Created->push_back(NPQ.getNode()); 2577 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2578 if (Created) 2579 Created->push_back(NPQ.getNode()); 2580 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2581 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2582 } 2583} 2584 2585/// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET 2586/// node that don't prevent tail call optimization. 2587static SDValue IgnoreHarmlessInstructions(SDValue node) { 2588 // Found call return. 2589 if (node.getOpcode() == ISD::CALL) return node; 2590 // Ignore MERGE_VALUES. Will have at least one operand. 2591 if (node.getOpcode() == ISD::MERGE_VALUES) 2592 return IgnoreHarmlessInstructions(node.getOperand(0)); 2593 // Ignore ANY_EXTEND node. 2594 if (node.getOpcode() == ISD::ANY_EXTEND) 2595 return IgnoreHarmlessInstructions(node.getOperand(0)); 2596 if (node.getOpcode() == ISD::TRUNCATE) 2597 return IgnoreHarmlessInstructions(node.getOperand(0)); 2598 // Any other node type. 2599 return node; 2600} 2601 2602bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall, 2603 SDValue Ret) { 2604 unsigned NumOps = Ret.getNumOperands(); 2605 // ISD::CALL results:(value0, ..., valuen, chain) 2606 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn) 2607 // Value return: 2608 // Check that operand of the RET node sources from the CALL node. The RET node 2609 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the 2610 // value. 2611 // Also we need to check that there is no code in between the call and the 2612 // return. Hence we also check that the incomming chain to the return sources 2613 // from the outgoing chain of the call. 2614 if (NumOps > 1 && 2615 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0) && 2616 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2617 return true; 2618 // void return: The RET node has the chain result value of the CALL node as 2619 // input. 2620 if (NumOps == 1 && 2621 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1)) 2622 return true; 2623 2624 return false; 2625} 2626