TargetLowering.cpp revision f423a69839c4810b890f8a8b09fb8cfbd6bf0139
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/MC/MCAsmInfo.h" 16#include "llvm/MC/MCExpr.h" 17#include "llvm/Target/TargetData.h" 18#include "llvm/Target/TargetLoweringObjectFile.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/GlobalVariable.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/CodeGen/Analysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineJumpTableInfo.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33namespace llvm { 34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52} 53} 54 55/// InitLibcallNames - Set default libcall names. 56/// 57static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 245 Names[RTLIB::OEQ_F32] = "__eqsf2"; 246 Names[RTLIB::OEQ_F64] = "__eqdf2"; 247 Names[RTLIB::UNE_F32] = "__nesf2"; 248 Names[RTLIB::UNE_F64] = "__nedf2"; 249 Names[RTLIB::OGE_F32] = "__gesf2"; 250 Names[RTLIB::OGE_F64] = "__gedf2"; 251 Names[RTLIB::OLT_F32] = "__ltsf2"; 252 Names[RTLIB::OLT_F64] = "__ltdf2"; 253 Names[RTLIB::OLE_F32] = "__lesf2"; 254 Names[RTLIB::OLE_F64] = "__ledf2"; 255 Names[RTLIB::OGT_F32] = "__gtsf2"; 256 Names[RTLIB::OGT_F64] = "__gtdf2"; 257 Names[RTLIB::UO_F32] = "__unordsf2"; 258 Names[RTLIB::UO_F64] = "__unorddf2"; 259 Names[RTLIB::O_F32] = "__unordsf2"; 260 Names[RTLIB::O_F64] = "__unorddf2"; 261 Names[RTLIB::MEMCPY] = "memcpy"; 262 Names[RTLIB::MEMMOVE] = "memmove"; 263 Names[RTLIB::MEMSET] = "memset"; 264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 297} 298 299/// InitLibcallCallingConvs - Set default libcall CallingConvs. 300/// 301static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 303 CCs[i] = CallingConv::C; 304 } 305} 306 307/// getFPEXT - Return the FPEXT_*_* value for the given types, or 308/// UNKNOWN_LIBCALL if there is none. 309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 310 if (OpVT == MVT::f32) { 311 if (RetVT == MVT::f64) 312 return FPEXT_F32_F64; 313 } 314 315 return UNKNOWN_LIBCALL; 316} 317 318/// getFPROUND - Return the FPROUND_*_* value for the given types, or 319/// UNKNOWN_LIBCALL if there is none. 320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 321 if (RetVT == MVT::f32) { 322 if (OpVT == MVT::f64) 323 return FPROUND_F64_F32; 324 if (OpVT == MVT::f80) 325 return FPROUND_F80_F32; 326 if (OpVT == MVT::ppcf128) 327 return FPROUND_PPCF128_F32; 328 } else if (RetVT == MVT::f64) { 329 if (OpVT == MVT::f80) 330 return FPROUND_F80_F64; 331 if (OpVT == MVT::ppcf128) 332 return FPROUND_PPCF128_F64; 333 } 334 335 return UNKNOWN_LIBCALL; 336} 337 338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 339/// UNKNOWN_LIBCALL if there is none. 340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 341 if (OpVT == MVT::f32) { 342 if (RetVT == MVT::i8) 343 return FPTOSINT_F32_I8; 344 if (RetVT == MVT::i16) 345 return FPTOSINT_F32_I16; 346 if (RetVT == MVT::i32) 347 return FPTOSINT_F32_I32; 348 if (RetVT == MVT::i64) 349 return FPTOSINT_F32_I64; 350 if (RetVT == MVT::i128) 351 return FPTOSINT_F32_I128; 352 } else if (OpVT == MVT::f64) { 353 if (RetVT == MVT::i8) 354 return FPTOSINT_F64_I8; 355 if (RetVT == MVT::i16) 356 return FPTOSINT_F64_I16; 357 if (RetVT == MVT::i32) 358 return FPTOSINT_F64_I32; 359 if (RetVT == MVT::i64) 360 return FPTOSINT_F64_I64; 361 if (RetVT == MVT::i128) 362 return FPTOSINT_F64_I128; 363 } else if (OpVT == MVT::f80) { 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F80_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F80_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F80_I128; 370 } else if (OpVT == MVT::ppcf128) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_PPCF128_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_PPCF128_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_PPCF128_I128; 377 } 378 return UNKNOWN_LIBCALL; 379} 380 381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 382/// UNKNOWN_LIBCALL if there is none. 383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 384 if (OpVT == MVT::f32) { 385 if (RetVT == MVT::i8) 386 return FPTOUINT_F32_I8; 387 if (RetVT == MVT::i16) 388 return FPTOUINT_F32_I16; 389 if (RetVT == MVT::i32) 390 return FPTOUINT_F32_I32; 391 if (RetVT == MVT::i64) 392 return FPTOUINT_F32_I64; 393 if (RetVT == MVT::i128) 394 return FPTOUINT_F32_I128; 395 } else if (OpVT == MVT::f64) { 396 if (RetVT == MVT::i8) 397 return FPTOUINT_F64_I8; 398 if (RetVT == MVT::i16) 399 return FPTOUINT_F64_I16; 400 if (RetVT == MVT::i32) 401 return FPTOUINT_F64_I32; 402 if (RetVT == MVT::i64) 403 return FPTOUINT_F64_I64; 404 if (RetVT == MVT::i128) 405 return FPTOUINT_F64_I128; 406 } else if (OpVT == MVT::f80) { 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F80_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F80_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F80_I128; 413 } else if (OpVT == MVT::ppcf128) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_PPCF128_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_PPCF128_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_PPCF128_I128; 420 } 421 return UNKNOWN_LIBCALL; 422} 423 424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 425/// UNKNOWN_LIBCALL if there is none. 426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 427 if (OpVT == MVT::i32) { 428 if (RetVT == MVT::f32) 429 return SINTTOFP_I32_F32; 430 else if (RetVT == MVT::f64) 431 return SINTTOFP_I32_F64; 432 else if (RetVT == MVT::f80) 433 return SINTTOFP_I32_F80; 434 else if (RetVT == MVT::ppcf128) 435 return SINTTOFP_I32_PPCF128; 436 } else if (OpVT == MVT::i64) { 437 if (RetVT == MVT::f32) 438 return SINTTOFP_I64_F32; 439 else if (RetVT == MVT::f64) 440 return SINTTOFP_I64_F64; 441 else if (RetVT == MVT::f80) 442 return SINTTOFP_I64_F80; 443 else if (RetVT == MVT::ppcf128) 444 return SINTTOFP_I64_PPCF128; 445 } else if (OpVT == MVT::i128) { 446 if (RetVT == MVT::f32) 447 return SINTTOFP_I128_F32; 448 else if (RetVT == MVT::f64) 449 return SINTTOFP_I128_F64; 450 else if (RetVT == MVT::f80) 451 return SINTTOFP_I128_F80; 452 else if (RetVT == MVT::ppcf128) 453 return SINTTOFP_I128_PPCF128; 454 } 455 return UNKNOWN_LIBCALL; 456} 457 458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 459/// UNKNOWN_LIBCALL if there is none. 460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 461 if (OpVT == MVT::i32) { 462 if (RetVT == MVT::f32) 463 return UINTTOFP_I32_F32; 464 else if (RetVT == MVT::f64) 465 return UINTTOFP_I32_F64; 466 else if (RetVT == MVT::f80) 467 return UINTTOFP_I32_F80; 468 else if (RetVT == MVT::ppcf128) 469 return UINTTOFP_I32_PPCF128; 470 } else if (OpVT == MVT::i64) { 471 if (RetVT == MVT::f32) 472 return UINTTOFP_I64_F32; 473 else if (RetVT == MVT::f64) 474 return UINTTOFP_I64_F64; 475 else if (RetVT == MVT::f80) 476 return UINTTOFP_I64_F80; 477 else if (RetVT == MVT::ppcf128) 478 return UINTTOFP_I64_PPCF128; 479 } else if (OpVT == MVT::i128) { 480 if (RetVT == MVT::f32) 481 return UINTTOFP_I128_F32; 482 else if (RetVT == MVT::f64) 483 return UINTTOFP_I128_F64; 484 else if (RetVT == MVT::f80) 485 return UINTTOFP_I128_F80; 486 else if (RetVT == MVT::ppcf128) 487 return UINTTOFP_I128_PPCF128; 488 } 489 return UNKNOWN_LIBCALL; 490} 491 492/// InitCmpLibcallCCs - Set default comparison libcall CC. 493/// 494static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 498 CCs[RTLIB::UNE_F32] = ISD::SETNE; 499 CCs[RTLIB::UNE_F64] = ISD::SETNE; 500 CCs[RTLIB::OGE_F32] = ISD::SETGE; 501 CCs[RTLIB::OGE_F64] = ISD::SETGE; 502 CCs[RTLIB::OLT_F32] = ISD::SETLT; 503 CCs[RTLIB::OLT_F64] = ISD::SETLT; 504 CCs[RTLIB::OLE_F32] = ISD::SETLE; 505 CCs[RTLIB::OLE_F64] = ISD::SETLE; 506 CCs[RTLIB::OGT_F32] = ISD::SETGT; 507 CCs[RTLIB::OGT_F64] = ISD::SETGT; 508 CCs[RTLIB::UO_F32] = ISD::SETNE; 509 CCs[RTLIB::UO_F64] = ISD::SETNE; 510 CCs[RTLIB::O_F32] = ISD::SETEQ; 511 CCs[RTLIB::O_F64] = ISD::SETEQ; 512} 513 514/// NOTE: The constructor takes ownership of TLOF. 515TargetLowering::TargetLowering(const TargetMachine &tm, 516 const TargetLoweringObjectFile *tlof) 517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 518 // All operations default to being supported. 519 memset(OpActions, 0, sizeof(OpActions)); 520 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 523 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 524 525 // Set default actions for various operations. 526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 527 // Default all indexed load / store to expand. 528 for (unsigned IM = (unsigned)ISD::PRE_INC; 529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 532 } 533 534 // These operations default to expand. 535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 537 } 538 539 // Most targets ignore the @llvm.prefetch intrinsic. 540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 541 542 // ConstantFP nodes default to expand. Targets can either change this to 543 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 544 // to optimize expansions for certain constants. 545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 548 549 // These library functions default to expand. 550 setOperationAction(ISD::FLOG , MVT::f64, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 552 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 553 setOperationAction(ISD::FEXP , MVT::f64, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 555 setOperationAction(ISD::FLOG , MVT::f32, Expand); 556 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 557 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 558 setOperationAction(ISD::FEXP , MVT::f32, Expand); 559 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 560 561 // Default ISD::TRAP to expand (which turns it into abort). 562 setOperationAction(ISD::TRAP, MVT::Other, Expand); 563 564 IsLittleEndian = TD->isLittleEndian(); 565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 569 benefitFromCodePlacementOpt = false; 570 UseUnderscoreSetJmp = false; 571 UseUnderscoreLongJmp = false; 572 SelectIsExpensive = false; 573 IntDivIsCheap = false; 574 Pow2DivIsCheap = false; 575 StackPointerRegisterToSaveRestore = 0; 576 ExceptionPointerRegister = 0; 577 ExceptionSelectorRegister = 0; 578 BooleanContents = UndefinedBooleanContent; 579 SchedPreferenceInfo = Sched::Latency; 580 JumpBufSize = 0; 581 JumpBufAlignment = 0; 582 PrefLoopAlignment = 0; 583 ShouldFoldAtomicFences = false; 584 585 InitLibcallNames(LibcallRoutineNames); 586 InitCmpLibcallCCs(CmpLibcallCCs); 587 InitLibcallCallingConvs(LibcallCallingConvs); 588} 589 590TargetLowering::~TargetLowering() { 591 delete &TLOF; 592} 593 594/// canOpTrap - Returns true if the operation can trap for the value type. 595/// VT must be a legal type. 596bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 597 assert(isTypeLegal(VT)); 598 switch (Op) { 599 default: 600 return false; 601 case ISD::FDIV: 602 case ISD::FREM: 603 case ISD::SDIV: 604 case ISD::UDIV: 605 case ISD::SREM: 606 case ISD::UREM: 607 return true; 608 } 609} 610 611 612static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 613 unsigned &NumIntermediates, 614 EVT &RegisterVT, 615 TargetLowering *TLI) { 616 // Figure out the right, legal destination reg to copy into. 617 unsigned NumElts = VT.getVectorNumElements(); 618 MVT EltTy = VT.getVectorElementType(); 619 620 unsigned NumVectorRegs = 1; 621 622 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 623 // could break down into LHS/RHS like LegalizeDAG does. 624 if (!isPowerOf2_32(NumElts)) { 625 NumVectorRegs = NumElts; 626 NumElts = 1; 627 } 628 629 // Divide the input until we get to a supported size. This will always 630 // end with a scalar if the target doesn't support vectors. 631 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 632 NumElts >>= 1; 633 NumVectorRegs <<= 1; 634 } 635 636 NumIntermediates = NumVectorRegs; 637 638 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 639 if (!TLI->isTypeLegal(NewVT)) 640 NewVT = EltTy; 641 IntermediateVT = NewVT; 642 643 EVT DestVT = TLI->getRegisterType(NewVT); 644 RegisterVT = DestVT; 645 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 646 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 647 648 // Otherwise, promotion or legal types use the same number of registers as 649 // the vector decimated to the appropriate level. 650 return NumVectorRegs; 651} 652 653/// computeRegisterProperties - Once all of the register classes are added, 654/// this allows us to compute derived properties we expose. 655void TargetLowering::computeRegisterProperties() { 656 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 657 "Too many value types for ValueTypeActions to hold!"); 658 659 // Everything defaults to needing one register. 660 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 661 NumRegistersForVT[i] = 1; 662 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 663 } 664 // ...except isVoid, which doesn't need any registers. 665 NumRegistersForVT[MVT::isVoid] = 0; 666 667 // Find the largest integer register class. 668 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 669 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 670 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 671 672 // Every integer value type larger than this largest register takes twice as 673 // many registers to represent as the previous ValueType. 674 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 675 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 676 if (!ExpandedVT.isInteger()) 677 break; 678 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 679 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 680 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 681 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 682 } 683 684 // Inspect all of the ValueType's smaller than the largest integer 685 // register to see which ones need promotion. 686 unsigned LegalIntReg = LargestIntReg; 687 for (unsigned IntReg = LargestIntReg - 1; 688 IntReg >= (unsigned)MVT::i1; --IntReg) { 689 EVT IVT = (MVT::SimpleValueType)IntReg; 690 if (isTypeLegal(IVT)) { 691 LegalIntReg = IntReg; 692 } else { 693 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 694 (MVT::SimpleValueType)LegalIntReg; 695 ValueTypeActions.setTypeAction(IVT, Promote); 696 } 697 } 698 699 // ppcf128 type is really two f64's. 700 if (!isTypeLegal(MVT::ppcf128)) { 701 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 702 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 703 TransformToType[MVT::ppcf128] = MVT::f64; 704 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 705 } 706 707 // Decide how to handle f64. If the target does not have native f64 support, 708 // expand it to i64 and we will be generating soft float library calls. 709 if (!isTypeLegal(MVT::f64)) { 710 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 711 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 712 TransformToType[MVT::f64] = MVT::i64; 713 ValueTypeActions.setTypeAction(MVT::f64, Expand); 714 } 715 716 // Decide how to handle f32. If the target does not have native support for 717 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 718 if (!isTypeLegal(MVT::f32)) { 719 if (isTypeLegal(MVT::f64)) { 720 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 721 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 722 TransformToType[MVT::f32] = MVT::f64; 723 ValueTypeActions.setTypeAction(MVT::f32, Promote); 724 } else { 725 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 726 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 727 TransformToType[MVT::f32] = MVT::i32; 728 ValueTypeActions.setTypeAction(MVT::f32, Expand); 729 } 730 } 731 732 // Loop over all of the vector value types to see which need transformations. 733 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 734 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 735 MVT VT = (MVT::SimpleValueType)i; 736 if (isTypeLegal(VT)) continue; 737 738 MVT IntermediateVT; 739 EVT RegisterVT; 740 unsigned NumIntermediates; 741 NumRegistersForVT[i] = 742 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 743 RegisterVT, this); 744 RegisterTypeForVT[i] = RegisterVT; 745 746 // Determine if there is a legal wider type. 747 bool IsLegalWiderType = false; 748 EVT EltVT = VT.getVectorElementType(); 749 unsigned NElts = VT.getVectorNumElements(); 750 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 751 EVT SVT = (MVT::SimpleValueType)nVT; 752 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 753 SVT.getVectorNumElements() > NElts && NElts != 1) { 754 TransformToType[i] = SVT; 755 ValueTypeActions.setTypeAction(VT, Promote); 756 IsLegalWiderType = true; 757 break; 758 } 759 } 760 if (!IsLegalWiderType) { 761 EVT NVT = VT.getPow2VectorType(); 762 if (NVT == VT) { 763 // Type is already a power of 2. The default action is to split. 764 TransformToType[i] = MVT::Other; 765 ValueTypeActions.setTypeAction(VT, Expand); 766 } else { 767 TransformToType[i] = NVT; 768 ValueTypeActions.setTypeAction(VT, Promote); 769 } 770 } 771 } 772} 773 774const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 775 return NULL; 776} 777 778 779MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 780 return PointerTy.SimpleTy; 781} 782 783MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 784 return MVT::i32; // return the default value 785} 786 787/// getVectorTypeBreakdown - Vector types are broken down into some number of 788/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 789/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 790/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 791/// 792/// This method returns the number of registers needed, and the VT for each 793/// register. It also returns the VT and quantity of the intermediate values 794/// before they are promoted/expanded. 795/// 796unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 797 EVT &IntermediateVT, 798 unsigned &NumIntermediates, 799 EVT &RegisterVT) const { 800 // Figure out the right, legal destination reg to copy into. 801 unsigned NumElts = VT.getVectorNumElements(); 802 EVT EltTy = VT.getVectorElementType(); 803 804 unsigned NumVectorRegs = 1; 805 806 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 807 // could break down into LHS/RHS like LegalizeDAG does. 808 if (!isPowerOf2_32(NumElts)) { 809 NumVectorRegs = NumElts; 810 NumElts = 1; 811 } 812 813 // Divide the input until we get to a supported size. This will always 814 // end with a scalar if the target doesn't support vectors. 815 while (NumElts > 1 && !isTypeLegal( 816 EVT::getVectorVT(Context, EltTy, NumElts))) { 817 NumElts >>= 1; 818 NumVectorRegs <<= 1; 819 } 820 821 NumIntermediates = NumVectorRegs; 822 823 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 824 if (!isTypeLegal(NewVT)) 825 NewVT = EltTy; 826 IntermediateVT = NewVT; 827 828 EVT DestVT = getRegisterType(Context, NewVT); 829 RegisterVT = DestVT; 830 if (DestVT.bitsLT(NewVT)) { 831 // Value is expanded, e.g. i64 -> i16. 832 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 833 } else { 834 // Otherwise, promotion or legal types use the same number of registers as 835 // the vector decimated to the appropriate level. 836 return NumVectorRegs; 837 } 838 839 return 1; 840} 841 842/// Get the EVTs and ArgFlags collections that represent the legalized return 843/// type of the given function. This does not require a DAG or a return value, 844/// and is suitable for use before any DAGs for the function are constructed. 845/// TODO: Move this out of TargetLowering.cpp. 846void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 847 SmallVectorImpl<ISD::OutputArg> &Outs, 848 const TargetLowering &TLI, 849 SmallVectorImpl<uint64_t> *Offsets) { 850 SmallVector<EVT, 4> ValueVTs; 851 ComputeValueVTs(TLI, ReturnType, ValueVTs); 852 unsigned NumValues = ValueVTs.size(); 853 if (NumValues == 0) return; 854 unsigned Offset = 0; 855 856 for (unsigned j = 0, f = NumValues; j != f; ++j) { 857 EVT VT = ValueVTs[j]; 858 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 859 860 if (attr & Attribute::SExt) 861 ExtendKind = ISD::SIGN_EXTEND; 862 else if (attr & Attribute::ZExt) 863 ExtendKind = ISD::ZERO_EXTEND; 864 865 // FIXME: C calling convention requires the return type to be promoted to 866 // at least 32-bit. But this is not necessary for non-C calling 867 // conventions. The frontend should mark functions whose return values 868 // require promoting with signext or zeroext attributes. 869 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 870 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 871 if (VT.bitsLT(MinVT)) 872 VT = MinVT; 873 } 874 875 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 876 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 877 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 878 PartVT.getTypeForEVT(ReturnType->getContext())); 879 880 // 'inreg' on function refers to return value 881 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 882 if (attr & Attribute::InReg) 883 Flags.setInReg(); 884 885 // Propagate extension type if any 886 if (attr & Attribute::SExt) 887 Flags.setSExt(); 888 else if (attr & Attribute::ZExt) 889 Flags.setZExt(); 890 891 for (unsigned i = 0; i < NumParts; ++i) { 892 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 893 if (Offsets) { 894 Offsets->push_back(Offset); 895 Offset += PartSize; 896 } 897 } 898 } 899} 900 901/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 902/// function arguments in the caller parameter area. This is the actual 903/// alignment, not its logarithm. 904unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 905 return TD->getCallFrameTypeAlignment(Ty); 906} 907 908/// getJumpTableEncoding - Return the entry encoding for a jump table in the 909/// current function. The returned value is a member of the 910/// MachineJumpTableInfo::JTEntryKind enum. 911unsigned TargetLowering::getJumpTableEncoding() const { 912 // In non-pic modes, just use the address of a block. 913 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 914 return MachineJumpTableInfo::EK_BlockAddress; 915 916 // In PIC mode, if the target supports a GPRel32 directive, use it. 917 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 918 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 919 920 // Otherwise, use a label difference. 921 return MachineJumpTableInfo::EK_LabelDifference32; 922} 923 924SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 925 SelectionDAG &DAG) const { 926 // If our PIC model is GP relative, use the global offset table as the base. 927 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 928 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 929 return Table; 930} 931 932/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 933/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 934/// MCExpr. 935const MCExpr * 936TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 937 unsigned JTI,MCContext &Ctx) const{ 938 // The normal PIC reloc base is the label at the start of the jump table. 939 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 940} 941 942bool 943TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 944 // Assume that everything is safe in static mode. 945 if (getTargetMachine().getRelocationModel() == Reloc::Static) 946 return true; 947 948 // In dynamic-no-pic mode, assume that known defined values are safe. 949 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 950 GA && 951 !GA->getGlobal()->isDeclaration() && 952 !GA->getGlobal()->isWeakForLinker()) 953 return true; 954 955 // Otherwise assume nothing is safe. 956 return false; 957} 958 959//===----------------------------------------------------------------------===// 960// Optimization Methods 961//===----------------------------------------------------------------------===// 962 963/// ShrinkDemandedConstant - Check to see if the specified operand of the 964/// specified instruction is a constant integer. If so, check to see if there 965/// are any bits set in the constant that are not demanded. If so, shrink the 966/// constant and return true. 967bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 968 const APInt &Demanded) { 969 DebugLoc dl = Op.getDebugLoc(); 970 971 // FIXME: ISD::SELECT, ISD::SELECT_CC 972 switch (Op.getOpcode()) { 973 default: break; 974 case ISD::XOR: 975 case ISD::AND: 976 case ISD::OR: { 977 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 978 if (!C) return false; 979 980 if (Op.getOpcode() == ISD::XOR && 981 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 982 return false; 983 984 // if we can expand it to have all bits set, do it 985 if (C->getAPIntValue().intersects(~Demanded)) { 986 EVT VT = Op.getValueType(); 987 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 988 DAG.getConstant(Demanded & 989 C->getAPIntValue(), 990 VT)); 991 return CombineTo(Op, New); 992 } 993 994 break; 995 } 996 } 997 998 return false; 999} 1000 1001/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1002/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1003/// cast, but it could be generalized for targets with other types of 1004/// implicit widening casts. 1005bool 1006TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1007 unsigned BitWidth, 1008 const APInt &Demanded, 1009 DebugLoc dl) { 1010 assert(Op.getNumOperands() == 2 && 1011 "ShrinkDemandedOp only supports binary operators!"); 1012 assert(Op.getNode()->getNumValues() == 1 && 1013 "ShrinkDemandedOp only supports nodes with one result!"); 1014 1015 // Don't do this if the node has another user, which may require the 1016 // full value. 1017 if (!Op.getNode()->hasOneUse()) 1018 return false; 1019 1020 // Search for the smallest integer type with free casts to and from 1021 // Op's type. For expedience, just check power-of-2 integer types. 1022 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1023 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1024 if (!isPowerOf2_32(SmallVTBits)) 1025 SmallVTBits = NextPowerOf2(SmallVTBits); 1026 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1027 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1028 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1029 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1030 // We found a type with free casts. 1031 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1032 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1033 Op.getNode()->getOperand(0)), 1034 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1035 Op.getNode()->getOperand(1))); 1036 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1037 return CombineTo(Op, Z); 1038 } 1039 } 1040 return false; 1041} 1042 1043/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1044/// DemandedMask bits of the result of Op are ever used downstream. If we can 1045/// use this information to simplify Op, create a new simplified DAG node and 1046/// return true, returning the original and new nodes in Old and New. Otherwise, 1047/// analyze the expression and return a mask of KnownOne and KnownZero bits for 1048/// the expression (used to simplify the caller). The KnownZero/One bits may 1049/// only be accurate for those bits in the DemandedMask. 1050bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1051 const APInt &DemandedMask, 1052 APInt &KnownZero, 1053 APInt &KnownOne, 1054 TargetLoweringOpt &TLO, 1055 unsigned Depth) const { 1056 unsigned BitWidth = DemandedMask.getBitWidth(); 1057 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1058 "Mask size mismatches value type size!"); 1059 APInt NewMask = DemandedMask; 1060 DebugLoc dl = Op.getDebugLoc(); 1061 1062 // Don't know anything. 1063 KnownZero = KnownOne = APInt(BitWidth, 0); 1064 1065 // Other users may use these bits. 1066 if (!Op.getNode()->hasOneUse()) { 1067 if (Depth != 0) { 1068 // If not at the root, Just compute the KnownZero/KnownOne bits to 1069 // simplify things downstream. 1070 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1071 return false; 1072 } 1073 // If this is the root being simplified, allow it to have multiple uses, 1074 // just set the NewMask to all bits. 1075 NewMask = APInt::getAllOnesValue(BitWidth); 1076 } else if (DemandedMask == 0) { 1077 // Not demanding any bits from Op. 1078 if (Op.getOpcode() != ISD::UNDEF) 1079 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1080 return false; 1081 } else if (Depth == 6) { // Limit search depth. 1082 return false; 1083 } 1084 1085 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1086 switch (Op.getOpcode()) { 1087 case ISD::Constant: 1088 // We know all of the bits for a constant! 1089 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1090 KnownZero = ~KnownOne & NewMask; 1091 return false; // Don't fall through, will infinitely loop. 1092 case ISD::AND: 1093 // If the RHS is a constant, check to see if the LHS would be zero without 1094 // using the bits from the RHS. Below, we use knowledge about the RHS to 1095 // simplify the LHS, here we're using information from the LHS to simplify 1096 // the RHS. 1097 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1098 APInt LHSZero, LHSOne; 1099 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1100 LHSZero, LHSOne, Depth+1); 1101 // If the LHS already has zeros where RHSC does, this and is dead. 1102 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1103 return TLO.CombineTo(Op, Op.getOperand(0)); 1104 // If any of the set bits in the RHS are known zero on the LHS, shrink 1105 // the constant. 1106 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1107 return true; 1108 } 1109 1110 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1111 KnownOne, TLO, Depth+1)) 1112 return true; 1113 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1114 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1115 KnownZero2, KnownOne2, TLO, Depth+1)) 1116 return true; 1117 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1118 1119 // If all of the demanded bits are known one on one side, return the other. 1120 // These bits cannot contribute to the result of the 'and'. 1121 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1122 return TLO.CombineTo(Op, Op.getOperand(0)); 1123 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1124 return TLO.CombineTo(Op, Op.getOperand(1)); 1125 // If all of the demanded bits in the inputs are known zeros, return zero. 1126 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1127 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1128 // If the RHS is a constant, see if we can simplify it. 1129 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1130 return true; 1131 // If the operation can be done in a smaller type, do so. 1132 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1133 return true; 1134 1135 // Output known-1 bits are only known if set in both the LHS & RHS. 1136 KnownOne &= KnownOne2; 1137 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1138 KnownZero |= KnownZero2; 1139 break; 1140 case ISD::OR: 1141 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1142 KnownOne, TLO, Depth+1)) 1143 return true; 1144 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1145 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1146 KnownZero2, KnownOne2, TLO, Depth+1)) 1147 return true; 1148 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1149 1150 // If all of the demanded bits are known zero on one side, return the other. 1151 // These bits cannot contribute to the result of the 'or'. 1152 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1153 return TLO.CombineTo(Op, Op.getOperand(0)); 1154 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1155 return TLO.CombineTo(Op, Op.getOperand(1)); 1156 // If all of the potentially set bits on one side are known to be set on 1157 // the other side, just use the 'other' side. 1158 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1159 return TLO.CombineTo(Op, Op.getOperand(0)); 1160 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1161 return TLO.CombineTo(Op, Op.getOperand(1)); 1162 // If the RHS is a constant, see if we can simplify it. 1163 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1164 return true; 1165 // If the operation can be done in a smaller type, do so. 1166 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1167 return true; 1168 1169 // Output known-0 bits are only known if clear in both the LHS & RHS. 1170 KnownZero &= KnownZero2; 1171 // Output known-1 are known to be set if set in either the LHS | RHS. 1172 KnownOne |= KnownOne2; 1173 break; 1174 case ISD::XOR: 1175 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1176 KnownOne, TLO, Depth+1)) 1177 return true; 1178 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1179 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1180 KnownOne2, TLO, Depth+1)) 1181 return true; 1182 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1183 1184 // If all of the demanded bits are known zero on one side, return the other. 1185 // These bits cannot contribute to the result of the 'xor'. 1186 if ((KnownZero & NewMask) == NewMask) 1187 return TLO.CombineTo(Op, Op.getOperand(0)); 1188 if ((KnownZero2 & NewMask) == NewMask) 1189 return TLO.CombineTo(Op, Op.getOperand(1)); 1190 // If the operation can be done in a smaller type, do so. 1191 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1192 return true; 1193 1194 // If all of the unknown bits are known to be zero on one side or the other 1195 // (but not both) turn this into an *inclusive* or. 1196 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1197 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1198 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1199 Op.getOperand(0), 1200 Op.getOperand(1))); 1201 1202 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1203 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1204 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1205 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1206 1207 // If all of the demanded bits on one side are known, and all of the set 1208 // bits on that side are also known to be set on the other side, turn this 1209 // into an AND, as we know the bits will be cleared. 1210 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1211 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1212 if ((KnownOne & KnownOne2) == KnownOne) { 1213 EVT VT = Op.getValueType(); 1214 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1215 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1216 Op.getOperand(0), ANDC)); 1217 } 1218 } 1219 1220 // If the RHS is a constant, see if we can simplify it. 1221 // for XOR, we prefer to force bits to 1 if they will make a -1. 1222 // if we can't force bits, try to shrink constant 1223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1224 APInt Expanded = C->getAPIntValue() | (~NewMask); 1225 // if we can expand it to have all bits set, do it 1226 if (Expanded.isAllOnesValue()) { 1227 if (Expanded != C->getAPIntValue()) { 1228 EVT VT = Op.getValueType(); 1229 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1230 TLO.DAG.getConstant(Expanded, VT)); 1231 return TLO.CombineTo(Op, New); 1232 } 1233 // if it already has all the bits set, nothing to change 1234 // but don't shrink either! 1235 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1236 return true; 1237 } 1238 } 1239 1240 KnownZero = KnownZeroOut; 1241 KnownOne = KnownOneOut; 1242 break; 1243 case ISD::SELECT: 1244 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1245 KnownOne, TLO, Depth+1)) 1246 return true; 1247 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1248 KnownOne2, TLO, Depth+1)) 1249 return true; 1250 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1251 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1252 1253 // If the operands are constants, see if we can simplify them. 1254 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1255 return true; 1256 1257 // Only known if known in both the LHS and RHS. 1258 KnownOne &= KnownOne2; 1259 KnownZero &= KnownZero2; 1260 break; 1261 case ISD::SELECT_CC: 1262 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1263 KnownOne, TLO, Depth+1)) 1264 return true; 1265 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1266 KnownOne2, TLO, Depth+1)) 1267 return true; 1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1269 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1270 1271 // If the operands are constants, see if we can simplify them. 1272 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1273 return true; 1274 1275 // Only known if known in both the LHS and RHS. 1276 KnownOne &= KnownOne2; 1277 KnownZero &= KnownZero2; 1278 break; 1279 case ISD::SHL: 1280 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1281 unsigned ShAmt = SA->getZExtValue(); 1282 SDValue InOp = Op.getOperand(0); 1283 1284 // If the shift count is an invalid immediate, don't do anything. 1285 if (ShAmt >= BitWidth) 1286 break; 1287 1288 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1289 // single shift. We can do this if the bottom bits (which are shifted 1290 // out) are never demanded. 1291 if (InOp.getOpcode() == ISD::SRL && 1292 isa<ConstantSDNode>(InOp.getOperand(1))) { 1293 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1294 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1295 unsigned Opc = ISD::SHL; 1296 int Diff = ShAmt-C1; 1297 if (Diff < 0) { 1298 Diff = -Diff; 1299 Opc = ISD::SRL; 1300 } 1301 1302 SDValue NewSA = 1303 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1304 EVT VT = Op.getValueType(); 1305 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1306 InOp.getOperand(0), NewSA)); 1307 } 1308 } 1309 1310 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1311 KnownZero, KnownOne, TLO, Depth+1)) 1312 return true; 1313 KnownZero <<= SA->getZExtValue(); 1314 KnownOne <<= SA->getZExtValue(); 1315 // low bits known zero. 1316 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1317 } 1318 break; 1319 case ISD::SRL: 1320 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1321 EVT VT = Op.getValueType(); 1322 unsigned ShAmt = SA->getZExtValue(); 1323 unsigned VTSize = VT.getSizeInBits(); 1324 SDValue InOp = Op.getOperand(0); 1325 1326 // If the shift count is an invalid immediate, don't do anything. 1327 if (ShAmt >= BitWidth) 1328 break; 1329 1330 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1331 // single shift. We can do this if the top bits (which are shifted out) 1332 // are never demanded. 1333 if (InOp.getOpcode() == ISD::SHL && 1334 isa<ConstantSDNode>(InOp.getOperand(1))) { 1335 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1336 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1337 unsigned Opc = ISD::SRL; 1338 int Diff = ShAmt-C1; 1339 if (Diff < 0) { 1340 Diff = -Diff; 1341 Opc = ISD::SHL; 1342 } 1343 1344 SDValue NewSA = 1345 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1346 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1347 InOp.getOperand(0), NewSA)); 1348 } 1349 } 1350 1351 // Compute the new bits that are at the top now. 1352 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1353 KnownZero, KnownOne, TLO, Depth+1)) 1354 return true; 1355 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1356 KnownZero = KnownZero.lshr(ShAmt); 1357 KnownOne = KnownOne.lshr(ShAmt); 1358 1359 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1360 KnownZero |= HighBits; // High bits known zero. 1361 } 1362 break; 1363 case ISD::SRA: 1364 // If this is an arithmetic shift right and only the low-bit is set, we can 1365 // always convert this into a logical shr, even if the shift amount is 1366 // variable. The low bit of the shift cannot be an input sign bit unless 1367 // the shift amount is >= the size of the datatype, which is undefined. 1368 if (DemandedMask == 1) 1369 return TLO.CombineTo(Op, 1370 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1371 Op.getOperand(0), Op.getOperand(1))); 1372 1373 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1374 EVT VT = Op.getValueType(); 1375 unsigned ShAmt = SA->getZExtValue(); 1376 1377 // If the shift count is an invalid immediate, don't do anything. 1378 if (ShAmt >= BitWidth) 1379 break; 1380 1381 APInt InDemandedMask = (NewMask << ShAmt); 1382 1383 // If any of the demanded bits are produced by the sign extension, we also 1384 // demand the input sign bit. 1385 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1386 if (HighBits.intersects(NewMask)) 1387 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1388 1389 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1390 KnownZero, KnownOne, TLO, Depth+1)) 1391 return true; 1392 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1393 KnownZero = KnownZero.lshr(ShAmt); 1394 KnownOne = KnownOne.lshr(ShAmt); 1395 1396 // Handle the sign bit, adjusted to where it is now in the mask. 1397 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1398 1399 // If the input sign bit is known to be zero, or if none of the top bits 1400 // are demanded, turn this into an unsigned shift right. 1401 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1402 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1403 Op.getOperand(0), 1404 Op.getOperand(1))); 1405 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1406 KnownOne |= HighBits; 1407 } 1408 } 1409 break; 1410 case ISD::SIGN_EXTEND_INREG: { 1411 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1412 1413 // Sign extension. Compute the demanded bits in the result that are not 1414 // present in the input. 1415 APInt NewBits = 1416 APInt::getHighBitsSet(BitWidth, 1417 BitWidth - EVT.getScalarType().getSizeInBits()) & 1418 NewMask; 1419 1420 // If none of the extended bits are demanded, eliminate the sextinreg. 1421 if (NewBits == 0) 1422 return TLO.CombineTo(Op, Op.getOperand(0)); 1423 1424 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1425 InSignBit.zext(BitWidth); 1426 APInt InputDemandedBits = 1427 APInt::getLowBitsSet(BitWidth, 1428 EVT.getScalarType().getSizeInBits()) & 1429 NewMask; 1430 1431 // Since the sign extended bits are demanded, we know that the sign 1432 // bit is demanded. 1433 InputDemandedBits |= InSignBit; 1434 1435 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1436 KnownZero, KnownOne, TLO, Depth+1)) 1437 return true; 1438 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1439 1440 // If the sign bit of the input is known set or clear, then we know the 1441 // top bits of the result. 1442 1443 // If the input sign bit is known zero, convert this into a zero extension. 1444 if (KnownZero.intersects(InSignBit)) 1445 return TLO.CombineTo(Op, 1446 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1447 1448 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1449 KnownOne |= NewBits; 1450 KnownZero &= ~NewBits; 1451 } else { // Input sign bit unknown 1452 KnownZero &= ~NewBits; 1453 KnownOne &= ~NewBits; 1454 } 1455 break; 1456 } 1457 case ISD::ZERO_EXTEND: { 1458 unsigned OperandBitWidth = 1459 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1460 APInt InMask = NewMask; 1461 InMask.trunc(OperandBitWidth); 1462 1463 // If none of the top bits are demanded, convert this into an any_extend. 1464 APInt NewBits = 1465 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1466 if (!NewBits.intersects(NewMask)) 1467 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1468 Op.getValueType(), 1469 Op.getOperand(0))); 1470 1471 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1472 KnownZero, KnownOne, TLO, Depth+1)) 1473 return true; 1474 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1475 KnownZero.zext(BitWidth); 1476 KnownOne.zext(BitWidth); 1477 KnownZero |= NewBits; 1478 break; 1479 } 1480 case ISD::SIGN_EXTEND: { 1481 EVT InVT = Op.getOperand(0).getValueType(); 1482 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1483 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1484 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1485 APInt NewBits = ~InMask & NewMask; 1486 1487 // If none of the top bits are demanded, convert this into an any_extend. 1488 if (NewBits == 0) 1489 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1490 Op.getValueType(), 1491 Op.getOperand(0))); 1492 1493 // Since some of the sign extended bits are demanded, we know that the sign 1494 // bit is demanded. 1495 APInt InDemandedBits = InMask & NewMask; 1496 InDemandedBits |= InSignBit; 1497 InDemandedBits.trunc(InBits); 1498 1499 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1500 KnownOne, TLO, Depth+1)) 1501 return true; 1502 KnownZero.zext(BitWidth); 1503 KnownOne.zext(BitWidth); 1504 1505 // If the sign bit is known zero, convert this to a zero extend. 1506 if (KnownZero.intersects(InSignBit)) 1507 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1508 Op.getValueType(), 1509 Op.getOperand(0))); 1510 1511 // If the sign bit is known one, the top bits match. 1512 if (KnownOne.intersects(InSignBit)) { 1513 KnownOne |= NewBits; 1514 KnownZero &= ~NewBits; 1515 } else { // Otherwise, top bits aren't known. 1516 KnownOne &= ~NewBits; 1517 KnownZero &= ~NewBits; 1518 } 1519 break; 1520 } 1521 case ISD::ANY_EXTEND: { 1522 unsigned OperandBitWidth = 1523 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1524 APInt InMask = NewMask; 1525 InMask.trunc(OperandBitWidth); 1526 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1527 KnownZero, KnownOne, TLO, Depth+1)) 1528 return true; 1529 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1530 KnownZero.zext(BitWidth); 1531 KnownOne.zext(BitWidth); 1532 break; 1533 } 1534 case ISD::TRUNCATE: { 1535 // Simplify the input, using demanded bit information, and compute the known 1536 // zero/one bits live out. 1537 unsigned OperandBitWidth = 1538 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1539 APInt TruncMask = NewMask; 1540 TruncMask.zext(OperandBitWidth); 1541 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1542 KnownZero, KnownOne, TLO, Depth+1)) 1543 return true; 1544 KnownZero.trunc(BitWidth); 1545 KnownOne.trunc(BitWidth); 1546 1547 // If the input is only used by this truncate, see if we can shrink it based 1548 // on the known demanded bits. 1549 if (Op.getOperand(0).getNode()->hasOneUse()) { 1550 SDValue In = Op.getOperand(0); 1551 switch (In.getOpcode()) { 1552 default: break; 1553 case ISD::SRL: 1554 // Shrink SRL by a constant if none of the high bits shifted in are 1555 // demanded. 1556 if (TLO.LegalTypes() && 1557 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1558 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1559 // undesirable. 1560 break; 1561 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1562 if (!ShAmt) 1563 break; 1564 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1565 OperandBitWidth - BitWidth); 1566 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1567 HighBits.trunc(BitWidth); 1568 1569 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1570 // None of the shifted in bits are needed. Add a truncate of the 1571 // shift input, then shift it. 1572 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1573 Op.getValueType(), 1574 In.getOperand(0)); 1575 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1576 Op.getValueType(), 1577 NewTrunc, 1578 In.getOperand(1))); 1579 } 1580 break; 1581 } 1582 } 1583 1584 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1585 break; 1586 } 1587 case ISD::AssertZext: { 1588 // Demand all the bits of the input that are demanded in the output. 1589 // The low bits are obvious; the high bits are demanded because we're 1590 // asserting that they're zero here. 1591 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1592 KnownZero, KnownOne, TLO, Depth+1)) 1593 return true; 1594 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1595 1596 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1597 APInt InMask = APInt::getLowBitsSet(BitWidth, 1598 VT.getSizeInBits()); 1599 KnownZero |= ~InMask & NewMask; 1600 break; 1601 } 1602 case ISD::BIT_CONVERT: 1603#if 0 1604 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1605 // is demanded, turn this into a FGETSIGN. 1606 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1607 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1608 !MVT::isVector(Op.getOperand(0).getValueType())) { 1609 // Only do this xform if FGETSIGN is valid or if before legalize. 1610 if (!TLO.AfterLegalize || 1611 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1612 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1613 // place. We expect the SHL to be eliminated by other optimizations. 1614 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1615 Op.getOperand(0)); 1616 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1617 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1618 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1619 Sign, ShAmt)); 1620 } 1621 } 1622#endif 1623 break; 1624 case ISD::ADD: 1625 case ISD::MUL: 1626 case ISD::SUB: { 1627 // Add, Sub, and Mul don't demand any bits in positions beyond that 1628 // of the highest bit demanded of them. 1629 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1630 BitWidth - NewMask.countLeadingZeros()); 1631 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1632 KnownOne2, TLO, Depth+1)) 1633 return true; 1634 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1635 KnownOne2, TLO, Depth+1)) 1636 return true; 1637 // See if the operation should be performed at a smaller bit width. 1638 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1639 return true; 1640 } 1641 // FALL THROUGH 1642 default: 1643 // Just use ComputeMaskedBits to compute output bits. 1644 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1645 break; 1646 } 1647 1648 // If we know the value of all of the demanded bits, return this as a 1649 // constant. 1650 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1651 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1652 1653 return false; 1654} 1655 1656/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1657/// in Mask are known to be either zero or one and return them in the 1658/// KnownZero/KnownOne bitsets. 1659void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1660 const APInt &Mask, 1661 APInt &KnownZero, 1662 APInt &KnownOne, 1663 const SelectionDAG &DAG, 1664 unsigned Depth) const { 1665 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1666 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1667 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1668 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1669 "Should use MaskedValueIsZero if you don't know whether Op" 1670 " is a target node!"); 1671 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1672} 1673 1674/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1675/// targets that want to expose additional information about sign bits to the 1676/// DAG Combiner. 1677unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1678 unsigned Depth) const { 1679 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1680 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1681 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1682 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1683 "Should use ComputeNumSignBits if you don't know whether Op" 1684 " is a target node!"); 1685 return 1; 1686} 1687 1688/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1689/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1690/// determine which bit is set. 1691/// 1692static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1693 // A left-shift of a constant one will have exactly one bit set, because 1694 // shifting the bit off the end is undefined. 1695 if (Val.getOpcode() == ISD::SHL) 1696 if (ConstantSDNode *C = 1697 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1698 if (C->getAPIntValue() == 1) 1699 return true; 1700 1701 // Similarly, a right-shift of a constant sign-bit will have exactly 1702 // one bit set. 1703 if (Val.getOpcode() == ISD::SRL) 1704 if (ConstantSDNode *C = 1705 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1706 if (C->getAPIntValue().isSignBit()) 1707 return true; 1708 1709 // More could be done here, though the above checks are enough 1710 // to handle some common cases. 1711 1712 // Fall back to ComputeMaskedBits to catch other known cases. 1713 EVT OpVT = Val.getValueType(); 1714 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1715 APInt Mask = APInt::getAllOnesValue(BitWidth); 1716 APInt KnownZero, KnownOne; 1717 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1718 return (KnownZero.countPopulation() == BitWidth - 1) && 1719 (KnownOne.countPopulation() == 1); 1720} 1721 1722/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1723/// and cc. If it is unable to simplify it, return a null SDValue. 1724SDValue 1725TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1726 ISD::CondCode Cond, bool foldBooleans, 1727 DAGCombinerInfo &DCI, DebugLoc dl) const { 1728 SelectionDAG &DAG = DCI.DAG; 1729 LLVMContext &Context = *DAG.getContext(); 1730 1731 // These setcc operations always fold. 1732 switch (Cond) { 1733 default: break; 1734 case ISD::SETFALSE: 1735 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1736 case ISD::SETTRUE: 1737 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1738 } 1739 1740 if (isa<ConstantSDNode>(N0.getNode())) { 1741 // Ensure that the constant occurs on the RHS, and fold constant 1742 // comparisons. 1743 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1744 } 1745 1746 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1747 const APInt &C1 = N1C->getAPIntValue(); 1748 1749 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1750 // equality comparison, then we're just comparing whether X itself is 1751 // zero. 1752 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1753 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1754 N0.getOperand(1).getOpcode() == ISD::Constant) { 1755 const APInt &ShAmt 1756 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1757 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1758 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1759 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1760 // (srl (ctlz x), 5) == 0 -> X != 0 1761 // (srl (ctlz x), 5) != 1 -> X != 0 1762 Cond = ISD::SETNE; 1763 } else { 1764 // (srl (ctlz x), 5) != 0 -> X == 0 1765 // (srl (ctlz x), 5) == 1 -> X == 0 1766 Cond = ISD::SETEQ; 1767 } 1768 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1769 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1770 Zero, Cond); 1771 } 1772 } 1773 1774 // If the LHS is '(and load, const)', the RHS is 0, 1775 // the test is for equality or unsigned, and all 1 bits of the const are 1776 // in the same partial word, see if we can shorten the load. 1777 if (DCI.isBeforeLegalize() && 1778 N0.getOpcode() == ISD::AND && C1 == 0 && 1779 N0.getNode()->hasOneUse() && 1780 isa<LoadSDNode>(N0.getOperand(0)) && 1781 N0.getOperand(0).getNode()->hasOneUse() && 1782 isa<ConstantSDNode>(N0.getOperand(1))) { 1783 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1784 APInt bestMask; 1785 unsigned bestWidth = 0, bestOffset = 0; 1786 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1787 unsigned origWidth = N0.getValueType().getSizeInBits(); 1788 unsigned maskWidth = origWidth; 1789 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1790 // 8 bits, but have to be careful... 1791 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1792 origWidth = Lod->getMemoryVT().getSizeInBits(); 1793 const APInt &Mask = 1794 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1795 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1796 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1797 for (unsigned offset=0; offset<origWidth/width; offset++) { 1798 if ((newMask & Mask) == Mask) { 1799 if (!TD->isLittleEndian()) 1800 bestOffset = (origWidth/width - offset - 1) * (width/8); 1801 else 1802 bestOffset = (uint64_t)offset * (width/8); 1803 bestMask = Mask.lshr(offset * (width/8) * 8); 1804 bestWidth = width; 1805 break; 1806 } 1807 newMask = newMask << width; 1808 } 1809 } 1810 } 1811 if (bestWidth) { 1812 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1813 if (newVT.isRound()) { 1814 EVT PtrType = Lod->getOperand(1).getValueType(); 1815 SDValue Ptr = Lod->getBasePtr(); 1816 if (bestOffset != 0) 1817 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1818 DAG.getConstant(bestOffset, PtrType)); 1819 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1820 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1821 Lod->getSrcValue(), 1822 Lod->getSrcValueOffset() + bestOffset, 1823 false, false, NewAlign); 1824 return DAG.getSetCC(dl, VT, 1825 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1826 DAG.getConstant(bestMask.trunc(bestWidth), 1827 newVT)), 1828 DAG.getConstant(0LL, newVT), Cond); 1829 } 1830 } 1831 } 1832 1833 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1834 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1835 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1836 1837 // If the comparison constant has bits in the upper part, the 1838 // zero-extended value could never match. 1839 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1840 C1.getBitWidth() - InSize))) { 1841 switch (Cond) { 1842 case ISD::SETUGT: 1843 case ISD::SETUGE: 1844 case ISD::SETEQ: return DAG.getConstant(0, VT); 1845 case ISD::SETULT: 1846 case ISD::SETULE: 1847 case ISD::SETNE: return DAG.getConstant(1, VT); 1848 case ISD::SETGT: 1849 case ISD::SETGE: 1850 // True if the sign bit of C1 is set. 1851 return DAG.getConstant(C1.isNegative(), VT); 1852 case ISD::SETLT: 1853 case ISD::SETLE: 1854 // True if the sign bit of C1 isn't set. 1855 return DAG.getConstant(C1.isNonNegative(), VT); 1856 default: 1857 break; 1858 } 1859 } 1860 1861 // Otherwise, we can perform the comparison with the low bits. 1862 switch (Cond) { 1863 case ISD::SETEQ: 1864 case ISD::SETNE: 1865 case ISD::SETUGT: 1866 case ISD::SETUGE: 1867 case ISD::SETULT: 1868 case ISD::SETULE: { 1869 EVT newVT = N0.getOperand(0).getValueType(); 1870 if (DCI.isBeforeLegalizeOps() || 1871 (isOperationLegal(ISD::SETCC, newVT) && 1872 getCondCodeAction(Cond, newVT)==Legal)) 1873 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1874 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1875 Cond); 1876 break; 1877 } 1878 default: 1879 break; // todo, be more careful with signed comparisons 1880 } 1881 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1882 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1883 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1884 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1885 EVT ExtDstTy = N0.getValueType(); 1886 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1887 1888 // If the extended part has any inconsistent bits, it cannot ever 1889 // compare equal. In other words, they have to be all ones or all 1890 // zeros. 1891 APInt ExtBits = 1892 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1893 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1894 return DAG.getConstant(Cond == ISD::SETNE, VT); 1895 1896 SDValue ZextOp; 1897 EVT Op0Ty = N0.getOperand(0).getValueType(); 1898 if (Op0Ty == ExtSrcTy) { 1899 ZextOp = N0.getOperand(0); 1900 } else { 1901 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1902 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1903 DAG.getConstant(Imm, Op0Ty)); 1904 } 1905 if (!DCI.isCalledByLegalizer()) 1906 DCI.AddToWorklist(ZextOp.getNode()); 1907 // Otherwise, make this a use of a zext. 1908 return DAG.getSetCC(dl, VT, ZextOp, 1909 DAG.getConstant(C1 & APInt::getLowBitsSet( 1910 ExtDstTyBits, 1911 ExtSrcTyBits), 1912 ExtDstTy), 1913 Cond); 1914 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1915 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1916 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1917 if (N0.getOpcode() == ISD::SETCC && 1918 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1919 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1920 if (TrueWhenTrue) 1921 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1922 // Invert the condition. 1923 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1924 CC = ISD::getSetCCInverse(CC, 1925 N0.getOperand(0).getValueType().isInteger()); 1926 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1927 } 1928 1929 if ((N0.getOpcode() == ISD::XOR || 1930 (N0.getOpcode() == ISD::AND && 1931 N0.getOperand(0).getOpcode() == ISD::XOR && 1932 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1933 isa<ConstantSDNode>(N0.getOperand(1)) && 1934 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1935 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1936 // can only do this if the top bits are known zero. 1937 unsigned BitWidth = N0.getValueSizeInBits(); 1938 if (DAG.MaskedValueIsZero(N0, 1939 APInt::getHighBitsSet(BitWidth, 1940 BitWidth-1))) { 1941 // Okay, get the un-inverted input value. 1942 SDValue Val; 1943 if (N0.getOpcode() == ISD::XOR) 1944 Val = N0.getOperand(0); 1945 else { 1946 assert(N0.getOpcode() == ISD::AND && 1947 N0.getOperand(0).getOpcode() == ISD::XOR); 1948 // ((X^1)&1)^1 -> X & 1 1949 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1950 N0.getOperand(0).getOperand(0), 1951 N0.getOperand(1)); 1952 } 1953 1954 return DAG.getSetCC(dl, VT, Val, N1, 1955 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1956 } 1957 } else if (N1C->getAPIntValue() == 1 && 1958 (VT == MVT::i1 || 1959 getBooleanContents() == ZeroOrOneBooleanContent)) { 1960 SDValue Op0 = N0; 1961 if (Op0.getOpcode() == ISD::TRUNCATE) 1962 Op0 = Op0.getOperand(0); 1963 1964 if ((Op0.getOpcode() == ISD::XOR) && 1965 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1966 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1967 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1968 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1969 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1970 Cond); 1971 } else if (Op0.getOpcode() == ISD::AND && 1972 isa<ConstantSDNode>(Op0.getOperand(1)) && 1973 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1974 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1975 if (Op0.getValueType().bitsGT(VT)) 1976 Op0 = DAG.getNode(ISD::AND, dl, VT, 1977 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1978 DAG.getConstant(1, VT)); 1979 else if (Op0.getValueType().bitsLT(VT)) 1980 Op0 = DAG.getNode(ISD::AND, dl, VT, 1981 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1982 DAG.getConstant(1, VT)); 1983 1984 return DAG.getSetCC(dl, VT, Op0, 1985 DAG.getConstant(0, Op0.getValueType()), 1986 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1987 } 1988 } 1989 } 1990 1991 APInt MinVal, MaxVal; 1992 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1993 if (ISD::isSignedIntSetCC(Cond)) { 1994 MinVal = APInt::getSignedMinValue(OperandBitSize); 1995 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1996 } else { 1997 MinVal = APInt::getMinValue(OperandBitSize); 1998 MaxVal = APInt::getMaxValue(OperandBitSize); 1999 } 2000 2001 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2002 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2003 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2004 // X >= C0 --> X > (C0-1) 2005 return DAG.getSetCC(dl, VT, N0, 2006 DAG.getConstant(C1-1, N1.getValueType()), 2007 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2008 } 2009 2010 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2011 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2012 // X <= C0 --> X < (C0+1) 2013 return DAG.getSetCC(dl, VT, N0, 2014 DAG.getConstant(C1+1, N1.getValueType()), 2015 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2016 } 2017 2018 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2019 return DAG.getConstant(0, VT); // X < MIN --> false 2020 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2021 return DAG.getConstant(1, VT); // X >= MIN --> true 2022 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2023 return DAG.getConstant(0, VT); // X > MAX --> false 2024 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2025 return DAG.getConstant(1, VT); // X <= MAX --> true 2026 2027 // Canonicalize setgt X, Min --> setne X, Min 2028 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2029 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2030 // Canonicalize setlt X, Max --> setne X, Max 2031 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2032 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2033 2034 // If we have setult X, 1, turn it into seteq X, 0 2035 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2036 return DAG.getSetCC(dl, VT, N0, 2037 DAG.getConstant(MinVal, N0.getValueType()), 2038 ISD::SETEQ); 2039 // If we have setugt X, Max-1, turn it into seteq X, Max 2040 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2041 return DAG.getSetCC(dl, VT, N0, 2042 DAG.getConstant(MaxVal, N0.getValueType()), 2043 ISD::SETEQ); 2044 2045 // If we have "setcc X, C0", check to see if we can shrink the immediate 2046 // by changing cc. 2047 2048 // SETUGT X, SINTMAX -> SETLT X, 0 2049 if (Cond == ISD::SETUGT && 2050 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2051 return DAG.getSetCC(dl, VT, N0, 2052 DAG.getConstant(0, N1.getValueType()), 2053 ISD::SETLT); 2054 2055 // SETULT X, SINTMIN -> SETGT X, -1 2056 if (Cond == ISD::SETULT && 2057 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2058 SDValue ConstMinusOne = 2059 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2060 N1.getValueType()); 2061 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2062 } 2063 2064 // Fold bit comparisons when we can. 2065 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2066 (VT == N0.getValueType() || 2067 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2068 N0.getOpcode() == ISD::AND) 2069 if (ConstantSDNode *AndRHS = 2070 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2071 EVT ShiftTy = DCI.isBeforeLegalize() ? 2072 getPointerTy() : getShiftAmountTy(); 2073 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2074 // Perform the xform if the AND RHS is a single bit. 2075 if (AndRHS->getAPIntValue().isPowerOf2()) { 2076 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2077 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2078 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2079 } 2080 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2081 // (X & 8) == 8 --> (X & 8) >> 3 2082 // Perform the xform if C1 is a single bit. 2083 if (C1.isPowerOf2()) { 2084 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2085 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2086 DAG.getConstant(C1.logBase2(), ShiftTy))); 2087 } 2088 } 2089 } 2090 } 2091 2092 if (isa<ConstantFPSDNode>(N0.getNode())) { 2093 // Constant fold or commute setcc. 2094 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2095 if (O.getNode()) return O; 2096 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2097 // If the RHS of an FP comparison is a constant, simplify it away in 2098 // some cases. 2099 if (CFP->getValueAPF().isNaN()) { 2100 // If an operand is known to be a nan, we can fold it. 2101 switch (ISD::getUnorderedFlavor(Cond)) { 2102 default: llvm_unreachable("Unknown flavor!"); 2103 case 0: // Known false. 2104 return DAG.getConstant(0, VT); 2105 case 1: // Known true. 2106 return DAG.getConstant(1, VT); 2107 case 2: // Undefined. 2108 return DAG.getUNDEF(VT); 2109 } 2110 } 2111 2112 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2113 // constant if knowing that the operand is non-nan is enough. We prefer to 2114 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2115 // materialize 0.0. 2116 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2117 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2118 2119 // If the condition is not legal, see if we can find an equivalent one 2120 // which is legal. 2121 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2122 // If the comparison was an awkward floating-point == or != and one of 2123 // the comparison operands is infinity or negative infinity, convert the 2124 // condition to a less-awkward <= or >=. 2125 if (CFP->getValueAPF().isInfinity()) { 2126 if (CFP->getValueAPF().isNegative()) { 2127 if (Cond == ISD::SETOEQ && 2128 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2129 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2130 if (Cond == ISD::SETUEQ && 2131 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2132 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2133 if (Cond == ISD::SETUNE && 2134 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2135 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2136 if (Cond == ISD::SETONE && 2137 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2138 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2139 } else { 2140 if (Cond == ISD::SETOEQ && 2141 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2142 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2143 if (Cond == ISD::SETUEQ && 2144 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2145 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2146 if (Cond == ISD::SETUNE && 2147 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2148 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2149 if (Cond == ISD::SETONE && 2150 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2151 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2152 } 2153 } 2154 } 2155 } 2156 2157 if (N0 == N1) { 2158 // We can always fold X == X for integer setcc's. 2159 if (N0.getValueType().isInteger()) 2160 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2161 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2162 if (UOF == 2) // FP operators that are undefined on NaNs. 2163 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2164 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2165 return DAG.getConstant(UOF, VT); 2166 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2167 // if it is not already. 2168 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2169 if (NewCond != Cond) 2170 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2171 } 2172 2173 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2174 N0.getValueType().isInteger()) { 2175 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2176 N0.getOpcode() == ISD::XOR) { 2177 // Simplify (X+Y) == (X+Z) --> Y == Z 2178 if (N0.getOpcode() == N1.getOpcode()) { 2179 if (N0.getOperand(0) == N1.getOperand(0)) 2180 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2181 if (N0.getOperand(1) == N1.getOperand(1)) 2182 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2183 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2184 // If X op Y == Y op X, try other combinations. 2185 if (N0.getOperand(0) == N1.getOperand(1)) 2186 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2187 Cond); 2188 if (N0.getOperand(1) == N1.getOperand(0)) 2189 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2190 Cond); 2191 } 2192 } 2193 2194 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2195 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2196 // Turn (X+C1) == C2 --> X == C2-C1 2197 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2198 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2199 DAG.getConstant(RHSC->getAPIntValue()- 2200 LHSR->getAPIntValue(), 2201 N0.getValueType()), Cond); 2202 } 2203 2204 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2205 if (N0.getOpcode() == ISD::XOR) 2206 // If we know that all of the inverted bits are zero, don't bother 2207 // performing the inversion. 2208 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2209 return 2210 DAG.getSetCC(dl, VT, N0.getOperand(0), 2211 DAG.getConstant(LHSR->getAPIntValue() ^ 2212 RHSC->getAPIntValue(), 2213 N0.getValueType()), 2214 Cond); 2215 } 2216 2217 // Turn (C1-X) == C2 --> X == C1-C2 2218 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2219 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2220 return 2221 DAG.getSetCC(dl, VT, N0.getOperand(1), 2222 DAG.getConstant(SUBC->getAPIntValue() - 2223 RHSC->getAPIntValue(), 2224 N0.getValueType()), 2225 Cond); 2226 } 2227 } 2228 } 2229 2230 // Simplify (X+Z) == X --> Z == 0 2231 if (N0.getOperand(0) == N1) 2232 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2233 DAG.getConstant(0, N0.getValueType()), Cond); 2234 if (N0.getOperand(1) == N1) { 2235 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2236 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2237 DAG.getConstant(0, N0.getValueType()), Cond); 2238 else if (N0.getNode()->hasOneUse()) { 2239 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2240 // (Z-X) == X --> Z == X<<1 2241 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2242 N1, 2243 DAG.getConstant(1, getShiftAmountTy())); 2244 if (!DCI.isCalledByLegalizer()) 2245 DCI.AddToWorklist(SH.getNode()); 2246 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2247 } 2248 } 2249 } 2250 2251 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2252 N1.getOpcode() == ISD::XOR) { 2253 // Simplify X == (X+Z) --> Z == 0 2254 if (N1.getOperand(0) == N0) { 2255 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2256 DAG.getConstant(0, N1.getValueType()), Cond); 2257 } else if (N1.getOperand(1) == N0) { 2258 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2259 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2260 DAG.getConstant(0, N1.getValueType()), Cond); 2261 } else if (N1.getNode()->hasOneUse()) { 2262 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2263 // X == (Z-X) --> X<<1 == Z 2264 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2265 DAG.getConstant(1, getShiftAmountTy())); 2266 if (!DCI.isCalledByLegalizer()) 2267 DCI.AddToWorklist(SH.getNode()); 2268 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2269 } 2270 } 2271 } 2272 2273 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2274 // Note that where y is variable and is known to have at most 2275 // one bit set (for example, if it is z&1) we cannot do this; 2276 // the expressions are not equivalent when y==0. 2277 if (N0.getOpcode() == ISD::AND) 2278 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2279 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2280 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2281 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2282 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2283 } 2284 } 2285 if (N1.getOpcode() == ISD::AND) 2286 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2287 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2288 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2289 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2290 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2291 } 2292 } 2293 } 2294 2295 // Fold away ALL boolean setcc's. 2296 SDValue Temp; 2297 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2298 switch (Cond) { 2299 default: llvm_unreachable("Unknown integer setcc!"); 2300 case ISD::SETEQ: // X == Y -> ~(X^Y) 2301 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2302 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2303 if (!DCI.isCalledByLegalizer()) 2304 DCI.AddToWorklist(Temp.getNode()); 2305 break; 2306 case ISD::SETNE: // X != Y --> (X^Y) 2307 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2308 break; 2309 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2310 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2311 Temp = DAG.getNOT(dl, N0, MVT::i1); 2312 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2313 if (!DCI.isCalledByLegalizer()) 2314 DCI.AddToWorklist(Temp.getNode()); 2315 break; 2316 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2317 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2318 Temp = DAG.getNOT(dl, N1, MVT::i1); 2319 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2320 if (!DCI.isCalledByLegalizer()) 2321 DCI.AddToWorklist(Temp.getNode()); 2322 break; 2323 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2324 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2325 Temp = DAG.getNOT(dl, N0, MVT::i1); 2326 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2327 if (!DCI.isCalledByLegalizer()) 2328 DCI.AddToWorklist(Temp.getNode()); 2329 break; 2330 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2331 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2332 Temp = DAG.getNOT(dl, N1, MVT::i1); 2333 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2334 break; 2335 } 2336 if (VT != MVT::i1) { 2337 if (!DCI.isCalledByLegalizer()) 2338 DCI.AddToWorklist(N0.getNode()); 2339 // FIXME: If running after legalize, we probably can't do this. 2340 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2341 } 2342 return N0; 2343 } 2344 2345 // Could not fold it. 2346 return SDValue(); 2347} 2348 2349/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2350/// node is a GlobalAddress + offset. 2351bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2352 int64_t &Offset) const { 2353 if (isa<GlobalAddressSDNode>(N)) { 2354 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2355 GA = GASD->getGlobal(); 2356 Offset += GASD->getOffset(); 2357 return true; 2358 } 2359 2360 if (N->getOpcode() == ISD::ADD) { 2361 SDValue N1 = N->getOperand(0); 2362 SDValue N2 = N->getOperand(1); 2363 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2364 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2365 if (V) { 2366 Offset += V->getSExtValue(); 2367 return true; 2368 } 2369 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2370 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2371 if (V) { 2372 Offset += V->getSExtValue(); 2373 return true; 2374 } 2375 } 2376 } 2377 return false; 2378} 2379 2380 2381SDValue TargetLowering:: 2382PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2383 // Default implementation: no optimization. 2384 return SDValue(); 2385} 2386 2387//===----------------------------------------------------------------------===// 2388// Inline Assembler Implementation Methods 2389//===----------------------------------------------------------------------===// 2390 2391 2392TargetLowering::ConstraintType 2393TargetLowering::getConstraintType(const std::string &Constraint) const { 2394 // FIXME: lots more standard ones to handle. 2395 if (Constraint.size() == 1) { 2396 switch (Constraint[0]) { 2397 default: break; 2398 case 'r': return C_RegisterClass; 2399 case 'm': // memory 2400 case 'o': // offsetable 2401 case 'V': // not offsetable 2402 return C_Memory; 2403 case 'i': // Simple Integer or Relocatable Constant 2404 case 'n': // Simple Integer 2405 case 's': // Relocatable Constant 2406 case 'X': // Allow ANY value. 2407 case 'I': // Target registers. 2408 case 'J': 2409 case 'K': 2410 case 'L': 2411 case 'M': 2412 case 'N': 2413 case 'O': 2414 case 'P': 2415 return C_Other; 2416 } 2417 } 2418 2419 if (Constraint.size() > 1 && Constraint[0] == '{' && 2420 Constraint[Constraint.size()-1] == '}') 2421 return C_Register; 2422 return C_Unknown; 2423} 2424 2425/// LowerXConstraint - try to replace an X constraint, which matches anything, 2426/// with another that has more specific requirements based on the type of the 2427/// corresponding operand. 2428const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2429 if (ConstraintVT.isInteger()) 2430 return "r"; 2431 if (ConstraintVT.isFloatingPoint()) 2432 return "f"; // works for many targets 2433 return 0; 2434} 2435 2436/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2437/// vector. If it is invalid, don't add anything to Ops. 2438void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2439 char ConstraintLetter, 2440 std::vector<SDValue> &Ops, 2441 SelectionDAG &DAG) const { 2442 switch (ConstraintLetter) { 2443 default: break; 2444 case 'X': // Allows any operand; labels (basic block) use this. 2445 if (Op.getOpcode() == ISD::BasicBlock) { 2446 Ops.push_back(Op); 2447 return; 2448 } 2449 // fall through 2450 case 'i': // Simple Integer or Relocatable Constant 2451 case 'n': // Simple Integer 2452 case 's': { // Relocatable Constant 2453 // These operands are interested in values of the form (GV+C), where C may 2454 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2455 // is possible and fine if either GV or C are missing. 2456 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2457 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2458 2459 // If we have "(add GV, C)", pull out GV/C 2460 if (Op.getOpcode() == ISD::ADD) { 2461 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2462 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2463 if (C == 0 || GA == 0) { 2464 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2465 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2466 } 2467 if (C == 0 || GA == 0) 2468 C = 0, GA = 0; 2469 } 2470 2471 // If we find a valid operand, map to the TargetXXX version so that the 2472 // value itself doesn't get selected. 2473 if (GA) { // Either &GV or &GV+C 2474 if (ConstraintLetter != 'n') { 2475 int64_t Offs = GA->getOffset(); 2476 if (C) Offs += C->getZExtValue(); 2477 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2478 C->getDebugLoc(), 2479 Op.getValueType(), Offs)); 2480 return; 2481 } 2482 } 2483 if (C) { // just C, no GV. 2484 // Simple constants are not allowed for 's'. 2485 if (ConstraintLetter != 's') { 2486 // gcc prints these as sign extended. Sign extend value to 64 bits 2487 // now; without this it would get ZExt'd later in 2488 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2489 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2490 MVT::i64)); 2491 return; 2492 } 2493 } 2494 break; 2495 } 2496 } 2497} 2498 2499std::vector<unsigned> TargetLowering:: 2500getRegClassForInlineAsmConstraint(const std::string &Constraint, 2501 EVT VT) const { 2502 return std::vector<unsigned>(); 2503} 2504 2505 2506std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2507getRegForInlineAsmConstraint(const std::string &Constraint, 2508 EVT VT) const { 2509 if (Constraint[0] != '{') 2510 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2511 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2512 2513 // Remove the braces from around the name. 2514 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2515 2516 // Figure out which register class contains this reg. 2517 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2518 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2519 E = RI->regclass_end(); RCI != E; ++RCI) { 2520 const TargetRegisterClass *RC = *RCI; 2521 2522 // If none of the value types for this register class are valid, we 2523 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2524 bool isLegal = false; 2525 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2526 I != E; ++I) { 2527 if (isTypeLegal(*I)) { 2528 isLegal = true; 2529 break; 2530 } 2531 } 2532 2533 if (!isLegal) continue; 2534 2535 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2536 I != E; ++I) { 2537 if (RegName.equals_lower(RI->getName(*I))) 2538 return std::make_pair(*I, RC); 2539 } 2540 } 2541 2542 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2543} 2544 2545//===----------------------------------------------------------------------===// 2546// Constraint Selection. 2547 2548/// isMatchingInputConstraint - Return true of this is an input operand that is 2549/// a matching constraint like "4". 2550bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2551 assert(!ConstraintCode.empty() && "No known constraint!"); 2552 return isdigit(ConstraintCode[0]); 2553} 2554 2555/// getMatchedOperand - If this is an input matching constraint, this method 2556/// returns the output operand it matches. 2557unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2558 assert(!ConstraintCode.empty() && "No known constraint!"); 2559 return atoi(ConstraintCode.c_str()); 2560} 2561 2562 2563/// getConstraintGenerality - Return an integer indicating how general CT 2564/// is. 2565static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2566 switch (CT) { 2567 default: llvm_unreachable("Unknown constraint type!"); 2568 case TargetLowering::C_Other: 2569 case TargetLowering::C_Unknown: 2570 return 0; 2571 case TargetLowering::C_Register: 2572 return 1; 2573 case TargetLowering::C_RegisterClass: 2574 return 2; 2575 case TargetLowering::C_Memory: 2576 return 3; 2577 } 2578} 2579 2580/// ChooseConstraint - If there are multiple different constraints that we 2581/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2582/// This is somewhat tricky: constraints fall into four classes: 2583/// Other -> immediates and magic values 2584/// Register -> one specific register 2585/// RegisterClass -> a group of regs 2586/// Memory -> memory 2587/// Ideally, we would pick the most specific constraint possible: if we have 2588/// something that fits into a register, we would pick it. The problem here 2589/// is that if we have something that could either be in a register or in 2590/// memory that use of the register could cause selection of *other* 2591/// operands to fail: they might only succeed if we pick memory. Because of 2592/// this the heuristic we use is: 2593/// 2594/// 1) If there is an 'other' constraint, and if the operand is valid for 2595/// that constraint, use it. This makes us take advantage of 'i' 2596/// constraints when available. 2597/// 2) Otherwise, pick the most general constraint present. This prefers 2598/// 'm' over 'r', for example. 2599/// 2600static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2601 const TargetLowering &TLI, 2602 SDValue Op, SelectionDAG *DAG) { 2603 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2604 unsigned BestIdx = 0; 2605 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2606 int BestGenerality = -1; 2607 2608 // Loop over the options, keeping track of the most general one. 2609 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2610 TargetLowering::ConstraintType CType = 2611 TLI.getConstraintType(OpInfo.Codes[i]); 2612 2613 // If this is an 'other' constraint, see if the operand is valid for it. 2614 // For example, on X86 we might have an 'rI' constraint. If the operand 2615 // is an integer in the range [0..31] we want to use I (saving a load 2616 // of a register), otherwise we must use 'r'. 2617 if (CType == TargetLowering::C_Other && Op.getNode()) { 2618 assert(OpInfo.Codes[i].size() == 1 && 2619 "Unhandled multi-letter 'other' constraint"); 2620 std::vector<SDValue> ResultOps; 2621 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2622 ResultOps, *DAG); 2623 if (!ResultOps.empty()) { 2624 BestType = CType; 2625 BestIdx = i; 2626 break; 2627 } 2628 } 2629 2630 // Things with matching constraints can only be registers, per gcc 2631 // documentation. This mainly affects "g" constraints. 2632 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2633 continue; 2634 2635 // This constraint letter is more general than the previous one, use it. 2636 int Generality = getConstraintGenerality(CType); 2637 if (Generality > BestGenerality) { 2638 BestType = CType; 2639 BestIdx = i; 2640 BestGenerality = Generality; 2641 } 2642 } 2643 2644 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2645 OpInfo.ConstraintType = BestType; 2646} 2647 2648/// ComputeConstraintToUse - Determines the constraint code and constraint 2649/// type to use for the specific AsmOperandInfo, setting 2650/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2651void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2652 SDValue Op, 2653 SelectionDAG *DAG) const { 2654 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2655 2656 // Single-letter constraints ('r') are very common. 2657 if (OpInfo.Codes.size() == 1) { 2658 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2659 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2660 } else { 2661 ChooseConstraint(OpInfo, *this, Op, DAG); 2662 } 2663 2664 // 'X' matches anything. 2665 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2666 // Labels and constants are handled elsewhere ('X' is the only thing 2667 // that matches labels). For Functions, the type here is the type of 2668 // the result, which is not what we want to look at; leave them alone. 2669 Value *v = OpInfo.CallOperandVal; 2670 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2671 OpInfo.CallOperandVal = v; 2672 return; 2673 } 2674 2675 // Otherwise, try to resolve it to something we know about by looking at 2676 // the actual operand type. 2677 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2678 OpInfo.ConstraintCode = Repl; 2679 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2680 } 2681 } 2682} 2683 2684//===----------------------------------------------------------------------===// 2685// Loop Strength Reduction hooks 2686//===----------------------------------------------------------------------===// 2687 2688/// isLegalAddressingMode - Return true if the addressing mode represented 2689/// by AM is legal for this target, for a load/store of the specified type. 2690bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2691 const Type *Ty) const { 2692 // The default implementation of this implements a conservative RISCy, r+r and 2693 // r+i addr mode. 2694 2695 // Allows a sign-extended 16-bit immediate field. 2696 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2697 return false; 2698 2699 // No global is ever allowed as a base. 2700 if (AM.BaseGV) 2701 return false; 2702 2703 // Only support r+r, 2704 switch (AM.Scale) { 2705 case 0: // "r+i" or just "i", depending on HasBaseReg. 2706 break; 2707 case 1: 2708 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2709 return false; 2710 // Otherwise we have r+r or r+i. 2711 break; 2712 case 2: 2713 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2714 return false; 2715 // Allow 2*r as r+r. 2716 break; 2717 } 2718 2719 return true; 2720} 2721 2722/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2723/// return a DAG expression to select that will generate the same value by 2724/// multiplying by a magic number. See: 2725/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2726SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2727 std::vector<SDNode*>* Created) const { 2728 EVT VT = N->getValueType(0); 2729 DebugLoc dl= N->getDebugLoc(); 2730 2731 // Check to see if we can do this. 2732 // FIXME: We should be more aggressive here. 2733 if (!isTypeLegal(VT)) 2734 return SDValue(); 2735 2736 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2737 APInt::ms magics = d.magic(); 2738 2739 // Multiply the numerator (operand 0) by the magic value 2740 // FIXME: We should support doing a MUL in a wider type 2741 SDValue Q; 2742 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2743 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2744 DAG.getConstant(magics.m, VT)); 2745 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2746 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2747 N->getOperand(0), 2748 DAG.getConstant(magics.m, VT)).getNode(), 1); 2749 else 2750 return SDValue(); // No mulhs or equvialent 2751 // If d > 0 and m < 0, add the numerator 2752 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2753 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2754 if (Created) 2755 Created->push_back(Q.getNode()); 2756 } 2757 // If d < 0 and m > 0, subtract the numerator. 2758 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2759 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2760 if (Created) 2761 Created->push_back(Q.getNode()); 2762 } 2763 // Shift right algebraic if shift value is nonzero 2764 if (magics.s > 0) { 2765 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2766 DAG.getConstant(magics.s, getShiftAmountTy())); 2767 if (Created) 2768 Created->push_back(Q.getNode()); 2769 } 2770 // Extract the sign bit and add it to the quotient 2771 SDValue T = 2772 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2773 getShiftAmountTy())); 2774 if (Created) 2775 Created->push_back(T.getNode()); 2776 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2777} 2778 2779/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2780/// return a DAG expression to select that will generate the same value by 2781/// multiplying by a magic number. See: 2782/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2783SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2784 std::vector<SDNode*>* Created) const { 2785 EVT VT = N->getValueType(0); 2786 DebugLoc dl = N->getDebugLoc(); 2787 2788 // Check to see if we can do this. 2789 // FIXME: We should be more aggressive here. 2790 if (!isTypeLegal(VT)) 2791 return SDValue(); 2792 2793 // FIXME: We should use a narrower constant when the upper 2794 // bits are known to be zero. 2795 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2796 APInt::mu magics = N1C->getAPIntValue().magicu(); 2797 2798 // Multiply the numerator (operand 0) by the magic value 2799 // FIXME: We should support doing a MUL in a wider type 2800 SDValue Q; 2801 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2802 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2803 DAG.getConstant(magics.m, VT)); 2804 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2805 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2806 N->getOperand(0), 2807 DAG.getConstant(magics.m, VT)).getNode(), 1); 2808 else 2809 return SDValue(); // No mulhu or equvialent 2810 if (Created) 2811 Created->push_back(Q.getNode()); 2812 2813 if (magics.a == 0) { 2814 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2815 "We shouldn't generate an undefined shift!"); 2816 return DAG.getNode(ISD::SRL, dl, VT, Q, 2817 DAG.getConstant(magics.s, getShiftAmountTy())); 2818 } else { 2819 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2820 if (Created) 2821 Created->push_back(NPQ.getNode()); 2822 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2823 DAG.getConstant(1, getShiftAmountTy())); 2824 if (Created) 2825 Created->push_back(NPQ.getNode()); 2826 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2827 if (Created) 2828 Created->push_back(NPQ.getNode()); 2829 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2830 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2831 } 2832} 2833