TargetLowering.cpp revision f9a5e40b90e5a98cfae5c0f8a42eedd71c849dbc
1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/CodeGen/Analysis.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineJumpTableInfo.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/IR/DataLayout.h" 23#include "llvm/IR/DerivedTypes.h" 24#include "llvm/IR/GlobalVariable.h" 25#include "llvm/MC/MCAsmInfo.h" 26#include "llvm/MC/MCExpr.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetLoweringObjectFile.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Target/TargetRegisterInfo.h" 33#include <cctype> 34using namespace llvm; 35 36/// NOTE: The constructor takes ownership of TLOF. 37TargetLowering::TargetLowering(const TargetMachine &tm, 38 const TargetLoweringObjectFile *tlof) 39 : TargetLoweringBase(tm, tlof) {} 40 41const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 42 return NULL; 43} 44 45/// Check whether a given call node is in tail position within its function. If 46/// so, it sets Chain to the input chain of the tail call. 47bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 48 SDValue &Chain) const { 49 const Function *F = DAG.getMachineFunction().getFunction(); 50 51 // Conservatively require the attributes of the call to match those of 52 // the return. Ignore noalias because it doesn't affect the call sequence. 53 AttributeSet CallerAttrs = F->getAttributes(); 54 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex) 55 .removeAttribute(Attribute::NoAlias).hasAttributes()) 56 return false; 57 58 // It's not safe to eliminate the sign / zero extension of the return value. 59 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) || 60 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 61 return false; 62 63 // Check if the only use is a function return node. 64 return isUsedByReturnOnly(Node, Chain); 65} 66 67 68/// Generate a libcall taking the given operands as arguments and returning a 69/// result of type RetVT. 70std::pair<SDValue, SDValue> 71TargetLowering::makeLibCall(SelectionDAG &DAG, 72 RTLIB::Libcall LC, EVT RetVT, 73 const SDValue *Ops, unsigned NumOps, 74 bool isSigned, SDLoc dl, 75 bool doesNotReturn, 76 bool isReturnValueUsed) const { 77 TargetLowering::ArgListTy Args; 78 Args.reserve(NumOps); 79 80 TargetLowering::ArgListEntry Entry; 81 for (unsigned i = 0; i != NumOps; ++i) { 82 Entry.Node = Ops[i]; 83 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 84 Entry.isSExt = isSigned; 85 Entry.isZExt = !isSigned; 86 Args.push_back(Entry); 87 } 88 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy()); 89 90 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 91 TargetLowering:: 92 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 93 false, 0, getLibcallCallingConv(LC), 94 /*isTailCall=*/false, 95 doesNotReturn, isReturnValueUsed, Callee, Args, 96 DAG, dl); 97 return LowerCallTo(CLI); 98} 99 100 101/// SoftenSetCCOperands - Soften the operands of a comparison. This code is 102/// shared among BR_CC, SELECT_CC, and SETCC handlers. 103void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, 104 SDValue &NewLHS, SDValue &NewRHS, 105 ISD::CondCode &CCCode, 106 SDLoc dl) const { 107 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) 108 && "Unsupported setcc type!"); 109 110 // Expand into one or more soft-fp libcall(s). 111 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 112 switch (CCCode) { 113 case ISD::SETEQ: 114 case ISD::SETOEQ: 115 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 116 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 117 break; 118 case ISD::SETNE: 119 case ISD::SETUNE: 120 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : 121 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; 122 break; 123 case ISD::SETGE: 124 case ISD::SETOGE: 125 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 126 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 127 break; 128 case ISD::SETLT: 129 case ISD::SETOLT: 130 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 131 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 132 break; 133 case ISD::SETLE: 134 case ISD::SETOLE: 135 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 136 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 137 break; 138 case ISD::SETGT: 139 case ISD::SETOGT: 140 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 141 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 142 break; 143 case ISD::SETUO: 144 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 145 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 146 break; 147 case ISD::SETO: 148 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : 149 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128; 150 break; 151 default: 152 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : 153 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128; 154 switch (CCCode) { 155 case ISD::SETONE: 156 // SETONE = SETOLT | SETOGT 157 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 158 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 159 // Fallthrough 160 case ISD::SETUGT: 161 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : 162 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128; 163 break; 164 case ISD::SETUGE: 165 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : 166 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; 167 break; 168 case ISD::SETULT: 169 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : 170 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; 171 break; 172 case ISD::SETULE: 173 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : 174 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128; 175 break; 176 case ISD::SETUEQ: 177 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : 178 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; 179 break; 180 default: llvm_unreachable("Do not know how to soften this setcc!"); 181 } 182 } 183 184 // Use the target specific return value for comparions lib calls. 185 EVT RetVT = getCmpLibcallReturnType(); 186 SDValue Ops[2] = { NewLHS, NewRHS }; 187 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/, 188 dl).first; 189 NewRHS = DAG.getConstant(0, RetVT); 190 CCCode = getCmpLibcallCC(LC1); 191 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 192 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, 193 getSetCCResultType(*DAG.getContext(), RetVT), 194 NewLHS, NewRHS, DAG.getCondCode(CCCode)); 195 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, 196 dl).first; 197 NewLHS = DAG.getNode(ISD::SETCC, dl, 198 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS, 199 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); 200 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); 201 NewRHS = SDValue(); 202 } 203} 204 205/// getJumpTableEncoding - Return the entry encoding for a jump table in the 206/// current function. The returned value is a member of the 207/// MachineJumpTableInfo::JTEntryKind enum. 208unsigned TargetLowering::getJumpTableEncoding() const { 209 // In non-pic modes, just use the address of a block. 210 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 211 return MachineJumpTableInfo::EK_BlockAddress; 212 213 // In PIC mode, if the target supports a GPRel32 directive, use it. 214 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 215 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 216 217 // Otherwise, use a label difference. 218 return MachineJumpTableInfo::EK_LabelDifference32; 219} 220 221SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 222 SelectionDAG &DAG) const { 223 // If our PIC model is GP relative, use the global offset table as the base. 224 unsigned JTEncoding = getJumpTableEncoding(); 225 226 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) || 227 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress)) 228 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0)); 229 230 return Table; 231} 232 233/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 234/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 235/// MCExpr. 236const MCExpr * 237TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 238 unsigned JTI,MCContext &Ctx) const{ 239 // The normal PIC reloc base is the label at the start of the jump table. 240 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 241} 242 243bool 244TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 245 // Assume that everything is safe in static mode. 246 if (getTargetMachine().getRelocationModel() == Reloc::Static) 247 return true; 248 249 // In dynamic-no-pic mode, assume that known defined values are safe. 250 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 251 GA && 252 !GA->getGlobal()->isDeclaration() && 253 !GA->getGlobal()->isWeakForLinker()) 254 return true; 255 256 // Otherwise assume nothing is safe. 257 return false; 258} 259 260//===----------------------------------------------------------------------===// 261// Optimization Methods 262//===----------------------------------------------------------------------===// 263 264/// ShrinkDemandedConstant - Check to see if the specified operand of the 265/// specified instruction is a constant integer. If so, check to see if there 266/// are any bits set in the constant that are not demanded. If so, shrink the 267/// constant and return true. 268bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 269 const APInt &Demanded) { 270 SDLoc dl(Op); 271 272 // FIXME: ISD::SELECT, ISD::SELECT_CC 273 switch (Op.getOpcode()) { 274 default: break; 275 case ISD::XOR: 276 case ISD::AND: 277 case ISD::OR: { 278 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 279 if (!C) return false; 280 281 if (Op.getOpcode() == ISD::XOR && 282 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 283 return false; 284 285 // if we can expand it to have all bits set, do it 286 if (C->getAPIntValue().intersects(~Demanded)) { 287 EVT VT = Op.getValueType(); 288 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 289 DAG.getConstant(Demanded & 290 C->getAPIntValue(), 291 VT)); 292 return CombineTo(Op, New); 293 } 294 295 break; 296 } 297 } 298 299 return false; 300} 301 302/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 303/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 304/// cast, but it could be generalized for targets with other types of 305/// implicit widening casts. 306bool 307TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 308 unsigned BitWidth, 309 const APInt &Demanded, 310 SDLoc dl) { 311 assert(Op.getNumOperands() == 2 && 312 "ShrinkDemandedOp only supports binary operators!"); 313 assert(Op.getNode()->getNumValues() == 1 && 314 "ShrinkDemandedOp only supports nodes with one result!"); 315 316 // Don't do this if the node has another user, which may require the 317 // full value. 318 if (!Op.getNode()->hasOneUse()) 319 return false; 320 321 // Search for the smallest integer type with free casts to and from 322 // Op's type. For expedience, just check power-of-2 integer types. 323 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 324 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros(); 325 unsigned SmallVTBits = DemandedSize; 326 if (!isPowerOf2_32(SmallVTBits)) 327 SmallVTBits = NextPowerOf2(SmallVTBits); 328 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 329 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 330 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 331 TLI.isZExtFree(SmallVT, Op.getValueType())) { 332 // We found a type with free casts. 333 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 334 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 335 Op.getNode()->getOperand(0)), 336 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 337 Op.getNode()->getOperand(1))); 338 bool NeedZext = DemandedSize > SmallVTBits; 339 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, 340 dl, Op.getValueType(), X); 341 return CombineTo(Op, Z); 342 } 343 } 344 return false; 345} 346 347/// SimplifyDemandedBits - Look at Op. At this point, we know that only the 348/// DemandedMask bits of the result of Op are ever used downstream. If we can 349/// use this information to simplify Op, create a new simplified DAG node and 350/// return true, returning the original and new nodes in Old and New. Otherwise, 351/// analyze the expression and return a mask of KnownOne and KnownZero bits for 352/// the expression (used to simplify the caller). The KnownZero/One bits may 353/// only be accurate for those bits in the DemandedMask. 354bool TargetLowering::SimplifyDemandedBits(SDValue Op, 355 const APInt &DemandedMask, 356 APInt &KnownZero, 357 APInt &KnownOne, 358 TargetLoweringOpt &TLO, 359 unsigned Depth) const { 360 unsigned BitWidth = DemandedMask.getBitWidth(); 361 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 362 "Mask size mismatches value type size!"); 363 APInt NewMask = DemandedMask; 364 SDLoc dl(Op); 365 366 // Don't know anything. 367 KnownZero = KnownOne = APInt(BitWidth, 0); 368 369 // Other users may use these bits. 370 if (!Op.getNode()->hasOneUse()) { 371 if (Depth != 0) { 372 // If not at the root, Just compute the KnownZero/KnownOne bits to 373 // simplify things downstream. 374 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 375 return false; 376 } 377 // If this is the root being simplified, allow it to have multiple uses, 378 // just set the NewMask to all bits. 379 NewMask = APInt::getAllOnesValue(BitWidth); 380 } else if (DemandedMask == 0) { 381 // Not demanding any bits from Op. 382 if (Op.getOpcode() != ISD::UNDEF) 383 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 384 return false; 385 } else if (Depth == 6) { // Limit search depth. 386 return false; 387 } 388 389 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 390 switch (Op.getOpcode()) { 391 case ISD::Constant: 392 // We know all of the bits for a constant! 393 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue(); 394 KnownZero = ~KnownOne; 395 return false; // Don't fall through, will infinitely loop. 396 case ISD::AND: 397 // If the RHS is a constant, check to see if the LHS would be zero without 398 // using the bits from the RHS. Below, we use knowledge about the RHS to 399 // simplify the LHS, here we're using information from the LHS to simplify 400 // the RHS. 401 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 402 APInt LHSZero, LHSOne; 403 // Do not increment Depth here; that can cause an infinite loop. 404 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); 405 // If the LHS already has zeros where RHSC does, this and is dead. 406 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 407 return TLO.CombineTo(Op, Op.getOperand(0)); 408 // If any of the set bits in the RHS are known zero on the LHS, shrink 409 // the constant. 410 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 411 return true; 412 } 413 414 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 415 KnownOne, TLO, Depth+1)) 416 return true; 417 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 418 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 419 KnownZero2, KnownOne2, TLO, Depth+1)) 420 return true; 421 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 422 423 // If all of the demanded bits are known one on one side, return the other. 424 // These bits cannot contribute to the result of the 'and'. 425 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 426 return TLO.CombineTo(Op, Op.getOperand(0)); 427 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 428 return TLO.CombineTo(Op, Op.getOperand(1)); 429 // If all of the demanded bits in the inputs are known zeros, return zero. 430 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 431 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 432 // If the RHS is a constant, see if we can simplify it. 433 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 434 return true; 435 // If the operation can be done in a smaller type, do so. 436 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 437 return true; 438 439 // Output known-1 bits are only known if set in both the LHS & RHS. 440 KnownOne &= KnownOne2; 441 // Output known-0 are known to be clear if zero in either the LHS | RHS. 442 KnownZero |= KnownZero2; 443 break; 444 case ISD::OR: 445 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 446 KnownOne, TLO, Depth+1)) 447 return true; 448 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 449 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 450 KnownZero2, KnownOne2, TLO, Depth+1)) 451 return true; 452 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 453 454 // If all of the demanded bits are known zero on one side, return the other. 455 // These bits cannot contribute to the result of the 'or'. 456 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 457 return TLO.CombineTo(Op, Op.getOperand(0)); 458 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 459 return TLO.CombineTo(Op, Op.getOperand(1)); 460 // If all of the potentially set bits on one side are known to be set on 461 // the other side, just use the 'other' side. 462 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 463 return TLO.CombineTo(Op, Op.getOperand(0)); 464 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 465 return TLO.CombineTo(Op, Op.getOperand(1)); 466 // If the RHS is a constant, see if we can simplify it. 467 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 468 return true; 469 // If the operation can be done in a smaller type, do so. 470 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 471 return true; 472 473 // Output known-0 bits are only known if clear in both the LHS & RHS. 474 KnownZero &= KnownZero2; 475 // Output known-1 are known to be set if set in either the LHS | RHS. 476 KnownOne |= KnownOne2; 477 break; 478 case ISD::XOR: 479 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 480 KnownOne, TLO, Depth+1)) 481 return true; 482 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 483 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 484 KnownOne2, TLO, Depth+1)) 485 return true; 486 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 487 488 // If all of the demanded bits are known zero on one side, return the other. 489 // These bits cannot contribute to the result of the 'xor'. 490 if ((KnownZero & NewMask) == NewMask) 491 return TLO.CombineTo(Op, Op.getOperand(0)); 492 if ((KnownZero2 & NewMask) == NewMask) 493 return TLO.CombineTo(Op, Op.getOperand(1)); 494 // If the operation can be done in a smaller type, do so. 495 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 496 return true; 497 498 // If all of the unknown bits are known to be zero on one side or the other 499 // (but not both) turn this into an *inclusive* or. 500 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 501 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 502 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 503 Op.getOperand(0), 504 Op.getOperand(1))); 505 506 // Output known-0 bits are known if clear or set in both the LHS & RHS. 507 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 508 // Output known-1 are known to be set if set in only one of the LHS, RHS. 509 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 510 511 // If all of the demanded bits on one side are known, and all of the set 512 // bits on that side are also known to be set on the other side, turn this 513 // into an AND, as we know the bits will be cleared. 514 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 515 // NB: it is okay if more bits are known than are requested 516 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side 517 if (KnownOne == KnownOne2) { // set bits are the same on both sides 518 EVT VT = Op.getValueType(); 519 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 520 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 521 Op.getOperand(0), ANDC)); 522 } 523 } 524 525 // If the RHS is a constant, see if we can simplify it. 526 // for XOR, we prefer to force bits to 1 if they will make a -1. 527 // if we can't force bits, try to shrink constant 528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 529 APInt Expanded = C->getAPIntValue() | (~NewMask); 530 // if we can expand it to have all bits set, do it 531 if (Expanded.isAllOnesValue()) { 532 if (Expanded != C->getAPIntValue()) { 533 EVT VT = Op.getValueType(); 534 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 535 TLO.DAG.getConstant(Expanded, VT)); 536 return TLO.CombineTo(Op, New); 537 } 538 // if it already has all the bits set, nothing to change 539 // but don't shrink either! 540 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 541 return true; 542 } 543 } 544 545 KnownZero = KnownZeroOut; 546 KnownOne = KnownOneOut; 547 break; 548 case ISD::SELECT: 549 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 550 KnownOne, TLO, Depth+1)) 551 return true; 552 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 553 KnownOne2, TLO, Depth+1)) 554 return true; 555 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 556 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 557 558 // If the operands are constants, see if we can simplify them. 559 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 560 return true; 561 562 // Only known if known in both the LHS and RHS. 563 KnownOne &= KnownOne2; 564 KnownZero &= KnownZero2; 565 break; 566 case ISD::SELECT_CC: 567 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 568 KnownOne, TLO, Depth+1)) 569 return true; 570 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 571 KnownOne2, TLO, Depth+1)) 572 return true; 573 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 574 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 575 576 // If the operands are constants, see if we can simplify them. 577 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 578 return true; 579 580 // Only known if known in both the LHS and RHS. 581 KnownOne &= KnownOne2; 582 KnownZero &= KnownZero2; 583 break; 584 case ISD::SHL: 585 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 586 unsigned ShAmt = SA->getZExtValue(); 587 SDValue InOp = Op.getOperand(0); 588 589 // If the shift count is an invalid immediate, don't do anything. 590 if (ShAmt >= BitWidth) 591 break; 592 593 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 594 // single shift. We can do this if the bottom bits (which are shifted 595 // out) are never demanded. 596 if (InOp.getOpcode() == ISD::SRL && 597 isa<ConstantSDNode>(InOp.getOperand(1))) { 598 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 599 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 600 unsigned Opc = ISD::SHL; 601 int Diff = ShAmt-C1; 602 if (Diff < 0) { 603 Diff = -Diff; 604 Opc = ISD::SRL; 605 } 606 607 SDValue NewSA = 608 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 609 EVT VT = Op.getValueType(); 610 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 611 InOp.getOperand(0), NewSA)); 612 } 613 } 614 615 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), 616 KnownZero, KnownOne, TLO, Depth+1)) 617 return true; 618 619 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits 620 // are not demanded. This will likely allow the anyext to be folded away. 621 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) { 622 SDValue InnerOp = InOp.getNode()->getOperand(0); 623 EVT InnerVT = InnerOp.getValueType(); 624 unsigned InnerBits = InnerVT.getSizeInBits(); 625 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 && 626 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 627 EVT ShTy = getShiftAmountTy(InnerVT); 628 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) 629 ShTy = InnerVT; 630 SDValue NarrowShl = 631 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 632 TLO.DAG.getConstant(ShAmt, ShTy)); 633 return 634 TLO.CombineTo(Op, 635 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), 636 NarrowShl)); 637 } 638 // Repeat the SHL optimization above in cases where an extension 639 // intervenes: (shl (anyext (shr x, c1)), c2) to 640 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits 641 // aren't demanded (as above) and that the shifted upper c1 bits of 642 // x aren't demanded. 643 if (InOp.hasOneUse() && 644 InnerOp.getOpcode() == ISD::SRL && 645 InnerOp.hasOneUse() && 646 isa<ConstantSDNode>(InnerOp.getOperand(1))) { 647 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1)) 648 ->getZExtValue(); 649 if (InnerShAmt < ShAmt && 650 InnerShAmt < InnerBits && 651 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && 652 NewMask.trunc(ShAmt) == 0) { 653 SDValue NewSA = 654 TLO.DAG.getConstant(ShAmt - InnerShAmt, 655 Op.getOperand(1).getValueType()); 656 EVT VT = Op.getValueType(); 657 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, 658 InnerOp.getOperand(0)); 659 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, 660 NewExt, NewSA)); 661 } 662 } 663 } 664 665 KnownZero <<= SA->getZExtValue(); 666 KnownOne <<= SA->getZExtValue(); 667 // low bits known zero. 668 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 669 } 670 break; 671 case ISD::SRL: 672 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 673 EVT VT = Op.getValueType(); 674 unsigned ShAmt = SA->getZExtValue(); 675 unsigned VTSize = VT.getSizeInBits(); 676 SDValue InOp = Op.getOperand(0); 677 678 // If the shift count is an invalid immediate, don't do anything. 679 if (ShAmt >= BitWidth) 680 break; 681 682 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 683 // single shift. We can do this if the top bits (which are shifted out) 684 // are never demanded. 685 if (InOp.getOpcode() == ISD::SHL && 686 isa<ConstantSDNode>(InOp.getOperand(1))) { 687 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 688 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 689 unsigned Opc = ISD::SRL; 690 int Diff = ShAmt-C1; 691 if (Diff < 0) { 692 Diff = -Diff; 693 Opc = ISD::SHL; 694 } 695 696 SDValue NewSA = 697 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 698 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 699 InOp.getOperand(0), NewSA)); 700 } 701 } 702 703 // Compute the new bits that are at the top now. 704 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 705 KnownZero, KnownOne, TLO, Depth+1)) 706 return true; 707 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 708 KnownZero = KnownZero.lshr(ShAmt); 709 KnownOne = KnownOne.lshr(ShAmt); 710 711 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 712 KnownZero |= HighBits; // High bits known zero. 713 } 714 break; 715 case ISD::SRA: 716 // If this is an arithmetic shift right and only the low-bit is set, we can 717 // always convert this into a logical shr, even if the shift amount is 718 // variable. The low bit of the shift cannot be an input sign bit unless 719 // the shift amount is >= the size of the datatype, which is undefined. 720 if (NewMask == 1) 721 return TLO.CombineTo(Op, 722 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 723 Op.getOperand(0), Op.getOperand(1))); 724 725 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 726 EVT VT = Op.getValueType(); 727 unsigned ShAmt = SA->getZExtValue(); 728 729 // If the shift count is an invalid immediate, don't do anything. 730 if (ShAmt >= BitWidth) 731 break; 732 733 APInt InDemandedMask = (NewMask << ShAmt); 734 735 // If any of the demanded bits are produced by the sign extension, we also 736 // demand the input sign bit. 737 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 738 if (HighBits.intersects(NewMask)) 739 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 740 741 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 742 KnownZero, KnownOne, TLO, Depth+1)) 743 return true; 744 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 745 KnownZero = KnownZero.lshr(ShAmt); 746 KnownOne = KnownOne.lshr(ShAmt); 747 748 // Handle the sign bit, adjusted to where it is now in the mask. 749 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 750 751 // If the input sign bit is known to be zero, or if none of the top bits 752 // are demanded, turn this into an unsigned shift right. 753 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) 754 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 755 Op.getOperand(0), 756 Op.getOperand(1))); 757 758 int Log2 = NewMask.exactLogBase2(); 759 if (Log2 >= 0) { 760 // The bit must come from the sign. 761 SDValue NewSA = 762 TLO.DAG.getConstant(BitWidth - 1 - Log2, 763 Op.getOperand(1).getValueType()); 764 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 765 Op.getOperand(0), NewSA)); 766 } 767 768 if (KnownOne.intersects(SignBit)) 769 // New bits are known one. 770 KnownOne |= HighBits; 771 } 772 break; 773 case ISD::SIGN_EXTEND_INREG: { 774 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 775 776 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1); 777 // If we only care about the highest bit, don't bother shifting right. 778 if (MsbMask == DemandedMask) { 779 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); 780 SDValue InOp = Op.getOperand(0); 781 782 // Compute the correct shift amount type, which must be getShiftAmountTy 783 // for scalar types after legalization. 784 EVT ShiftAmtTy = Op.getValueType(); 785 if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) 786 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy); 787 788 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); 789 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 790 Op.getValueType(), InOp, ShiftAmt)); 791 } 792 793 // Sign extension. Compute the demanded bits in the result that are not 794 // present in the input. 795 APInt NewBits = 796 APInt::getHighBitsSet(BitWidth, 797 BitWidth - ExVT.getScalarType().getSizeInBits()); 798 799 // If none of the extended bits are demanded, eliminate the sextinreg. 800 if ((NewBits & NewMask) == 0) 801 return TLO.CombineTo(Op, Op.getOperand(0)); 802 803 APInt InSignBit = 804 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); 805 APInt InputDemandedBits = 806 APInt::getLowBitsSet(BitWidth, 807 ExVT.getScalarType().getSizeInBits()) & 808 NewMask; 809 810 // Since the sign extended bits are demanded, we know that the sign 811 // bit is demanded. 812 InputDemandedBits |= InSignBit; 813 814 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 815 KnownZero, KnownOne, TLO, Depth+1)) 816 return true; 817 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 818 819 // If the sign bit of the input is known set or clear, then we know the 820 // top bits of the result. 821 822 // If the input sign bit is known zero, convert this into a zero extension. 823 if (KnownZero.intersects(InSignBit)) 824 return TLO.CombineTo(Op, 825 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); 826 827 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 828 KnownOne |= NewBits; 829 KnownZero &= ~NewBits; 830 } else { // Input sign bit unknown 831 KnownZero &= ~NewBits; 832 KnownOne &= ~NewBits; 833 } 834 break; 835 } 836 case ISD::ZERO_EXTEND: { 837 unsigned OperandBitWidth = 838 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 839 APInt InMask = NewMask.trunc(OperandBitWidth); 840 841 // If none of the top bits are demanded, convert this into an any_extend. 842 APInt NewBits = 843 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 844 if (!NewBits.intersects(NewMask)) 845 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 846 Op.getValueType(), 847 Op.getOperand(0))); 848 849 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 850 KnownZero, KnownOne, TLO, Depth+1)) 851 return true; 852 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 853 KnownZero = KnownZero.zext(BitWidth); 854 KnownOne = KnownOne.zext(BitWidth); 855 KnownZero |= NewBits; 856 break; 857 } 858 case ISD::SIGN_EXTEND: { 859 EVT InVT = Op.getOperand(0).getValueType(); 860 unsigned InBits = InVT.getScalarType().getSizeInBits(); 861 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 862 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 863 APInt NewBits = ~InMask & NewMask; 864 865 // If none of the top bits are demanded, convert this into an any_extend. 866 if (NewBits == 0) 867 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 868 Op.getValueType(), 869 Op.getOperand(0))); 870 871 // Since some of the sign extended bits are demanded, we know that the sign 872 // bit is demanded. 873 APInt InDemandedBits = InMask & NewMask; 874 InDemandedBits |= InSignBit; 875 InDemandedBits = InDemandedBits.trunc(InBits); 876 877 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 878 KnownOne, TLO, Depth+1)) 879 return true; 880 KnownZero = KnownZero.zext(BitWidth); 881 KnownOne = KnownOne.zext(BitWidth); 882 883 // If the sign bit is known zero, convert this to a zero extend. 884 if (KnownZero.intersects(InSignBit)) 885 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 886 Op.getValueType(), 887 Op.getOperand(0))); 888 889 // If the sign bit is known one, the top bits match. 890 if (KnownOne.intersects(InSignBit)) { 891 KnownOne |= NewBits; 892 assert((KnownZero & NewBits) == 0); 893 } else { // Otherwise, top bits aren't known. 894 assert((KnownOne & NewBits) == 0); 895 assert((KnownZero & NewBits) == 0); 896 } 897 break; 898 } 899 case ISD::ANY_EXTEND: { 900 unsigned OperandBitWidth = 901 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 902 APInt InMask = NewMask.trunc(OperandBitWidth); 903 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 904 KnownZero, KnownOne, TLO, Depth+1)) 905 return true; 906 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 907 KnownZero = KnownZero.zext(BitWidth); 908 KnownOne = KnownOne.zext(BitWidth); 909 break; 910 } 911 case ISD::TRUNCATE: { 912 // Simplify the input, using demanded bit information, and compute the known 913 // zero/one bits live out. 914 unsigned OperandBitWidth = 915 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 916 APInt TruncMask = NewMask.zext(OperandBitWidth); 917 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 918 KnownZero, KnownOne, TLO, Depth+1)) 919 return true; 920 KnownZero = KnownZero.trunc(BitWidth); 921 KnownOne = KnownOne.trunc(BitWidth); 922 923 // If the input is only used by this truncate, see if we can shrink it based 924 // on the known demanded bits. 925 if (Op.getOperand(0).getNode()->hasOneUse()) { 926 SDValue In = Op.getOperand(0); 927 switch (In.getOpcode()) { 928 default: break; 929 case ISD::SRL: 930 // Shrink SRL by a constant if none of the high bits shifted in are 931 // demanded. 932 if (TLO.LegalTypes() && 933 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 934 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 935 // undesirable. 936 break; 937 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 938 if (!ShAmt) 939 break; 940 SDValue Shift = In.getOperand(1); 941 if (TLO.LegalTypes()) { 942 uint64_t ShVal = ShAmt->getZExtValue(); 943 Shift = 944 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType())); 945 } 946 947 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 948 OperandBitWidth - BitWidth); 949 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); 950 951 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 952 // None of the shifted in bits are needed. Add a truncate of the 953 // shift input, then shift it. 954 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 955 Op.getValueType(), 956 In.getOperand(0)); 957 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 958 Op.getValueType(), 959 NewTrunc, 960 Shift)); 961 } 962 break; 963 } 964 } 965 966 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 967 break; 968 } 969 case ISD::AssertZext: { 970 // AssertZext demands all of the high bits, plus any of the low bits 971 // demanded by its users. 972 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 973 APInt InMask = APInt::getLowBitsSet(BitWidth, 974 VT.getSizeInBits()); 975 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, 976 KnownZero, KnownOne, TLO, Depth+1)) 977 return true; 978 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 979 980 KnownZero |= ~InMask & NewMask; 981 break; 982 } 983 case ISD::BITCAST: 984 // If this is an FP->Int bitcast and if the sign bit is the only 985 // thing demanded, turn this into a FGETSIGN. 986 if (!TLO.LegalOperations() && 987 !Op.getValueType().isVector() && 988 !Op.getOperand(0).getValueType().isVector() && 989 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && 990 Op.getOperand(0).getValueType().isFloatingPoint()) { 991 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); 992 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); 993 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) { 994 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; 995 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 996 // place. We expect the SHL to be eliminated by other optimizations. 997 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); 998 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); 999 if (!OpVTLegal && OpVTSizeInBits > 32) 1000 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); 1001 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1002 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); 1003 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1004 Op.getValueType(), 1005 Sign, ShAmt)); 1006 } 1007 } 1008 break; 1009 case ISD::ADD: 1010 case ISD::MUL: 1011 case ISD::SUB: { 1012 // Add, Sub, and Mul don't demand any bits in positions beyond that 1013 // of the highest bit demanded of them. 1014 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1015 BitWidth - NewMask.countLeadingZeros()); 1016 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1017 KnownOne2, TLO, Depth+1)) 1018 return true; 1019 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1020 KnownOne2, TLO, Depth+1)) 1021 return true; 1022 // See if the operation should be performed at a smaller bit width. 1023 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1024 return true; 1025 } 1026 // FALL THROUGH 1027 default: 1028 // Just use ComputeMaskedBits to compute output bits. 1029 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); 1030 break; 1031 } 1032 1033 // If we know the value of all of the demanded bits, return this as a 1034 // constant. 1035 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1036 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1037 1038 return false; 1039} 1040 1041/// computeMaskedBitsForTargetNode - Determine which of the bits specified 1042/// in Mask are known to be either zero or one and return them in the 1043/// KnownZero/KnownOne bitsets. 1044void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1045 APInt &KnownZero, 1046 APInt &KnownOne, 1047 const SelectionDAG &DAG, 1048 unsigned Depth) const { 1049 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1050 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1051 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1052 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1053 "Should use MaskedValueIsZero if you don't know whether Op" 1054 " is a target node!"); 1055 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); 1056} 1057 1058/// ComputeNumSignBitsForTargetNode - This method can be implemented by 1059/// targets that want to expose additional information about sign bits to the 1060/// DAG Combiner. 1061unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1062 unsigned Depth) const { 1063 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1064 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1065 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1066 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1067 "Should use ComputeNumSignBits if you don't know whether Op" 1068 " is a target node!"); 1069 return 1; 1070} 1071 1072/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1073/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1074/// determine which bit is set. 1075/// 1076static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1077 // A left-shift of a constant one will have exactly one bit set, because 1078 // shifting the bit off the end is undefined. 1079 if (Val.getOpcode() == ISD::SHL) 1080 if (ConstantSDNode *C = 1081 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1082 if (C->getAPIntValue() == 1) 1083 return true; 1084 1085 // Similarly, a right-shift of a constant sign-bit will have exactly 1086 // one bit set. 1087 if (Val.getOpcode() == ISD::SRL) 1088 if (ConstantSDNode *C = 1089 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1090 if (C->getAPIntValue().isSignBit()) 1091 return true; 1092 1093 // More could be done here, though the above checks are enough 1094 // to handle some common cases. 1095 1096 // Fall back to ComputeMaskedBits to catch other known cases. 1097 EVT OpVT = Val.getValueType(); 1098 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1099 APInt KnownZero, KnownOne; 1100 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); 1101 return (KnownZero.countPopulation() == BitWidth - 1) && 1102 (KnownOne.countPopulation() == 1); 1103} 1104 1105/// SimplifySetCC - Try to simplify a setcc built with the specified operands 1106/// and cc. If it is unable to simplify it, return a null SDValue. 1107SDValue 1108TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1109 ISD::CondCode Cond, bool foldBooleans, 1110 DAGCombinerInfo &DCI, SDLoc dl) const { 1111 SelectionDAG &DAG = DCI.DAG; 1112 1113 // These setcc operations always fold. 1114 switch (Cond) { 1115 default: break; 1116 case ISD::SETFALSE: 1117 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1118 case ISD::SETTRUE: 1119 case ISD::SETTRUE2: { 1120 TargetLowering::BooleanContent Cnt = getBooleanContents(VT.isVector()); 1121 return DAG.getConstant( 1122 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT); 1123 } 1124 } 1125 1126 // Ensure that the constant occurs on the RHS, and fold constant 1127 // comparisons. 1128 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond); 1129 if (isa<ConstantSDNode>(N0.getNode()) && 1130 (DCI.isBeforeLegalizeOps() || 1131 isCondCodeLegal(SwappedCC, N0.getSimpleValueType()))) 1132 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); 1133 1134 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1135 const APInt &C1 = N1C->getAPIntValue(); 1136 1137 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1138 // equality comparison, then we're just comparing whether X itself is 1139 // zero. 1140 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1141 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1142 N0.getOperand(1).getOpcode() == ISD::Constant) { 1143 const APInt &ShAmt 1144 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1145 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1146 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1147 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1148 // (srl (ctlz x), 5) == 0 -> X != 0 1149 // (srl (ctlz x), 5) != 1 -> X != 0 1150 Cond = ISD::SETNE; 1151 } else { 1152 // (srl (ctlz x), 5) != 0 -> X == 0 1153 // (srl (ctlz x), 5) == 1 -> X == 0 1154 Cond = ISD::SETEQ; 1155 } 1156 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1157 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1158 Zero, Cond); 1159 } 1160 } 1161 1162 SDValue CTPOP = N0; 1163 // Look through truncs that don't change the value of a ctpop. 1164 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) 1165 CTPOP = N0.getOperand(0); 1166 1167 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && 1168 (N0 == CTPOP || N0.getValueType().getSizeInBits() > 1169 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { 1170 EVT CTVT = CTPOP.getValueType(); 1171 SDValue CTOp = CTPOP.getOperand(0); 1172 1173 // (ctpop x) u< 2 -> (x & x-1) == 0 1174 // (ctpop x) u> 1 -> (x & x-1) != 0 1175 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1176 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 1177 DAG.getConstant(1, CTVT)); 1178 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); 1179 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1180 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC); 1181 } 1182 1183 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal. 1184 } 1185 1186 // (zext x) == C --> x == (trunc C) 1187 if (DCI.isBeforeLegalize() && N0->hasOneUse() && 1188 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1189 unsigned MinBits = N0.getValueSizeInBits(); 1190 SDValue PreZExt; 1191 if (N0->getOpcode() == ISD::ZERO_EXTEND) { 1192 // ZExt 1193 MinBits = N0->getOperand(0).getValueSizeInBits(); 1194 PreZExt = N0->getOperand(0); 1195 } else if (N0->getOpcode() == ISD::AND) { 1196 // DAGCombine turns costly ZExts into ANDs 1197 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) 1198 if ((C->getAPIntValue()+1).isPowerOf2()) { 1199 MinBits = C->getAPIntValue().countTrailingOnes(); 1200 PreZExt = N0->getOperand(0); 1201 } 1202 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) { 1203 // ZEXTLOAD 1204 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { 1205 MinBits = LN0->getMemoryVT().getSizeInBits(); 1206 PreZExt = N0; 1207 } 1208 } 1209 1210 // Make sure we're not losing bits from the constant. 1211 if (MinBits > 0 && 1212 MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) { 1213 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); 1214 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { 1215 // Will get folded away. 1216 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); 1217 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT); 1218 return DAG.getSetCC(dl, VT, Trunc, C, Cond); 1219 } 1220 } 1221 } 1222 1223 // If the LHS is '(and load, const)', the RHS is 0, 1224 // the test is for equality or unsigned, and all 1 bits of the const are 1225 // in the same partial word, see if we can shorten the load. 1226 if (DCI.isBeforeLegalize() && 1227 !ISD::isSignedIntSetCC(Cond) && 1228 N0.getOpcode() == ISD::AND && C1 == 0 && 1229 N0.getNode()->hasOneUse() && 1230 isa<LoadSDNode>(N0.getOperand(0)) && 1231 N0.getOperand(0).getNode()->hasOneUse() && 1232 isa<ConstantSDNode>(N0.getOperand(1))) { 1233 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1234 APInt bestMask; 1235 unsigned bestWidth = 0, bestOffset = 0; 1236 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1237 unsigned origWidth = N0.getValueType().getSizeInBits(); 1238 unsigned maskWidth = origWidth; 1239 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1240 // 8 bits, but have to be careful... 1241 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1242 origWidth = Lod->getMemoryVT().getSizeInBits(); 1243 const APInt &Mask = 1244 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1245 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1246 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1247 for (unsigned offset=0; offset<origWidth/width; offset++) { 1248 if ((newMask & Mask) == Mask) { 1249 if (!getDataLayout()->isLittleEndian()) 1250 bestOffset = (origWidth/width - offset - 1) * (width/8); 1251 else 1252 bestOffset = (uint64_t)offset * (width/8); 1253 bestMask = Mask.lshr(offset * (width/8) * 8); 1254 bestWidth = width; 1255 break; 1256 } 1257 newMask = newMask << width; 1258 } 1259 } 1260 } 1261 if (bestWidth) { 1262 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth); 1263 if (newVT.isRound()) { 1264 EVT PtrType = Lod->getOperand(1).getValueType(); 1265 SDValue Ptr = Lod->getBasePtr(); 1266 if (bestOffset != 0) 1267 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1268 DAG.getConstant(bestOffset, PtrType)); 1269 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1270 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1271 Lod->getPointerInfo().getWithOffset(bestOffset), 1272 false, false, false, NewAlign); 1273 return DAG.getSetCC(dl, VT, 1274 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1275 DAG.getConstant(bestMask.trunc(bestWidth), 1276 newVT)), 1277 DAG.getConstant(0LL, newVT), Cond); 1278 } 1279 } 1280 } 1281 1282 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1283 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1284 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1285 1286 // If the comparison constant has bits in the upper part, the 1287 // zero-extended value could never match. 1288 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1289 C1.getBitWidth() - InSize))) { 1290 switch (Cond) { 1291 case ISD::SETUGT: 1292 case ISD::SETUGE: 1293 case ISD::SETEQ: return DAG.getConstant(0, VT); 1294 case ISD::SETULT: 1295 case ISD::SETULE: 1296 case ISD::SETNE: return DAG.getConstant(1, VT); 1297 case ISD::SETGT: 1298 case ISD::SETGE: 1299 // True if the sign bit of C1 is set. 1300 return DAG.getConstant(C1.isNegative(), VT); 1301 case ISD::SETLT: 1302 case ISD::SETLE: 1303 // True if the sign bit of C1 isn't set. 1304 return DAG.getConstant(C1.isNonNegative(), VT); 1305 default: 1306 break; 1307 } 1308 } 1309 1310 // Otherwise, we can perform the comparison with the low bits. 1311 switch (Cond) { 1312 case ISD::SETEQ: 1313 case ISD::SETNE: 1314 case ISD::SETUGT: 1315 case ISD::SETUGE: 1316 case ISD::SETULT: 1317 case ISD::SETULE: { 1318 EVT newVT = N0.getOperand(0).getValueType(); 1319 if (DCI.isBeforeLegalizeOps() || 1320 (isOperationLegal(ISD::SETCC, newVT) && 1321 getCondCodeAction(Cond, newVT.getSimpleVT())==Legal)) 1322 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1323 DAG.getConstant(C1.trunc(InSize), newVT), 1324 Cond); 1325 break; 1326 } 1327 default: 1328 break; // todo, be more careful with signed comparisons 1329 } 1330 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1331 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1332 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1333 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1334 EVT ExtDstTy = N0.getValueType(); 1335 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1336 1337 // If the constant doesn't fit into the number of bits for the source of 1338 // the sign extension, it is impossible for both sides to be equal. 1339 if (C1.getMinSignedBits() > ExtSrcTyBits) 1340 return DAG.getConstant(Cond == ISD::SETNE, VT); 1341 1342 SDValue ZextOp; 1343 EVT Op0Ty = N0.getOperand(0).getValueType(); 1344 if (Op0Ty == ExtSrcTy) { 1345 ZextOp = N0.getOperand(0); 1346 } else { 1347 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1348 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1349 DAG.getConstant(Imm, Op0Ty)); 1350 } 1351 if (!DCI.isCalledByLegalizer()) 1352 DCI.AddToWorklist(ZextOp.getNode()); 1353 // Otherwise, make this a use of a zext. 1354 return DAG.getSetCC(dl, VT, ZextOp, 1355 DAG.getConstant(C1 & APInt::getLowBitsSet( 1356 ExtDstTyBits, 1357 ExtSrcTyBits), 1358 ExtDstTy), 1359 Cond); 1360 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1361 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1362 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1363 if (N0.getOpcode() == ISD::SETCC && 1364 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1365 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1366 if (TrueWhenTrue) 1367 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1368 // Invert the condition. 1369 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1370 CC = ISD::getSetCCInverse(CC, 1371 N0.getOperand(0).getValueType().isInteger()); 1372 if (DCI.isBeforeLegalizeOps() || 1373 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) 1374 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1375 } 1376 1377 if ((N0.getOpcode() == ISD::XOR || 1378 (N0.getOpcode() == ISD::AND && 1379 N0.getOperand(0).getOpcode() == ISD::XOR && 1380 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1381 isa<ConstantSDNode>(N0.getOperand(1)) && 1382 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1383 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1384 // can only do this if the top bits are known zero. 1385 unsigned BitWidth = N0.getValueSizeInBits(); 1386 if (DAG.MaskedValueIsZero(N0, 1387 APInt::getHighBitsSet(BitWidth, 1388 BitWidth-1))) { 1389 // Okay, get the un-inverted input value. 1390 SDValue Val; 1391 if (N0.getOpcode() == ISD::XOR) 1392 Val = N0.getOperand(0); 1393 else { 1394 assert(N0.getOpcode() == ISD::AND && 1395 N0.getOperand(0).getOpcode() == ISD::XOR); 1396 // ((X^1)&1)^1 -> X & 1 1397 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1398 N0.getOperand(0).getOperand(0), 1399 N0.getOperand(1)); 1400 } 1401 1402 return DAG.getSetCC(dl, VT, Val, N1, 1403 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1404 } 1405 } else if (N1C->getAPIntValue() == 1 && 1406 (VT == MVT::i1 || 1407 getBooleanContents(false) == ZeroOrOneBooleanContent)) { 1408 SDValue Op0 = N0; 1409 if (Op0.getOpcode() == ISD::TRUNCATE) 1410 Op0 = Op0.getOperand(0); 1411 1412 if ((Op0.getOpcode() == ISD::XOR) && 1413 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1414 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1415 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1416 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1417 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1418 Cond); 1419 } 1420 if (Op0.getOpcode() == ISD::AND && 1421 isa<ConstantSDNode>(Op0.getOperand(1)) && 1422 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1423 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1424 if (Op0.getValueType().bitsGT(VT)) 1425 Op0 = DAG.getNode(ISD::AND, dl, VT, 1426 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1427 DAG.getConstant(1, VT)); 1428 else if (Op0.getValueType().bitsLT(VT)) 1429 Op0 = DAG.getNode(ISD::AND, dl, VT, 1430 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1431 DAG.getConstant(1, VT)); 1432 1433 return DAG.getSetCC(dl, VT, Op0, 1434 DAG.getConstant(0, Op0.getValueType()), 1435 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1436 } 1437 if (Op0.getOpcode() == ISD::AssertZext && 1438 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) 1439 return DAG.getSetCC(dl, VT, Op0, 1440 DAG.getConstant(0, Op0.getValueType()), 1441 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1442 } 1443 } 1444 1445 APInt MinVal, MaxVal; 1446 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1447 if (ISD::isSignedIntSetCC(Cond)) { 1448 MinVal = APInt::getSignedMinValue(OperandBitSize); 1449 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1450 } else { 1451 MinVal = APInt::getMinValue(OperandBitSize); 1452 MaxVal = APInt::getMaxValue(OperandBitSize); 1453 } 1454 1455 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1456 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1457 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1458 // X >= C0 --> X > (C0-1) 1459 return DAG.getSetCC(dl, VT, N0, 1460 DAG.getConstant(C1-1, N1.getValueType()), 1461 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1462 } 1463 1464 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1465 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1466 // X <= C0 --> X < (C0+1) 1467 return DAG.getSetCC(dl, VT, N0, 1468 DAG.getConstant(C1+1, N1.getValueType()), 1469 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1470 } 1471 1472 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1473 return DAG.getConstant(0, VT); // X < MIN --> false 1474 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 1475 return DAG.getConstant(1, VT); // X >= MIN --> true 1476 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 1477 return DAG.getConstant(0, VT); // X > MAX --> false 1478 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 1479 return DAG.getConstant(1, VT); // X <= MAX --> true 1480 1481 // Canonicalize setgt X, Min --> setne X, Min 1482 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1483 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1484 // Canonicalize setlt X, Max --> setne X, Max 1485 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1486 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 1487 1488 // If we have setult X, 1, turn it into seteq X, 0 1489 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1490 return DAG.getSetCC(dl, VT, N0, 1491 DAG.getConstant(MinVal, N0.getValueType()), 1492 ISD::SETEQ); 1493 // If we have setugt X, Max-1, turn it into seteq X, Max 1494 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1495 return DAG.getSetCC(dl, VT, N0, 1496 DAG.getConstant(MaxVal, N0.getValueType()), 1497 ISD::SETEQ); 1498 1499 // If we have "setcc X, C0", check to see if we can shrink the immediate 1500 // by changing cc. 1501 1502 // SETUGT X, SINTMAX -> SETLT X, 0 1503 if (Cond == ISD::SETUGT && 1504 C1 == APInt::getSignedMaxValue(OperandBitSize)) 1505 return DAG.getSetCC(dl, VT, N0, 1506 DAG.getConstant(0, N1.getValueType()), 1507 ISD::SETLT); 1508 1509 // SETULT X, SINTMIN -> SETGT X, -1 1510 if (Cond == ISD::SETULT && 1511 C1 == APInt::getSignedMinValue(OperandBitSize)) { 1512 SDValue ConstMinusOne = 1513 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 1514 N1.getValueType()); 1515 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 1516 } 1517 1518 // Fold bit comparisons when we can. 1519 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1520 (VT == N0.getValueType() || 1521 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 1522 N0.getOpcode() == ISD::AND) 1523 if (ConstantSDNode *AndRHS = 1524 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1525 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1526 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1527 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1528 // Perform the xform if the AND RHS is a single bit. 1529 if (AndRHS->getAPIntValue().isPowerOf2()) { 1530 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1531 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1532 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 1533 } 1534 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 1535 // (X & 8) == 8 --> (X & 8) >> 3 1536 // Perform the xform if C1 is a single bit. 1537 if (C1.isPowerOf2()) { 1538 return DAG.getNode(ISD::TRUNCATE, dl, VT, 1539 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 1540 DAG.getConstant(C1.logBase2(), ShiftTy))); 1541 } 1542 } 1543 } 1544 1545 if (C1.getMinSignedBits() <= 64 && 1546 !isLegalICmpImmediate(C1.getSExtValue())) { 1547 // (X & -256) == 256 -> (X >> 8) == 1 1548 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1549 N0.getOpcode() == ISD::AND && N0.hasOneUse()) { 1550 if (ConstantSDNode *AndRHS = 1551 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1552 const APInt &AndRHSC = AndRHS->getAPIntValue(); 1553 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { 1554 unsigned ShiftBits = AndRHSC.countTrailingZeros(); 1555 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1556 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1557 EVT CmpTy = N0.getValueType(); 1558 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), 1559 DAG.getConstant(ShiftBits, ShiftTy)); 1560 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); 1561 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); 1562 } 1563 } 1564 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || 1565 Cond == ISD::SETULE || Cond == ISD::SETUGT) { 1566 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); 1567 // X < 0x100000000 -> (X >> 32) < 1 1568 // X >= 0x100000000 -> (X >> 32) >= 1 1569 // X <= 0x0ffffffff -> (X >> 32) < 1 1570 // X > 0x0ffffffff -> (X >> 32) >= 1 1571 unsigned ShiftBits; 1572 APInt NewC = C1; 1573 ISD::CondCode NewCond = Cond; 1574 if (AdjOne) { 1575 ShiftBits = C1.countTrailingOnes(); 1576 NewC = NewC + 1; 1577 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1578 } else { 1579 ShiftBits = C1.countTrailingZeros(); 1580 } 1581 NewC = NewC.lshr(ShiftBits); 1582 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { 1583 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? 1584 getPointerTy() : getShiftAmountTy(N0.getValueType()); 1585 EVT CmpTy = N0.getValueType(); 1586 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0, 1587 DAG.getConstant(ShiftBits, ShiftTy)); 1588 SDValue CmpRHS = DAG.getConstant(NewC, CmpTy); 1589 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond); 1590 } 1591 } 1592 } 1593 } 1594 1595 if (isa<ConstantFPSDNode>(N0.getNode())) { 1596 // Constant fold or commute setcc. 1597 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 1598 if (O.getNode()) return O; 1599 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 1600 // If the RHS of an FP comparison is a constant, simplify it away in 1601 // some cases. 1602 if (CFP->getValueAPF().isNaN()) { 1603 // If an operand is known to be a nan, we can fold it. 1604 switch (ISD::getUnorderedFlavor(Cond)) { 1605 default: llvm_unreachable("Unknown flavor!"); 1606 case 0: // Known false. 1607 return DAG.getConstant(0, VT); 1608 case 1: // Known true. 1609 return DAG.getConstant(1, VT); 1610 case 2: // Undefined. 1611 return DAG.getUNDEF(VT); 1612 } 1613 } 1614 1615 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 1616 // constant if knowing that the operand is non-nan is enough. We prefer to 1617 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 1618 // materialize 0.0. 1619 if (Cond == ISD::SETO || Cond == ISD::SETUO) 1620 return DAG.getSetCC(dl, VT, N0, N0, Cond); 1621 1622 // If the condition is not legal, see if we can find an equivalent one 1623 // which is legal. 1624 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1625 // If the comparison was an awkward floating-point == or != and one of 1626 // the comparison operands is infinity or negative infinity, convert the 1627 // condition to a less-awkward <= or >=. 1628 if (CFP->getValueAPF().isInfinity()) { 1629 if (CFP->getValueAPF().isNegative()) { 1630 if (Cond == ISD::SETOEQ && 1631 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1632 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 1633 if (Cond == ISD::SETUEQ && 1634 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) 1635 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 1636 if (Cond == ISD::SETUNE && 1637 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1638 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 1639 if (Cond == ISD::SETONE && 1640 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType())) 1641 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 1642 } else { 1643 if (Cond == ISD::SETOEQ && 1644 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1645 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 1646 if (Cond == ISD::SETUEQ && 1647 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) 1648 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 1649 if (Cond == ISD::SETUNE && 1650 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1651 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 1652 if (Cond == ISD::SETONE && 1653 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType())) 1654 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 1655 } 1656 } 1657 } 1658 } 1659 1660 if (N0 == N1) { 1661 // The sext(setcc()) => setcc() optimization relies on the appropriate 1662 // constant being emitted. 1663 uint64_t EqVal = 0; 1664 switch (getBooleanContents(N0.getValueType().isVector())) { 1665 case UndefinedBooleanContent: 1666 case ZeroOrOneBooleanContent: 1667 EqVal = ISD::isTrueWhenEqual(Cond); 1668 break; 1669 case ZeroOrNegativeOneBooleanContent: 1670 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0; 1671 break; 1672 } 1673 1674 // We can always fold X == X for integer setcc's. 1675 if (N0.getValueType().isInteger()) { 1676 return DAG.getConstant(EqVal, VT); 1677 } 1678 unsigned UOF = ISD::getUnorderedFlavor(Cond); 1679 if (UOF == 2) // FP operators that are undefined on NaNs. 1680 return DAG.getConstant(EqVal, VT); 1681 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 1682 return DAG.getConstant(EqVal, VT); 1683 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 1684 // if it is not already. 1685 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 1686 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || 1687 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) 1688 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 1689 } 1690 1691 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1692 N0.getValueType().isInteger()) { 1693 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1694 N0.getOpcode() == ISD::XOR) { 1695 // Simplify (X+Y) == (X+Z) --> Y == Z 1696 if (N0.getOpcode() == N1.getOpcode()) { 1697 if (N0.getOperand(0) == N1.getOperand(0)) 1698 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 1699 if (N0.getOperand(1) == N1.getOperand(1)) 1700 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 1701 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 1702 // If X op Y == Y op X, try other combinations. 1703 if (N0.getOperand(0) == N1.getOperand(1)) 1704 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 1705 Cond); 1706 if (N0.getOperand(1) == N1.getOperand(0)) 1707 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 1708 Cond); 1709 } 1710 } 1711 1712 // If RHS is a legal immediate value for a compare instruction, we need 1713 // to be careful about increasing register pressure needlessly. 1714 bool LegalRHSImm = false; 1715 1716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 1717 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1718 // Turn (X+C1) == C2 --> X == C2-C1 1719 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1720 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1721 DAG.getConstant(RHSC->getAPIntValue()- 1722 LHSR->getAPIntValue(), 1723 N0.getValueType()), Cond); 1724 } 1725 1726 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 1727 if (N0.getOpcode() == ISD::XOR) 1728 // If we know that all of the inverted bits are zero, don't bother 1729 // performing the inversion. 1730 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 1731 return 1732 DAG.getSetCC(dl, VT, N0.getOperand(0), 1733 DAG.getConstant(LHSR->getAPIntValue() ^ 1734 RHSC->getAPIntValue(), 1735 N0.getValueType()), 1736 Cond); 1737 } 1738 1739 // Turn (C1-X) == C2 --> X == C1-C2 1740 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 1741 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 1742 return 1743 DAG.getSetCC(dl, VT, N0.getOperand(1), 1744 DAG.getConstant(SUBC->getAPIntValue() - 1745 RHSC->getAPIntValue(), 1746 N0.getValueType()), 1747 Cond); 1748 } 1749 } 1750 1751 // Could RHSC fold directly into a compare? 1752 if (RHSC->getValueType(0).getSizeInBits() <= 64) 1753 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue()); 1754 } 1755 1756 // Simplify (X+Z) == X --> Z == 0 1757 // Don't do this if X is an immediate that can fold into a cmp 1758 // instruction and X+Z has other uses. It could be an induction variable 1759 // chain, and the transform would increase register pressure. 1760 if (!LegalRHSImm || N0.getNode()->hasOneUse()) { 1761 if (N0.getOperand(0) == N1) 1762 return DAG.getSetCC(dl, VT, N0.getOperand(1), 1763 DAG.getConstant(0, N0.getValueType()), Cond); 1764 if (N0.getOperand(1) == N1) { 1765 if (DAG.isCommutativeBinOp(N0.getOpcode())) 1766 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1767 DAG.getConstant(0, N0.getValueType()), Cond); 1768 if (N0.getNode()->hasOneUse()) { 1769 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 1770 // (Z-X) == X --> Z == X<<1 1771 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1, 1772 DAG.getConstant(1, getShiftAmountTy(N1.getValueType()))); 1773 if (!DCI.isCalledByLegalizer()) 1774 DCI.AddToWorklist(SH.getNode()); 1775 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 1776 } 1777 } 1778 } 1779 } 1780 1781 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1782 N1.getOpcode() == ISD::XOR) { 1783 // Simplify X == (X+Z) --> Z == 0 1784 if (N1.getOperand(0) == N0) 1785 return DAG.getSetCC(dl, VT, N1.getOperand(1), 1786 DAG.getConstant(0, N1.getValueType()), Cond); 1787 if (N1.getOperand(1) == N0) { 1788 if (DAG.isCommutativeBinOp(N1.getOpcode())) 1789 return DAG.getSetCC(dl, VT, N1.getOperand(0), 1790 DAG.getConstant(0, N1.getValueType()), Cond); 1791 if (N1.getNode()->hasOneUse()) { 1792 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 1793 // X == (Z-X) --> X<<1 == Z 1794 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 1795 DAG.getConstant(1, getShiftAmountTy(N0.getValueType()))); 1796 if (!DCI.isCalledByLegalizer()) 1797 DCI.AddToWorklist(SH.getNode()); 1798 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 1799 } 1800 } 1801 } 1802 1803 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 1804 // Note that where y is variable and is known to have at most 1805 // one bit set (for example, if it is z&1) we cannot do this; 1806 // the expressions are not equivalent when y==0. 1807 if (N0.getOpcode() == ISD::AND) 1808 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 1809 if (ValueHasExactlyOneBitSet(N1, DAG)) { 1810 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1811 if (DCI.isBeforeLegalizeOps() || 1812 isCondCodeLegal(Cond, N0.getSimpleValueType())) { 1813 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 1814 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 1815 } 1816 } 1817 } 1818 if (N1.getOpcode() == ISD::AND) 1819 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 1820 if (ValueHasExactlyOneBitSet(N0, DAG)) { 1821 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 1822 if (DCI.isBeforeLegalizeOps() || 1823 isCondCodeLegal(Cond, N1.getSimpleValueType())) { 1824 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1825 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 1826 } 1827 } 1828 } 1829 } 1830 1831 // Fold away ALL boolean setcc's. 1832 SDValue Temp; 1833 if (N0.getValueType() == MVT::i1 && foldBooleans) { 1834 switch (Cond) { 1835 default: llvm_unreachable("Unknown integer setcc!"); 1836 case ISD::SETEQ: // X == Y -> ~(X^Y) 1837 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1838 N0 = DAG.getNOT(dl, Temp, MVT::i1); 1839 if (!DCI.isCalledByLegalizer()) 1840 DCI.AddToWorklist(Temp.getNode()); 1841 break; 1842 case ISD::SETNE: // X != Y --> (X^Y) 1843 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 1844 break; 1845 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 1846 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 1847 Temp = DAG.getNOT(dl, N0, MVT::i1); 1848 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 1849 if (!DCI.isCalledByLegalizer()) 1850 DCI.AddToWorklist(Temp.getNode()); 1851 break; 1852 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 1853 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 1854 Temp = DAG.getNOT(dl, N1, MVT::i1); 1855 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 1856 if (!DCI.isCalledByLegalizer()) 1857 DCI.AddToWorklist(Temp.getNode()); 1858 break; 1859 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 1860 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 1861 Temp = DAG.getNOT(dl, N0, MVT::i1); 1862 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 1863 if (!DCI.isCalledByLegalizer()) 1864 DCI.AddToWorklist(Temp.getNode()); 1865 break; 1866 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 1867 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 1868 Temp = DAG.getNOT(dl, N1, MVT::i1); 1869 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 1870 break; 1871 } 1872 if (VT != MVT::i1) { 1873 if (!DCI.isCalledByLegalizer()) 1874 DCI.AddToWorklist(N0.getNode()); 1875 // FIXME: If running after legalize, we probably can't do this. 1876 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 1877 } 1878 return N0; 1879 } 1880 1881 // Could not fold it. 1882 return SDValue(); 1883} 1884 1885/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 1886/// node is a GlobalAddress + offset. 1887bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA, 1888 int64_t &Offset) const { 1889 if (isa<GlobalAddressSDNode>(N)) { 1890 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 1891 GA = GASD->getGlobal(); 1892 Offset += GASD->getOffset(); 1893 return true; 1894 } 1895 1896 if (N->getOpcode() == ISD::ADD) { 1897 SDValue N1 = N->getOperand(0); 1898 SDValue N2 = N->getOperand(1); 1899 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 1900 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 1901 if (V) { 1902 Offset += V->getSExtValue(); 1903 return true; 1904 } 1905 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 1906 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 1907 if (V) { 1908 Offset += V->getSExtValue(); 1909 return true; 1910 } 1911 } 1912 } 1913 1914 return false; 1915} 1916 1917 1918SDValue TargetLowering:: 1919PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1920 // Default implementation: no optimization. 1921 return SDValue(); 1922} 1923 1924//===----------------------------------------------------------------------===// 1925// Inline Assembler Implementation Methods 1926//===----------------------------------------------------------------------===// 1927 1928 1929TargetLowering::ConstraintType 1930TargetLowering::getConstraintType(const std::string &Constraint) const { 1931 unsigned S = Constraint.size(); 1932 1933 if (S == 1) { 1934 switch (Constraint[0]) { 1935 default: break; 1936 case 'r': return C_RegisterClass; 1937 case 'm': // memory 1938 case 'o': // offsetable 1939 case 'V': // not offsetable 1940 return C_Memory; 1941 case 'i': // Simple Integer or Relocatable Constant 1942 case 'n': // Simple Integer 1943 case 'E': // Floating Point Constant 1944 case 'F': // Floating Point Constant 1945 case 's': // Relocatable Constant 1946 case 'p': // Address. 1947 case 'X': // Allow ANY value. 1948 case 'I': // Target registers. 1949 case 'J': 1950 case 'K': 1951 case 'L': 1952 case 'M': 1953 case 'N': 1954 case 'O': 1955 case 'P': 1956 case '<': 1957 case '>': 1958 return C_Other; 1959 } 1960 } 1961 1962 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { 1963 if (S == 8 && !Constraint.compare(1, 6, "memory", 6)) // "{memory}" 1964 return C_Memory; 1965 return C_Register; 1966 } 1967 return C_Unknown; 1968} 1969 1970/// LowerXConstraint - try to replace an X constraint, which matches anything, 1971/// with another that has more specific requirements based on the type of the 1972/// corresponding operand. 1973const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 1974 if (ConstraintVT.isInteger()) 1975 return "r"; 1976 if (ConstraintVT.isFloatingPoint()) 1977 return "f"; // works for many targets 1978 return 0; 1979} 1980 1981/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1982/// vector. If it is invalid, don't add anything to Ops. 1983void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 1984 std::string &Constraint, 1985 std::vector<SDValue> &Ops, 1986 SelectionDAG &DAG) const { 1987 1988 if (Constraint.length() > 1) return; 1989 1990 char ConstraintLetter = Constraint[0]; 1991 switch (ConstraintLetter) { 1992 default: break; 1993 case 'X': // Allows any operand; labels (basic block) use this. 1994 if (Op.getOpcode() == ISD::BasicBlock) { 1995 Ops.push_back(Op); 1996 return; 1997 } 1998 // fall through 1999 case 'i': // Simple Integer or Relocatable Constant 2000 case 'n': // Simple Integer 2001 case 's': { // Relocatable Constant 2002 // These operands are interested in values of the form (GV+C), where C may 2003 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2004 // is possible and fine if either GV or C are missing. 2005 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2006 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2007 2008 // If we have "(add GV, C)", pull out GV/C 2009 if (Op.getOpcode() == ISD::ADD) { 2010 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2011 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2012 if (C == 0 || GA == 0) { 2013 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2014 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2015 } 2016 if (C == 0 || GA == 0) 2017 C = 0, GA = 0; 2018 } 2019 2020 // If we find a valid operand, map to the TargetXXX version so that the 2021 // value itself doesn't get selected. 2022 if (GA) { // Either &GV or &GV+C 2023 if (ConstraintLetter != 'n') { 2024 int64_t Offs = GA->getOffset(); 2025 if (C) Offs += C->getZExtValue(); 2026 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2027 C ? SDLoc(C) : SDLoc(), 2028 Op.getValueType(), Offs)); 2029 return; 2030 } 2031 } 2032 if (C) { // just C, no GV. 2033 // Simple constants are not allowed for 's'. 2034 if (ConstraintLetter != 's') { 2035 // gcc prints these as sign extended. Sign extend value to 64 bits 2036 // now; without this it would get ZExt'd later in 2037 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2038 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2039 MVT::i64)); 2040 return; 2041 } 2042 } 2043 break; 2044 } 2045 } 2046} 2047 2048std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2049getRegForInlineAsmConstraint(const std::string &Constraint, 2050 MVT VT) const { 2051 if (Constraint.empty() || Constraint[0] != '{') 2052 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2053 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2054 2055 // Remove the braces from around the name. 2056 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2057 2058 std::pair<unsigned, const TargetRegisterClass*> R = 2059 std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2060 2061 // Figure out which register class contains this reg. 2062 const TargetRegisterInfo *RI = getTargetMachine().getRegisterInfo(); 2063 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2064 E = RI->regclass_end(); RCI != E; ++RCI) { 2065 const TargetRegisterClass *RC = *RCI; 2066 2067 // If none of the value types for this register class are valid, we 2068 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2069 if (!isLegalRC(RC)) 2070 continue; 2071 2072 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2073 I != E; ++I) { 2074 if (RegName.equals_lower(RI->getName(*I))) { 2075 std::pair<unsigned, const TargetRegisterClass*> S = 2076 std::make_pair(*I, RC); 2077 2078 // If this register class has the requested value type, return it, 2079 // otherwise keep searching and return the first class found 2080 // if no other is found which explicitly has the requested type. 2081 if (RC->hasType(VT)) 2082 return S; 2083 else if (!R.second) 2084 R = S; 2085 } 2086 } 2087 } 2088 2089 return R; 2090} 2091 2092//===----------------------------------------------------------------------===// 2093// Constraint Selection. 2094 2095/// isMatchingInputConstraint - Return true of this is an input operand that is 2096/// a matching constraint like "4". 2097bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2098 assert(!ConstraintCode.empty() && "No known constraint!"); 2099 return isdigit(static_cast<unsigned char>(ConstraintCode[0])); 2100} 2101 2102/// getMatchedOperand - If this is an input matching constraint, this method 2103/// returns the output operand it matches. 2104unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2105 assert(!ConstraintCode.empty() && "No known constraint!"); 2106 return atoi(ConstraintCode.c_str()); 2107} 2108 2109 2110/// ParseConstraints - Split up the constraint string from the inline 2111/// assembly value into the specific constraints and their prefixes, 2112/// and also tie in the associated operand values. 2113/// If this returns an empty vector, and if the constraint string itself 2114/// isn't empty, there was an error parsing. 2115TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints( 2116 ImmutableCallSite CS) const { 2117 /// ConstraintOperands - Information about all of the constraints. 2118 AsmOperandInfoVector ConstraintOperands; 2119 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 2120 unsigned maCount = 0; // Largest number of multiple alternative constraints. 2121 2122 // Do a prepass over the constraints, canonicalizing them, and building up the 2123 // ConstraintOperands list. 2124 InlineAsm::ConstraintInfoVector 2125 ConstraintInfos = IA->ParseConstraints(); 2126 2127 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 2128 unsigned ResNo = 0; // ResNo - The result number of the next output. 2129 2130 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { 2131 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i])); 2132 AsmOperandInfo &OpInfo = ConstraintOperands.back(); 2133 2134 // Update multiple alternative constraint count. 2135 if (OpInfo.multipleAlternatives.size() > maCount) 2136 maCount = OpInfo.multipleAlternatives.size(); 2137 2138 OpInfo.ConstraintVT = MVT::Other; 2139 2140 // Compute the value type for each operand. 2141 switch (OpInfo.Type) { 2142 case InlineAsm::isOutput: 2143 // Indirect outputs just consume an argument. 2144 if (OpInfo.isIndirect) { 2145 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2146 break; 2147 } 2148 2149 // The return value of the call is this value. As such, there is no 2150 // corresponding argument. 2151 assert(!CS.getType()->isVoidTy() && 2152 "Bad inline asm!"); 2153 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 2154 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo)); 2155 } else { 2156 assert(ResNo == 0 && "Asm only has one result!"); 2157 OpInfo.ConstraintVT = getSimpleValueType(CS.getType()); 2158 } 2159 ++ResNo; 2160 break; 2161 case InlineAsm::isInput: 2162 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 2163 break; 2164 case InlineAsm::isClobber: 2165 // Nothing to do. 2166 break; 2167 } 2168 2169 if (OpInfo.CallOperandVal) { 2170 llvm::Type *OpTy = OpInfo.CallOperandVal->getType(); 2171 if (OpInfo.isIndirect) { 2172 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 2173 if (!PtrTy) 2174 report_fatal_error("Indirect operand for inline asm not a pointer!"); 2175 OpTy = PtrTy->getElementType(); 2176 } 2177 2178 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 2179 if (StructType *STy = dyn_cast<StructType>(OpTy)) 2180 if (STy->getNumElements() == 1) 2181 OpTy = STy->getElementType(0); 2182 2183 // If OpTy is not a single value, it may be a struct/union that we 2184 // can tile with integers. 2185 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 2186 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy); 2187 switch (BitSize) { 2188 default: break; 2189 case 1: 2190 case 8: 2191 case 16: 2192 case 32: 2193 case 64: 2194 case 128: 2195 OpInfo.ConstraintVT = 2196 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); 2197 break; 2198 } 2199 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) { 2200 unsigned PtrSize 2201 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace()); 2202 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize); 2203 } else { 2204 OpInfo.ConstraintVT = MVT::getVT(OpTy, true); 2205 } 2206 } 2207 } 2208 2209 // If we have multiple alternative constraints, select the best alternative. 2210 if (ConstraintInfos.size()) { 2211 if (maCount) { 2212 unsigned bestMAIndex = 0; 2213 int bestWeight = -1; 2214 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match. 2215 int weight = -1; 2216 unsigned maIndex; 2217 // Compute the sums of the weights for each alternative, keeping track 2218 // of the best (highest weight) one so far. 2219 for (maIndex = 0; maIndex < maCount; ++maIndex) { 2220 int weightSum = 0; 2221 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2222 cIndex != eIndex; ++cIndex) { 2223 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2224 if (OpInfo.Type == InlineAsm::isClobber) 2225 continue; 2226 2227 // If this is an output operand with a matching input operand, 2228 // look up the matching input. If their types mismatch, e.g. one 2229 // is an integer, the other is floating point, or their sizes are 2230 // different, flag it as an maCantMatch. 2231 if (OpInfo.hasMatchingInput()) { 2232 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2233 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2234 if ((OpInfo.ConstraintVT.isInteger() != 2235 Input.ConstraintVT.isInteger()) || 2236 (OpInfo.ConstraintVT.getSizeInBits() != 2237 Input.ConstraintVT.getSizeInBits())) { 2238 weightSum = -1; // Can't match. 2239 break; 2240 } 2241 } 2242 } 2243 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex); 2244 if (weight == -1) { 2245 weightSum = -1; 2246 break; 2247 } 2248 weightSum += weight; 2249 } 2250 // Update best. 2251 if (weightSum > bestWeight) { 2252 bestWeight = weightSum; 2253 bestMAIndex = maIndex; 2254 } 2255 } 2256 2257 // Now select chosen alternative in each constraint. 2258 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2259 cIndex != eIndex; ++cIndex) { 2260 AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; 2261 if (cInfo.Type == InlineAsm::isClobber) 2262 continue; 2263 cInfo.selectAlternative(bestMAIndex); 2264 } 2265 } 2266 } 2267 2268 // Check and hook up tied operands, choose constraint code to use. 2269 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); 2270 cIndex != eIndex; ++cIndex) { 2271 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; 2272 2273 // If this is an output operand with a matching input operand, look up the 2274 // matching input. If their types mismatch, e.g. one is an integer, the 2275 // other is floating point, or their sizes are different, flag it as an 2276 // error. 2277 if (OpInfo.hasMatchingInput()) { 2278 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 2279 2280 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 2281 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 2282 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 2283 OpInfo.ConstraintVT); 2284 std::pair<unsigned, const TargetRegisterClass*> InputRC = 2285 getRegForInlineAsmConstraint(Input.ConstraintCode, 2286 Input.ConstraintVT); 2287 if ((OpInfo.ConstraintVT.isInteger() != 2288 Input.ConstraintVT.isInteger()) || 2289 (MatchRC.second != InputRC.second)) { 2290 report_fatal_error("Unsupported asm: input constraint" 2291 " with a matching output constraint of" 2292 " incompatible type!"); 2293 } 2294 } 2295 2296 } 2297 } 2298 2299 return ConstraintOperands; 2300} 2301 2302 2303/// getConstraintGenerality - Return an integer indicating how general CT 2304/// is. 2305static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2306 switch (CT) { 2307 case TargetLowering::C_Other: 2308 case TargetLowering::C_Unknown: 2309 return 0; 2310 case TargetLowering::C_Register: 2311 return 1; 2312 case TargetLowering::C_RegisterClass: 2313 return 2; 2314 case TargetLowering::C_Memory: 2315 return 3; 2316 } 2317 llvm_unreachable("Invalid constraint type"); 2318} 2319 2320/// Examine constraint type and operand type and determine a weight value. 2321/// This object must already have been set up with the operand type 2322/// and the current alternative constraint selected. 2323TargetLowering::ConstraintWeight 2324 TargetLowering::getMultipleConstraintMatchWeight( 2325 AsmOperandInfo &info, int maIndex) const { 2326 InlineAsm::ConstraintCodeVector *rCodes; 2327 if (maIndex >= (int)info.multipleAlternatives.size()) 2328 rCodes = &info.Codes; 2329 else 2330 rCodes = &info.multipleAlternatives[maIndex].Codes; 2331 ConstraintWeight BestWeight = CW_Invalid; 2332 2333 // Loop over the options, keeping track of the most general one. 2334 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { 2335 ConstraintWeight weight = 2336 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); 2337 if (weight > BestWeight) 2338 BestWeight = weight; 2339 } 2340 2341 return BestWeight; 2342} 2343 2344/// Examine constraint type and operand type and determine a weight value. 2345/// This object must already have been set up with the operand type 2346/// and the current alternative constraint selected. 2347TargetLowering::ConstraintWeight 2348 TargetLowering::getSingleConstraintMatchWeight( 2349 AsmOperandInfo &info, const char *constraint) const { 2350 ConstraintWeight weight = CW_Invalid; 2351 Value *CallOperandVal = info.CallOperandVal; 2352 // If we don't have a value, we can't do a match, 2353 // but allow it at the lowest weight. 2354 if (CallOperandVal == NULL) 2355 return CW_Default; 2356 // Look at the constraint type. 2357 switch (*constraint) { 2358 case 'i': // immediate integer. 2359 case 'n': // immediate integer with a known value. 2360 if (isa<ConstantInt>(CallOperandVal)) 2361 weight = CW_Constant; 2362 break; 2363 case 's': // non-explicit intregal immediate. 2364 if (isa<GlobalValue>(CallOperandVal)) 2365 weight = CW_Constant; 2366 break; 2367 case 'E': // immediate float if host format. 2368 case 'F': // immediate float. 2369 if (isa<ConstantFP>(CallOperandVal)) 2370 weight = CW_Constant; 2371 break; 2372 case '<': // memory operand with autodecrement. 2373 case '>': // memory operand with autoincrement. 2374 case 'm': // memory operand. 2375 case 'o': // offsettable memory operand 2376 case 'V': // non-offsettable memory operand 2377 weight = CW_Memory; 2378 break; 2379 case 'r': // general register. 2380 case 'g': // general register, memory operand or immediate integer. 2381 // note: Clang converts "g" to "imr". 2382 if (CallOperandVal->getType()->isIntegerTy()) 2383 weight = CW_Register; 2384 break; 2385 case 'X': // any operand. 2386 default: 2387 weight = CW_Default; 2388 break; 2389 } 2390 return weight; 2391} 2392 2393/// ChooseConstraint - If there are multiple different constraints that we 2394/// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2395/// This is somewhat tricky: constraints fall into four classes: 2396/// Other -> immediates and magic values 2397/// Register -> one specific register 2398/// RegisterClass -> a group of regs 2399/// Memory -> memory 2400/// Ideally, we would pick the most specific constraint possible: if we have 2401/// something that fits into a register, we would pick it. The problem here 2402/// is that if we have something that could either be in a register or in 2403/// memory that use of the register could cause selection of *other* 2404/// operands to fail: they might only succeed if we pick memory. Because of 2405/// this the heuristic we use is: 2406/// 2407/// 1) If there is an 'other' constraint, and if the operand is valid for 2408/// that constraint, use it. This makes us take advantage of 'i' 2409/// constraints when available. 2410/// 2) Otherwise, pick the most general constraint present. This prefers 2411/// 'm' over 'r', for example. 2412/// 2413static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2414 const TargetLowering &TLI, 2415 SDValue Op, SelectionDAG *DAG) { 2416 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2417 unsigned BestIdx = 0; 2418 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2419 int BestGenerality = -1; 2420 2421 // Loop over the options, keeping track of the most general one. 2422 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2423 TargetLowering::ConstraintType CType = 2424 TLI.getConstraintType(OpInfo.Codes[i]); 2425 2426 // If this is an 'other' constraint, see if the operand is valid for it. 2427 // For example, on X86 we might have an 'rI' constraint. If the operand 2428 // is an integer in the range [0..31] we want to use I (saving a load 2429 // of a register), otherwise we must use 'r'. 2430 if (CType == TargetLowering::C_Other && Op.getNode()) { 2431 assert(OpInfo.Codes[i].size() == 1 && 2432 "Unhandled multi-letter 'other' constraint"); 2433 std::vector<SDValue> ResultOps; 2434 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], 2435 ResultOps, *DAG); 2436 if (!ResultOps.empty()) { 2437 BestType = CType; 2438 BestIdx = i; 2439 break; 2440 } 2441 } 2442 2443 // Things with matching constraints can only be registers, per gcc 2444 // documentation. This mainly affects "g" constraints. 2445 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2446 continue; 2447 2448 // This constraint letter is more general than the previous one, use it. 2449 int Generality = getConstraintGenerality(CType); 2450 if (Generality > BestGenerality) { 2451 BestType = CType; 2452 BestIdx = i; 2453 BestGenerality = Generality; 2454 } 2455 } 2456 2457 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2458 OpInfo.ConstraintType = BestType; 2459} 2460 2461/// ComputeConstraintToUse - Determines the constraint code and constraint 2462/// type to use for the specific AsmOperandInfo, setting 2463/// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2464void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2465 SDValue Op, 2466 SelectionDAG *DAG) const { 2467 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2468 2469 // Single-letter constraints ('r') are very common. 2470 if (OpInfo.Codes.size() == 1) { 2471 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2472 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2473 } else { 2474 ChooseConstraint(OpInfo, *this, Op, DAG); 2475 } 2476 2477 // 'X' matches anything. 2478 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2479 // Labels and constants are handled elsewhere ('X' is the only thing 2480 // that matches labels). For Functions, the type here is the type of 2481 // the result, which is not what we want to look at; leave them alone. 2482 Value *v = OpInfo.CallOperandVal; 2483 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2484 OpInfo.CallOperandVal = v; 2485 return; 2486 } 2487 2488 // Otherwise, try to resolve it to something we know about by looking at 2489 // the actual operand type. 2490 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2491 OpInfo.ConstraintCode = Repl; 2492 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2493 } 2494 } 2495} 2496 2497/// \brief Given an exact SDIV by a constant, create a multiplication 2498/// with the multiplicative inverse of the constant. 2499SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, 2500 SelectionDAG &DAG) const { 2501 ConstantSDNode *C = cast<ConstantSDNode>(Op2); 2502 APInt d = C->getAPIntValue(); 2503 assert(d != 0 && "Division by zero!"); 2504 2505 // Shift the value upfront if it is even, so the LSB is one. 2506 unsigned ShAmt = d.countTrailingZeros(); 2507 if (ShAmt) { 2508 // TODO: For UDIV use SRL instead of SRA. 2509 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); 2510 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt); 2511 d = d.ashr(ShAmt); 2512 } 2513 2514 // Calculate the multiplicative inverse, using Newton's method. 2515 APInt t, xn = d; 2516 while ((t = d*xn) != 1) 2517 xn *= APInt(d.getBitWidth(), 2) - t; 2518 2519 Op2 = DAG.getConstant(xn, Op1.getValueType()); 2520 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2); 2521} 2522 2523/// \brief Given an ISD::SDIV node expressing a divide by constant, 2524/// return a DAG expression to select that will generate the same value by 2525/// multiplying by a magic number. See: 2526/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2527SDValue TargetLowering:: 2528BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2529 std::vector<SDNode*> *Created) const { 2530 EVT VT = N->getValueType(0); 2531 SDLoc dl(N); 2532 2533 // Check to see if we can do this. 2534 // FIXME: We should be more aggressive here. 2535 if (!isTypeLegal(VT)) 2536 return SDValue(); 2537 2538 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2539 APInt::ms magics = d.magic(); 2540 2541 // Multiply the numerator (operand 0) by the magic value 2542 // FIXME: We should support doing a MUL in a wider type 2543 SDValue Q; 2544 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : 2545 isOperationLegalOrCustom(ISD::MULHS, VT)) 2546 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2547 DAG.getConstant(magics.m, VT)); 2548 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : 2549 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2550 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2551 N->getOperand(0), 2552 DAG.getConstant(magics.m, VT)).getNode(), 1); 2553 else 2554 return SDValue(); // No mulhs or equvialent 2555 // If d > 0 and m < 0, add the numerator 2556 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2557 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2558 if (Created) 2559 Created->push_back(Q.getNode()); 2560 } 2561 // If d < 0 and m > 0, subtract the numerator. 2562 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2563 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2564 if (Created) 2565 Created->push_back(Q.getNode()); 2566 } 2567 // Shift right algebraic if shift value is nonzero 2568 if (magics.s > 0) { 2569 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2570 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2571 if (Created) 2572 Created->push_back(Q.getNode()); 2573 } 2574 // Extract the sign bit and add it to the quotient 2575 SDValue T = 2576 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2577 getShiftAmountTy(Q.getValueType()))); 2578 if (Created) 2579 Created->push_back(T.getNode()); 2580 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2581} 2582 2583/// \brief Given an ISD::UDIV node expressing a divide by constant, 2584/// return a DAG expression to select that will generate the same value by 2585/// multiplying by a magic number. See: 2586/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2587SDValue TargetLowering:: 2588BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 2589 std::vector<SDNode*> *Created) const { 2590 EVT VT = N->getValueType(0); 2591 SDLoc dl(N); 2592 2593 // Check to see if we can do this. 2594 // FIXME: We should be more aggressive here. 2595 if (!isTypeLegal(VT)) 2596 return SDValue(); 2597 2598 // FIXME: We should use a narrower constant when the upper 2599 // bits are known to be zero. 2600 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2601 APInt::mu magics = N1C.magicu(); 2602 2603 SDValue Q = N->getOperand(0); 2604 2605 // If the divisor is even, we can avoid using the expensive fixup by shifting 2606 // the divided value upfront. 2607 if (magics.a != 0 && !N1C[0]) { 2608 unsigned Shift = N1C.countTrailingZeros(); 2609 Q = DAG.getNode(ISD::SRL, dl, VT, Q, 2610 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType()))); 2611 if (Created) 2612 Created->push_back(Q.getNode()); 2613 2614 // Get magic number for the shifted divisor. 2615 magics = N1C.lshr(Shift).magicu(Shift); 2616 assert(magics.a == 0 && "Should use cheap fixup now"); 2617 } 2618 2619 // Multiply the numerator (operand 0) by the magic value 2620 // FIXME: We should support doing a MUL in a wider type 2621 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : 2622 isOperationLegalOrCustom(ISD::MULHU, VT)) 2623 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); 2624 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : 2625 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2626 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, 2627 DAG.getConstant(magics.m, VT)).getNode(), 1); 2628 else 2629 return SDValue(); // No mulhu or equvialent 2630 if (Created) 2631 Created->push_back(Q.getNode()); 2632 2633 if (magics.a == 0) { 2634 assert(magics.s < N1C.getBitWidth() && 2635 "We shouldn't generate an undefined shift!"); 2636 return DAG.getNode(ISD::SRL, dl, VT, Q, 2637 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType()))); 2638 } else { 2639 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2640 if (Created) 2641 Created->push_back(NPQ.getNode()); 2642 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2643 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType()))); 2644 if (Created) 2645 Created->push_back(NPQ.getNode()); 2646 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2647 if (Created) 2648 Created->push_back(NPQ.getNode()); 2649 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2650 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); 2651 } 2652} 2653