SplitKit.cpp revision 4751eb760e7f4e51cfd594cbe46c7d0d7865d693 
1//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SplitAnalysis class as well as mutator functions for
11// live range splitting.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "SplitKit.h"
17#include "LiveRangeEdit.h"
18#include "VirtRegMap.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/LiveIntervalAnalysis.h"
21#include "llvm/CodeGen/MachineDominators.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetInstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28
29using namespace llvm;
30
31STATISTIC(NumFinished, "Number of splits finished");
32STATISTIC(NumSimple,   "Number of splits that were simple");
33STATISTIC(NumCopies,   "Number of copies inserted for splitting");
34STATISTIC(NumRemats,   "Number of rematerialized defs for splitting");
35STATISTIC(NumRepairs,  "Number of invalid live ranges repaired");
36
37//===----------------------------------------------------------------------===//
38//                                 Split Analysis
39//===----------------------------------------------------------------------===//
40
41SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42                             const LiveIntervals &lis,
43                             const MachineLoopInfo &mli)
44  : MF(vrm.getMachineFunction()),
45    VRM(vrm),
46    LIS(lis),
47    Loops(mli),
48    TII(*MF.getTarget().getInstrInfo()),
49    CurLI(0),
50    LastSplitPoint(MF.getNumBlockIDs()) {}
51
52void SplitAnalysis::clear() {
53  UseSlots.clear();
54  UseBlocks.clear();
55  ThroughBlocks.clear();
56  CurLI = 0;
57  DidRepairRange = false;
58}
59
60SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61  const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62  const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63  std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
64
65  // Compute split points on the first call. The pair is independent of the
66  // current live interval.
67  if (!LSP.first.isValid()) {
68    MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69    if (FirstTerm == MBB->end())
70      LSP.first = LIS.getMBBEndIdx(MBB);
71    else
72      LSP.first = LIS.getInstructionIndex(FirstTerm);
73
74    // If there is a landing pad successor, also find the call instruction.
75    if (!LPad)
76      return LSP.first;
77    // There may not be a call instruction (?) in which case we ignore LPad.
78    LSP.second = LSP.first;
79    for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
80         I != E;) {
81      --I;
82      if (I->getDesc().isCall()) {
83        LSP.second = LIS.getInstructionIndex(I);
84        break;
85      }
86    }
87  }
88
89  // If CurLI is live into a landing pad successor, move the last split point
90  // back to the call that may throw.
91  if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
92    return LSP.second;
93  else
94    return LSP.first;
95}
96
97/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98void SplitAnalysis::analyzeUses() {
99  assert(UseSlots.empty() && "Call clear first");
100
101  // First get all the defs from the interval values. This provides the correct
102  // slots for early clobbers.
103  for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104       E = CurLI->vni_end(); I != E; ++I)
105    if (!(*I)->isPHIDef() && !(*I)->isUnused())
106      UseSlots.push_back((*I)->def);
107
108  // Get use slots form the use-def chain.
109  const MachineRegisterInfo &MRI = MF.getRegInfo();
110  for (MachineRegisterInfo::use_nodbg_iterator
111       I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
112       ++I)
113    if (!I.getOperand().isUndef())
114      UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
115
116  array_pod_sort(UseSlots.begin(), UseSlots.end());
117
118  // Remove duplicates, keeping the smaller slot for each instruction.
119  // That is what we want for early clobbers.
120  UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121                             SlotIndex::isSameInstr),
122                 UseSlots.end());
123
124  // Compute per-live block info.
125  if (!calcLiveBlockInfo()) {
126    // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127    // I am looking at you, RegisterCoalescer!
128    DidRepairRange = true;
129    ++NumRepairs;
130    DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131    const_cast<LiveIntervals&>(LIS)
132      .shrinkToUses(const_cast<LiveInterval*>(CurLI));
133    UseBlocks.clear();
134    ThroughBlocks.clear();
135    bool fixed = calcLiveBlockInfo();
136    (void)fixed;
137    assert(fixed && "Couldn't fix broken live interval");
138  }
139
140  DEBUG(dbgs() << "Analyze counted "
141               << UseSlots.size() << " instrs in "
142               << UseBlocks.size() << " blocks, through "
143               << NumThroughBlocks << " blocks.\n");
144}
145
146/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147/// where CurLI is live.
148bool SplitAnalysis::calcLiveBlockInfo() {
149  ThroughBlocks.resize(MF.getNumBlockIDs());
150  NumThroughBlocks = NumGapBlocks = 0;
151  if (CurLI->empty())
152    return true;
153
154  LiveInterval::const_iterator LVI = CurLI->begin();
155  LiveInterval::const_iterator LVE = CurLI->end();
156
157  SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158  UseI = UseSlots.begin();
159  UseE = UseSlots.end();
160
161  // Loop over basic blocks where CurLI is live.
162  MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
163  for (;;) {
164    BlockInfo BI;
165    BI.MBB = MFI;
166    SlotIndex Start, Stop;
167    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
168
169    // If the block contains no uses, the range must be live through. At one
170    // point, RegisterCoalescer could create dangling ranges that ended
171    // mid-block.
172    if (UseI == UseE || *UseI >= Stop) {
173      ++NumThroughBlocks;
174      ThroughBlocks.set(BI.MBB->getNumber());
175      // The range shouldn't end mid-block if there are no uses. This shouldn't
176      // happen.
177      if (LVI->end < Stop)
178        return false;
179    } else {
180      // This block has uses. Find the first and last uses in the block.
181      BI.FirstUse = *UseI;
182      assert(BI.FirstUse >= Start);
183      do ++UseI;
184      while (UseI != UseE && *UseI < Stop);
185      BI.LastUse = UseI[-1];
186      assert(BI.LastUse < Stop);
187
188      // LVI is the first live segment overlapping MBB.
189      BI.LiveIn = LVI->start <= Start;
190
191      // Look for gaps in the live range.
192      BI.LiveOut = true;
193      while (LVI->end < Stop) {
194        SlotIndex LastStop = LVI->end;
195        if (++LVI == LVE || LVI->start >= Stop) {
196          BI.LiveOut = false;
197          BI.LastUse = LastStop;
198          break;
199        }
200        if (LastStop < LVI->start) {
201          // There is a gap in the live range. Create duplicate entries for the
202          // live-in snippet and the live-out snippet.
203          ++NumGapBlocks;
204
205          // Push the Live-in part.
206          BI.LiveOut = false;
207          UseBlocks.push_back(BI);
208          UseBlocks.back().LastUse = LastStop;
209
210          // Set up BI for the live-out part.
211          BI.LiveIn = false;
212          BI.LiveOut = true;
213          BI.FirstUse = LVI->start;
214        }
215      }
216
217      UseBlocks.push_back(BI);
218
219      // LVI is now at LVE or LVI->end >= Stop.
220      if (LVI == LVE)
221        break;
222    }
223
224    // Live segment ends exactly at Stop. Move to the next segment.
225    if (LVI->end == Stop && ++LVI == LVE)
226      break;
227
228    // Pick the next basic block.
229    if (LVI->start < Stop)
230      ++MFI;
231    else
232      MFI = LIS.getMBBFromIndex(LVI->start);
233  }
234
235  assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
236  return true;
237}
238
239unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
240  if (cli->empty())
241    return 0;
242  LiveInterval *li = const_cast<LiveInterval*>(cli);
243  LiveInterval::iterator LVI = li->begin();
244  LiveInterval::iterator LVE = li->end();
245  unsigned Count = 0;
246
247  // Loop over basic blocks where li is live.
248  MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
249  SlotIndex Stop = LIS.getMBBEndIdx(MFI);
250  for (;;) {
251    ++Count;
252    LVI = li->advanceTo(LVI, Stop);
253    if (LVI == LVE)
254      return Count;
255    do {
256      ++MFI;
257      Stop = LIS.getMBBEndIdx(MFI);
258    } while (Stop <= LVI->start);
259  }
260}
261
262bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
263  unsigned OrigReg = VRM.getOriginal(CurLI->reg);
264  const LiveInterval &Orig = LIS.getInterval(OrigReg);
265  assert(!Orig.empty() && "Splitting empty interval?");
266  LiveInterval::const_iterator I = Orig.find(Idx);
267
268  // Range containing Idx should begin at Idx.
269  if (I != Orig.end() && I->start <= Idx)
270    return I->start == Idx;
271
272  // Range does not contain Idx, previous must end at Idx.
273  return I != Orig.begin() && (--I)->end == Idx;
274}
275
276void SplitAnalysis::analyze(const LiveInterval *li) {
277  clear();
278  CurLI = li;
279  analyzeUses();
280}
281
282
283//===----------------------------------------------------------------------===//
284//                               Split Editor
285//===----------------------------------------------------------------------===//
286
287/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
288SplitEditor::SplitEditor(SplitAnalysis &sa,
289                         LiveIntervals &lis,
290                         VirtRegMap &vrm,
291                         MachineDominatorTree &mdt)
292  : SA(sa), LIS(lis), VRM(vrm),
293    MRI(vrm.getMachineFunction().getRegInfo()),
294    MDT(mdt),
295    TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
296    TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
297    Edit(0),
298    OpenIdx(0),
299    RegAssign(Allocator)
300{}
301
302void SplitEditor::reset(LiveRangeEdit &lre) {
303  Edit = &lre;
304  OpenIdx = 0;
305  RegAssign.clear();
306  Values.clear();
307
308  // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
309  LiveOutSeen.clear();
310
311  // We don't need an AliasAnalysis since we will only be performing
312  // cheap-as-a-copy remats anyway.
313  Edit->anyRematerializable(LIS, TII, 0);
314}
315
316void SplitEditor::dump() const {
317  if (RegAssign.empty()) {
318    dbgs() << " empty\n";
319    return;
320  }
321
322  for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
323    dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
324  dbgs() << '\n';
325}
326
327VNInfo *SplitEditor::defValue(unsigned RegIdx,
328                              const VNInfo *ParentVNI,
329                              SlotIndex Idx) {
330  assert(ParentVNI && "Mapping  NULL value");
331  assert(Idx.isValid() && "Invalid SlotIndex");
332  assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
333  LiveInterval *LI = Edit->get(RegIdx);
334
335  // Create a new value.
336  VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
337
338  // Use insert for lookup, so we can add missing values with a second lookup.
339  std::pair<ValueMap::iterator, bool> InsP =
340    Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
341
342  // This was the first time (RegIdx, ParentVNI) was mapped.
343  // Keep it as a simple def without any liveness.
344  if (InsP.second)
345    return VNI;
346
347  // If the previous value was a simple mapping, add liveness for it now.
348  if (VNInfo *OldVNI = InsP.first->second) {
349    SlotIndex Def = OldVNI->def;
350    LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
351    // No longer a simple mapping.
352    InsP.first->second = 0;
353  }
354
355  // This is a complex mapping, add liveness for VNI
356  SlotIndex Def = VNI->def;
357  LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
358
359  return VNI;
360}
361
362void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
363  assert(ParentVNI && "Mapping  NULL value");
364  VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
365
366  // ParentVNI was either unmapped or already complex mapped. Either way.
367  if (!VNI)
368    return;
369
370  // This was previously a single mapping. Make sure the old def is represented
371  // by a trivial live range.
372  SlotIndex Def = VNI->def;
373  Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
374  VNI = 0;
375}
376
377// extendRange - Extend the live range to reach Idx.
378// Potentially create phi-def values.
379void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
380  assert(Idx.isValid() && "Invalid SlotIndex");
381  MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
382  assert(IdxMBB && "No MBB at Idx");
383  LiveInterval *LI = Edit->get(RegIdx);
384
385  // Is there a def in the same MBB we can extend?
386  if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
387    return;
388
389  // Now for the fun part. We know that ParentVNI potentially has multiple defs,
390  // and we may need to create even more phi-defs to preserve VNInfo SSA form.
391  // Perform a search for all predecessor blocks where we know the dominating
392  // VNInfo.
393  VNInfo *VNI = findReachingDefs(LI, IdxMBB, Idx.getNextSlot());
394
395  // When there were multiple different values, we may need new PHIs.
396  if (!VNI)
397    return updateSSA();
398
399  // Poor man's SSA update for the single-value case.
400  LiveOutPair LOP(VNI, MDT[LIS.getMBBFromIndex(VNI->def)]);
401  for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
402         E = LiveInBlocks.end(); I != E; ++I) {
403    MachineBasicBlock *MBB = I->DomNode->getBlock();
404    SlotIndex Start = LIS.getMBBStartIdx(MBB);
405    if (I->Kill.isValid())
406      LI->addRange(LiveRange(Start, I->Kill, VNI));
407    else {
408      LiveOutCache[MBB] = LOP;
409      LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
410    }
411  }
412}
413
414/// findReachingDefs - Search the CFG for known live-out values.
415/// Add required live-in blocks to LiveInBlocks.
416VNInfo *SplitEditor::findReachingDefs(LiveInterval *LI,
417                                      MachineBasicBlock *KillMBB,
418                                      SlotIndex Kill) {
419  // Initialize the live-out cache the first time it is needed.
420  if (LiveOutSeen.empty()) {
421    unsigned N = VRM.getMachineFunction().getNumBlockIDs();
422    LiveOutSeen.resize(N);
423    LiveOutCache.resize(N);
424  }
425
426  // Blocks where LI should be live-in.
427  SmallVector<MachineBasicBlock*, 16> WorkList(1, KillMBB);
428
429  // Remember if we have seen more than one value.
430  bool UniqueVNI = true;
431  VNInfo *TheVNI = 0;
432
433  // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
434  for (unsigned i = 0; i != WorkList.size(); ++i) {
435    MachineBasicBlock *MBB = WorkList[i];
436    assert(!MBB->pred_empty() && "Value live-in to entry block?");
437    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
438           PE = MBB->pred_end(); PI != PE; ++PI) {
439       MachineBasicBlock *Pred = *PI;
440       LiveOutPair &LOP = LiveOutCache[Pred];
441
442       // Is this a known live-out block?
443       if (LiveOutSeen.test(Pred->getNumber())) {
444         if (VNInfo *VNI = LOP.first) {
445           if (TheVNI && TheVNI != VNI)
446             UniqueVNI = false;
447           TheVNI = VNI;
448         }
449         continue;
450       }
451
452       // First time. LOP is garbage and must be cleared below.
453       LiveOutSeen.set(Pred->getNumber());
454
455       // Does Pred provide a live-out value?
456       SlotIndex Start, Last;
457       tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
458       Last = Last.getPrevSlot();
459       VNInfo *VNI = LI->extendInBlock(Start, Last);
460       LOP.first = VNI;
461       if (VNI) {
462         LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
463         if (TheVNI && TheVNI != VNI)
464           UniqueVNI = false;
465         TheVNI = VNI;
466         continue;
467       }
468       LOP.second = 0;
469
470       // No, we need a live-in value for Pred as well
471       if (Pred != KillMBB)
472          WorkList.push_back(Pred);
473       else
474          // Loopback to KillMBB, so value is really live through.
475         Kill = SlotIndex();
476    }
477  }
478
479  // Transfer WorkList to LiveInBlocks in reverse order.
480  // This ordering works best with updateSSA().
481  LiveInBlocks.clear();
482  LiveInBlocks.reserve(WorkList.size());
483  while(!WorkList.empty())
484    LiveInBlocks.push_back(MDT[WorkList.pop_back_val()]);
485
486  // The kill block may not be live-through.
487  assert(LiveInBlocks.back().DomNode->getBlock() == KillMBB);
488  LiveInBlocks.back().Kill = Kill;
489
490  return UniqueVNI ? TheVNI : 0;
491}
492
493void SplitEditor::updateSSA() {
494  // This is essentially the same iterative algorithm that SSAUpdater uses,
495  // except we already have a dominator tree, so we don't have to recompute it.
496  unsigned Changes;
497  do {
498    Changes = 0;
499    // Propagate live-out values down the dominator tree, inserting phi-defs
500    // when necessary.
501    for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
502           E = LiveInBlocks.end(); I != E; ++I) {
503      MachineDomTreeNode *Node = I->DomNode;
504      // Skip block if the live-in value has already been determined.
505      if (!Node)
506        continue;
507      MachineBasicBlock *MBB = Node->getBlock();
508      MachineDomTreeNode *IDom = Node->getIDom();
509      LiveOutPair IDomValue;
510
511      // We need a live-in value to a block with no immediate dominator?
512      // This is probably an unreachable block that has survived somehow.
513      bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
514
515      // IDom dominates all of our predecessors, but it may not be their
516      // immediate dominator. Check if any of them have live-out values that are
517      // properly dominated by IDom. If so, we need a phi-def here.
518      if (!needPHI) {
519        IDomValue = LiveOutCache[IDom->getBlock()];
520        for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
521               PE = MBB->pred_end(); PI != PE; ++PI) {
522          LiveOutPair Value = LiveOutCache[*PI];
523          if (!Value.first || Value.first == IDomValue.first)
524            continue;
525          // This predecessor is carrying something other than IDomValue.
526          // It could be because IDomValue hasn't propagated yet, or it could be
527          // because MBB is in the dominance frontier of that value.
528          if (MDT.dominates(IDom, Value.second)) {
529            needPHI = true;
530            break;
531          }
532        }
533      }
534
535      // The value may be live-through even if Kill is set, as can happen when
536      // we are called from extendRange. In that case LiveOutSeen is true, and
537      // LiveOutCache indicates a foreign or missing value.
538      LiveOutPair &LOP = LiveOutCache[MBB];
539
540      // Create a phi-def if required.
541      if (needPHI) {
542        ++Changes;
543        SlotIndex Start = LIS.getMBBStartIdx(MBB);
544        unsigned RegIdx = RegAssign.lookup(Start);
545        LiveInterval *LI = Edit->get(RegIdx);
546        VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
547        VNI->setIsPHIDef(true);
548        I->Value = VNI;
549        // This block is done, we know the final value.
550        I->DomNode = 0;
551        if (I->Kill.isValid())
552          LI->addRange(LiveRange(Start, I->Kill, VNI));
553        else {
554          LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
555          LOP = LiveOutPair(VNI, Node);
556        }
557      } else if (IDomValue.first) {
558        // No phi-def here. Remember incoming value.
559        I->Value = IDomValue.first;
560        if (I->Kill.isValid())
561          continue;
562        // Propagate IDomValue if needed:
563        // MBB is live-out and doesn't define its own value.
564        if (LOP.second != Node && LOP.first != IDomValue.first) {
565          ++Changes;
566          LOP = IDomValue;
567        }
568      }
569    }
570  } while (Changes);
571
572  // The values in LiveInBlocks are now accurate. No more phi-defs are needed
573  // for these blocks, so we can color the live ranges.
574  for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
575         E = LiveInBlocks.end(); I != E; ++I) {
576    if (!I->DomNode)
577      continue;
578    assert(I->Value && "No live-in value found");
579    MachineBasicBlock *MBB = I->DomNode->getBlock();
580    SlotIndex Start = LIS.getMBBStartIdx(MBB);
581    unsigned RegIdx = RegAssign.lookup(Start);
582    LiveInterval *LI = Edit->get(RegIdx);
583    LI->addRange(LiveRange(Start, I->Kill.isValid() ?
584                                  I->Kill : LIS.getMBBEndIdx(MBB), I->Value));
585  }
586}
587
588VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
589                                   VNInfo *ParentVNI,
590                                   SlotIndex UseIdx,
591                                   MachineBasicBlock &MBB,
592                                   MachineBasicBlock::iterator I) {
593  MachineInstr *CopyMI = 0;
594  SlotIndex Def;
595  LiveInterval *LI = Edit->get(RegIdx);
596
597  // We may be trying to avoid interference that ends at a deleted instruction,
598  // so always begin RegIdx 0 early and all others late.
599  bool Late = RegIdx != 0;
600
601  // Attempt cheap-as-a-copy rematerialization.
602  LiveRangeEdit::Remat RM(ParentVNI);
603  if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
604    Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
605    ++NumRemats;
606  } else {
607    // Can't remat, just insert a copy from parent.
608    CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
609               .addReg(Edit->getReg());
610    Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
611            .getDefIndex();
612    ++NumCopies;
613  }
614
615  // Define the value in Reg.
616  VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
617  VNI->setCopy(CopyMI);
618  return VNI;
619}
620
621/// Create a new virtual register and live interval.
622unsigned SplitEditor::openIntv() {
623  // Create the complement as index 0.
624  if (Edit->empty())
625    Edit->create(LIS, VRM);
626
627  // Create the open interval.
628  OpenIdx = Edit->size();
629  Edit->create(LIS, VRM);
630  return OpenIdx;
631}
632
633void SplitEditor::selectIntv(unsigned Idx) {
634  assert(Idx != 0 && "Cannot select the complement interval");
635  assert(Idx < Edit->size() && "Can only select previously opened interval");
636  DEBUG(dbgs() << "    selectIntv " << OpenIdx << " -> " << Idx << '\n');
637  OpenIdx = Idx;
638}
639
640SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
641  assert(OpenIdx && "openIntv not called before enterIntvBefore");
642  DEBUG(dbgs() << "    enterIntvBefore " << Idx);
643  Idx = Idx.getBaseIndex();
644  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
645  if (!ParentVNI) {
646    DEBUG(dbgs() << ": not live\n");
647    return Idx;
648  }
649  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
650  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
651  assert(MI && "enterIntvBefore called with invalid index");
652
653  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
654  return VNI->def;
655}
656
657SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
658  assert(OpenIdx && "openIntv not called before enterIntvAfter");
659  DEBUG(dbgs() << "    enterIntvAfter " << Idx);
660  Idx = Idx.getBoundaryIndex();
661  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
662  if (!ParentVNI) {
663    DEBUG(dbgs() << ": not live\n");
664    return Idx;
665  }
666  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
667  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
668  assert(MI && "enterIntvAfter called with invalid index");
669
670  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
671                              llvm::next(MachineBasicBlock::iterator(MI)));
672  return VNI->def;
673}
674
675SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
676  assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
677  SlotIndex End = LIS.getMBBEndIdx(&MBB);
678  SlotIndex Last = End.getPrevSlot();
679  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
680  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
681  if (!ParentVNI) {
682    DEBUG(dbgs() << ": not live\n");
683    return End;
684  }
685  DEBUG(dbgs() << ": valno " << ParentVNI->id);
686  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
687                              LIS.getLastSplitPoint(Edit->getParent(), &MBB));
688  RegAssign.insert(VNI->def, End, OpenIdx);
689  DEBUG(dump());
690  return VNI->def;
691}
692
693/// useIntv - indicate that all instructions in MBB should use OpenLI.
694void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
695  useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
696}
697
698void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
699  assert(OpenIdx && "openIntv not called before useIntv");
700  DEBUG(dbgs() << "    useIntv [" << Start << ';' << End << "):");
701  RegAssign.insert(Start, End, OpenIdx);
702  DEBUG(dump());
703}
704
705SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
706  assert(OpenIdx && "openIntv not called before leaveIntvAfter");
707  DEBUG(dbgs() << "    leaveIntvAfter " << Idx);
708
709  // The interval must be live beyond the instruction at Idx.
710  Idx = Idx.getBoundaryIndex();
711  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
712  if (!ParentVNI) {
713    DEBUG(dbgs() << ": not live\n");
714    return Idx.getNextSlot();
715  }
716  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
717
718  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
719  assert(MI && "No instruction at index");
720  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
721                              llvm::next(MachineBasicBlock::iterator(MI)));
722  return VNI->def;
723}
724
725SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
726  assert(OpenIdx && "openIntv not called before leaveIntvBefore");
727  DEBUG(dbgs() << "    leaveIntvBefore " << Idx);
728
729  // The interval must be live into the instruction at Idx.
730  Idx = Idx.getBaseIndex();
731  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
732  if (!ParentVNI) {
733    DEBUG(dbgs() << ": not live\n");
734    return Idx.getNextSlot();
735  }
736  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
737
738  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
739  assert(MI && "No instruction at index");
740  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
741  return VNI->def;
742}
743
744SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
745  assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
746  SlotIndex Start = LIS.getMBBStartIdx(&MBB);
747  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
748
749  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
750  if (!ParentVNI) {
751    DEBUG(dbgs() << ": not live\n");
752    return Start;
753  }
754
755  VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
756                              MBB.SkipPHIsAndLabels(MBB.begin()));
757  RegAssign.insert(Start, VNI->def, OpenIdx);
758  DEBUG(dump());
759  return VNI->def;
760}
761
762void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
763  assert(OpenIdx && "openIntv not called before overlapIntv");
764  const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
765  assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
766         "Parent changes value in extended range");
767  assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
768         "Range cannot span basic blocks");
769
770  // The complement interval will be extended as needed by extendRange().
771  if (ParentVNI)
772    markComplexMapped(0, ParentVNI);
773  DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
774  RegAssign.insert(Start, End, OpenIdx);
775  DEBUG(dump());
776}
777
778/// transferValues - Transfer all possible values to the new live ranges.
779/// Values that were rematerialized are left alone, they need extendRange().
780bool SplitEditor::transferValues() {
781  bool Skipped = false;
782  LiveInBlocks.clear();
783  RegAssignMap::const_iterator AssignI = RegAssign.begin();
784  for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
785         ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
786    DEBUG(dbgs() << "  blit " << *ParentI << ':');
787    VNInfo *ParentVNI = ParentI->valno;
788    // RegAssign has holes where RegIdx 0 should be used.
789    SlotIndex Start = ParentI->start;
790    AssignI.advanceTo(Start);
791    do {
792      unsigned RegIdx;
793      SlotIndex End = ParentI->end;
794      if (!AssignI.valid()) {
795        RegIdx = 0;
796      } else if (AssignI.start() <= Start) {
797        RegIdx = AssignI.value();
798        if (AssignI.stop() < End) {
799          End = AssignI.stop();
800          ++AssignI;
801        }
802      } else {
803        RegIdx = 0;
804        End = std::min(End, AssignI.start());
805      }
806
807      // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
808      DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
809      LiveInterval *LI = Edit->get(RegIdx);
810
811      // Check for a simply defined value that can be blitted directly.
812      if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
813        DEBUG(dbgs() << ':' << VNI->id);
814        LI->addRange(LiveRange(Start, End, VNI));
815        Start = End;
816        continue;
817      }
818
819      // Skip rematerialized values, we need to use extendRange() and
820      // extendPHIKillRanges() to completely recompute the live ranges.
821      if (Edit->didRematerialize(ParentVNI)) {
822        DEBUG(dbgs() << "(remat)");
823        Skipped = true;
824        Start = End;
825        continue;
826      }
827
828      // Initialize the live-out cache the first time it is needed.
829      if (LiveOutSeen.empty()) {
830        unsigned N = VRM.getMachineFunction().getNumBlockIDs();
831        LiveOutSeen.resize(N);
832        LiveOutCache.resize(N);
833      }
834
835      // This value has multiple defs in RegIdx, but it wasn't rematerialized,
836      // so the live range is accurate. Add live-in blocks in [Start;End) to the
837      // LiveInBlocks.
838      MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
839      SlotIndex BlockStart, BlockEnd;
840      tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
841
842      // The first block may be live-in, or it may have its own def.
843      if (Start != BlockStart) {
844        VNInfo *VNI = LI->extendInBlock(BlockStart,
845                                        std::min(BlockEnd, End).getPrevSlot());
846        assert(VNI && "Missing def for complex mapped value");
847        DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
848        // MBB has its own def. Is it also live-out?
849        if (BlockEnd <= End) {
850          LiveOutSeen.set(MBB->getNumber());
851          LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
852        }
853        // Skip to the next block for live-in.
854        ++MBB;
855        BlockStart = BlockEnd;
856      }
857
858      // Handle the live-in blocks covered by [Start;End).
859      assert(Start <= BlockStart && "Expected live-in block");
860      while (BlockStart < End) {
861        DEBUG(dbgs() << ">BB#" << MBB->getNumber());
862        BlockEnd = LIS.getMBBEndIdx(MBB);
863        if (BlockStart == ParentVNI->def) {
864          // This block has the def of a parent PHI, so it isn't live-in.
865          assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
866          VNInfo *VNI = LI->extendInBlock(BlockStart,
867                                         std::min(BlockEnd, End).getPrevSlot());
868          assert(VNI && "Missing def for complex mapped parent PHI");
869          if (End >= BlockEnd) {
870            // Live-out as well.
871            LiveOutSeen.set(MBB->getNumber());
872            LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
873          }
874        } else {
875          // This block needs a live-in value.
876          LiveInBlocks.push_back(MDT[MBB]);
877          // The last block covered may not be live-out.
878          if (End < BlockEnd)
879            LiveInBlocks.back().Kill = End;
880          else {
881            // Live-out, but we need updateSSA to tell us the value.
882            LiveOutSeen.set(MBB->getNumber());
883            LiveOutCache[MBB] = LiveOutPair((VNInfo*)0,
884                                            (MachineDomTreeNode*)0);
885          }
886        }
887        BlockStart = BlockEnd;
888        ++MBB;
889      }
890      Start = End;
891    } while (Start != ParentI->end);
892    DEBUG(dbgs() << '\n');
893  }
894
895  if (!LiveInBlocks.empty())
896    updateSSA();
897
898  return Skipped;
899}
900
901void SplitEditor::extendPHIKillRanges() {
902    // Extend live ranges to be live-out for successor PHI values.
903  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
904       E = Edit->getParent().vni_end(); I != E; ++I) {
905    const VNInfo *PHIVNI = *I;
906    if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
907      continue;
908    unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
909    MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
910    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
911         PE = MBB->pred_end(); PI != PE; ++PI) {
912      SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
913      // The predecessor may not have a live-out value. That is OK, like an
914      // undef PHI operand.
915      if (Edit->getParent().liveAt(End)) {
916        assert(RegAssign.lookup(End) == RegIdx &&
917               "Different register assignment in phi predecessor");
918        extendRange(RegIdx, End);
919      }
920    }
921  }
922}
923
924/// rewriteAssigned - Rewrite all uses of Edit->getReg().
925void SplitEditor::rewriteAssigned(bool ExtendRanges) {
926  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
927       RE = MRI.reg_end(); RI != RE;) {
928    MachineOperand &MO = RI.getOperand();
929    MachineInstr *MI = MO.getParent();
930    ++RI;
931    // LiveDebugVariables should have handled all DBG_VALUE instructions.
932    if (MI->isDebugValue()) {
933      DEBUG(dbgs() << "Zapping " << *MI);
934      MO.setReg(0);
935      continue;
936    }
937
938    // <undef> operands don't really read the register, so it doesn't matter
939    // which register we choose.  When the use operand is tied to a def, we must
940    // use the same register as the def, so just do that always.
941    SlotIndex Idx = LIS.getInstructionIndex(MI);
942    if (MO.isDef() || MO.isUndef())
943      Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
944
945    // Rewrite to the mapped register at Idx.
946    unsigned RegIdx = RegAssign.lookup(Idx);
947    MO.setReg(Edit->get(RegIdx)->reg);
948    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
949                 << Idx << ':' << RegIdx << '\t' << *MI);
950
951    // Extend liveness to Idx if the instruction reads reg.
952    if (!ExtendRanges || MO.isUndef())
953      continue;
954
955    // Skip instructions that don't read Reg.
956    if (MO.isDef()) {
957      if (!MO.getSubReg() && !MO.isEarlyClobber())
958        continue;
959      // We may wan't to extend a live range for a partial redef, or for a use
960      // tied to an early clobber.
961      Idx = Idx.getPrevSlot();
962      if (!Edit->getParent().liveAt(Idx))
963        continue;
964    } else
965      Idx = Idx.getUseIndex();
966
967    extendRange(RegIdx, Idx);
968  }
969}
970
971void SplitEditor::deleteRematVictims() {
972  SmallVector<MachineInstr*, 8> Dead;
973  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
974    LiveInterval *LI = *I;
975    for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
976           LII != LIE; ++LII) {
977      // Dead defs end at the store slot.
978      if (LII->end != LII->valno->def.getNextSlot())
979        continue;
980      MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
981      assert(MI && "Missing instruction for dead def");
982      MI->addRegisterDead(LI->reg, &TRI);
983
984      if (!MI->allDefsAreDead())
985        continue;
986
987      DEBUG(dbgs() << "All defs dead: " << *MI);
988      Dead.push_back(MI);
989    }
990  }
991
992  if (Dead.empty())
993    return;
994
995  Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
996}
997
998void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
999  ++NumFinished;
1000
1001  // At this point, the live intervals in Edit contain VNInfos corresponding to
1002  // the inserted copies.
1003
1004  // Add the original defs from the parent interval.
1005  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1006         E = Edit->getParent().vni_end(); I != E; ++I) {
1007    const VNInfo *ParentVNI = *I;
1008    if (ParentVNI->isUnused())
1009      continue;
1010    unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1011    VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1012    VNI->setIsPHIDef(ParentVNI->isPHIDef());
1013    VNI->setCopy(ParentVNI->getCopy());
1014
1015    // Mark rematted values as complex everywhere to force liveness computation.
1016    // The new live ranges may be truncated.
1017    if (Edit->didRematerialize(ParentVNI))
1018      for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1019        markComplexMapped(i, ParentVNI);
1020  }
1021
1022  // Transfer the simply mapped values, check if any are skipped.
1023  bool Skipped = transferValues();
1024  if (Skipped)
1025    extendPHIKillRanges();
1026  else
1027    ++NumSimple;
1028
1029  // Rewrite virtual registers, possibly extending ranges.
1030  rewriteAssigned(Skipped);
1031
1032  // Delete defs that were rematted everywhere.
1033  if (Skipped)
1034    deleteRematVictims();
1035
1036  // Get rid of unused values and set phi-kill flags.
1037  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1038    (*I)->RenumberValues(LIS);
1039
1040  // Provide a reverse mapping from original indices to Edit ranges.
1041  if (LRMap) {
1042    LRMap->clear();
1043    for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1044      LRMap->push_back(i);
1045  }
1046
1047  // Now check if any registers were separated into multiple components.
1048  ConnectedVNInfoEqClasses ConEQ(LIS);
1049  for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1050    // Don't use iterators, they are invalidated by create() below.
1051    LiveInterval *li = Edit->get(i);
1052    unsigned NumComp = ConEQ.Classify(li);
1053    if (NumComp <= 1)
1054      continue;
1055    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
1056    SmallVector<LiveInterval*, 8> dups;
1057    dups.push_back(li);
1058    for (unsigned j = 1; j != NumComp; ++j)
1059      dups.push_back(&Edit->create(LIS, VRM));
1060    ConEQ.Distribute(&dups[0], MRI);
1061    // The new intervals all map back to i.
1062    if (LRMap)
1063      LRMap->resize(Edit->size(), i);
1064  }
1065
1066  // Calculate spill weight and allocation hints for new intervals.
1067  Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1068
1069  assert(!LRMap || LRMap->size() == Edit->size());
1070}
1071
1072
1073//===----------------------------------------------------------------------===//
1074//                            Single Block Splitting
1075//===----------------------------------------------------------------------===//
1076
1077/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
1078/// may be an advantage to split CurLI for the duration of the block.
1079bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
1080  // If CurLI is local to one block, there is no point to splitting it.
1081  if (UseBlocks.size() <= 1)
1082    return false;
1083  // Add blocks with multiple uses.
1084  for (unsigned i = 0, e = UseBlocks.size(); i != e; ++i) {
1085    const BlockInfo &BI = UseBlocks[i];
1086    if (BI.FirstUse == BI.LastUse)
1087      continue;
1088    Blocks.insert(BI.MBB);
1089  }
1090  return !Blocks.empty();
1091}
1092
1093void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1094  openIntv();
1095  SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1096  SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
1097    LastSplitPoint));
1098  if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
1099    useIntv(SegStart, leaveIntvAfter(BI.LastUse));
1100  } else {
1101      // The last use is after the last valid split point.
1102    SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1103    useIntv(SegStart, SegStop);
1104    overlapIntv(SegStop, BI.LastUse);
1105  }
1106}
1107
1108/// splitSingleBlocks - Split CurLI into a separate live interval inside each
1109/// basic block in Blocks.
1110void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
1111  DEBUG(dbgs() << "  splitSingleBlocks for " << Blocks.size() << " blocks.\n");
1112  ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA.getUseBlocks();
1113  for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1114    const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1115    if (Blocks.count(BI.MBB))
1116      splitSingleBlock(BI);
1117  }
1118  finish();
1119}
1120
1121
1122//===----------------------------------------------------------------------===//
1123//                    Global Live Range Splitting Support
1124//===----------------------------------------------------------------------===//
1125
1126// These methods support a method of global live range splitting that uses a
1127// global algorithm to decide intervals for CFG edges. They will insert split
1128// points and color intervals in basic blocks while avoiding interference.
1129//
1130// Note that splitSingleBlock is also useful for blocks where both CFG edges
1131// are on the stack.
1132
1133void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1134                                        unsigned IntvIn, SlotIndex LeaveBefore,
1135                                        unsigned IntvOut, SlotIndex EnterAfter){
1136  SlotIndex Start, Stop;
1137  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1138
1139  DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1140               << ") intf " << LeaveBefore << '-' << EnterAfter
1141               << ", live-through " << IntvIn << " -> " << IntvOut);
1142
1143  assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1144
1145  assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1146  assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1147  assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1148
1149  MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1150
1151  if (!IntvOut) {
1152    DEBUG(dbgs() << ", spill on entry.\n");
1153    //
1154    //        <<<<<<<<<    Possible LeaveBefore interference.
1155    //    |-----------|    Live through.
1156    //    -____________    Spill on entry.
1157    //
1158    selectIntv(IntvIn);
1159    SlotIndex Idx = leaveIntvAtTop(*MBB);
1160    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1161    (void)Idx;
1162    return;
1163  }
1164
1165  if (!IntvIn) {
1166    DEBUG(dbgs() << ", reload on exit.\n");
1167    //
1168    //    >>>>>>>          Possible EnterAfter interference.
1169    //    |-----------|    Live through.
1170    //    ___________--    Reload on exit.
1171    //
1172    selectIntv(IntvOut);
1173    SlotIndex Idx = enterIntvAtEnd(*MBB);
1174    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1175    (void)Idx;
1176    return;
1177  }
1178
1179  if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1180    DEBUG(dbgs() << ", straight through.\n");
1181    //
1182    //    |-----------|    Live through.
1183    //    -------------    Straight through, same intv, no interference.
1184    //
1185    selectIntv(IntvOut);
1186    useIntv(Start, Stop);
1187    return;
1188  }
1189
1190  // We cannot legally insert splits after LSP.
1191  SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1192  assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1193
1194  if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1195                  LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1196    DEBUG(dbgs() << ", switch avoiding interference.\n");
1197    //
1198    //    >>>>     <<<<    Non-overlapping EnterAfter/LeaveBefore interference.
1199    //    |-----------|    Live through.
1200    //    ------=======    Switch intervals between interference.
1201    //
1202    selectIntv(IntvOut);
1203    SlotIndex Idx;
1204    if (LeaveBefore && LeaveBefore < LSP) {
1205      Idx = enterIntvBefore(LeaveBefore);
1206      useIntv(Idx, Stop);
1207    } else {
1208      Idx = enterIntvAtEnd(*MBB);
1209    }
1210    selectIntv(IntvIn);
1211    useIntv(Start, Idx);
1212    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1213    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1214    return;
1215  }
1216
1217  DEBUG(dbgs() << ", create local intv for interference.\n");
1218  //
1219  //    >>><><><><<<<    Overlapping EnterAfter/LeaveBefore interference.
1220  //    |-----------|    Live through.
1221  //    ==---------==    Switch intervals before/after interference.
1222  //
1223  assert(LeaveBefore <= EnterAfter && "Missed case");
1224
1225  selectIntv(IntvOut);
1226  SlotIndex Idx = enterIntvAfter(EnterAfter);
1227  useIntv(Idx, Stop);
1228  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1229
1230  selectIntv(IntvIn);
1231  Idx = leaveIntvBefore(LeaveBefore);
1232  useIntv(Start, Idx);
1233  assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1234}
1235
1236
1237void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1238                                  unsigned IntvIn, SlotIndex LeaveBefore) {
1239  SlotIndex Start, Stop;
1240  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1241
1242  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1243               << "), uses " << BI.FirstUse << '-' << BI.LastUse
1244               << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1245               << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1246
1247  assert(IntvIn && "Must have register in");
1248  assert(BI.LiveIn && "Must be live-in");
1249  assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1250
1251  if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastUse)) {
1252    DEBUG(dbgs() << " before interference.\n");
1253    //
1254    //               <<<    Interference after kill.
1255    //     |---o---x   |    Killed in block.
1256    //     =========        Use IntvIn everywhere.
1257    //
1258    selectIntv(IntvIn);
1259    useIntv(Start, BI.LastUse);
1260    return;
1261  }
1262
1263  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1264
1265  if (!LeaveBefore || LeaveBefore > BI.LastUse.getBoundaryIndex()) {
1266    //
1267    //               <<<    Possible interference after last use.
1268    //     |---o---o---|    Live-out on stack.
1269    //     =========____    Leave IntvIn after last use.
1270    //
1271    //                 <    Interference after last use.
1272    //     |---o---o--o|    Live-out on stack, late last use.
1273    //     ============     Copy to stack after LSP, overlap IntvIn.
1274    //            \_____    Stack interval is live-out.
1275    //
1276    if (BI.LastUse < LSP) {
1277      DEBUG(dbgs() << ", spill after last use before interference.\n");
1278      selectIntv(IntvIn);
1279      SlotIndex Idx = leaveIntvAfter(BI.LastUse);
1280      useIntv(Start, Idx);
1281      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1282    } else {
1283      DEBUG(dbgs() << ", spill before last split point.\n");
1284      selectIntv(IntvIn);
1285      SlotIndex Idx = leaveIntvBefore(LSP);
1286      overlapIntv(Idx, BI.LastUse);
1287      useIntv(Start, Idx);
1288      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1289    }
1290    return;
1291  }
1292
1293  // The interference is overlapping somewhere we wanted to use IntvIn. That
1294  // means we need to create a local interval that can be allocated a
1295  // different register.
1296  unsigned LocalIntv = openIntv();
1297  (void)LocalIntv;
1298  DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1299
1300  if (!BI.LiveOut || BI.LastUse < LSP) {
1301    //
1302    //           <<<<<<<    Interference overlapping uses.
1303    //     |---o---o---|    Live-out on stack.
1304    //     =====----____    Leave IntvIn before interference, then spill.
1305    //
1306    SlotIndex To = leaveIntvAfter(BI.LastUse);
1307    SlotIndex From = enterIntvBefore(LeaveBefore);
1308    useIntv(From, To);
1309    selectIntv(IntvIn);
1310    useIntv(Start, From);
1311    assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1312    return;
1313  }
1314
1315  //           <<<<<<<    Interference overlapping uses.
1316  //     |---o---o--o|    Live-out on stack, late last use.
1317  //     =====-------     Copy to stack before LSP, overlap LocalIntv.
1318  //            \_____    Stack interval is live-out.
1319  //
1320  SlotIndex To = leaveIntvBefore(LSP);
1321  overlapIntv(To, BI.LastUse);
1322  SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1323  useIntv(From, To);
1324  selectIntv(IntvIn);
1325  useIntv(Start, From);
1326  assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1327}
1328
1329void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1330                                   unsigned IntvOut, SlotIndex EnterAfter) {
1331  SlotIndex Start, Stop;
1332  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1333
1334  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1335               << "), uses " << BI.FirstUse << '-' << BI.LastUse
1336               << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1337               << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1338
1339  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1340
1341  assert(IntvOut && "Must have register out");
1342  assert(BI.LiveOut && "Must be live-out");
1343  assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1344
1345  if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstUse)) {
1346    DEBUG(dbgs() << " after interference.\n");
1347    //
1348    //    >>>>             Interference before def.
1349    //    |   o---o---|    Defined in block.
1350    //        =========    Use IntvOut everywhere.
1351    //
1352    selectIntv(IntvOut);
1353    useIntv(BI.FirstUse, Stop);
1354    return;
1355  }
1356
1357  if (!EnterAfter || EnterAfter < BI.FirstUse.getBaseIndex()) {
1358    DEBUG(dbgs() << ", reload after interference.\n");
1359    //
1360    //    >>>>             Interference before def.
1361    //    |---o---o---|    Live-through, stack-in.
1362    //    ____=========    Enter IntvOut before first use.
1363    //
1364    selectIntv(IntvOut);
1365    SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstUse));
1366    useIntv(Idx, Stop);
1367    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1368    return;
1369  }
1370
1371  // The interference is overlapping somewhere we wanted to use IntvOut. That
1372  // means we need to create a local interval that can be allocated a
1373  // different register.
1374  DEBUG(dbgs() << ", interference overlaps uses.\n");
1375  //
1376  //    >>>>>>>          Interference overlapping uses.
1377  //    |---o---o---|    Live-through, stack-in.
1378  //    ____---======    Create local interval for interference range.
1379  //
1380  selectIntv(IntvOut);
1381  SlotIndex Idx = enterIntvAfter(EnterAfter);
1382  useIntv(Idx, Stop);
1383  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1384
1385  openIntv();
1386  SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstUse));
1387  useIntv(From, Idx);
1388}
1389