TargetLoweringBase.cpp revision 41418d17cced656f91038b2482bc9d173b4974b0
1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the TargetLoweringBase class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Target/TargetLowering.h" 15#include "llvm/ADT/BitVector.h" 16#include "llvm/ADT/STLExtras.h" 17#include "llvm/ADT/Triple.h" 18#include "llvm/CodeGen/Analysis.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineJumpTableInfo.h" 22#include "llvm/IR/DataLayout.h" 23#include "llvm/IR/DerivedTypes.h" 24#include "llvm/IR/GlobalVariable.h" 25#include "llvm/MC/MCAsmInfo.h" 26#include "llvm/MC/MCExpr.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Target/TargetLoweringObjectFile.h" 31#include "llvm/Target/TargetMachine.h" 32#include "llvm/Target/TargetRegisterInfo.h" 33#include <cctype> 34using namespace llvm; 35 36/// InitLibcallNames - Set default libcall names. 37/// 38static void InitLibcallNames(const char **Names, const TargetMachine &TM) { 39 Names[RTLIB::SHL_I16] = "__ashlhi3"; 40 Names[RTLIB::SHL_I32] = "__ashlsi3"; 41 Names[RTLIB::SHL_I64] = "__ashldi3"; 42 Names[RTLIB::SHL_I128] = "__ashlti3"; 43 Names[RTLIB::SRL_I16] = "__lshrhi3"; 44 Names[RTLIB::SRL_I32] = "__lshrsi3"; 45 Names[RTLIB::SRL_I64] = "__lshrdi3"; 46 Names[RTLIB::SRL_I128] = "__lshrti3"; 47 Names[RTLIB::SRA_I16] = "__ashrhi3"; 48 Names[RTLIB::SRA_I32] = "__ashrsi3"; 49 Names[RTLIB::SRA_I64] = "__ashrdi3"; 50 Names[RTLIB::SRA_I128] = "__ashrti3"; 51 Names[RTLIB::MUL_I8] = "__mulqi3"; 52 Names[RTLIB::MUL_I16] = "__mulhi3"; 53 Names[RTLIB::MUL_I32] = "__mulsi3"; 54 Names[RTLIB::MUL_I64] = "__muldi3"; 55 Names[RTLIB::MUL_I128] = "__multi3"; 56 Names[RTLIB::MULO_I32] = "__mulosi4"; 57 Names[RTLIB::MULO_I64] = "__mulodi4"; 58 Names[RTLIB::MULO_I128] = "__muloti4"; 59 Names[RTLIB::SDIV_I8] = "__divqi3"; 60 Names[RTLIB::SDIV_I16] = "__divhi3"; 61 Names[RTLIB::SDIV_I32] = "__divsi3"; 62 Names[RTLIB::SDIV_I64] = "__divdi3"; 63 Names[RTLIB::SDIV_I128] = "__divti3"; 64 Names[RTLIB::UDIV_I8] = "__udivqi3"; 65 Names[RTLIB::UDIV_I16] = "__udivhi3"; 66 Names[RTLIB::UDIV_I32] = "__udivsi3"; 67 Names[RTLIB::UDIV_I64] = "__udivdi3"; 68 Names[RTLIB::UDIV_I128] = "__udivti3"; 69 Names[RTLIB::SREM_I8] = "__modqi3"; 70 Names[RTLIB::SREM_I16] = "__modhi3"; 71 Names[RTLIB::SREM_I32] = "__modsi3"; 72 Names[RTLIB::SREM_I64] = "__moddi3"; 73 Names[RTLIB::SREM_I128] = "__modti3"; 74 Names[RTLIB::UREM_I8] = "__umodqi3"; 75 Names[RTLIB::UREM_I16] = "__umodhi3"; 76 Names[RTLIB::UREM_I32] = "__umodsi3"; 77 Names[RTLIB::UREM_I64] = "__umoddi3"; 78 Names[RTLIB::UREM_I128] = "__umodti3"; 79 80 // These are generally not available. 81 Names[RTLIB::SDIVREM_I8] = 0; 82 Names[RTLIB::SDIVREM_I16] = 0; 83 Names[RTLIB::SDIVREM_I32] = 0; 84 Names[RTLIB::SDIVREM_I64] = 0; 85 Names[RTLIB::SDIVREM_I128] = 0; 86 Names[RTLIB::UDIVREM_I8] = 0; 87 Names[RTLIB::UDIVREM_I16] = 0; 88 Names[RTLIB::UDIVREM_I32] = 0; 89 Names[RTLIB::UDIVREM_I64] = 0; 90 Names[RTLIB::UDIVREM_I128] = 0; 91 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_F128] = "__addtf3"; 98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 99 Names[RTLIB::SUB_F32] = "__subsf3"; 100 Names[RTLIB::SUB_F64] = "__subdf3"; 101 Names[RTLIB::SUB_F80] = "__subxf3"; 102 Names[RTLIB::SUB_F128] = "__subtf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_F128] = "__multf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_F128] = "__divtf3"; 113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 114 Names[RTLIB::REM_F32] = "fmodf"; 115 Names[RTLIB::REM_F64] = "fmod"; 116 Names[RTLIB::REM_F80] = "fmodl"; 117 Names[RTLIB::REM_F128] = "fmodl"; 118 Names[RTLIB::REM_PPCF128] = "fmodl"; 119 Names[RTLIB::FMA_F32] = "fmaf"; 120 Names[RTLIB::FMA_F64] = "fma"; 121 Names[RTLIB::FMA_F80] = "fmal"; 122 Names[RTLIB::FMA_F128] = "fmal"; 123 Names[RTLIB::FMA_PPCF128] = "fmal"; 124 Names[RTLIB::POWI_F32] = "__powisf2"; 125 Names[RTLIB::POWI_F64] = "__powidf2"; 126 Names[RTLIB::POWI_F80] = "__powixf2"; 127 Names[RTLIB::POWI_F128] = "__powitf2"; 128 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 129 Names[RTLIB::SQRT_F32] = "sqrtf"; 130 Names[RTLIB::SQRT_F64] = "sqrt"; 131 Names[RTLIB::SQRT_F80] = "sqrtl"; 132 Names[RTLIB::SQRT_F128] = "sqrtl"; 133 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 134 Names[RTLIB::LOG_F32] = "logf"; 135 Names[RTLIB::LOG_F64] = "log"; 136 Names[RTLIB::LOG_F80] = "logl"; 137 Names[RTLIB::LOG_F128] = "logl"; 138 Names[RTLIB::LOG_PPCF128] = "logl"; 139 Names[RTLIB::LOG2_F32] = "log2f"; 140 Names[RTLIB::LOG2_F64] = "log2"; 141 Names[RTLIB::LOG2_F80] = "log2l"; 142 Names[RTLIB::LOG2_F128] = "log2l"; 143 Names[RTLIB::LOG2_PPCF128] = "log2l"; 144 Names[RTLIB::LOG10_F32] = "log10f"; 145 Names[RTLIB::LOG10_F64] = "log10"; 146 Names[RTLIB::LOG10_F80] = "log10l"; 147 Names[RTLIB::LOG10_F128] = "log10l"; 148 Names[RTLIB::LOG10_PPCF128] = "log10l"; 149 Names[RTLIB::EXP_F32] = "expf"; 150 Names[RTLIB::EXP_F64] = "exp"; 151 Names[RTLIB::EXP_F80] = "expl"; 152 Names[RTLIB::EXP_F128] = "expl"; 153 Names[RTLIB::EXP_PPCF128] = "expl"; 154 Names[RTLIB::EXP2_F32] = "exp2f"; 155 Names[RTLIB::EXP2_F64] = "exp2"; 156 Names[RTLIB::EXP2_F80] = "exp2l"; 157 Names[RTLIB::EXP2_F128] = "exp2l"; 158 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 159 Names[RTLIB::SIN_F32] = "sinf"; 160 Names[RTLIB::SIN_F64] = "sin"; 161 Names[RTLIB::SIN_F80] = "sinl"; 162 Names[RTLIB::SIN_F128] = "sinl"; 163 Names[RTLIB::SIN_PPCF128] = "sinl"; 164 Names[RTLIB::COS_F32] = "cosf"; 165 Names[RTLIB::COS_F64] = "cos"; 166 Names[RTLIB::COS_F80] = "cosl"; 167 Names[RTLIB::COS_F128] = "cosl"; 168 Names[RTLIB::COS_PPCF128] = "cosl"; 169 Names[RTLIB::POW_F32] = "powf"; 170 Names[RTLIB::POW_F64] = "pow"; 171 Names[RTLIB::POW_F80] = "powl"; 172 Names[RTLIB::POW_F128] = "powl"; 173 Names[RTLIB::POW_PPCF128] = "powl"; 174 Names[RTLIB::CEIL_F32] = "ceilf"; 175 Names[RTLIB::CEIL_F64] = "ceil"; 176 Names[RTLIB::CEIL_F80] = "ceill"; 177 Names[RTLIB::CEIL_F128] = "ceill"; 178 Names[RTLIB::CEIL_PPCF128] = "ceill"; 179 Names[RTLIB::TRUNC_F32] = "truncf"; 180 Names[RTLIB::TRUNC_F64] = "trunc"; 181 Names[RTLIB::TRUNC_F80] = "truncl"; 182 Names[RTLIB::TRUNC_F128] = "truncl"; 183 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 184 Names[RTLIB::RINT_F32] = "rintf"; 185 Names[RTLIB::RINT_F64] = "rint"; 186 Names[RTLIB::RINT_F80] = "rintl"; 187 Names[RTLIB::RINT_F128] = "rintl"; 188 Names[RTLIB::RINT_PPCF128] = "rintl"; 189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 190 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 194 Names[RTLIB::ROUND_F32] = "roundf"; 195 Names[RTLIB::ROUND_F64] = "round"; 196 Names[RTLIB::ROUND_F80] = "roundl"; 197 Names[RTLIB::ROUND_F128] = "roundl"; 198 Names[RTLIB::ROUND_PPCF128] = "roundl"; 199 Names[RTLIB::FLOOR_F32] = "floorf"; 200 Names[RTLIB::FLOOR_F64] = "floor"; 201 Names[RTLIB::FLOOR_F80] = "floorl"; 202 Names[RTLIB::FLOOR_F128] = "floorl"; 203 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 204 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 205 Names[RTLIB::COPYSIGN_F64] = "copysign"; 206 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 207 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 208 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 209 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 210 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 211 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 212 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 213 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 214 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 215 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 216 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 217 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 218 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 219 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 220 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 221 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 222 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 223 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 224 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 225 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 226 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 227 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 228 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 229 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 230 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 231 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 232 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 233 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 234 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 235 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 236 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 237 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 238 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 239 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 240 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 241 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 242 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 243 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 244 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 245 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 246 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 247 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 248 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 249 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 250 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 251 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 252 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 253 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 254 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 255 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 256 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 257 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 258 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 259 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 260 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 261 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 262 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 263 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 264 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 265 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 266 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 267 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 268 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 269 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 270 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 271 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 272 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 273 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 274 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 275 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 276 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 277 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 278 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 279 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 280 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 281 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 282 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 283 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 284 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 285 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 286 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 287 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 288 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 289 Names[RTLIB::OEQ_F32] = "__eqsf2"; 290 Names[RTLIB::OEQ_F64] = "__eqdf2"; 291 Names[RTLIB::OEQ_F128] = "__eqtf2"; 292 Names[RTLIB::UNE_F32] = "__nesf2"; 293 Names[RTLIB::UNE_F64] = "__nedf2"; 294 Names[RTLIB::UNE_F128] = "__netf2"; 295 Names[RTLIB::OGE_F32] = "__gesf2"; 296 Names[RTLIB::OGE_F64] = "__gedf2"; 297 Names[RTLIB::OGE_F128] = "__getf2"; 298 Names[RTLIB::OLT_F32] = "__ltsf2"; 299 Names[RTLIB::OLT_F64] = "__ltdf2"; 300 Names[RTLIB::OLT_F128] = "__lttf2"; 301 Names[RTLIB::OLE_F32] = "__lesf2"; 302 Names[RTLIB::OLE_F64] = "__ledf2"; 303 Names[RTLIB::OLE_F128] = "__letf2"; 304 Names[RTLIB::OGT_F32] = "__gtsf2"; 305 Names[RTLIB::OGT_F64] = "__gtdf2"; 306 Names[RTLIB::OGT_F128] = "__gttf2"; 307 Names[RTLIB::UO_F32] = "__unordsf2"; 308 Names[RTLIB::UO_F64] = "__unorddf2"; 309 Names[RTLIB::UO_F128] = "__unordtf2"; 310 Names[RTLIB::O_F32] = "__unordsf2"; 311 Names[RTLIB::O_F64] = "__unorddf2"; 312 Names[RTLIB::O_F128] = "__unordtf2"; 313 Names[RTLIB::MEMCPY] = "memcpy"; 314 Names[RTLIB::MEMMOVE] = "memmove"; 315 Names[RTLIB::MEMSET] = "memset"; 316 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 317 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 318 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 319 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 320 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 321 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 322 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 323 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 324 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 325 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 326 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 327 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 328 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 329 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 330 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 331 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 332 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 333 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 334 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 335 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 336 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 337 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 338 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 339 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 340 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 341 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 342 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 343 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 344 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 345 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 346 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 347 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 348 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 349 350 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) { 351 Names[RTLIB::SINCOS_F32] = "sincosf"; 352 Names[RTLIB::SINCOS_F64] = "sincos"; 353 Names[RTLIB::SINCOS_F80] = "sincosl"; 354 Names[RTLIB::SINCOS_F128] = "sincosl"; 355 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 356 } else { 357 // These are generally not available. 358 Names[RTLIB::SINCOS_F32] = 0; 359 Names[RTLIB::SINCOS_F64] = 0; 360 Names[RTLIB::SINCOS_F80] = 0; 361 Names[RTLIB::SINCOS_F128] = 0; 362 Names[RTLIB::SINCOS_PPCF128] = 0; 363 } 364} 365 366/// InitLibcallCallingConvs - Set default libcall CallingConvs. 367/// 368static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 369 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 370 CCs[i] = CallingConv::C; 371 } 372} 373 374/// getFPEXT - Return the FPEXT_*_* value for the given types, or 375/// UNKNOWN_LIBCALL if there is none. 376RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 377 if (OpVT == MVT::f32) { 378 if (RetVT == MVT::f64) 379 return FPEXT_F32_F64; 380 if (RetVT == MVT::f128) 381 return FPEXT_F32_F128; 382 } else if (OpVT == MVT::f64) { 383 if (RetVT == MVT::f128) 384 return FPEXT_F64_F128; 385 } 386 387 return UNKNOWN_LIBCALL; 388} 389 390/// getFPROUND - Return the FPROUND_*_* value for the given types, or 391/// UNKNOWN_LIBCALL if there is none. 392RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 393 if (RetVT == MVT::f32) { 394 if (OpVT == MVT::f64) 395 return FPROUND_F64_F32; 396 if (OpVT == MVT::f80) 397 return FPROUND_F80_F32; 398 if (OpVT == MVT::f128) 399 return FPROUND_F128_F32; 400 if (OpVT == MVT::ppcf128) 401 return FPROUND_PPCF128_F32; 402 } else if (RetVT == MVT::f64) { 403 if (OpVT == MVT::f80) 404 return FPROUND_F80_F64; 405 if (OpVT == MVT::f128) 406 return FPROUND_F128_F64; 407 if (OpVT == MVT::ppcf128) 408 return FPROUND_PPCF128_F64; 409 } 410 411 return UNKNOWN_LIBCALL; 412} 413 414/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 415/// UNKNOWN_LIBCALL if there is none. 416RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 417 if (OpVT == MVT::f32) { 418 if (RetVT == MVT::i8) 419 return FPTOSINT_F32_I8; 420 if (RetVT == MVT::i16) 421 return FPTOSINT_F32_I16; 422 if (RetVT == MVT::i32) 423 return FPTOSINT_F32_I32; 424 if (RetVT == MVT::i64) 425 return FPTOSINT_F32_I64; 426 if (RetVT == MVT::i128) 427 return FPTOSINT_F32_I128; 428 } else if (OpVT == MVT::f64) { 429 if (RetVT == MVT::i8) 430 return FPTOSINT_F64_I8; 431 if (RetVT == MVT::i16) 432 return FPTOSINT_F64_I16; 433 if (RetVT == MVT::i32) 434 return FPTOSINT_F64_I32; 435 if (RetVT == MVT::i64) 436 return FPTOSINT_F64_I64; 437 if (RetVT == MVT::i128) 438 return FPTOSINT_F64_I128; 439 } else if (OpVT == MVT::f80) { 440 if (RetVT == MVT::i32) 441 return FPTOSINT_F80_I32; 442 if (RetVT == MVT::i64) 443 return FPTOSINT_F80_I64; 444 if (RetVT == MVT::i128) 445 return FPTOSINT_F80_I128; 446 } else if (OpVT == MVT::f128) { 447 if (RetVT == MVT::i32) 448 return FPTOSINT_F128_I32; 449 if (RetVT == MVT::i64) 450 return FPTOSINT_F128_I64; 451 if (RetVT == MVT::i128) 452 return FPTOSINT_F128_I128; 453 } else if (OpVT == MVT::ppcf128) { 454 if (RetVT == MVT::i32) 455 return FPTOSINT_PPCF128_I32; 456 if (RetVT == MVT::i64) 457 return FPTOSINT_PPCF128_I64; 458 if (RetVT == MVT::i128) 459 return FPTOSINT_PPCF128_I128; 460 } 461 return UNKNOWN_LIBCALL; 462} 463 464/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 465/// UNKNOWN_LIBCALL if there is none. 466RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 467 if (OpVT == MVT::f32) { 468 if (RetVT == MVT::i8) 469 return FPTOUINT_F32_I8; 470 if (RetVT == MVT::i16) 471 return FPTOUINT_F32_I16; 472 if (RetVT == MVT::i32) 473 return FPTOUINT_F32_I32; 474 if (RetVT == MVT::i64) 475 return FPTOUINT_F32_I64; 476 if (RetVT == MVT::i128) 477 return FPTOUINT_F32_I128; 478 } else if (OpVT == MVT::f64) { 479 if (RetVT == MVT::i8) 480 return FPTOUINT_F64_I8; 481 if (RetVT == MVT::i16) 482 return FPTOUINT_F64_I16; 483 if (RetVT == MVT::i32) 484 return FPTOUINT_F64_I32; 485 if (RetVT == MVT::i64) 486 return FPTOUINT_F64_I64; 487 if (RetVT == MVT::i128) 488 return FPTOUINT_F64_I128; 489 } else if (OpVT == MVT::f80) { 490 if (RetVT == MVT::i32) 491 return FPTOUINT_F80_I32; 492 if (RetVT == MVT::i64) 493 return FPTOUINT_F80_I64; 494 if (RetVT == MVT::i128) 495 return FPTOUINT_F80_I128; 496 } else if (OpVT == MVT::f128) { 497 if (RetVT == MVT::i32) 498 return FPTOUINT_F128_I32; 499 if (RetVT == MVT::i64) 500 return FPTOUINT_F128_I64; 501 if (RetVT == MVT::i128) 502 return FPTOUINT_F128_I128; 503 } else if (OpVT == MVT::ppcf128) { 504 if (RetVT == MVT::i32) 505 return FPTOUINT_PPCF128_I32; 506 if (RetVT == MVT::i64) 507 return FPTOUINT_PPCF128_I64; 508 if (RetVT == MVT::i128) 509 return FPTOUINT_PPCF128_I128; 510 } 511 return UNKNOWN_LIBCALL; 512} 513 514/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 515/// UNKNOWN_LIBCALL if there is none. 516RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 517 if (OpVT == MVT::i32) { 518 if (RetVT == MVT::f32) 519 return SINTTOFP_I32_F32; 520 if (RetVT == MVT::f64) 521 return SINTTOFP_I32_F64; 522 if (RetVT == MVT::f80) 523 return SINTTOFP_I32_F80; 524 if (RetVT == MVT::f128) 525 return SINTTOFP_I32_F128; 526 if (RetVT == MVT::ppcf128) 527 return SINTTOFP_I32_PPCF128; 528 } else if (OpVT == MVT::i64) { 529 if (RetVT == MVT::f32) 530 return SINTTOFP_I64_F32; 531 if (RetVT == MVT::f64) 532 return SINTTOFP_I64_F64; 533 if (RetVT == MVT::f80) 534 return SINTTOFP_I64_F80; 535 if (RetVT == MVT::f128) 536 return SINTTOFP_I64_F128; 537 if (RetVT == MVT::ppcf128) 538 return SINTTOFP_I64_PPCF128; 539 } else if (OpVT == MVT::i128) { 540 if (RetVT == MVT::f32) 541 return SINTTOFP_I128_F32; 542 if (RetVT == MVT::f64) 543 return SINTTOFP_I128_F64; 544 if (RetVT == MVT::f80) 545 return SINTTOFP_I128_F80; 546 if (RetVT == MVT::f128) 547 return SINTTOFP_I128_F128; 548 if (RetVT == MVT::ppcf128) 549 return SINTTOFP_I128_PPCF128; 550 } 551 return UNKNOWN_LIBCALL; 552} 553 554/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 555/// UNKNOWN_LIBCALL if there is none. 556RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 557 if (OpVT == MVT::i32) { 558 if (RetVT == MVT::f32) 559 return UINTTOFP_I32_F32; 560 if (RetVT == MVT::f64) 561 return UINTTOFP_I32_F64; 562 if (RetVT == MVT::f80) 563 return UINTTOFP_I32_F80; 564 if (RetVT == MVT::f128) 565 return UINTTOFP_I32_F128; 566 if (RetVT == MVT::ppcf128) 567 return UINTTOFP_I32_PPCF128; 568 } else if (OpVT == MVT::i64) { 569 if (RetVT == MVT::f32) 570 return UINTTOFP_I64_F32; 571 if (RetVT == MVT::f64) 572 return UINTTOFP_I64_F64; 573 if (RetVT == MVT::f80) 574 return UINTTOFP_I64_F80; 575 if (RetVT == MVT::f128) 576 return UINTTOFP_I64_F128; 577 if (RetVT == MVT::ppcf128) 578 return UINTTOFP_I64_PPCF128; 579 } else if (OpVT == MVT::i128) { 580 if (RetVT == MVT::f32) 581 return UINTTOFP_I128_F32; 582 if (RetVT == MVT::f64) 583 return UINTTOFP_I128_F64; 584 if (RetVT == MVT::f80) 585 return UINTTOFP_I128_F80; 586 if (RetVT == MVT::f128) 587 return UINTTOFP_I128_F128; 588 if (RetVT == MVT::ppcf128) 589 return UINTTOFP_I128_PPCF128; 590 } 591 return UNKNOWN_LIBCALL; 592} 593 594/// InitCmpLibcallCCs - Set default comparison libcall CC. 595/// 596static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 597 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 598 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 599 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 600 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 601 CCs[RTLIB::UNE_F32] = ISD::SETNE; 602 CCs[RTLIB::UNE_F64] = ISD::SETNE; 603 CCs[RTLIB::UNE_F128] = ISD::SETNE; 604 CCs[RTLIB::OGE_F32] = ISD::SETGE; 605 CCs[RTLIB::OGE_F64] = ISD::SETGE; 606 CCs[RTLIB::OGE_F128] = ISD::SETGE; 607 CCs[RTLIB::OLT_F32] = ISD::SETLT; 608 CCs[RTLIB::OLT_F64] = ISD::SETLT; 609 CCs[RTLIB::OLT_F128] = ISD::SETLT; 610 CCs[RTLIB::OLE_F32] = ISD::SETLE; 611 CCs[RTLIB::OLE_F64] = ISD::SETLE; 612 CCs[RTLIB::OLE_F128] = ISD::SETLE; 613 CCs[RTLIB::OGT_F32] = ISD::SETGT; 614 CCs[RTLIB::OGT_F64] = ISD::SETGT; 615 CCs[RTLIB::OGT_F128] = ISD::SETGT; 616 CCs[RTLIB::UO_F32] = ISD::SETNE; 617 CCs[RTLIB::UO_F64] = ISD::SETNE; 618 CCs[RTLIB::UO_F128] = ISD::SETNE; 619 CCs[RTLIB::O_F32] = ISD::SETEQ; 620 CCs[RTLIB::O_F64] = ISD::SETEQ; 621 CCs[RTLIB::O_F128] = ISD::SETEQ; 622} 623 624/// NOTE: The constructor takes ownership of TLOF. 625TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 626 const TargetLoweringObjectFile *tlof) 627 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 628 initActions(); 629 630 // Perform these initializations only once. 631 IsLittleEndian = TD->isLittleEndian(); 632 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0)); 633 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 634 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 635 = MaxStoresPerMemmoveOptSize = 4; 636 UseUnderscoreSetJmp = false; 637 UseUnderscoreLongJmp = false; 638 SelectIsExpensive = false; 639 IntDivIsCheap = false; 640 Pow2DivIsCheap = false; 641 JumpIsExpensive = false; 642 PredictableSelectIsExpensive = false; 643 StackPointerRegisterToSaveRestore = 0; 644 ExceptionPointerRegister = 0; 645 ExceptionSelectorRegister = 0; 646 BooleanContents = UndefinedBooleanContent; 647 BooleanVectorContents = UndefinedBooleanContent; 648 SchedPreferenceInfo = Sched::ILP; 649 JumpBufSize = 0; 650 JumpBufAlignment = 0; 651 MinFunctionAlignment = 0; 652 PrefFunctionAlignment = 0; 653 PrefLoopAlignment = 0; 654 MinStackArgumentAlignment = 1; 655 InsertFencesForAtomic = false; 656 SupportJumpTables = true; 657 MinimumJumpTableEntries = 4; 658 659 InitLibcallNames(LibcallRoutineNames, TM); 660 InitCmpLibcallCCs(CmpLibcallCCs); 661 InitLibcallCallingConvs(LibcallCallingConvs); 662} 663 664TargetLoweringBase::~TargetLoweringBase() { 665 delete &TLOF; 666} 667 668void TargetLoweringBase::initActions() { 669 // All operations default to being supported. 670 memset(OpActions, 0, sizeof(OpActions)); 671 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 672 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 673 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 674 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 675 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 676 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 677 678 // Set default actions for various operations. 679 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 680 // Default all indexed load / store to expand. 681 for (unsigned IM = (unsigned)ISD::PRE_INC; 682 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 683 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 684 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 685 } 686 687 // These operations default to expand. 688 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 690 } 691 692 // Most targets ignore the @llvm.prefetch intrinsic. 693 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 694 695 // ConstantFP nodes default to expand. Targets can either change this to 696 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 697 // to optimize expansions for certain constants. 698 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 699 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 700 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 701 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 702 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 703 704 // These library functions default to expand. 705 setOperationAction(ISD::FLOG , MVT::f16, Expand); 706 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 707 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 708 setOperationAction(ISD::FEXP , MVT::f16, Expand); 709 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 710 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 711 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 712 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 713 setOperationAction(ISD::FRINT, MVT::f16, Expand); 714 setOperationAction(ISD::FROUND, MVT::f16, Expand); 715 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 716 setOperationAction(ISD::FLOG , MVT::f32, Expand); 717 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 718 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 719 setOperationAction(ISD::FEXP , MVT::f32, Expand); 720 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 721 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 722 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 723 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 724 setOperationAction(ISD::FRINT, MVT::f32, Expand); 725 setOperationAction(ISD::FROUND, MVT::f32, Expand); 726 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 727 setOperationAction(ISD::FLOG , MVT::f64, Expand); 728 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 729 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 730 setOperationAction(ISD::FEXP , MVT::f64, Expand); 731 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 732 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 733 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 734 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 735 setOperationAction(ISD::FRINT, MVT::f64, Expand); 736 setOperationAction(ISD::FROUND, MVT::f64, Expand); 737 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 738 setOperationAction(ISD::FLOG , MVT::f128, Expand); 739 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 740 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 741 setOperationAction(ISD::FEXP , MVT::f128, Expand); 742 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 743 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 744 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 745 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 746 setOperationAction(ISD::FRINT, MVT::f128, Expand); 747 setOperationAction(ISD::FROUND, MVT::f128, Expand); 748 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 749 750 // Default ISD::TRAP to expand (which turns it into abort). 751 setOperationAction(ISD::TRAP, MVT::Other, Expand); 752 753 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 754 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 755 // 756 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 757} 758 759MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 760 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 761} 762 763EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 764 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 765 if (LHSTy.isVector()) 766 return LHSTy; 767 return getScalarShiftAmountTy(LHSTy); 768} 769 770/// canOpTrap - Returns true if the operation can trap for the value type. 771/// VT must be a legal type. 772bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 773 assert(isTypeLegal(VT)); 774 switch (Op) { 775 default: 776 return false; 777 case ISD::FDIV: 778 case ISD::FREM: 779 case ISD::SDIV: 780 case ISD::UDIV: 781 case ISD::SREM: 782 case ISD::UREM: 783 return true; 784 } 785} 786 787 788static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 789 unsigned &NumIntermediates, 790 MVT &RegisterVT, 791 TargetLoweringBase *TLI) { 792 // Figure out the right, legal destination reg to copy into. 793 unsigned NumElts = VT.getVectorNumElements(); 794 MVT EltTy = VT.getVectorElementType(); 795 796 unsigned NumVectorRegs = 1; 797 798 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 799 // could break down into LHS/RHS like LegalizeDAG does. 800 if (!isPowerOf2_32(NumElts)) { 801 NumVectorRegs = NumElts; 802 NumElts = 1; 803 } 804 805 // Divide the input until we get to a supported size. This will always 806 // end with a scalar if the target doesn't support vectors. 807 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 808 NumElts >>= 1; 809 NumVectorRegs <<= 1; 810 } 811 812 NumIntermediates = NumVectorRegs; 813 814 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 815 if (!TLI->isTypeLegal(NewVT)) 816 NewVT = EltTy; 817 IntermediateVT = NewVT; 818 819 unsigned NewVTSize = NewVT.getSizeInBits(); 820 821 // Convert sizes such as i33 to i64. 822 if (!isPowerOf2_32(NewVTSize)) 823 NewVTSize = NextPowerOf2(NewVTSize); 824 825 MVT DestVT = TLI->getRegisterType(NewVT); 826 RegisterVT = DestVT; 827 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 828 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 829 830 // Otherwise, promotion or legal types use the same number of registers as 831 // the vector decimated to the appropriate level. 832 return NumVectorRegs; 833} 834 835/// isLegalRC - Return true if the value types that can be represented by the 836/// specified register class are all legal. 837bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 838 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 839 I != E; ++I) { 840 if (isTypeLegal(*I)) 841 return true; 842 } 843 return false; 844} 845 846/// findRepresentativeClass - Return the largest legal super-reg register class 847/// of the register class for the specified type and its associated "cost". 848std::pair<const TargetRegisterClass*, uint8_t> 849TargetLoweringBase::findRepresentativeClass(MVT VT) const { 850 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 851 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 852 if (!RC) 853 return std::make_pair(RC, 0); 854 855 // Compute the set of all super-register classes. 856 BitVector SuperRegRC(TRI->getNumRegClasses()); 857 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 858 SuperRegRC.setBitsInMask(RCI.getMask()); 859 860 // Find the first legal register class with the largest spill size. 861 const TargetRegisterClass *BestRC = RC; 862 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 863 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 864 // We want the largest possible spill size. 865 if (SuperRC->getSize() <= BestRC->getSize()) 866 continue; 867 if (!isLegalRC(SuperRC)) 868 continue; 869 BestRC = SuperRC; 870 } 871 return std::make_pair(BestRC, 1); 872} 873 874/// computeRegisterProperties - Once all of the register classes are added, 875/// this allows us to compute derived properties we expose. 876void TargetLoweringBase::computeRegisterProperties() { 877 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 878 "Too many value types for ValueTypeActions to hold!"); 879 880 // Everything defaults to needing one register. 881 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 882 NumRegistersForVT[i] = 1; 883 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 884 } 885 // ...except isVoid, which doesn't need any registers. 886 NumRegistersForVT[MVT::isVoid] = 0; 887 888 // Find the largest integer register class. 889 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 890 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 891 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 892 893 // Every integer value type larger than this largest register takes twice as 894 // many registers to represent as the previous ValueType. 895 for (unsigned ExpandedReg = LargestIntReg + 1; 896 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 897 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 898 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 899 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 900 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 901 TypeExpandInteger); 902 } 903 904 // Inspect all of the ValueType's smaller than the largest integer 905 // register to see which ones need promotion. 906 unsigned LegalIntReg = LargestIntReg; 907 for (unsigned IntReg = LargestIntReg - 1; 908 IntReg >= (unsigned)MVT::i1; --IntReg) { 909 MVT IVT = (MVT::SimpleValueType)IntReg; 910 if (isTypeLegal(IVT)) { 911 LegalIntReg = IntReg; 912 } else { 913 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 914 (const MVT::SimpleValueType)LegalIntReg; 915 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 916 } 917 } 918 919 // ppcf128 type is really two f64's. 920 if (!isTypeLegal(MVT::ppcf128)) { 921 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 922 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 923 TransformToType[MVT::ppcf128] = MVT::f64; 924 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 925 } 926 927 // Decide how to handle f128. If the target does not have native f128 support, 928 // expand it to i128 and we will be generating soft float library calls. 929 if (!isTypeLegal(MVT::f128)) { 930 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 931 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 932 TransformToType[MVT::f128] = MVT::i128; 933 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 934 } 935 936 // Decide how to handle f64. If the target does not have native f64 support, 937 // expand it to i64 and we will be generating soft float library calls. 938 if (!isTypeLegal(MVT::f64)) { 939 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 940 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 941 TransformToType[MVT::f64] = MVT::i64; 942 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 943 } 944 945 // Decide how to handle f32. If the target does not have native support for 946 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 947 if (!isTypeLegal(MVT::f32)) { 948 if (isTypeLegal(MVT::f64)) { 949 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 950 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 951 TransformToType[MVT::f32] = MVT::f64; 952 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 953 } else { 954 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 955 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 956 TransformToType[MVT::f32] = MVT::i32; 957 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 958 } 959 } 960 961 // Loop over all of the vector value types to see which need transformations. 962 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 963 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 964 MVT VT = (MVT::SimpleValueType)i; 965 if (isTypeLegal(VT)) continue; 966 967 // Determine if there is a legal wider type. If so, we should promote to 968 // that wider vector type. 969 MVT EltVT = VT.getVectorElementType(); 970 unsigned NElts = VT.getVectorNumElements(); 971 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 972 bool IsLegalWiderType = false; 973 // First try to promote the elements of integer vectors. If no legal 974 // promotion was found, fallback to the widen-vector method. 975 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 976 MVT SVT = (MVT::SimpleValueType)nVT; 977 // Promote vectors of integers to vectors with the same number 978 // of elements, with a wider element type. 979 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 980 && SVT.getVectorNumElements() == NElts && 981 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 982 TransformToType[i] = SVT; 983 RegisterTypeForVT[i] = SVT; 984 NumRegistersForVT[i] = 1; 985 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 986 IsLegalWiderType = true; 987 break; 988 } 989 } 990 991 if (IsLegalWiderType) continue; 992 993 // Try to widen the vector. 994 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 995 MVT SVT = (MVT::SimpleValueType)nVT; 996 if (SVT.getVectorElementType() == EltVT && 997 SVT.getVectorNumElements() > NElts && 998 isTypeLegal(SVT)) { 999 TransformToType[i] = SVT; 1000 RegisterTypeForVT[i] = SVT; 1001 NumRegistersForVT[i] = 1; 1002 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1003 IsLegalWiderType = true; 1004 break; 1005 } 1006 } 1007 if (IsLegalWiderType) continue; 1008 } 1009 1010 MVT IntermediateVT; 1011 MVT RegisterVT; 1012 unsigned NumIntermediates; 1013 NumRegistersForVT[i] = 1014 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 1015 RegisterVT, this); 1016 RegisterTypeForVT[i] = RegisterVT; 1017 1018 MVT NVT = VT.getPow2VectorType(); 1019 if (NVT == VT) { 1020 // Type is already a power of 2. The default action is to split. 1021 TransformToType[i] = MVT::Other; 1022 unsigned NumElts = VT.getVectorNumElements(); 1023 ValueTypeActions.setTypeAction(VT, 1024 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 1025 } else { 1026 TransformToType[i] = NVT; 1027 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1028 } 1029 } 1030 1031 // Determine the 'representative' register class for each value type. 1032 // An representative register class is the largest (meaning one which is 1033 // not a sub-register class / subreg register class) legal register class for 1034 // a group of value types. For example, on i386, i8, i16, and i32 1035 // representative would be GR32; while on x86_64 it's GR64. 1036 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1037 const TargetRegisterClass* RRC; 1038 uint8_t Cost; 1039 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1040 RepRegClassForVT[i] = RRC; 1041 RepRegClassCostForVT[i] = Cost; 1042 } 1043} 1044 1045EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1046 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1047 return getPointerTy(0).SimpleTy; 1048} 1049 1050MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1051 return MVT::i32; // return the default value 1052} 1053 1054/// getVectorTypeBreakdown - Vector types are broken down into some number of 1055/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1056/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1057/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1058/// 1059/// This method returns the number of registers needed, and the VT for each 1060/// register. It also returns the VT and quantity of the intermediate values 1061/// before they are promoted/expanded. 1062/// 1063unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1064 EVT &IntermediateVT, 1065 unsigned &NumIntermediates, 1066 MVT &RegisterVT) const { 1067 unsigned NumElts = VT.getVectorNumElements(); 1068 1069 // If there is a wider vector type with the same element type as this one, 1070 // or a promoted vector type that has the same number of elements which 1071 // are wider, then we should convert to that legal vector type. 1072 // This handles things like <2 x float> -> <4 x float> and 1073 // <4 x i1> -> <4 x i32>. 1074 LegalizeTypeAction TA = getTypeAction(Context, VT); 1075 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1076 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1077 if (isTypeLegal(RegisterEVT)) { 1078 IntermediateVT = RegisterEVT; 1079 RegisterVT = RegisterEVT.getSimpleVT(); 1080 NumIntermediates = 1; 1081 return 1; 1082 } 1083 } 1084 1085 // Figure out the right, legal destination reg to copy into. 1086 EVT EltTy = VT.getVectorElementType(); 1087 1088 unsigned NumVectorRegs = 1; 1089 1090 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1091 // could break down into LHS/RHS like LegalizeDAG does. 1092 if (!isPowerOf2_32(NumElts)) { 1093 NumVectorRegs = NumElts; 1094 NumElts = 1; 1095 } 1096 1097 // Divide the input until we get to a supported size. This will always 1098 // end with a scalar if the target doesn't support vectors. 1099 while (NumElts > 1 && !isTypeLegal( 1100 EVT::getVectorVT(Context, EltTy, NumElts))) { 1101 NumElts >>= 1; 1102 NumVectorRegs <<= 1; 1103 } 1104 1105 NumIntermediates = NumVectorRegs; 1106 1107 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1108 if (!isTypeLegal(NewVT)) 1109 NewVT = EltTy; 1110 IntermediateVT = NewVT; 1111 1112 MVT DestVT = getRegisterType(Context, NewVT); 1113 RegisterVT = DestVT; 1114 unsigned NewVTSize = NewVT.getSizeInBits(); 1115 1116 // Convert sizes such as i33 to i64. 1117 if (!isPowerOf2_32(NewVTSize)) 1118 NewVTSize = NextPowerOf2(NewVTSize); 1119 1120 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1121 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1122 1123 // Otherwise, promotion or legal types use the same number of registers as 1124 // the vector decimated to the appropriate level. 1125 return NumVectorRegs; 1126} 1127 1128/// Get the EVTs and ArgFlags collections that represent the legalized return 1129/// type of the given function. This does not require a DAG or a return value, 1130/// and is suitable for use before any DAGs for the function are constructed. 1131/// TODO: Move this out of TargetLowering.cpp. 1132void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1133 SmallVectorImpl<ISD::OutputArg> &Outs, 1134 const TargetLowering &TLI) { 1135 SmallVector<EVT, 4> ValueVTs; 1136 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1137 unsigned NumValues = ValueVTs.size(); 1138 if (NumValues == 0) return; 1139 1140 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1141 EVT VT = ValueVTs[j]; 1142 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1143 1144 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1145 ExtendKind = ISD::SIGN_EXTEND; 1146 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1147 ExtendKind = ISD::ZERO_EXTEND; 1148 1149 // FIXME: C calling convention requires the return type to be promoted to 1150 // at least 32-bit. But this is not necessary for non-C calling 1151 // conventions. The frontend should mark functions whose return values 1152 // require promoting with signext or zeroext attributes. 1153 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1154 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1155 if (VT.bitsLT(MinVT)) 1156 VT = MinVT; 1157 } 1158 1159 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1160 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1161 1162 // 'inreg' on function refers to return value 1163 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1164 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1165 Flags.setInReg(); 1166 1167 // Propagate extension type if any 1168 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1169 Flags.setSExt(); 1170 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1171 Flags.setZExt(); 1172 1173 for (unsigned i = 0; i < NumParts; ++i) 1174 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1175 } 1176} 1177 1178/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1179/// function arguments in the caller parameter area. This is the actual 1180/// alignment, not its logarithm. 1181unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1182 return TD->getCallFrameTypeAlignment(Ty); 1183} 1184 1185//===----------------------------------------------------------------------===// 1186// TargetTransformInfo Helpers 1187//===----------------------------------------------------------------------===// 1188 1189int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1190 enum InstructionOpcodes { 1191#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1192#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1193#include "llvm/IR/Instruction.def" 1194 }; 1195 switch (static_cast<InstructionOpcodes>(Opcode)) { 1196 case Ret: return 0; 1197 case Br: return 0; 1198 case Switch: return 0; 1199 case IndirectBr: return 0; 1200 case Invoke: return 0; 1201 case Resume: return 0; 1202 case Unreachable: return 0; 1203 case Add: return ISD::ADD; 1204 case FAdd: return ISD::FADD; 1205 case Sub: return ISD::SUB; 1206 case FSub: return ISD::FSUB; 1207 case Mul: return ISD::MUL; 1208 case FMul: return ISD::FMUL; 1209 case UDiv: return ISD::UDIV; 1210 case SDiv: return ISD::UDIV; 1211 case FDiv: return ISD::FDIV; 1212 case URem: return ISD::UREM; 1213 case SRem: return ISD::SREM; 1214 case FRem: return ISD::FREM; 1215 case Shl: return ISD::SHL; 1216 case LShr: return ISD::SRL; 1217 case AShr: return ISD::SRA; 1218 case And: return ISD::AND; 1219 case Or: return ISD::OR; 1220 case Xor: return ISD::XOR; 1221 case Alloca: return 0; 1222 case Load: return ISD::LOAD; 1223 case Store: return ISD::STORE; 1224 case GetElementPtr: return 0; 1225 case Fence: return 0; 1226 case AtomicCmpXchg: return 0; 1227 case AtomicRMW: return 0; 1228 case Trunc: return ISD::TRUNCATE; 1229 case ZExt: return ISD::ZERO_EXTEND; 1230 case SExt: return ISD::SIGN_EXTEND; 1231 case FPToUI: return ISD::FP_TO_UINT; 1232 case FPToSI: return ISD::FP_TO_SINT; 1233 case UIToFP: return ISD::UINT_TO_FP; 1234 case SIToFP: return ISD::SINT_TO_FP; 1235 case FPTrunc: return ISD::FP_ROUND; 1236 case FPExt: return ISD::FP_EXTEND; 1237 case PtrToInt: return ISD::BITCAST; 1238 case IntToPtr: return ISD::BITCAST; 1239 case BitCast: return ISD::BITCAST; 1240 case ICmp: return ISD::SETCC; 1241 case FCmp: return ISD::SETCC; 1242 case PHI: return 0; 1243 case Call: return 0; 1244 case Select: return ISD::SELECT; 1245 case UserOp1: return 0; 1246 case UserOp2: return 0; 1247 case VAArg: return 0; 1248 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1249 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1250 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1251 case ExtractValue: return ISD::MERGE_VALUES; 1252 case InsertValue: return ISD::MERGE_VALUES; 1253 case LandingPad: return 0; 1254 } 1255 1256 llvm_unreachable("Unknown instruction type encountered!"); 1257} 1258 1259std::pair<unsigned, MVT> 1260TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1261 LLVMContext &C = Ty->getContext(); 1262 EVT MTy = getValueType(Ty); 1263 1264 unsigned Cost = 1; 1265 // We keep legalizing the type until we find a legal kind. We assume that 1266 // the only operation that costs anything is the split. After splitting 1267 // we need to handle two types. 1268 while (true) { 1269 LegalizeKind LK = getTypeConversion(C, MTy); 1270 1271 if (LK.first == TypeLegal) 1272 return std::make_pair(Cost, MTy.getSimpleVT()); 1273 1274 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1275 Cost *= 2; 1276 1277 // Keep legalizing the type. 1278 MTy = LK.second; 1279 } 1280} 1281 1282//===----------------------------------------------------------------------===// 1283// Loop Strength Reduction hooks 1284//===----------------------------------------------------------------------===// 1285 1286/// isLegalAddressingMode - Return true if the addressing mode represented 1287/// by AM is legal for this target, for a load/store of the specified type. 1288bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1289 Type *Ty) const { 1290 // The default implementation of this implements a conservative RISCy, r+r and 1291 // r+i addr mode. 1292 1293 // Allows a sign-extended 16-bit immediate field. 1294 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1295 return false; 1296 1297 // No global is ever allowed as a base. 1298 if (AM.BaseGV) 1299 return false; 1300 1301 // Only support r+r, 1302 switch (AM.Scale) { 1303 case 0: // "r+i" or just "i", depending on HasBaseReg. 1304 break; 1305 case 1: 1306 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1307 return false; 1308 // Otherwise we have r+r or r+i. 1309 break; 1310 case 2: 1311 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1312 return false; 1313 // Allow 2*r as r+r. 1314 break; 1315 } 1316 1317 return true; 1318} 1319