TwoAddressInstructionPass.cpp revision 2a4410df44cd710e20b3f12873c35405830d66fb
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/Analysis/AliasAnalysis.h" 39#include "llvm/MC/MCInstrItineraries.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Support/ErrorHandling.h" 46#include "llvm/ADT/BitVector.h" 47#include "llvm/ADT/DenseMap.h" 48#include "llvm/ADT/SmallSet.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/ADT/STLExtras.h" 51using namespace llvm; 52 53STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 54STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 55STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 56STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 57STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 58STATISTIC(NumReMats, "Number of instructions re-materialized"); 59STATISTIC(NumDeletes, "Number of dead instructions deleted"); 60STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up"); 61STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down"); 62 63namespace { 64 class TwoAddressInstructionPass : public MachineFunctionPass { 65 const TargetInstrInfo *TII; 66 const TargetRegisterInfo *TRI; 67 const InstrItineraryData *InstrItins; 68 MachineRegisterInfo *MRI; 69 LiveVariables *LV; 70 AliasAnalysis *AA; 71 72 // DistanceMap - Keep track the distance of a MI from the start of the 73 // current basic block. 74 DenseMap<MachineInstr*, unsigned> DistanceMap; 75 76 // SrcRegMap - A map from virtual registers to physical registers which 77 // are likely targets to be coalesced to due to copies from physical 78 // registers to virtual registers. e.g. v1024 = move r0. 79 DenseMap<unsigned, unsigned> SrcRegMap; 80 81 // DstRegMap - A map from virtual registers to physical registers which 82 // are likely targets to be coalesced to due to copies to physical 83 // registers from virtual registers. e.g. r1 = move v1024. 84 DenseMap<unsigned, unsigned> DstRegMap; 85 86 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen 87 /// during the initial walk of the machine function. 88 SmallVector<MachineInstr*, 16> RegSequences; 89 90 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 91 unsigned Reg, 92 MachineBasicBlock::iterator OldPos); 93 94 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 95 MachineInstr *MI, MachineInstr *DefMI, 96 MachineBasicBlock *MBB, unsigned Loc); 97 98 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 99 unsigned &LastDef); 100 101 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 102 unsigned Dist); 103 104 bool isProfitableToCommute(unsigned regB, unsigned regC, 105 MachineInstr *MI, MachineBasicBlock *MBB, 106 unsigned Dist); 107 108 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 109 MachineFunction::iterator &mbbi, 110 unsigned RegB, unsigned RegC, unsigned Dist); 111 112 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB); 113 114 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 115 MachineBasicBlock::iterator &nmi, 116 MachineFunction::iterator &mbbi, 117 unsigned RegA, unsigned RegB, unsigned Dist); 118 119 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill; 120 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 121 SmallVector<NewKill, 4> &NewKills, 122 MachineBasicBlock *MBB, unsigned Dist); 123 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 124 MachineBasicBlock::iterator &nmi, 125 MachineFunction::iterator &mbbi, unsigned Dist); 126 127 bool isDefTooClose(unsigned Reg, unsigned Dist, 128 MachineInstr *MI, MachineBasicBlock *MBB); 129 130 bool RescheduleMIBelowKill(MachineBasicBlock *MBB, 131 MachineBasicBlock::iterator &mi, 132 MachineBasicBlock::iterator &nmi, 133 unsigned Reg); 134 bool RescheduleKillAboveMI(MachineBasicBlock *MBB, 135 MachineBasicBlock::iterator &mi, 136 MachineBasicBlock::iterator &nmi, 137 unsigned Reg); 138 139 bool TryInstructionTransform(MachineBasicBlock::iterator &mi, 140 MachineBasicBlock::iterator &nmi, 141 MachineFunction::iterator &mbbi, 142 unsigned SrcIdx, unsigned DstIdx, 143 unsigned Dist, 144 SmallPtrSet<MachineInstr*, 8> &Processed); 145 146 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 147 SmallPtrSet<MachineInstr*, 8> &Processed); 148 149 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 150 SmallPtrSet<MachineInstr*, 8> &Processed); 151 152 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg); 153 154 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 155 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as 156 /// sub-register references of the register defined by REG_SEQUENCE. 157 bool EliminateRegSequences(); 158 159 public: 160 static char ID; // Pass identification, replacement for typeid 161 TwoAddressInstructionPass() : MachineFunctionPass(ID) { 162 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 163 } 164 165 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 166 AU.setPreservesCFG(); 167 AU.addRequired<AliasAnalysis>(); 168 AU.addPreserved<LiveVariables>(); 169 AU.addPreservedID(MachineLoopInfoID); 170 AU.addPreservedID(MachineDominatorsID); 171 AU.addPreservedID(PHIEliminationID); 172 MachineFunctionPass::getAnalysisUsage(AU); 173 } 174 175 /// runOnMachineFunction - Pass entry point. 176 bool runOnMachineFunction(MachineFunction&); 177 }; 178} 179 180char TwoAddressInstructionPass::ID = 0; 181INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction", 182 "Two-Address instruction pass", false, false) 183INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 184INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction", 185 "Two-Address instruction pass", false, false) 186 187char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID; 188 189/// Sink3AddrInstruction - A two-address instruction has been converted to a 190/// three-address instruction to avoid clobbering a register. Try to sink it 191/// past the instruction that would kill the above mentioned register to reduce 192/// register pressure. 193bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 194 MachineInstr *MI, unsigned SavedReg, 195 MachineBasicBlock::iterator OldPos) { 196 // FIXME: Shouldn't we be trying to do this before we three-addressify the 197 // instruction? After this transformation is done, we no longer need 198 // the instruction to be in three-address form. 199 200 // Check if it's safe to move this instruction. 201 bool SeenStore = true; // Be conservative. 202 if (!MI->isSafeToMove(TII, AA, SeenStore)) 203 return false; 204 205 unsigned DefReg = 0; 206 SmallSet<unsigned, 4> UseRegs; 207 208 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 209 const MachineOperand &MO = MI->getOperand(i); 210 if (!MO.isReg()) 211 continue; 212 unsigned MOReg = MO.getReg(); 213 if (!MOReg) 214 continue; 215 if (MO.isUse() && MOReg != SavedReg) 216 UseRegs.insert(MO.getReg()); 217 if (!MO.isDef()) 218 continue; 219 if (MO.isImplicit()) 220 // Don't try to move it if it implicitly defines a register. 221 return false; 222 if (DefReg) 223 // For now, don't move any instructions that define multiple registers. 224 return false; 225 DefReg = MO.getReg(); 226 } 227 228 // Find the instruction that kills SavedReg. 229 MachineInstr *KillMI = NULL; 230 for (MachineRegisterInfo::use_nodbg_iterator 231 UI = MRI->use_nodbg_begin(SavedReg), 232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 233 MachineOperand &UseMO = UI.getOperand(); 234 if (!UseMO.isKill()) 235 continue; 236 KillMI = UseMO.getParent(); 237 break; 238 } 239 240 // If we find the instruction that kills SavedReg, and it is in an 241 // appropriate location, we can try to sink the current instruction 242 // past it. 243 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || 244 KillMI->getDesc().isTerminator()) 245 return false; 246 247 // If any of the definitions are used by another instruction between the 248 // position and the kill use, then it's not safe to sink it. 249 // 250 // FIXME: This can be sped up if there is an easy way to query whether an 251 // instruction is before or after another instruction. Then we can use 252 // MachineRegisterInfo def / use instead. 253 MachineOperand *KillMO = NULL; 254 MachineBasicBlock::iterator KillPos = KillMI; 255 ++KillPos; 256 257 unsigned NumVisited = 0; 258 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) { 259 MachineInstr *OtherMI = I; 260 // DBG_VALUE cannot be counted against the limit. 261 if (OtherMI->isDebugValue()) 262 continue; 263 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 264 return false; 265 ++NumVisited; 266 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 267 MachineOperand &MO = OtherMI->getOperand(i); 268 if (!MO.isReg()) 269 continue; 270 unsigned MOReg = MO.getReg(); 271 if (!MOReg) 272 continue; 273 if (DefReg == MOReg) 274 return false; 275 276 if (MO.isKill()) { 277 if (OtherMI == KillMI && MOReg == SavedReg) 278 // Save the operand that kills the register. We want to unset the kill 279 // marker if we can sink MI past it. 280 KillMO = &MO; 281 else if (UseRegs.count(MOReg)) 282 // One of the uses is killed before the destination. 283 return false; 284 } 285 } 286 } 287 288 // Update kill and LV information. 289 KillMO->setIsKill(false); 290 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 291 KillMO->setIsKill(true); 292 293 if (LV) 294 LV->replaceKillInstruction(SavedReg, KillMI, MI); 295 296 // Move instruction to its destination. 297 MBB->remove(MI); 298 MBB->insert(KillPos, MI); 299 300 ++Num3AddrSunk; 301 return true; 302} 303 304/// isTwoAddrUse - Return true if the specified MI is using the specified 305/// register as a two-address operand. 306static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 307 const MCInstrDesc &MCID = UseMI->getDesc(); 308 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 309 MachineOperand &MO = UseMI->getOperand(i); 310 if (MO.isReg() && MO.getReg() == Reg && 311 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 312 // Earlier use is a two-address one. 313 return true; 314 } 315 return false; 316} 317 318/// isProfitableToReMat - Return true if the heuristics determines it is likely 319/// to be profitable to re-materialize the definition of Reg rather than copy 320/// the register. 321bool 322TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 323 const TargetRegisterClass *RC, 324 MachineInstr *MI, MachineInstr *DefMI, 325 MachineBasicBlock *MBB, unsigned Loc) { 326 bool OtherUse = false; 327 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg), 328 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 329 MachineOperand &UseMO = UI.getOperand(); 330 MachineInstr *UseMI = UseMO.getParent(); 331 MachineBasicBlock *UseMBB = UseMI->getParent(); 332 if (UseMBB == MBB) { 333 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 334 if (DI != DistanceMap.end() && DI->second == Loc) 335 continue; // Current use. 336 OtherUse = true; 337 // There is at least one other use in the MBB that will clobber the 338 // register. 339 if (isTwoAddrUse(UseMI, Reg)) 340 return true; 341 } 342 } 343 344 // If other uses in MBB are not two-address uses, then don't remat. 345 if (OtherUse) 346 return false; 347 348 // No other uses in the same block, remat if it's defined in the same 349 // block so it does not unnecessarily extend the live range. 350 return MBB == DefMI->getParent(); 351} 352 353/// NoUseAfterLastDef - Return true if there are no intervening uses between the 354/// last instruction in the MBB that defines the specified register and the 355/// two-address instruction which is being processed. It also returns the last 356/// def location by reference 357bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 358 MachineBasicBlock *MBB, unsigned Dist, 359 unsigned &LastDef) { 360 LastDef = 0; 361 unsigned LastUse = Dist; 362 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 363 E = MRI->reg_end(); I != E; ++I) { 364 MachineOperand &MO = I.getOperand(); 365 MachineInstr *MI = MO.getParent(); 366 if (MI->getParent() != MBB || MI->isDebugValue()) 367 continue; 368 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 369 if (DI == DistanceMap.end()) 370 continue; 371 if (MO.isUse() && DI->second < LastUse) 372 LastUse = DI->second; 373 if (MO.isDef() && DI->second > LastDef) 374 LastDef = DI->second; 375 } 376 377 return !(LastUse > LastDef && LastUse < Dist); 378} 379 380MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 381 MachineBasicBlock *MBB, 382 unsigned Dist) { 383 unsigned LastUseDist = 0; 384 MachineInstr *LastUse = 0; 385 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 386 E = MRI->reg_end(); I != E; ++I) { 387 MachineOperand &MO = I.getOperand(); 388 MachineInstr *MI = MO.getParent(); 389 if (MI->getParent() != MBB || MI->isDebugValue()) 390 continue; 391 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 392 if (DI == DistanceMap.end()) 393 continue; 394 if (DI->second >= Dist) 395 continue; 396 397 if (MO.isUse() && DI->second > LastUseDist) { 398 LastUse = DI->first; 399 LastUseDist = DI->second; 400 } 401 } 402 return LastUse; 403} 404 405/// isCopyToReg - Return true if the specified MI is a copy instruction or 406/// a extract_subreg instruction. It also returns the source and destination 407/// registers and whether they are physical registers by reference. 408static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 409 unsigned &SrcReg, unsigned &DstReg, 410 bool &IsSrcPhys, bool &IsDstPhys) { 411 SrcReg = 0; 412 DstReg = 0; 413 if (MI.isCopy()) { 414 DstReg = MI.getOperand(0).getReg(); 415 SrcReg = MI.getOperand(1).getReg(); 416 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { 417 DstReg = MI.getOperand(0).getReg(); 418 SrcReg = MI.getOperand(2).getReg(); 419 } else 420 return false; 421 422 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 424 return true; 425} 426 427/// isKilled - Test if the given register value, which is used by the given 428/// instruction, is killed by the given instruction. This looks through 429/// coalescable copies to see if the original value is potentially not killed. 430/// 431/// For example, in this code: 432/// 433/// %reg1034 = copy %reg1024 434/// %reg1035 = copy %reg1025<kill> 435/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 436/// 437/// %reg1034 is not considered to be killed, since it is copied from a 438/// register which is not killed. Treating it as not killed lets the 439/// normal heuristics commute the (two-address) add, which lets 440/// coalescing eliminate the extra copy. 441/// 442static bool isKilled(MachineInstr &MI, unsigned Reg, 443 const MachineRegisterInfo *MRI, 444 const TargetInstrInfo *TII) { 445 MachineInstr *DefMI = &MI; 446 for (;;) { 447 if (!DefMI->killsRegister(Reg)) 448 return false; 449 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 450 return true; 451 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 452 // If there are multiple defs, we can't do a simple analysis, so just 453 // go with what the kill flag says. 454 if (llvm::next(Begin) != MRI->def_end()) 455 return true; 456 DefMI = &*Begin; 457 bool IsSrcPhys, IsDstPhys; 458 unsigned SrcReg, DstReg; 459 // If the def is something other than a copy, then it isn't going to 460 // be coalesced, so follow the kill flag. 461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 462 return true; 463 Reg = SrcReg; 464 } 465} 466 467/// isTwoAddrUse - Return true if the specified MI uses the specified register 468/// as a two-address use. If so, return the destination register by reference. 469static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 470 const MCInstrDesc &MCID = MI.getDesc(); 471 unsigned NumOps = MI.isInlineAsm() 472 ? MI.getNumOperands() : MCID.getNumOperands(); 473 for (unsigned i = 0; i != NumOps; ++i) { 474 const MachineOperand &MO = MI.getOperand(i); 475 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 476 continue; 477 unsigned ti; 478 if (MI.isRegTiedToDefOperand(i, &ti)) { 479 DstReg = MI.getOperand(ti).getReg(); 480 return true; 481 } 482 } 483 return false; 484} 485 486/// findLocalKill - Look for an instruction below MI in the MBB that kills the 487/// specified register. Returns null if there are any other Reg use between the 488/// instructions. 489static 490MachineInstr *findLocalKill(unsigned Reg, MachineBasicBlock *MBB, 491 MachineInstr *MI, MachineRegisterInfo *MRI, 492 DenseMap<MachineInstr*, unsigned> &DistanceMap) { 493 MachineInstr *KillMI = 0; 494 for (MachineRegisterInfo::use_nodbg_iterator 495 UI = MRI->use_nodbg_begin(Reg), 496 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 497 MachineInstr *UseMI = &*UI; 498 if (UseMI == MI || UseMI->getParent() != MBB) 499 continue; 500 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 501 if (DI != DistanceMap.end()) 502 continue; 503 if (!UI.getOperand().isKill()) 504 return 0; 505 assert(!KillMI && "More than one local kills?"); 506 KillMI = UseMI; 507 } 508 509 return KillMI; 510} 511 512/// findOnlyInterestingUse - Given a register, if has a single in-basic block 513/// use, return the use instruction if it's a copy or a two-address use. 514static 515MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 516 MachineRegisterInfo *MRI, 517 const TargetInstrInfo *TII, 518 bool &IsCopy, 519 unsigned &DstReg, bool &IsDstPhys) { 520 if (!MRI->hasOneNonDBGUse(Reg)) 521 // None or more than one use. 522 return 0; 523 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); 524 if (UseMI.getParent() != MBB) 525 return 0; 526 unsigned SrcReg; 527 bool IsSrcPhys; 528 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 529 IsCopy = true; 530 return &UseMI; 531 } 532 IsDstPhys = false; 533 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 534 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 535 return &UseMI; 536 } 537 return 0; 538} 539 540/// getMappedReg - Return the physical register the specified virtual register 541/// might be mapped to. 542static unsigned 543getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 544 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 545 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 546 if (SI == RegMap.end()) 547 return 0; 548 Reg = SI->second; 549 } 550 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 551 return Reg; 552 return 0; 553} 554 555/// regsAreCompatible - Return true if the two registers are equal or aliased. 556/// 557static bool 558regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 559 if (RegA == RegB) 560 return true; 561 if (!RegA || !RegB) 562 return false; 563 return TRI->regsOverlap(RegA, RegB); 564} 565 566 567/// isProfitableToReMat - Return true if it's potentially profitable to commute 568/// the two-address instruction that's being processed. 569bool 570TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 571 MachineInstr *MI, MachineBasicBlock *MBB, 572 unsigned Dist) { 573 // Determine if it's profitable to commute this two address instruction. In 574 // general, we want no uses between this instruction and the definition of 575 // the two-address register. 576 // e.g. 577 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 578 // %reg1029<def> = MOV8rr %reg1028 579 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 580 // insert => %reg1030<def> = MOV8rr %reg1028 581 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 582 // In this case, it might not be possible to coalesce the second MOV8rr 583 // instruction if the first one is coalesced. So it would be profitable to 584 // commute it: 585 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 586 // %reg1029<def> = MOV8rr %reg1028 587 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 588 // insert => %reg1030<def> = MOV8rr %reg1029 589 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 590 591 if (!MI->killsRegister(regC)) 592 return false; 593 594 // Ok, we have something like: 595 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 596 // let's see if it's worth commuting it. 597 598 // Look for situations like this: 599 // %reg1024<def> = MOV r1 600 // %reg1025<def> = MOV r0 601 // %reg1026<def> = ADD %reg1024, %reg1025 602 // r0 = MOV %reg1026 603 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 604 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 605 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 606 unsigned ToRegB = getMappedReg(regB, DstRegMap); 607 unsigned ToRegC = getMappedReg(regC, DstRegMap); 608 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && 609 ((!FromRegC && !ToRegC) || 610 regsAreCompatible(FromRegB, ToRegC, TRI) || 611 regsAreCompatible(FromRegC, ToRegB, TRI))) 612 return true; 613 614 // If there is a use of regC between its last def (could be livein) and this 615 // instruction, then bail. 616 unsigned LastDefC = 0; 617 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 618 return false; 619 620 // If there is a use of regB between its last def (could be livein) and this 621 // instruction, then go ahead and make this transformation. 622 unsigned LastDefB = 0; 623 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 624 return true; 625 626 // Since there are no intervening uses for both registers, then commute 627 // if the def of regC is closer. Its live interval is shorter. 628 return LastDefB && LastDefC && LastDefC > LastDefB; 629} 630 631/// CommuteInstruction - Commute a two-address instruction and update the basic 632/// block, distance map, and live variables if needed. Return true if it is 633/// successful. 634bool 635TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 636 MachineFunction::iterator &mbbi, 637 unsigned RegB, unsigned RegC, unsigned Dist) { 638 MachineInstr *MI = mi; 639 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 640 MachineInstr *NewMI = TII->commuteInstruction(MI); 641 642 if (NewMI == 0) { 643 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 644 return false; 645 } 646 647 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 648 // If the instruction changed to commute it, update livevar. 649 if (NewMI != MI) { 650 if (LV) 651 // Update live variables 652 LV->replaceKillInstruction(RegC, MI, NewMI); 653 654 mbbi->insert(mi, NewMI); // Insert the new inst 655 mbbi->erase(mi); // Nuke the old inst. 656 mi = NewMI; 657 DistanceMap.insert(std::make_pair(NewMI, Dist)); 658 } 659 660 // Update source register map. 661 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 662 if (FromRegC) { 663 unsigned RegA = MI->getOperand(0).getReg(); 664 SrcRegMap[RegA] = FromRegC; 665 } 666 667 return true; 668} 669 670/// isProfitableToConv3Addr - Return true if it is profitable to convert the 671/// given 2-address instruction to a 3-address one. 672bool 673TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ 674 // Look for situations like this: 675 // %reg1024<def> = MOV r1 676 // %reg1025<def> = MOV r0 677 // %reg1026<def> = ADD %reg1024, %reg1025 678 // r2 = MOV %reg1026 679 // Turn ADD into a 3-address instruction to avoid a copy. 680 unsigned FromRegB = getMappedReg(RegB, SrcRegMap); 681 if (!FromRegB) 682 return false; 683 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 684 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 685} 686 687/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 688/// three address one. Return true if this transformation was successful. 689bool 690TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 691 MachineBasicBlock::iterator &nmi, 692 MachineFunction::iterator &mbbi, 693 unsigned RegA, unsigned RegB, 694 unsigned Dist) { 695 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 696 if (NewMI) { 697 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 698 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 699 bool Sunk = false; 700 701 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 702 // FIXME: Temporary workaround. If the new instruction doesn't 703 // uses RegB, convertToThreeAddress must have created more 704 // then one instruction. 705 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 706 707 mbbi->erase(mi); // Nuke the old inst. 708 709 if (!Sunk) { 710 DistanceMap.insert(std::make_pair(NewMI, Dist)); 711 mi = NewMI; 712 nmi = llvm::next(mi); 713 } 714 715 // Update source and destination register maps. 716 SrcRegMap.erase(RegA); 717 DstRegMap.erase(RegB); 718 return true; 719 } 720 721 return false; 722} 723 724/// ScanUses - Scan forward recursively for only uses, update maps if the use 725/// is a copy or a two-address instruction. 726void 727TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 728 SmallPtrSet<MachineInstr*, 8> &Processed) { 729 SmallVector<unsigned, 4> VirtRegPairs; 730 bool IsDstPhys; 731 bool IsCopy = false; 732 unsigned NewReg = 0; 733 unsigned Reg = DstReg; 734 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, 735 NewReg, IsDstPhys)) { 736 if (IsCopy && !Processed.insert(UseMI)) 737 break; 738 739 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 740 if (DI != DistanceMap.end()) 741 // Earlier in the same MBB.Reached via a back edge. 742 break; 743 744 if (IsDstPhys) { 745 VirtRegPairs.push_back(NewReg); 746 break; 747 } 748 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 749 if (!isNew) 750 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 751 VirtRegPairs.push_back(NewReg); 752 Reg = NewReg; 753 } 754 755 if (!VirtRegPairs.empty()) { 756 unsigned ToReg = VirtRegPairs.back(); 757 VirtRegPairs.pop_back(); 758 while (!VirtRegPairs.empty()) { 759 unsigned FromReg = VirtRegPairs.back(); 760 VirtRegPairs.pop_back(); 761 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 762 if (!isNew) 763 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!"); 764 ToReg = FromReg; 765 } 766 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second; 767 if (!isNew) 768 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!"); 769 } 770} 771 772/// ProcessCopy - If the specified instruction is not yet processed, process it 773/// if it's a copy. For a copy instruction, we find the physical registers the 774/// source and destination registers might be mapped to. These are kept in 775/// point-to maps used to determine future optimizations. e.g. 776/// v1024 = mov r0 777/// v1025 = mov r1 778/// v1026 = add v1024, v1025 779/// r1 = mov r1026 780/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 781/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 782/// potentially joined with r1 on the output side. It's worthwhile to commute 783/// 'add' to eliminate a copy. 784void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 785 MachineBasicBlock *MBB, 786 SmallPtrSet<MachineInstr*, 8> &Processed) { 787 if (Processed.count(MI)) 788 return; 789 790 bool IsSrcPhys, IsDstPhys; 791 unsigned SrcReg, DstReg; 792 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 793 return; 794 795 if (IsDstPhys && !IsSrcPhys) 796 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 797 else if (!IsDstPhys && IsSrcPhys) { 798 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 799 if (!isNew) 800 assert(SrcRegMap[DstReg] == SrcReg && 801 "Can't map to two src physical registers!"); 802 803 ScanUses(DstReg, MBB, Processed); 804 } 805 806 Processed.insert(MI); 807 return; 808} 809 810/// isSafeToDelete - If the specified instruction does not produce any side 811/// effects and all of its defs are dead, then it's safe to delete. 812static bool isSafeToDelete(MachineInstr *MI, 813 const TargetInstrInfo *TII, 814 SmallVector<unsigned, 4> &Kills) { 815 const MCInstrDesc &MCID = MI->getDesc(); 816 if (MCID.mayStore() || MCID.isCall()) 817 return false; 818 if (MCID.isTerminator() || MI->hasUnmodeledSideEffects()) 819 return false; 820 821 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 822 MachineOperand &MO = MI->getOperand(i); 823 if (!MO.isReg()) 824 continue; 825 if (MO.isDef() && !MO.isDead()) 826 return false; 827 if (MO.isUse() && MO.isKill()) 828 Kills.push_back(MO.getReg()); 829 } 830 return true; 831} 832 833/// canUpdateDeletedKills - Check if all the registers listed in Kills are 834/// killed by instructions in MBB preceding the current instruction at 835/// position Dist. If so, return true and record information about the 836/// preceding kills in NewKills. 837bool TwoAddressInstructionPass:: 838canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 839 SmallVector<NewKill, 4> &NewKills, 840 MachineBasicBlock *MBB, unsigned Dist) { 841 while (!Kills.empty()) { 842 unsigned Kill = Kills.back(); 843 Kills.pop_back(); 844 if (TargetRegisterInfo::isPhysicalRegister(Kill)) 845 return false; 846 847 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist); 848 if (!LastKill) 849 return false; 850 851 bool isModRef = LastKill->definesRegister(Kill); 852 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef), 853 LastKill)); 854 } 855 return true; 856} 857 858/// DeleteUnusedInstr - If an instruction with a tied register operand can 859/// be safely deleted, just delete it. 860bool 861TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 862 MachineBasicBlock::iterator &nmi, 863 MachineFunction::iterator &mbbi, 864 unsigned Dist) { 865 // Check if the instruction has no side effects and if all its defs are dead. 866 SmallVector<unsigned, 4> Kills; 867 if (!isSafeToDelete(mi, TII, Kills)) 868 return false; 869 870 // If this instruction kills some virtual registers, we need to 871 // update the kill information. If it's not possible to do so, 872 // then bail out. 873 SmallVector<NewKill, 4> NewKills; 874 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist)) 875 return false; 876 877 if (LV) { 878 while (!NewKills.empty()) { 879 MachineInstr *NewKill = NewKills.back().second; 880 unsigned Kill = NewKills.back().first.first; 881 bool isDead = NewKills.back().first.second; 882 NewKills.pop_back(); 883 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 884 if (isDead) 885 LV->addVirtualRegisterDead(Kill, NewKill); 886 else 887 LV->addVirtualRegisterKilled(Kill, NewKill); 888 } 889 } 890 } 891 892 mbbi->erase(mi); // Nuke the old inst. 893 mi = nmi; 894 return true; 895} 896 897/// RescheduleMIBelowKill - If there is one more local instruction that reads 898/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill 899/// instruction in order to eliminate the need for the copy. 900bool 901TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB, 902 MachineBasicBlock::iterator &mi, 903 MachineBasicBlock::iterator &nmi, 904 unsigned Reg) { 905 MachineInstr *MI = &*mi; 906 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 907 if (DI == DistanceMap.end()) 908 // Must be created from unfolded load. Don't waste time trying this. 909 return false; 910 911 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap); 912 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 913 // Don't mess with copies, they may be coalesced later. 914 return false; 915 916 const MCInstrDesc &MCID = KillMI->getDesc(); 917 if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() || 918 MCID.isTerminator()) 919 // Don't move pass calls, etc. 920 return false; 921 922 unsigned DstReg; 923 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 924 return false; 925 926 bool SeenStore; 927 if (!MI->isSafeToMove(TII, AA, SeenStore)) 928 return false; 929 930 if (TII->getInstrLatency(InstrItins, MI) > 1) 931 // FIXME: Needs more sophisticated heuristics. 932 return false; 933 934 SmallSet<unsigned, 2> Uses; 935 SmallSet<unsigned, 2> Defs; 936 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 937 const MachineOperand &MO = MI->getOperand(i); 938 if (!MO.isReg()) 939 continue; 940 unsigned MOReg = MO.getReg(); 941 if (!MOReg) 942 continue; 943 if (MO.isDef()) 944 Defs.insert(MOReg); 945 else 946 Uses.insert(MOReg); 947 } 948 949 // Move the copies connected to MI down as well. 950 MachineBasicBlock::iterator From = MI; 951 MachineBasicBlock::iterator To = llvm::next(From); 952 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) { 953 Defs.insert(To->getOperand(0).getReg()); 954 ++To; 955 } 956 957 // Check if the reschedule will not break depedencies. 958 unsigned NumVisited = 0; 959 MachineBasicBlock::iterator KillPos = KillMI; 960 ++KillPos; 961 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) { 962 MachineInstr *OtherMI = I; 963 // DBG_VALUE cannot be counted against the limit. 964 if (OtherMI->isDebugValue()) 965 continue; 966 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 967 return false; 968 ++NumVisited; 969 const MCInstrDesc &OMCID = OtherMI->getDesc(); 970 if (OMCID.hasUnmodeledSideEffects() || OMCID.isCall() || OMCID.isBranch() || 971 OMCID.isTerminator()) 972 // Don't move pass calls, etc. 973 return false; 974 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 975 const MachineOperand &MO = OtherMI->getOperand(i); 976 if (!MO.isReg()) 977 continue; 978 unsigned MOReg = MO.getReg(); 979 if (!MOReg) 980 continue; 981 if (MO.isDef()) { 982 if (Uses.count(MOReg)) 983 // Physical register use would be clobbered. 984 return false; 985 if (!MO.isDead() && Defs.count(MOReg)) 986 // May clobber a physical register def. 987 // FIXME: This may be too conservative. It's ok if the instruction 988 // is sunken completely below the use. 989 return false; 990 } else { 991 if (Defs.count(MOReg)) 992 return false; 993 if (MOReg != Reg && MO.isKill() && Uses.count(MOReg)) 994 // Don't want to extend other live ranges and update kills. 995 return false; 996 } 997 } 998 } 999 1000 // Move debug info as well. 1001 if (From != MBB->begin()) { 1002 while (llvm::prior(From)->isDebugValue()) 1003 --From; 1004 } 1005 1006 // Copies following MI may have been moved as well. 1007 nmi = To; 1008 MBB->splice(KillPos, MBB, From, To); 1009 DistanceMap.erase(DI); 1010 1011 if (LV) { 1012 // Update live variables 1013 LV->removeVirtualRegisterKilled(Reg, KillMI); 1014 LV->addVirtualRegisterKilled(Reg, MI); 1015 } else { 1016 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1017 MachineOperand &MO = KillMI->getOperand(i); 1018 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 1019 continue; 1020 MO.setIsKill(false); 1021 } 1022 MI->addRegisterKilled(Reg, 0); 1023 } 1024 1025 return true; 1026} 1027 1028/// isDefTooClose - Return true if the re-scheduling will put the given 1029/// instruction too close to the defs of its register dependencies. 1030bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, 1031 MachineInstr *MI, 1032 MachineBasicBlock *MBB) { 1033 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg), 1034 DE = MRI->def_end(); DI != DE; ++DI) { 1035 MachineInstr *DefMI = &*DI; 1036 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 1037 continue; 1038 if (DefMI == MI) 1039 return true; // MI is defining something KillMI uses 1040 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); 1041 if (DDI == DistanceMap.end()) 1042 return true; // Below MI 1043 unsigned DefDist = DDI->second; 1044 assert(Dist > DefDist && "Visited def already?"); 1045 if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist)) 1046 return true; 1047 } 1048 return false; 1049} 1050 1051/// RescheduleKillAboveMI - If there is one more local instruction that reads 1052/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the 1053/// current two-address instruction in order to eliminate the need for the 1054/// copy. 1055bool 1056TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB, 1057 MachineBasicBlock::iterator &mi, 1058 MachineBasicBlock::iterator &nmi, 1059 unsigned Reg) { 1060 MachineInstr *MI = &*mi; 1061 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 1062 if (DI == DistanceMap.end()) 1063 // Must be created from unfolded load. Don't waste time trying this. 1064 return false; 1065 1066 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap); 1067 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 1068 // Don't mess with copies, they may be coalesced later. 1069 return false; 1070 1071 unsigned DstReg; 1072 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 1073 return false; 1074 1075 bool SeenStore; 1076 if (!KillMI->isSafeToMove(TII, AA, SeenStore)) 1077 return false; 1078 1079 SmallSet<unsigned, 2> Uses; 1080 SmallSet<unsigned, 2> Kills; 1081 SmallSet<unsigned, 2> Defs; 1082 SmallSet<unsigned, 2> LiveDefs; 1083 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1084 const MachineOperand &MO = KillMI->getOperand(i); 1085 if (!MO.isReg()) 1086 continue; 1087 unsigned MOReg = MO.getReg(); 1088 if (MO.isUse()) { 1089 if (!MOReg) 1090 continue; 1091 if (isDefTooClose(MOReg, DI->second, MI, MBB)) 1092 return false; 1093 Uses.insert(MOReg); 1094 if (MO.isKill() && MOReg != Reg) 1095 Kills.insert(MOReg); 1096 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1097 Defs.insert(MOReg); 1098 if (!MO.isDead()) 1099 LiveDefs.insert(MOReg); 1100 } 1101 } 1102 1103 // Check if the reschedule will not break depedencies. 1104 unsigned NumVisited = 0; 1105 MachineBasicBlock::iterator KillPos = KillMI; 1106 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) { 1107 MachineInstr *OtherMI = I; 1108 // DBG_VALUE cannot be counted against the limit. 1109 if (OtherMI->isDebugValue()) 1110 continue; 1111 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 1112 return false; 1113 ++NumVisited; 1114 const MCInstrDesc &MCID = OtherMI->getDesc(); 1115 if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() || 1116 MCID.isTerminator()) 1117 // Don't move pass calls, etc. 1118 return false; 1119 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 1120 const MachineOperand &MO = OtherMI->getOperand(i); 1121 if (!MO.isReg()) 1122 continue; 1123 unsigned MOReg = MO.getReg(); 1124 if (!MOReg) 1125 continue; 1126 if (MO.isUse()) { 1127 if (Defs.count(MOReg)) 1128 // Moving KillMI can clobber the physical register if the def has 1129 // not been seen. 1130 return false; 1131 if (Kills.count(MOReg)) 1132 // Don't want to extend other live ranges and update kills. 1133 return false; 1134 } else { 1135 if (Uses.count(MOReg)) 1136 return false; 1137 if (TargetRegisterInfo::isPhysicalRegister(MOReg) && 1138 LiveDefs.count(MOReg)) 1139 return false; 1140 // Physical register def is seen. 1141 Defs.erase(MOReg); 1142 } 1143 } 1144 } 1145 1146 // Move the old kill above MI, don't forget to move debug info as well. 1147 MachineBasicBlock::iterator InsertPos = mi; 1148 if (InsertPos != MBB->begin()) 1149 while (llvm::prior(InsertPos)->isDebugValue()) 1150 --InsertPos; 1151 MachineBasicBlock::iterator From = KillMI; 1152 MachineBasicBlock::iterator To = llvm::next(From); 1153 while (llvm::prior(From)->isDebugValue()) 1154 --From; 1155 MBB->splice(InsertPos, MBB, From, To); 1156 1157 nmi = llvm::prior(mi); // Backtrack so we process the moved instruction. 1158 DistanceMap.erase(DI); 1159 1160 if (LV) { 1161 // Update live variables 1162 LV->removeVirtualRegisterKilled(Reg, KillMI); 1163 LV->addVirtualRegisterKilled(Reg, MI); 1164 } else { 1165 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1166 MachineOperand &MO = KillMI->getOperand(i); 1167 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 1168 continue; 1169 MO.setIsKill(false); 1170 } 1171 MI->addRegisterKilled(Reg, 0); 1172 } 1173 return true; 1174} 1175 1176/// TryInstructionTransform - For the case where an instruction has a single 1177/// pair of tied register operands, attempt some transformations that may 1178/// either eliminate the tied operands or improve the opportunities for 1179/// coalescing away the register copy. Returns true if the tied operands 1180/// are eliminated altogether. 1181bool TwoAddressInstructionPass:: 1182TryInstructionTransform(MachineBasicBlock::iterator &mi, 1183 MachineBasicBlock::iterator &nmi, 1184 MachineFunction::iterator &mbbi, 1185 unsigned SrcIdx, unsigned DstIdx, unsigned Dist, 1186 SmallPtrSet<MachineInstr*, 8> &Processed) { 1187 MachineInstr &MI = *mi; 1188 const MCInstrDesc &MCID = MI.getDesc(); 1189 unsigned regA = MI.getOperand(DstIdx).getReg(); 1190 unsigned regB = MI.getOperand(SrcIdx).getReg(); 1191 1192 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1193 "cannot make instruction into two-address form"); 1194 1195 // If regA is dead and the instruction can be deleted, just delete 1196 // it so it doesn't clobber regB. 1197 bool regBKilled = isKilled(MI, regB, MRI, TII); 1198 if (!regBKilled && MI.getOperand(DstIdx).isDead() && 1199 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { 1200 ++NumDeletes; 1201 return true; // Done with this instruction. 1202 } 1203 1204 // Check if it is profitable to commute the operands. 1205 unsigned SrcOp1, SrcOp2; 1206 unsigned regC = 0; 1207 unsigned regCIdx = ~0U; 1208 bool TryCommute = false; 1209 bool AggressiveCommute = false; 1210 if (MCID.isCommutable() && MI.getNumOperands() >= 3 && 1211 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) { 1212 if (SrcIdx == SrcOp1) 1213 regCIdx = SrcOp2; 1214 else if (SrcIdx == SrcOp2) 1215 regCIdx = SrcOp1; 1216 1217 if (regCIdx != ~0U) { 1218 regC = MI.getOperand(regCIdx).getReg(); 1219 if (!regBKilled && isKilled(MI, regC, MRI, TII)) 1220 // If C dies but B does not, swap the B and C operands. 1221 // This makes the live ranges of A and C joinable. 1222 TryCommute = true; 1223 else if (isProfitableToCommute(regB, regC, &MI, mbbi, Dist)) { 1224 TryCommute = true; 1225 AggressiveCommute = true; 1226 } 1227 } 1228 } 1229 1230 // If it's profitable to commute, try to do so. 1231 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 1232 ++NumCommuted; 1233 if (AggressiveCommute) 1234 ++NumAggrCommuted; 1235 return false; 1236 } 1237 1238 // If there is one more use of regB later in the same MBB, consider 1239 // re-schedule this MI below it. 1240 if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) { 1241 ++NumReSchedDowns; 1242 return true; 1243 } 1244 1245 if (TargetRegisterInfo::isVirtualRegister(regA)) 1246 ScanUses(regA, &*mbbi, Processed); 1247 1248 if (MCID.isConvertibleTo3Addr()) { 1249 // This instruction is potentially convertible to a true 1250 // three-address instruction. Check if it is profitable. 1251 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { 1252 // Try to convert it. 1253 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) { 1254 ++NumConvertedTo3Addr; 1255 return true; // Done with this instruction. 1256 } 1257 } 1258 } 1259 1260 // If there is one more use of regB later in the same MBB, consider 1261 // re-schedule it before this MI if it's legal. 1262 if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) { 1263 ++NumReSchedUps; 1264 return true; 1265 } 1266 1267 // If this is an instruction with a load folded into it, try unfolding 1268 // the load, e.g. avoid this: 1269 // movq %rdx, %rcx 1270 // addq (%rax), %rcx 1271 // in favor of this: 1272 // movq (%rax), %rcx 1273 // addq %rdx, %rcx 1274 // because it's preferable to schedule a load than a register copy. 1275 if (MCID.mayLoad() && !regBKilled) { 1276 // Determine if a load can be unfolded. 1277 unsigned LoadRegIndex; 1278 unsigned NewOpc = 1279 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 1280 /*UnfoldLoad=*/true, 1281 /*UnfoldStore=*/false, 1282 &LoadRegIndex); 1283 if (NewOpc != 0) { 1284 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); 1285 if (UnfoldMCID.getNumDefs() == 1) { 1286 MachineFunction &MF = *mbbi->getParent(); 1287 1288 // Unfold the load. 1289 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI); 1290 const TargetRegisterClass *RC = 1291 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); 1292 unsigned Reg = MRI->createVirtualRegister(RC); 1293 SmallVector<MachineInstr *, 2> NewMIs; 1294 if (!TII->unfoldMemoryOperand(MF, &MI, Reg, 1295 /*UnfoldLoad=*/true,/*UnfoldStore=*/false, 1296 NewMIs)) { 1297 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1298 return false; 1299 } 1300 assert(NewMIs.size() == 2 && 1301 "Unfolded a load into multiple instructions!"); 1302 // The load was previously folded, so this is the only use. 1303 NewMIs[1]->addRegisterKilled(Reg, TRI); 1304 1305 // Tentatively insert the instructions into the block so that they 1306 // look "normal" to the transformation logic. 1307 mbbi->insert(mi, NewMIs[0]); 1308 mbbi->insert(mi, NewMIs[1]); 1309 1310 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 1311 << "2addr: NEW INST: " << *NewMIs[1]); 1312 1313 // Transform the instruction, now that it no longer has a load. 1314 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 1315 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); 1316 MachineBasicBlock::iterator NewMI = NewMIs[1]; 1317 bool TransformSuccess = 1318 TryInstructionTransform(NewMI, mi, mbbi, 1319 NewSrcIdx, NewDstIdx, Dist, Processed); 1320 if (TransformSuccess || 1321 NewMIs[1]->getOperand(NewSrcIdx).isKill()) { 1322 // Success, or at least we made an improvement. Keep the unfolded 1323 // instructions and discard the original. 1324 if (LV) { 1325 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1326 MachineOperand &MO = MI.getOperand(i); 1327 if (MO.isReg() && 1328 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 1329 if (MO.isUse()) { 1330 if (MO.isKill()) { 1331 if (NewMIs[0]->killsRegister(MO.getReg())) 1332 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]); 1333 else { 1334 assert(NewMIs[1]->killsRegister(MO.getReg()) && 1335 "Kill missing after load unfold!"); 1336 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]); 1337 } 1338 } 1339 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) { 1340 if (NewMIs[1]->registerDefIsDead(MO.getReg())) 1341 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); 1342 else { 1343 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && 1344 "Dead flag missing after load unfold!"); 1345 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); 1346 } 1347 } 1348 } 1349 } 1350 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); 1351 } 1352 MI.eraseFromParent(); 1353 mi = NewMIs[1]; 1354 if (TransformSuccess) 1355 return true; 1356 } else { 1357 // Transforming didn't eliminate the tie and didn't lead to an 1358 // improvement. Clean up the unfolded instructions and keep the 1359 // original. 1360 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1361 NewMIs[0]->eraseFromParent(); 1362 NewMIs[1]->eraseFromParent(); 1363 } 1364 } 1365 } 1366 } 1367 1368 return false; 1369} 1370 1371/// runOnMachineFunction - Reduce two-address instructions to two operands. 1372/// 1373bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 1374 DEBUG(dbgs() << "Machine Function\n"); 1375 const TargetMachine &TM = MF.getTarget(); 1376 MRI = &MF.getRegInfo(); 1377 TII = TM.getInstrInfo(); 1378 TRI = TM.getRegisterInfo(); 1379 InstrItins = TM.getInstrItineraryData(); 1380 LV = getAnalysisIfAvailable<LiveVariables>(); 1381 AA = &getAnalysis<AliasAnalysis>(); 1382 1383 bool MadeChange = false; 1384 1385 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 1386 DEBUG(dbgs() << "********** Function: " 1387 << MF.getFunction()->getName() << '\n'); 1388 1389 // This pass takes the function out of SSA form. 1390 MRI->leaveSSA(); 1391 1392 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 1393 BitVector ReMatRegs(MRI->getNumVirtRegs()); 1394 1395 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > 1396 TiedOperandMap; 1397 TiedOperandMap TiedOperands(4); 1398 1399 SmallPtrSet<MachineInstr*, 8> Processed; 1400 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 1401 mbbi != mbbe; ++mbbi) { 1402 unsigned Dist = 0; 1403 DistanceMap.clear(); 1404 SrcRegMap.clear(); 1405 DstRegMap.clear(); 1406 Processed.clear(); 1407 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 1408 mi != me; ) { 1409 MachineBasicBlock::iterator nmi = llvm::next(mi); 1410 if (mi->isDebugValue()) { 1411 mi = nmi; 1412 continue; 1413 } 1414 1415 // Remember REG_SEQUENCE instructions, we'll deal with them later. 1416 if (mi->isRegSequence()) 1417 RegSequences.push_back(&*mi); 1418 1419 const MCInstrDesc &MCID = mi->getDesc(); 1420 bool FirstTied = true; 1421 1422 DistanceMap.insert(std::make_pair(mi, ++Dist)); 1423 1424 ProcessCopy(&*mi, &*mbbi, Processed); 1425 1426 // First scan through all the tied register uses in this instruction 1427 // and record a list of pairs of tied operands for each register. 1428 unsigned NumOps = mi->isInlineAsm() 1429 ? mi->getNumOperands() : MCID.getNumOperands(); 1430 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 1431 unsigned DstIdx = 0; 1432 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 1433 continue; 1434 1435 if (FirstTied) { 1436 FirstTied = false; 1437 ++NumTwoAddressInstrs; 1438 DEBUG(dbgs() << '\t' << *mi); 1439 } 1440 1441 assert(mi->getOperand(SrcIdx).isReg() && 1442 mi->getOperand(SrcIdx).getReg() && 1443 mi->getOperand(SrcIdx).isUse() && 1444 "two address instruction invalid"); 1445 1446 unsigned regB = mi->getOperand(SrcIdx).getReg(); 1447 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx)); 1448 } 1449 1450 // Now iterate over the information collected above. 1451 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 1452 OE = TiedOperands.end(); OI != OE; ++OI) { 1453 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second; 1454 1455 // If the instruction has a single pair of tied operands, try some 1456 // transformations that may either eliminate the tied operands or 1457 // improve the opportunities for coalescing away the register copy. 1458 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) { 1459 unsigned SrcIdx = TiedPairs[0].first; 1460 unsigned DstIdx = TiedPairs[0].second; 1461 1462 // If the registers are already equal, nothing needs to be done. 1463 if (mi->getOperand(SrcIdx).getReg() == 1464 mi->getOperand(DstIdx).getReg()) 1465 break; // Done with this instruction. 1466 1467 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist, 1468 Processed)) 1469 break; // The tied operands have been eliminated. 1470 } 1471 1472 bool IsEarlyClobber = false; 1473 bool RemovedKillFlag = false; 1474 bool AllUsesCopied = true; 1475 unsigned LastCopiedReg = 0; 1476 unsigned regB = OI->first; 1477 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1478 unsigned SrcIdx = TiedPairs[tpi].first; 1479 unsigned DstIdx = TiedPairs[tpi].second; 1480 1481 const MachineOperand &DstMO = mi->getOperand(DstIdx); 1482 unsigned regA = DstMO.getReg(); 1483 IsEarlyClobber |= DstMO.isEarlyClobber(); 1484 1485 // Grab regB from the instruction because it may have changed if the 1486 // instruction was commuted. 1487 regB = mi->getOperand(SrcIdx).getReg(); 1488 1489 if (regA == regB) { 1490 // The register is tied to multiple destinations (or else we would 1491 // not have continued this far), but this use of the register 1492 // already matches the tied destination. Leave it. 1493 AllUsesCopied = false; 1494 continue; 1495 } 1496 LastCopiedReg = regA; 1497 1498 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1499 "cannot make instruction into two-address form"); 1500 1501#ifndef NDEBUG 1502 // First, verify that we don't have a use of "a" in the instruction 1503 // (a = b + a for example) because our transformation will not 1504 // work. This should never occur because we are in SSA form. 1505 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 1506 assert(i == DstIdx || 1507 !mi->getOperand(i).isReg() || 1508 mi->getOperand(i).getReg() != regA); 1509#endif 1510 1511 // Emit a copy or rematerialize the definition. 1512 const TargetRegisterClass *rc = MRI->getRegClass(regB); 1513 MachineInstr *DefMI = MRI->getVRegDef(regB); 1514 // If it's safe and profitable, remat the definition instead of 1515 // copying it. 1516 if (DefMI && 1517 DefMI->getDesc().isAsCheapAsAMove() && 1518 DefMI->isSafeToReMat(TII, AA, regB) && 1519 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 1520 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); 1521 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); 1522 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); 1523 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); 1524 ++NumReMats; 1525 } else { 1526 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), 1527 regA).addReg(regB); 1528 } 1529 1530 MachineBasicBlock::iterator prevMI = prior(mi); 1531 // Update DistanceMap. 1532 DistanceMap.insert(std::make_pair(prevMI, Dist)); 1533 DistanceMap[mi] = ++Dist; 1534 1535 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI); 1536 1537 MachineOperand &MO = mi->getOperand(SrcIdx); 1538 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && 1539 "inconsistent operand info for 2-reg pass"); 1540 if (MO.isKill()) { 1541 MO.setIsKill(false); 1542 RemovedKillFlag = true; 1543 } 1544 MO.setReg(regA); 1545 } 1546 1547 if (AllUsesCopied) { 1548 if (!IsEarlyClobber) { 1549 // Replace other (un-tied) uses of regB with LastCopiedReg. 1550 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1551 MachineOperand &MO = mi->getOperand(i); 1552 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1553 if (MO.isKill()) { 1554 MO.setIsKill(false); 1555 RemovedKillFlag = true; 1556 } 1557 MO.setReg(LastCopiedReg); 1558 } 1559 } 1560 } 1561 1562 // Update live variables for regB. 1563 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi)) 1564 LV->addVirtualRegisterKilled(regB, prior(mi)); 1565 1566 } else if (RemovedKillFlag) { 1567 // Some tied uses of regB matched their destination registers, so 1568 // regB is still used in this instruction, but a kill flag was 1569 // removed from a different tied use of regB, so now we need to add 1570 // a kill flag to one of the remaining uses of regB. 1571 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1572 MachineOperand &MO = mi->getOperand(i); 1573 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1574 MO.setIsKill(true); 1575 break; 1576 } 1577 } 1578 } 1579 1580 // Schedule the source copy / remat inserted to form two-address 1581 // instruction. FIXME: Does it matter the distance map may not be 1582 // accurate after it's scheduled? 1583 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI); 1584 1585 MadeChange = true; 1586 1587 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1588 } 1589 1590 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. 1591 if (mi->isInsertSubreg()) { 1592 // From %reg = INSERT_SUBREG %reg, %subreg, subidx 1593 // To %reg:subidx = COPY %subreg 1594 unsigned SubIdx = mi->getOperand(3).getImm(); 1595 mi->RemoveOperand(3); 1596 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); 1597 mi->getOperand(0).setSubReg(SubIdx); 1598 mi->RemoveOperand(1); 1599 mi->setDesc(TII->get(TargetOpcode::COPY)); 1600 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); 1601 } 1602 1603 // Clear TiedOperands here instead of at the top of the loop 1604 // since most instructions do not have tied operands. 1605 TiedOperands.clear(); 1606 mi = nmi; 1607 } 1608 } 1609 1610 // Some remat'ed instructions are dead. 1611 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) { 1612 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); 1613 if (MRI->use_nodbg_empty(VReg)) { 1614 MachineInstr *DefMI = MRI->getVRegDef(VReg); 1615 DefMI->eraseFromParent(); 1616 } 1617 } 1618 1619 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve 1620 // SSA form. It's now safe to de-SSA. 1621 MadeChange |= EliminateRegSequences(); 1622 1623 return MadeChange; 1624} 1625 1626static void UpdateRegSequenceSrcs(unsigned SrcReg, 1627 unsigned DstReg, unsigned SubIdx, 1628 MachineRegisterInfo *MRI, 1629 const TargetRegisterInfo &TRI) { 1630 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 1631 RE = MRI->reg_end(); RI != RE; ) { 1632 MachineOperand &MO = RI.getOperand(); 1633 ++RI; 1634 MO.substVirtReg(DstReg, SubIdx, TRI); 1635 } 1636} 1637 1638/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are 1639/// EXTRACT_SUBREG from the same register and to the same virtual register 1640/// with different sub-register indices, attempt to combine the 1641/// EXTRACT_SUBREGs and pre-coalesce them. e.g. 1642/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 1643/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 1644/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 1645/// Since D subregs 5, 6 can combine to a Q register, we can coalesce 1646/// reg1026 to reg1029. 1647void 1648TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, 1649 unsigned DstReg) { 1650 SmallSet<unsigned, 4> Seen; 1651 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) { 1652 unsigned SrcReg = Srcs[i]; 1653 if (!Seen.insert(SrcReg)) 1654 continue; 1655 1656 // Check that the instructions are all in the same basic block. 1657 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg); 1658 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg); 1659 if (SrcDefMI->getParent() != DstDefMI->getParent()) 1660 continue; 1661 1662 // If there are no other uses than copies which feed into 1663 // the reg_sequence, then we might be able to coalesce them. 1664 bool CanCoalesce = true; 1665 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices; 1666 for (MachineRegisterInfo::use_nodbg_iterator 1667 UI = MRI->use_nodbg_begin(SrcReg), 1668 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1669 MachineInstr *UseMI = &*UI; 1670 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) { 1671 CanCoalesce = false; 1672 break; 1673 } 1674 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg()); 1675 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg()); 1676 } 1677 1678 if (!CanCoalesce || SrcSubIndices.size() < 2) 1679 continue; 1680 1681 // Check that the source subregisters can be combined. 1682 std::sort(SrcSubIndices.begin(), SrcSubIndices.end()); 1683 unsigned NewSrcSubIdx = 0; 1684 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, 1685 NewSrcSubIdx)) 1686 continue; 1687 1688 // Check that the destination subregisters can also be combined. 1689 std::sort(DstSubIndices.begin(), DstSubIndices.end()); 1690 unsigned NewDstSubIdx = 0; 1691 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, 1692 NewDstSubIdx)) 1693 continue; 1694 1695 // If neither source nor destination can be combined to the full register, 1696 // just give up. This could be improved if it ever matters. 1697 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) 1698 continue; 1699 1700 // Now that we know that all the uses are extract_subregs and that those 1701 // subregs can somehow be combined, scan all the extract_subregs again to 1702 // make sure the subregs are in the right order and can be composed. 1703 MachineInstr *SomeMI = 0; 1704 CanCoalesce = true; 1705 for (MachineRegisterInfo::use_nodbg_iterator 1706 UI = MRI->use_nodbg_begin(SrcReg), 1707 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1708 MachineInstr *UseMI = &*UI; 1709 assert(UseMI->isCopy()); 1710 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); 1711 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg(); 1712 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); 1713 if ((NewDstSubIdx == 0 && 1714 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || 1715 (NewSrcSubIdx == 0 && 1716 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { 1717 CanCoalesce = false; 1718 break; 1719 } 1720 // Keep track of one of the uses. 1721 SomeMI = UseMI; 1722 } 1723 if (!CanCoalesce) 1724 continue; 1725 1726 // Insert a copy to replace the original. 1727 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI, 1728 SomeMI->getDebugLoc(), 1729 TII->get(TargetOpcode::COPY)) 1730 .addReg(DstReg, RegState::Define, NewDstSubIdx) 1731 .addReg(SrcReg, 0, NewSrcSubIdx); 1732 1733 // Remove all the old extract instructions. 1734 for (MachineRegisterInfo::use_nodbg_iterator 1735 UI = MRI->use_nodbg_begin(SrcReg), 1736 UE = MRI->use_nodbg_end(); UI != UE; ) { 1737 MachineInstr *UseMI = &*UI; 1738 ++UI; 1739 if (UseMI == CopyMI) 1740 continue; 1741 assert(UseMI->isCopy()); 1742 // Move any kills to the new copy or extract instruction. 1743 if (UseMI->getOperand(1).isKill()) { 1744 CopyMI->getOperand(1).setIsKill(); 1745 if (LV) 1746 // Update live variables 1747 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI); 1748 } 1749 UseMI->eraseFromParent(); 1750 } 1751 } 1752} 1753 1754static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, 1755 MachineRegisterInfo *MRI) { 1756 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 1757 UE = MRI->use_end(); UI != UE; ++UI) { 1758 MachineInstr *UseMI = &*UI; 1759 if (UseMI != RegSeq && UseMI->isRegSequence()) 1760 return true; 1761 } 1762 return false; 1763} 1764 1765/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 1766/// of the de-ssa process. This replaces sources of REG_SEQUENCE as 1767/// sub-register references of the register defined by REG_SEQUENCE. e.g. 1768/// 1769/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ... 1770/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6 1771/// => 1772/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ... 1773bool TwoAddressInstructionPass::EliminateRegSequences() { 1774 if (RegSequences.empty()) 1775 return false; 1776 1777 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) { 1778 MachineInstr *MI = RegSequences[i]; 1779 unsigned DstReg = MI->getOperand(0).getReg(); 1780 if (MI->getOperand(0).getSubReg() || 1781 TargetRegisterInfo::isPhysicalRegister(DstReg) || 1782 !(MI->getNumOperands() & 1)) { 1783 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1784 llvm_unreachable(0); 1785 } 1786 1787 bool IsImpDef = true; 1788 SmallVector<unsigned, 4> RealSrcs; 1789 SmallSet<unsigned, 4> Seen; 1790 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1791 unsigned SrcReg = MI->getOperand(i).getReg(); 1792 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1793 if (MI->getOperand(i).getSubReg() || 1794 TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1795 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1796 llvm_unreachable(0); 1797 } 1798 1799 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 1800 if (DefMI->isImplicitDef()) { 1801 DefMI->eraseFromParent(); 1802 continue; 1803 } 1804 IsImpDef = false; 1805 1806 // Remember COPY sources. These might be candidate for coalescing. 1807 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg()) 1808 RealSrcs.push_back(DefMI->getOperand(1).getReg()); 1809 1810 bool isKill = MI->getOperand(i).isKill(); 1811 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() || 1812 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) || 1813 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), 1814 MRI->getRegClass(SrcReg), SubIdx)) { 1815 // REG_SEQUENCE cannot have duplicated operands, add a copy. 1816 // Also add an copy if the source is live-in the block. We don't want 1817 // to end up with a partial-redef of a livein, e.g. 1818 // BB0: 1819 // reg1051:10<def> = 1820 // ... 1821 // BB1: 1822 // ... = reg1051:10 1823 // BB2: 1824 // reg1051:9<def> = 1825 // LiveIntervalAnalysis won't like it. 1826 // 1827 // If the REG_SEQUENCE doesn't kill its source, keeping live variables 1828 // correctly up to date becomes very difficult. Insert a copy. 1829 1830 // Defer any kill flag to the last operand using SrcReg. Otherwise, we 1831 // might insert a COPY that uses SrcReg after is was killed. 1832 if (isKill) 1833 for (unsigned j = i + 2; j < e; j += 2) 1834 if (MI->getOperand(j).getReg() == SrcReg) { 1835 MI->getOperand(j).setIsKill(); 1836 isKill = false; 1837 break; 1838 } 1839 1840 MachineBasicBlock::iterator InsertLoc = MI; 1841 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc, 1842 MI->getDebugLoc(), TII->get(TargetOpcode::COPY)) 1843 .addReg(DstReg, RegState::Define, SubIdx) 1844 .addReg(SrcReg, getKillRegState(isKill)); 1845 MI->getOperand(i).setReg(0); 1846 if (LV && isKill) 1847 LV->replaceKillInstruction(SrcReg, MI, CopyMI); 1848 DEBUG(dbgs() << "Inserted: " << *CopyMI); 1849 } 1850 } 1851 1852 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1853 unsigned SrcReg = MI->getOperand(i).getReg(); 1854 if (!SrcReg) continue; 1855 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1856 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1857 } 1858 1859 if (IsImpDef) { 1860 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1861 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 1862 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) 1863 MI->RemoveOperand(j); 1864 } else { 1865 DEBUG(dbgs() << "Eliminated: " << *MI); 1866 MI->eraseFromParent(); 1867 } 1868 1869 // Try coalescing some EXTRACT_SUBREG instructions. This can create 1870 // INSERT_SUBREG instructions that must have <undef> flags added by 1871 // LiveIntervalAnalysis, so only run it when LiveVariables is available. 1872 if (LV) 1873 CoalesceExtSubRegs(RealSrcs, DstReg); 1874 } 1875 1876 RegSequences.clear(); 1877 return true; 1878} 1879