TwoAddressInstructionPass.cpp revision 4d96c638af0458f4de637998da942a5e166d6ea5
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/Analysis/AliasAnalysis.h" 39#include "llvm/Target/TargetRegisterInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetMachine.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/ErrorHandling.h" 45#include "llvm/ADT/BitVector.h" 46#include "llvm/ADT/DenseMap.h" 47#include "llvm/ADT/SmallSet.h" 48#include "llvm/ADT/Statistic.h" 49#include "llvm/ADT/STLExtras.h" 50using namespace llvm; 51 52STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 53STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 54STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 55STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 56STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 57STATISTIC(NumReMats, "Number of instructions re-materialized"); 58STATISTIC(NumDeletes, "Number of dead instructions deleted"); 59 60namespace { 61 class TwoAddressInstructionPass : public MachineFunctionPass { 62 const TargetInstrInfo *TII; 63 const TargetRegisterInfo *TRI; 64 MachineRegisterInfo *MRI; 65 LiveVariables *LV; 66 AliasAnalysis *AA; 67 68 // DistanceMap - Keep track the distance of a MI from the start of the 69 // current basic block. 70 DenseMap<MachineInstr*, unsigned> DistanceMap; 71 72 // SrcRegMap - A map from virtual registers to physical registers which 73 // are likely targets to be coalesced to due to copies from physical 74 // registers to virtual registers. e.g. v1024 = move r0. 75 DenseMap<unsigned, unsigned> SrcRegMap; 76 77 // DstRegMap - A map from virtual registers to physical registers which 78 // are likely targets to be coalesced to due to copies to physical 79 // registers from virtual registers. e.g. r1 = move v1024. 80 DenseMap<unsigned, unsigned> DstRegMap; 81 82 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen 83 /// during the initial walk of the machine function. 84 SmallVector<MachineInstr*, 16> RegSequences; 85 86 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 87 unsigned Reg, 88 MachineBasicBlock::iterator OldPos); 89 90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 91 MachineInstr *MI, MachineInstr *DefMI, 92 MachineBasicBlock *MBB, unsigned Loc); 93 94 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 95 unsigned &LastDef); 96 97 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 98 unsigned Dist); 99 100 bool isProfitableToCommute(unsigned regB, unsigned regC, 101 MachineInstr *MI, MachineBasicBlock *MBB, 102 unsigned Dist); 103 104 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 105 MachineFunction::iterator &mbbi, 106 unsigned RegB, unsigned RegC, unsigned Dist); 107 108 bool isProfitableToConv3Addr(unsigned RegA); 109 110 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 111 MachineBasicBlock::iterator &nmi, 112 MachineFunction::iterator &mbbi, 113 unsigned RegA, unsigned RegB, unsigned Dist); 114 115 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill; 116 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 117 SmallVector<NewKill, 4> &NewKills, 118 MachineBasicBlock *MBB, unsigned Dist); 119 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 120 MachineBasicBlock::iterator &nmi, 121 MachineFunction::iterator &mbbi, unsigned Dist); 122 123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi, 124 MachineBasicBlock::iterator &nmi, 125 MachineFunction::iterator &mbbi, 126 unsigned SrcIdx, unsigned DstIdx, 127 unsigned Dist); 128 129 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 130 SmallPtrSet<MachineInstr*, 8> &Processed); 131 132 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg); 133 134 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 135 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as 136 /// sub-register references of the register defined by REG_SEQUENCE. 137 bool EliminateRegSequences(); 138 139 public: 140 static char ID; // Pass identification, replacement for typeid 141 TwoAddressInstructionPass() : MachineFunctionPass(ID) { 142 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 143 } 144 145 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 146 AU.setPreservesCFG(); 147 AU.addRequired<AliasAnalysis>(); 148 AU.addPreserved<LiveVariables>(); 149 AU.addPreservedID(MachineLoopInfoID); 150 AU.addPreservedID(MachineDominatorsID); 151 AU.addPreservedID(PHIEliminationID); 152 MachineFunctionPass::getAnalysisUsage(AU); 153 } 154 155 /// runOnMachineFunction - Pass entry point. 156 bool runOnMachineFunction(MachineFunction&); 157 }; 158} 159 160char TwoAddressInstructionPass::ID = 0; 161INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction", 162 "Two-Address instruction pass", false, false) 163INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 164INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction", 165 "Two-Address instruction pass", false, false) 166 167char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID; 168 169/// Sink3AddrInstruction - A two-address instruction has been converted to a 170/// three-address instruction to avoid clobbering a register. Try to sink it 171/// past the instruction that would kill the above mentioned register to reduce 172/// register pressure. 173bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 174 MachineInstr *MI, unsigned SavedReg, 175 MachineBasicBlock::iterator OldPos) { 176 // Check if it's safe to move this instruction. 177 bool SeenStore = true; // Be conservative. 178 if (!MI->isSafeToMove(TII, AA, SeenStore)) 179 return false; 180 181 unsigned DefReg = 0; 182 SmallSet<unsigned, 4> UseRegs; 183 184 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 185 const MachineOperand &MO = MI->getOperand(i); 186 if (!MO.isReg()) 187 continue; 188 unsigned MOReg = MO.getReg(); 189 if (!MOReg) 190 continue; 191 if (MO.isUse() && MOReg != SavedReg) 192 UseRegs.insert(MO.getReg()); 193 if (!MO.isDef()) 194 continue; 195 if (MO.isImplicit()) 196 // Don't try to move it if it implicitly defines a register. 197 return false; 198 if (DefReg) 199 // For now, don't move any instructions that define multiple registers. 200 return false; 201 DefReg = MO.getReg(); 202 } 203 204 // Find the instruction that kills SavedReg. 205 MachineInstr *KillMI = NULL; 206 for (MachineRegisterInfo::use_nodbg_iterator 207 UI = MRI->use_nodbg_begin(SavedReg), 208 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 209 MachineOperand &UseMO = UI.getOperand(); 210 if (!UseMO.isKill()) 211 continue; 212 KillMI = UseMO.getParent(); 213 break; 214 } 215 216 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI) 217 return false; 218 219 // If any of the definitions are used by another instruction between the 220 // position and the kill use, then it's not safe to sink it. 221 // 222 // FIXME: This can be sped up if there is an easy way to query whether an 223 // instruction is before or after another instruction. Then we can use 224 // MachineRegisterInfo def / use instead. 225 MachineOperand *KillMO = NULL; 226 MachineBasicBlock::iterator KillPos = KillMI; 227 ++KillPos; 228 229 unsigned NumVisited = 0; 230 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) { 231 MachineInstr *OtherMI = I; 232 // DBG_VALUE cannot be counted against the limit. 233 if (OtherMI->isDebugValue()) 234 continue; 235 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 236 return false; 237 ++NumVisited; 238 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 239 MachineOperand &MO = OtherMI->getOperand(i); 240 if (!MO.isReg()) 241 continue; 242 unsigned MOReg = MO.getReg(); 243 if (!MOReg) 244 continue; 245 if (DefReg == MOReg) 246 return false; 247 248 if (MO.isKill()) { 249 if (OtherMI == KillMI && MOReg == SavedReg) 250 // Save the operand that kills the register. We want to unset the kill 251 // marker if we can sink MI past it. 252 KillMO = &MO; 253 else if (UseRegs.count(MOReg)) 254 // One of the uses is killed before the destination. 255 return false; 256 } 257 } 258 } 259 260 // Update kill and LV information. 261 KillMO->setIsKill(false); 262 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 263 KillMO->setIsKill(true); 264 265 if (LV) 266 LV->replaceKillInstruction(SavedReg, KillMI, MI); 267 268 // Move instruction to its destination. 269 MBB->remove(MI); 270 MBB->insert(KillPos, MI); 271 272 ++Num3AddrSunk; 273 return true; 274} 275 276/// isTwoAddrUse - Return true if the specified MI is using the specified 277/// register as a two-address operand. 278static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 279 const TargetInstrDesc &TID = UseMI->getDesc(); 280 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 281 MachineOperand &MO = UseMI->getOperand(i); 282 if (MO.isReg() && MO.getReg() == Reg && 283 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 284 // Earlier use is a two-address one. 285 return true; 286 } 287 return false; 288} 289 290/// isProfitableToReMat - Return true if the heuristics determines it is likely 291/// to be profitable to re-materialize the definition of Reg rather than copy 292/// the register. 293bool 294TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 295 const TargetRegisterClass *RC, 296 MachineInstr *MI, MachineInstr *DefMI, 297 MachineBasicBlock *MBB, unsigned Loc) { 298 bool OtherUse = false; 299 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg), 300 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 301 MachineOperand &UseMO = UI.getOperand(); 302 MachineInstr *UseMI = UseMO.getParent(); 303 MachineBasicBlock *UseMBB = UseMI->getParent(); 304 if (UseMBB == MBB) { 305 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 306 if (DI != DistanceMap.end() && DI->second == Loc) 307 continue; // Current use. 308 OtherUse = true; 309 // There is at least one other use in the MBB that will clobber the 310 // register. 311 if (isTwoAddrUse(UseMI, Reg)) 312 return true; 313 } 314 } 315 316 // If other uses in MBB are not two-address uses, then don't remat. 317 if (OtherUse) 318 return false; 319 320 // No other uses in the same block, remat if it's defined in the same 321 // block so it does not unnecessarily extend the live range. 322 return MBB == DefMI->getParent(); 323} 324 325/// NoUseAfterLastDef - Return true if there are no intervening uses between the 326/// last instruction in the MBB that defines the specified register and the 327/// two-address instruction which is being processed. It also returns the last 328/// def location by reference 329bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 330 MachineBasicBlock *MBB, unsigned Dist, 331 unsigned &LastDef) { 332 LastDef = 0; 333 unsigned LastUse = Dist; 334 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 335 E = MRI->reg_end(); I != E; ++I) { 336 MachineOperand &MO = I.getOperand(); 337 MachineInstr *MI = MO.getParent(); 338 if (MI->getParent() != MBB || MI->isDebugValue()) 339 continue; 340 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 341 if (DI == DistanceMap.end()) 342 continue; 343 if (MO.isUse() && DI->second < LastUse) 344 LastUse = DI->second; 345 if (MO.isDef() && DI->second > LastDef) 346 LastDef = DI->second; 347 } 348 349 return !(LastUse > LastDef && LastUse < Dist); 350} 351 352MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 353 MachineBasicBlock *MBB, 354 unsigned Dist) { 355 unsigned LastUseDist = 0; 356 MachineInstr *LastUse = 0; 357 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 358 E = MRI->reg_end(); I != E; ++I) { 359 MachineOperand &MO = I.getOperand(); 360 MachineInstr *MI = MO.getParent(); 361 if (MI->getParent() != MBB || MI->isDebugValue()) 362 continue; 363 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 364 if (DI == DistanceMap.end()) 365 continue; 366 if (DI->second >= Dist) 367 continue; 368 369 if (MO.isUse() && DI->second > LastUseDist) { 370 LastUse = DI->first; 371 LastUseDist = DI->second; 372 } 373 } 374 return LastUse; 375} 376 377/// isCopyToReg - Return true if the specified MI is a copy instruction or 378/// a extract_subreg instruction. It also returns the source and destination 379/// registers and whether they are physical registers by reference. 380static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 381 unsigned &SrcReg, unsigned &DstReg, 382 bool &IsSrcPhys, bool &IsDstPhys) { 383 SrcReg = 0; 384 DstReg = 0; 385 if (MI.isCopy()) { 386 DstReg = MI.getOperand(0).getReg(); 387 SrcReg = MI.getOperand(1).getReg(); 388 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { 389 DstReg = MI.getOperand(0).getReg(); 390 SrcReg = MI.getOperand(2).getReg(); 391 } else 392 return false; 393 394 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 395 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 396 return true; 397} 398 399/// isKilled - Test if the given register value, which is used by the given 400/// instruction, is killed by the given instruction. This looks through 401/// coalescable copies to see if the original value is potentially not killed. 402/// 403/// For example, in this code: 404/// 405/// %reg1034 = copy %reg1024 406/// %reg1035 = copy %reg1025<kill> 407/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 408/// 409/// %reg1034 is not considered to be killed, since it is copied from a 410/// register which is not killed. Treating it as not killed lets the 411/// normal heuristics commute the (two-address) add, which lets 412/// coalescing eliminate the extra copy. 413/// 414static bool isKilled(MachineInstr &MI, unsigned Reg, 415 const MachineRegisterInfo *MRI, 416 const TargetInstrInfo *TII) { 417 MachineInstr *DefMI = &MI; 418 for (;;) { 419 if (!DefMI->killsRegister(Reg)) 420 return false; 421 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 422 return true; 423 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 424 // If there are multiple defs, we can't do a simple analysis, so just 425 // go with what the kill flag says. 426 if (llvm::next(Begin) != MRI->def_end()) 427 return true; 428 DefMI = &*Begin; 429 bool IsSrcPhys, IsDstPhys; 430 unsigned SrcReg, DstReg; 431 // If the def is something other than a copy, then it isn't going to 432 // be coalesced, so follow the kill flag. 433 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 434 return true; 435 Reg = SrcReg; 436 } 437} 438 439/// isTwoAddrUse - Return true if the specified MI uses the specified register 440/// as a two-address use. If so, return the destination register by reference. 441static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 442 const TargetInstrDesc &TID = MI.getDesc(); 443 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands(); 444 for (unsigned i = 0; i != NumOps; ++i) { 445 const MachineOperand &MO = MI.getOperand(i); 446 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 447 continue; 448 unsigned ti; 449 if (MI.isRegTiedToDefOperand(i, &ti)) { 450 DstReg = MI.getOperand(ti).getReg(); 451 return true; 452 } 453 } 454 return false; 455} 456 457/// findOnlyInterestingUse - Given a register, if has a single in-basic block 458/// use, return the use instruction if it's a copy or a two-address use. 459static 460MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 461 MachineRegisterInfo *MRI, 462 const TargetInstrInfo *TII, 463 bool &IsCopy, 464 unsigned &DstReg, bool &IsDstPhys) { 465 if (!MRI->hasOneNonDBGUse(Reg)) 466 // None or more than one use. 467 return 0; 468 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); 469 if (UseMI.getParent() != MBB) 470 return 0; 471 unsigned SrcReg; 472 bool IsSrcPhys; 473 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 474 IsCopy = true; 475 return &UseMI; 476 } 477 IsDstPhys = false; 478 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 479 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 480 return &UseMI; 481 } 482 return 0; 483} 484 485/// getMappedReg - Return the physical register the specified virtual register 486/// might be mapped to. 487static unsigned 488getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 489 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 490 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 491 if (SI == RegMap.end()) 492 return 0; 493 Reg = SI->second; 494 } 495 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 496 return Reg; 497 return 0; 498} 499 500/// regsAreCompatible - Return true if the two registers are equal or aliased. 501/// 502static bool 503regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 504 if (RegA == RegB) 505 return true; 506 if (!RegA || !RegB) 507 return false; 508 return TRI->regsOverlap(RegA, RegB); 509} 510 511 512/// isProfitableToReMat - Return true if it's potentially profitable to commute 513/// the two-address instruction that's being processed. 514bool 515TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 516 MachineInstr *MI, MachineBasicBlock *MBB, 517 unsigned Dist) { 518 // Determine if it's profitable to commute this two address instruction. In 519 // general, we want no uses between this instruction and the definition of 520 // the two-address register. 521 // e.g. 522 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 523 // %reg1029<def> = MOV8rr %reg1028 524 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 525 // insert => %reg1030<def> = MOV8rr %reg1028 526 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 527 // In this case, it might not be possible to coalesce the second MOV8rr 528 // instruction if the first one is coalesced. So it would be profitable to 529 // commute it: 530 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 531 // %reg1029<def> = MOV8rr %reg1028 532 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 533 // insert => %reg1030<def> = MOV8rr %reg1029 534 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 535 536 if (!MI->killsRegister(regC)) 537 return false; 538 539 // Ok, we have something like: 540 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 541 // let's see if it's worth commuting it. 542 543 // Look for situations like this: 544 // %reg1024<def> = MOV r1 545 // %reg1025<def> = MOV r0 546 // %reg1026<def> = ADD %reg1024, %reg1025 547 // r0 = MOV %reg1026 548 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 549 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 550 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 551 unsigned ToRegB = getMappedReg(regB, DstRegMap); 552 unsigned ToRegC = getMappedReg(regC, DstRegMap); 553 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && 554 ((!FromRegC && !ToRegC) || 555 regsAreCompatible(FromRegB, ToRegC, TRI) || 556 regsAreCompatible(FromRegC, ToRegB, TRI))) 557 return true; 558 559 // If there is a use of regC between its last def (could be livein) and this 560 // instruction, then bail. 561 unsigned LastDefC = 0; 562 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 563 return false; 564 565 // If there is a use of regB between its last def (could be livein) and this 566 // instruction, then go ahead and make this transformation. 567 unsigned LastDefB = 0; 568 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 569 return true; 570 571 // Since there are no intervening uses for both registers, then commute 572 // if the def of regC is closer. Its live interval is shorter. 573 return LastDefB && LastDefC && LastDefC > LastDefB; 574} 575 576/// CommuteInstruction - Commute a two-address instruction and update the basic 577/// block, distance map, and live variables if needed. Return true if it is 578/// successful. 579bool 580TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 581 MachineFunction::iterator &mbbi, 582 unsigned RegB, unsigned RegC, unsigned Dist) { 583 MachineInstr *MI = mi; 584 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 585 MachineInstr *NewMI = TII->commuteInstruction(MI); 586 587 if (NewMI == 0) { 588 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 589 return false; 590 } 591 592 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 593 // If the instruction changed to commute it, update livevar. 594 if (NewMI != MI) { 595 if (LV) 596 // Update live variables 597 LV->replaceKillInstruction(RegC, MI, NewMI); 598 599 mbbi->insert(mi, NewMI); // Insert the new inst 600 mbbi->erase(mi); // Nuke the old inst. 601 mi = NewMI; 602 DistanceMap.insert(std::make_pair(NewMI, Dist)); 603 } 604 605 // Update source register map. 606 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 607 if (FromRegC) { 608 unsigned RegA = MI->getOperand(0).getReg(); 609 SrcRegMap[RegA] = FromRegC; 610 } 611 612 return true; 613} 614 615/// isProfitableToConv3Addr - Return true if it is profitable to convert the 616/// given 2-address instruction to a 3-address one. 617bool 618TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) { 619 // Look for situations like this: 620 // %reg1024<def> = MOV r1 621 // %reg1025<def> = MOV r0 622 // %reg1026<def> = ADD %reg1024, %reg1025 623 // r2 = MOV %reg1026 624 // Turn ADD into a 3-address instruction to avoid a copy. 625 unsigned FromRegA = getMappedReg(RegA, SrcRegMap); 626 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 627 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI)); 628} 629 630/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 631/// three address one. Return true if this transformation was successful. 632bool 633TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 634 MachineBasicBlock::iterator &nmi, 635 MachineFunction::iterator &mbbi, 636 unsigned RegA, unsigned RegB, 637 unsigned Dist) { 638 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 639 if (NewMI) { 640 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 641 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 642 bool Sunk = false; 643 644 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 645 // FIXME: Temporary workaround. If the new instruction doesn't 646 // uses RegB, convertToThreeAddress must have created more 647 // then one instruction. 648 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 649 650 mbbi->erase(mi); // Nuke the old inst. 651 652 if (!Sunk) { 653 DistanceMap.insert(std::make_pair(NewMI, Dist)); 654 mi = NewMI; 655 nmi = llvm::next(mi); 656 } 657 658 // Update source and destination register maps. 659 SrcRegMap.erase(RegA); 660 DstRegMap.erase(RegB); 661 return true; 662 } 663 664 return false; 665} 666 667/// ProcessCopy - If the specified instruction is not yet processed, process it 668/// if it's a copy. For a copy instruction, we find the physical registers the 669/// source and destination registers might be mapped to. These are kept in 670/// point-to maps used to determine future optimizations. e.g. 671/// v1024 = mov r0 672/// v1025 = mov r1 673/// v1026 = add v1024, v1025 674/// r1 = mov r1026 675/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 676/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 677/// potentially joined with r1 on the output side. It's worthwhile to commute 678/// 'add' to eliminate a copy. 679void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 680 MachineBasicBlock *MBB, 681 SmallPtrSet<MachineInstr*, 8> &Processed) { 682 if (Processed.count(MI)) 683 return; 684 685 bool IsSrcPhys, IsDstPhys; 686 unsigned SrcReg, DstReg; 687 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 688 return; 689 690 if (IsDstPhys && !IsSrcPhys) 691 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 692 else if (!IsDstPhys && IsSrcPhys) { 693 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 694 if (!isNew) 695 assert(SrcRegMap[DstReg] == SrcReg && 696 "Can't map to two src physical registers!"); 697 698 SmallVector<unsigned, 4> VirtRegPairs; 699 bool IsCopy = false; 700 unsigned NewReg = 0; 701 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII, 702 IsCopy, NewReg, IsDstPhys)) { 703 if (IsCopy) { 704 if (!Processed.insert(UseMI)) 705 break; 706 } 707 708 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 709 if (DI != DistanceMap.end()) 710 // Earlier in the same MBB.Reached via a back edge. 711 break; 712 713 if (IsDstPhys) { 714 VirtRegPairs.push_back(NewReg); 715 break; 716 } 717 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second; 718 if (!isNew) 719 assert(SrcRegMap[NewReg] == DstReg && 720 "Can't map to two src physical registers!"); 721 VirtRegPairs.push_back(NewReg); 722 DstReg = NewReg; 723 } 724 725 if (!VirtRegPairs.empty()) { 726 unsigned ToReg = VirtRegPairs.back(); 727 VirtRegPairs.pop_back(); 728 while (!VirtRegPairs.empty()) { 729 unsigned FromReg = VirtRegPairs.back(); 730 VirtRegPairs.pop_back(); 731 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 732 if (!isNew) 733 assert(DstRegMap[FromReg] == ToReg && 734 "Can't map to two dst physical registers!"); 735 ToReg = FromReg; 736 } 737 } 738 } 739 740 Processed.insert(MI); 741} 742 743/// isSafeToDelete - If the specified instruction does not produce any side 744/// effects and all of its defs are dead, then it's safe to delete. 745static bool isSafeToDelete(MachineInstr *MI, 746 const TargetInstrInfo *TII, 747 SmallVector<unsigned, 4> &Kills) { 748 const TargetInstrDesc &TID = MI->getDesc(); 749 if (TID.mayStore() || TID.isCall()) 750 return false; 751 if (TID.isTerminator() || MI->hasUnmodeledSideEffects()) 752 return false; 753 754 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 755 MachineOperand &MO = MI->getOperand(i); 756 if (!MO.isReg()) 757 continue; 758 if (MO.isDef() && !MO.isDead()) 759 return false; 760 if (MO.isUse() && MO.isKill()) 761 Kills.push_back(MO.getReg()); 762 } 763 return true; 764} 765 766/// canUpdateDeletedKills - Check if all the registers listed in Kills are 767/// killed by instructions in MBB preceding the current instruction at 768/// position Dist. If so, return true and record information about the 769/// preceding kills in NewKills. 770bool TwoAddressInstructionPass:: 771canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 772 SmallVector<NewKill, 4> &NewKills, 773 MachineBasicBlock *MBB, unsigned Dist) { 774 while (!Kills.empty()) { 775 unsigned Kill = Kills.back(); 776 Kills.pop_back(); 777 if (TargetRegisterInfo::isPhysicalRegister(Kill)) 778 return false; 779 780 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist); 781 if (!LastKill) 782 return false; 783 784 bool isModRef = LastKill->definesRegister(Kill); 785 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef), 786 LastKill)); 787 } 788 return true; 789} 790 791/// DeleteUnusedInstr - If an instruction with a tied register operand can 792/// be safely deleted, just delete it. 793bool 794TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 795 MachineBasicBlock::iterator &nmi, 796 MachineFunction::iterator &mbbi, 797 unsigned Dist) { 798 // Check if the instruction has no side effects and if all its defs are dead. 799 SmallVector<unsigned, 4> Kills; 800 if (!isSafeToDelete(mi, TII, Kills)) 801 return false; 802 803 // If this instruction kills some virtual registers, we need to 804 // update the kill information. If it's not possible to do so, 805 // then bail out. 806 SmallVector<NewKill, 4> NewKills; 807 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist)) 808 return false; 809 810 if (LV) { 811 while (!NewKills.empty()) { 812 MachineInstr *NewKill = NewKills.back().second; 813 unsigned Kill = NewKills.back().first.first; 814 bool isDead = NewKills.back().first.second; 815 NewKills.pop_back(); 816 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 817 if (isDead) 818 LV->addVirtualRegisterDead(Kill, NewKill); 819 else 820 LV->addVirtualRegisterKilled(Kill, NewKill); 821 } 822 } 823 } 824 825 mbbi->erase(mi); // Nuke the old inst. 826 mi = nmi; 827 return true; 828} 829 830/// TryInstructionTransform - For the case where an instruction has a single 831/// pair of tied register operands, attempt some transformations that may 832/// either eliminate the tied operands or improve the opportunities for 833/// coalescing away the register copy. Returns true if the tied operands 834/// are eliminated altogether. 835bool TwoAddressInstructionPass:: 836TryInstructionTransform(MachineBasicBlock::iterator &mi, 837 MachineBasicBlock::iterator &nmi, 838 MachineFunction::iterator &mbbi, 839 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) { 840 const TargetInstrDesc &TID = mi->getDesc(); 841 unsigned regA = mi->getOperand(DstIdx).getReg(); 842 unsigned regB = mi->getOperand(SrcIdx).getReg(); 843 844 assert(TargetRegisterInfo::isVirtualRegister(regB) && 845 "cannot make instruction into two-address form"); 846 847 // If regA is dead and the instruction can be deleted, just delete 848 // it so it doesn't clobber regB. 849 bool regBKilled = isKilled(*mi, regB, MRI, TII); 850 if (!regBKilled && mi->getOperand(DstIdx).isDead() && 851 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { 852 ++NumDeletes; 853 return true; // Done with this instruction. 854 } 855 856 // Check if it is profitable to commute the operands. 857 unsigned SrcOp1, SrcOp2; 858 unsigned regC = 0; 859 unsigned regCIdx = ~0U; 860 bool TryCommute = false; 861 bool AggressiveCommute = false; 862 if (TID.isCommutable() && mi->getNumOperands() >= 3 && 863 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) { 864 if (SrcIdx == SrcOp1) 865 regCIdx = SrcOp2; 866 else if (SrcIdx == SrcOp2) 867 regCIdx = SrcOp1; 868 869 if (regCIdx != ~0U) { 870 regC = mi->getOperand(regCIdx).getReg(); 871 if (!regBKilled && isKilled(*mi, regC, MRI, TII)) 872 // If C dies but B does not, swap the B and C operands. 873 // This makes the live ranges of A and C joinable. 874 TryCommute = true; 875 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) { 876 TryCommute = true; 877 AggressiveCommute = true; 878 } 879 } 880 } 881 882 // If it's profitable to commute, try to do so. 883 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 884 ++NumCommuted; 885 if (AggressiveCommute) 886 ++NumAggrCommuted; 887 return false; 888 } 889 890 if (TID.isConvertibleTo3Addr()) { 891 // This instruction is potentially convertible to a true 892 // three-address instruction. Check if it is profitable. 893 if (!regBKilled || isProfitableToConv3Addr(regA)) { 894 // Try to convert it. 895 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) { 896 ++NumConvertedTo3Addr; 897 return true; // Done with this instruction. 898 } 899 } 900 } 901 902 // If this is an instruction with a load folded into it, try unfolding 903 // the load, e.g. avoid this: 904 // movq %rdx, %rcx 905 // addq (%rax), %rcx 906 // in favor of this: 907 // movq (%rax), %rcx 908 // addq %rdx, %rcx 909 // because it's preferable to schedule a load than a register copy. 910 if (TID.mayLoad() && !regBKilled) { 911 // Determine if a load can be unfolded. 912 unsigned LoadRegIndex; 913 unsigned NewOpc = 914 TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(), 915 /*UnfoldLoad=*/true, 916 /*UnfoldStore=*/false, 917 &LoadRegIndex); 918 if (NewOpc != 0) { 919 const TargetInstrDesc &UnfoldTID = TII->get(NewOpc); 920 if (UnfoldTID.getNumDefs() == 1) { 921 MachineFunction &MF = *mbbi->getParent(); 922 923 // Unfold the load. 924 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi); 925 const TargetRegisterClass *RC = 926 UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI); 927 unsigned Reg = MRI->createVirtualRegister(RC); 928 SmallVector<MachineInstr *, 2> NewMIs; 929 if (!TII->unfoldMemoryOperand(MF, mi, Reg, 930 /*UnfoldLoad=*/true,/*UnfoldStore=*/false, 931 NewMIs)) { 932 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 933 return false; 934 } 935 assert(NewMIs.size() == 2 && 936 "Unfolded a load into multiple instructions!"); 937 // The load was previously folded, so this is the only use. 938 NewMIs[1]->addRegisterKilled(Reg, TRI); 939 940 // Tentatively insert the instructions into the block so that they 941 // look "normal" to the transformation logic. 942 mbbi->insert(mi, NewMIs[0]); 943 mbbi->insert(mi, NewMIs[1]); 944 945 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 946 << "2addr: NEW INST: " << *NewMIs[1]); 947 948 // Transform the instruction, now that it no longer has a load. 949 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 950 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); 951 MachineBasicBlock::iterator NewMI = NewMIs[1]; 952 bool TransformSuccess = 953 TryInstructionTransform(NewMI, mi, mbbi, 954 NewSrcIdx, NewDstIdx, Dist); 955 if (TransformSuccess || 956 NewMIs[1]->getOperand(NewSrcIdx).isKill()) { 957 // Success, or at least we made an improvement. Keep the unfolded 958 // instructions and discard the original. 959 if (LV) { 960 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 961 MachineOperand &MO = mi->getOperand(i); 962 if (MO.isReg() && 963 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 964 if (MO.isUse()) { 965 if (MO.isKill()) { 966 if (NewMIs[0]->killsRegister(MO.getReg())) 967 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]); 968 else { 969 assert(NewMIs[1]->killsRegister(MO.getReg()) && 970 "Kill missing after load unfold!"); 971 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]); 972 } 973 } 974 } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) { 975 if (NewMIs[1]->registerDefIsDead(MO.getReg())) 976 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); 977 else { 978 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && 979 "Dead flag missing after load unfold!"); 980 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); 981 } 982 } 983 } 984 } 985 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); 986 } 987 mi->eraseFromParent(); 988 mi = NewMIs[1]; 989 if (TransformSuccess) 990 return true; 991 } else { 992 // Transforming didn't eliminate the tie and didn't lead to an 993 // improvement. Clean up the unfolded instructions and keep the 994 // original. 995 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 996 NewMIs[0]->eraseFromParent(); 997 NewMIs[1]->eraseFromParent(); 998 } 999 } 1000 } 1001 } 1002 1003 return false; 1004} 1005 1006/// runOnMachineFunction - Reduce two-address instructions to two operands. 1007/// 1008bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 1009 DEBUG(dbgs() << "Machine Function\n"); 1010 const TargetMachine &TM = MF.getTarget(); 1011 MRI = &MF.getRegInfo(); 1012 TII = TM.getInstrInfo(); 1013 TRI = TM.getRegisterInfo(); 1014 LV = getAnalysisIfAvailable<LiveVariables>(); 1015 AA = &getAnalysis<AliasAnalysis>(); 1016 1017 bool MadeChange = false; 1018 1019 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 1020 DEBUG(dbgs() << "********** Function: " 1021 << MF.getFunction()->getName() << '\n'); 1022 1023 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 1024 BitVector ReMatRegs(MRI->getNumVirtRegs()); 1025 1026 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > 1027 TiedOperandMap; 1028 TiedOperandMap TiedOperands(4); 1029 1030 SmallPtrSet<MachineInstr*, 8> Processed; 1031 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 1032 mbbi != mbbe; ++mbbi) { 1033 unsigned Dist = 0; 1034 DistanceMap.clear(); 1035 SrcRegMap.clear(); 1036 DstRegMap.clear(); 1037 Processed.clear(); 1038 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 1039 mi != me; ) { 1040 MachineBasicBlock::iterator nmi = llvm::next(mi); 1041 if (mi->isDebugValue()) { 1042 mi = nmi; 1043 continue; 1044 } 1045 1046 // Remember REG_SEQUENCE instructions, we'll deal with them later. 1047 if (mi->isRegSequence()) 1048 RegSequences.push_back(&*mi); 1049 1050 const TargetInstrDesc &TID = mi->getDesc(); 1051 bool FirstTied = true; 1052 1053 DistanceMap.insert(std::make_pair(mi, ++Dist)); 1054 1055 ProcessCopy(&*mi, &*mbbi, Processed); 1056 1057 // First scan through all the tied register uses in this instruction 1058 // and record a list of pairs of tied operands for each register. 1059 unsigned NumOps = mi->isInlineAsm() 1060 ? mi->getNumOperands() : TID.getNumOperands(); 1061 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 1062 unsigned DstIdx = 0; 1063 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 1064 continue; 1065 1066 if (FirstTied) { 1067 FirstTied = false; 1068 ++NumTwoAddressInstrs; 1069 DEBUG(dbgs() << '\t' << *mi); 1070 } 1071 1072 assert(mi->getOperand(SrcIdx).isReg() && 1073 mi->getOperand(SrcIdx).getReg() && 1074 mi->getOperand(SrcIdx).isUse() && 1075 "two address instruction invalid"); 1076 1077 unsigned regB = mi->getOperand(SrcIdx).getReg(); 1078 TiedOperandMap::iterator OI = TiedOperands.find(regB); 1079 if (OI == TiedOperands.end()) { 1080 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair; 1081 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first; 1082 } 1083 OI->second.push_back(std::make_pair(SrcIdx, DstIdx)); 1084 } 1085 1086 // Now iterate over the information collected above. 1087 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 1088 OE = TiedOperands.end(); OI != OE; ++OI) { 1089 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second; 1090 1091 // If the instruction has a single pair of tied operands, try some 1092 // transformations that may either eliminate the tied operands or 1093 // improve the opportunities for coalescing away the register copy. 1094 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) { 1095 unsigned SrcIdx = TiedPairs[0].first; 1096 unsigned DstIdx = TiedPairs[0].second; 1097 1098 // If the registers are already equal, nothing needs to be done. 1099 if (mi->getOperand(SrcIdx).getReg() == 1100 mi->getOperand(DstIdx).getReg()) 1101 break; // Done with this instruction. 1102 1103 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist)) 1104 break; // The tied operands have been eliminated. 1105 } 1106 1107 bool RemovedKillFlag = false; 1108 bool AllUsesCopied = true; 1109 unsigned LastCopiedReg = 0; 1110 unsigned regB = OI->first; 1111 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1112 unsigned SrcIdx = TiedPairs[tpi].first; 1113 unsigned DstIdx = TiedPairs[tpi].second; 1114 unsigned regA = mi->getOperand(DstIdx).getReg(); 1115 // Grab regB from the instruction because it may have changed if the 1116 // instruction was commuted. 1117 regB = mi->getOperand(SrcIdx).getReg(); 1118 1119 if (regA == regB) { 1120 // The register is tied to multiple destinations (or else we would 1121 // not have continued this far), but this use of the register 1122 // already matches the tied destination. Leave it. 1123 AllUsesCopied = false; 1124 continue; 1125 } 1126 LastCopiedReg = regA; 1127 1128 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1129 "cannot make instruction into two-address form"); 1130 1131#ifndef NDEBUG 1132 // First, verify that we don't have a use of "a" in the instruction 1133 // (a = b + a for example) because our transformation will not 1134 // work. This should never occur because we are in SSA form. 1135 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 1136 assert(i == DstIdx || 1137 !mi->getOperand(i).isReg() || 1138 mi->getOperand(i).getReg() != regA); 1139#endif 1140 1141 // Emit a copy or rematerialize the definition. 1142 const TargetRegisterClass *rc = MRI->getRegClass(regB); 1143 MachineInstr *DefMI = MRI->getVRegDef(regB); 1144 // If it's safe and profitable, remat the definition instead of 1145 // copying it. 1146 if (DefMI && 1147 DefMI->getDesc().isAsCheapAsAMove() && 1148 DefMI->isSafeToReMat(TII, AA, regB) && 1149 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 1150 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); 1151 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); 1152 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); 1153 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); 1154 ++NumReMats; 1155 } else { 1156 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), 1157 regA).addReg(regB); 1158 } 1159 1160 MachineBasicBlock::iterator prevMI = prior(mi); 1161 // Update DistanceMap. 1162 DistanceMap.insert(std::make_pair(prevMI, Dist)); 1163 DistanceMap[mi] = ++Dist; 1164 1165 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI); 1166 1167 MachineOperand &MO = mi->getOperand(SrcIdx); 1168 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && 1169 "inconsistent operand info for 2-reg pass"); 1170 if (MO.isKill()) { 1171 MO.setIsKill(false); 1172 RemovedKillFlag = true; 1173 } 1174 MO.setReg(regA); 1175 } 1176 1177 if (AllUsesCopied) { 1178 // Replace other (un-tied) uses of regB with LastCopiedReg. 1179 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1180 MachineOperand &MO = mi->getOperand(i); 1181 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1182 if (MO.isKill()) { 1183 MO.setIsKill(false); 1184 RemovedKillFlag = true; 1185 } 1186 MO.setReg(LastCopiedReg); 1187 } 1188 } 1189 1190 // Update live variables for regB. 1191 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi)) 1192 LV->addVirtualRegisterKilled(regB, prior(mi)); 1193 1194 } else if (RemovedKillFlag) { 1195 // Some tied uses of regB matched their destination registers, so 1196 // regB is still used in this instruction, but a kill flag was 1197 // removed from a different tied use of regB, so now we need to add 1198 // a kill flag to one of the remaining uses of regB. 1199 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1200 MachineOperand &MO = mi->getOperand(i); 1201 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1202 MO.setIsKill(true); 1203 break; 1204 } 1205 } 1206 } 1207 1208 // Schedule the source copy / remat inserted to form two-address 1209 // instruction. FIXME: Does it matter the distance map may not be 1210 // accurate after it's scheduled? 1211 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI); 1212 1213 MadeChange = true; 1214 1215 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1216 } 1217 1218 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. 1219 if (mi->isInsertSubreg()) { 1220 // From %reg = INSERT_SUBREG %reg, %subreg, subidx 1221 // To %reg:subidx = COPY %subreg 1222 unsigned SubIdx = mi->getOperand(3).getImm(); 1223 mi->RemoveOperand(3); 1224 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); 1225 mi->getOperand(0).setSubReg(SubIdx); 1226 mi->RemoveOperand(1); 1227 mi->setDesc(TII->get(TargetOpcode::COPY)); 1228 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); 1229 } 1230 1231 // Clear TiedOperands here instead of at the top of the loop 1232 // since most instructions do not have tied operands. 1233 TiedOperands.clear(); 1234 mi = nmi; 1235 } 1236 } 1237 1238 // Some remat'ed instructions are dead. 1239 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) { 1240 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); 1241 if (MRI->use_nodbg_empty(VReg)) { 1242 MachineInstr *DefMI = MRI->getVRegDef(VReg); 1243 DefMI->eraseFromParent(); 1244 } 1245 } 1246 1247 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve 1248 // SSA form. It's now safe to de-SSA. 1249 MadeChange |= EliminateRegSequences(); 1250 1251 return MadeChange; 1252} 1253 1254static void UpdateRegSequenceSrcs(unsigned SrcReg, 1255 unsigned DstReg, unsigned SubIdx, 1256 MachineRegisterInfo *MRI, 1257 const TargetRegisterInfo &TRI) { 1258 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 1259 RE = MRI->reg_end(); RI != RE; ) { 1260 MachineOperand &MO = RI.getOperand(); 1261 ++RI; 1262 MO.substVirtReg(DstReg, SubIdx, TRI); 1263 } 1264} 1265 1266/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are 1267/// EXTRACT_SUBREG from the same register and to the same virtual register 1268/// with different sub-register indices, attempt to combine the 1269/// EXTRACT_SUBREGs and pre-coalesce them. e.g. 1270/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 1271/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 1272/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 1273/// Since D subregs 5, 6 can combine to a Q register, we can coalesce 1274/// reg1026 to reg1029. 1275void 1276TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, 1277 unsigned DstReg) { 1278 SmallSet<unsigned, 4> Seen; 1279 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) { 1280 unsigned SrcReg = Srcs[i]; 1281 if (!Seen.insert(SrcReg)) 1282 continue; 1283 1284 // Check that the instructions are all in the same basic block. 1285 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg); 1286 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg); 1287 if (SrcDefMI->getParent() != DstDefMI->getParent()) 1288 continue; 1289 1290 // If there are no other uses than copies which feed into 1291 // the reg_sequence, then we might be able to coalesce them. 1292 bool CanCoalesce = true; 1293 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices; 1294 for (MachineRegisterInfo::use_nodbg_iterator 1295 UI = MRI->use_nodbg_begin(SrcReg), 1296 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1297 MachineInstr *UseMI = &*UI; 1298 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) { 1299 CanCoalesce = false; 1300 break; 1301 } 1302 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg()); 1303 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg()); 1304 } 1305 1306 if (!CanCoalesce || SrcSubIndices.size() < 2) 1307 continue; 1308 1309 // Check that the source subregisters can be combined. 1310 std::sort(SrcSubIndices.begin(), SrcSubIndices.end()); 1311 unsigned NewSrcSubIdx = 0; 1312 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, 1313 NewSrcSubIdx)) 1314 continue; 1315 1316 // Check that the destination subregisters can also be combined. 1317 std::sort(DstSubIndices.begin(), DstSubIndices.end()); 1318 unsigned NewDstSubIdx = 0; 1319 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, 1320 NewDstSubIdx)) 1321 continue; 1322 1323 // If neither source nor destination can be combined to the full register, 1324 // just give up. This could be improved if it ever matters. 1325 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) 1326 continue; 1327 1328 // Now that we know that all the uses are extract_subregs and that those 1329 // subregs can somehow be combined, scan all the extract_subregs again to 1330 // make sure the subregs are in the right order and can be composed. 1331 MachineInstr *SomeMI = 0; 1332 CanCoalesce = true; 1333 for (MachineRegisterInfo::use_nodbg_iterator 1334 UI = MRI->use_nodbg_begin(SrcReg), 1335 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1336 MachineInstr *UseMI = &*UI; 1337 assert(UseMI->isCopy()); 1338 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); 1339 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg(); 1340 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); 1341 if ((NewDstSubIdx == 0 && 1342 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || 1343 (NewSrcSubIdx == 0 && 1344 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { 1345 CanCoalesce = false; 1346 break; 1347 } 1348 // Keep track of one of the uses. 1349 SomeMI = UseMI; 1350 } 1351 if (!CanCoalesce) 1352 continue; 1353 1354 // Insert a copy to replace the original. 1355 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI, 1356 SomeMI->getDebugLoc(), 1357 TII->get(TargetOpcode::COPY)) 1358 .addReg(DstReg, RegState::Define, NewDstSubIdx) 1359 .addReg(SrcReg, 0, NewSrcSubIdx); 1360 1361 // Remove all the old extract instructions. 1362 for (MachineRegisterInfo::use_nodbg_iterator 1363 UI = MRI->use_nodbg_begin(SrcReg), 1364 UE = MRI->use_nodbg_end(); UI != UE; ) { 1365 MachineInstr *UseMI = &*UI; 1366 ++UI; 1367 if (UseMI == CopyMI) 1368 continue; 1369 assert(UseMI->isCopy()); 1370 // Move any kills to the new copy or extract instruction. 1371 if (UseMI->getOperand(1).isKill()) { 1372 CopyMI->getOperand(1).setIsKill(); 1373 if (LV) 1374 // Update live variables 1375 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI); 1376 } 1377 UseMI->eraseFromParent(); 1378 } 1379 } 1380} 1381 1382static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, 1383 MachineRegisterInfo *MRI) { 1384 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 1385 UE = MRI->use_end(); UI != UE; ++UI) { 1386 MachineInstr *UseMI = &*UI; 1387 if (UseMI != RegSeq && UseMI->isRegSequence()) 1388 return true; 1389 } 1390 return false; 1391} 1392 1393/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 1394/// of the de-ssa process. This replaces sources of REG_SEQUENCE as 1395/// sub-register references of the register defined by REG_SEQUENCE. e.g. 1396/// 1397/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ... 1398/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6 1399/// => 1400/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ... 1401bool TwoAddressInstructionPass::EliminateRegSequences() { 1402 if (RegSequences.empty()) 1403 return false; 1404 1405 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) { 1406 MachineInstr *MI = RegSequences[i]; 1407 unsigned DstReg = MI->getOperand(0).getReg(); 1408 if (MI->getOperand(0).getSubReg() || 1409 TargetRegisterInfo::isPhysicalRegister(DstReg) || 1410 !(MI->getNumOperands() & 1)) { 1411 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1412 llvm_unreachable(0); 1413 } 1414 1415 bool IsImpDef = true; 1416 SmallVector<unsigned, 4> RealSrcs; 1417 SmallSet<unsigned, 4> Seen; 1418 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1419 unsigned SrcReg = MI->getOperand(i).getReg(); 1420 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1421 if (MI->getOperand(i).getSubReg() || 1422 TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1423 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1424 llvm_unreachable(0); 1425 } 1426 1427 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 1428 if (DefMI->isImplicitDef()) { 1429 DefMI->eraseFromParent(); 1430 continue; 1431 } 1432 IsImpDef = false; 1433 1434 // Remember COPY sources. These might be candidate for coalescing. 1435 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg()) 1436 RealSrcs.push_back(DefMI->getOperand(1).getReg()); 1437 1438 bool isKill = MI->getOperand(i).isKill(); 1439 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() || 1440 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) || 1441 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), 1442 MRI->getRegClass(SrcReg), SubIdx)) { 1443 // REG_SEQUENCE cannot have duplicated operands, add a copy. 1444 // Also add an copy if the source is live-in the block. We don't want 1445 // to end up with a partial-redef of a livein, e.g. 1446 // BB0: 1447 // reg1051:10<def> = 1448 // ... 1449 // BB1: 1450 // ... = reg1051:10 1451 // BB2: 1452 // reg1051:9<def> = 1453 // LiveIntervalAnalysis won't like it. 1454 // 1455 // If the REG_SEQUENCE doesn't kill its source, keeping live variables 1456 // correctly up to date becomes very difficult. Insert a copy. 1457 1458 // Defer any kill flag to the last operand using SrcReg. Otherwise, we 1459 // might insert a COPY that uses SrcReg after is was killed. 1460 if (isKill) 1461 for (unsigned j = i + 2; j < e; j += 2) 1462 if (MI->getOperand(j).getReg() == SrcReg) { 1463 MI->getOperand(j).setIsKill(); 1464 isKill = false; 1465 break; 1466 } 1467 1468 MachineBasicBlock::iterator InsertLoc = MI; 1469 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc, 1470 MI->getDebugLoc(), TII->get(TargetOpcode::COPY)) 1471 .addReg(DstReg, RegState::Define, SubIdx) 1472 .addReg(SrcReg, getKillRegState(isKill)); 1473 MI->getOperand(i).setReg(0); 1474 if (LV && isKill) 1475 LV->replaceKillInstruction(SrcReg, MI, CopyMI); 1476 DEBUG(dbgs() << "Inserted: " << *CopyMI); 1477 } 1478 } 1479 1480 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1481 unsigned SrcReg = MI->getOperand(i).getReg(); 1482 if (!SrcReg) continue; 1483 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1484 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1485 } 1486 1487 if (IsImpDef) { 1488 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1489 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 1490 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) 1491 MI->RemoveOperand(j); 1492 } else { 1493 DEBUG(dbgs() << "Eliminated: " << *MI); 1494 MI->eraseFromParent(); 1495 } 1496 1497 // Try coalescing some EXTRACT_SUBREG instructions. This can create 1498 // INSERT_SUBREG instructions that must have <undef> flags added by 1499 // LiveIntervalAnalysis, so only run it when LiveVariables is available. 1500 if (LV) 1501 CoalesceExtSubRegs(RealSrcs, DstReg); 1502 } 1503 1504 RegSequences.clear(); 1505 return true; 1506} 1507