TwoAddressInstructionPass.cpp revision 60dc7345eb1543546064a35c7c2c4ea08b40f9c0
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/Target/TargetRegisterInfo.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Target/TargetOptions.h" 41#include "llvm/Support/Compiler.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/DenseMap.h" 45#include "llvm/ADT/SmallSet.h" 46#include "llvm/ADT/Statistic.h" 47#include "llvm/ADT/STLExtras.h" 48using namespace llvm; 49 50STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 51STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 52STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 53STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 54STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 55STATISTIC(NumReMats, "Number of instructions re-materialized"); 56STATISTIC(NumDeletes, "Number of dead instructions deleted"); 57 58namespace { 59 class VISIBILITY_HIDDEN TwoAddressInstructionPass 60 : public MachineFunctionPass { 61 const TargetInstrInfo *TII; 62 const TargetRegisterInfo *TRI; 63 MachineRegisterInfo *MRI; 64 LiveVariables *LV; 65 66 // DistanceMap - Keep track the distance of a MI from the start of the 67 // current basic block. 68 DenseMap<MachineInstr*, unsigned> DistanceMap; 69 70 // SrcRegMap - A map from virtual registers to physical registers which 71 // are likely targets to be coalesced to due to copies from physical 72 // registers to virtual registers. e.g. v1024 = move r0. 73 DenseMap<unsigned, unsigned> SrcRegMap; 74 75 // DstRegMap - A map from virtual registers to physical registers which 76 // are likely targets to be coalesced to due to copies to physical 77 // registers from virtual registers. e.g. r1 = move v1024. 78 DenseMap<unsigned, unsigned> DstRegMap; 79 80 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 81 unsigned Reg, 82 MachineBasicBlock::iterator OldPos); 83 84 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 85 MachineInstr *MI, MachineInstr *DefMI, 86 MachineBasicBlock *MBB, unsigned Loc); 87 88 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 89 unsigned &LastDef); 90 91 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 92 unsigned Dist); 93 94 bool isProfitableToCommute(unsigned regB, unsigned regC, 95 MachineInstr *MI, MachineBasicBlock *MBB, 96 unsigned Dist); 97 98 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 99 MachineFunction::iterator &mbbi, 100 unsigned RegB, unsigned RegC, unsigned Dist); 101 102 bool isProfitableToConv3Addr(unsigned RegA); 103 104 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 105 MachineBasicBlock::iterator &nmi, 106 MachineFunction::iterator &mbbi, 107 unsigned RegB, unsigned Dist); 108 109 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 110 SmallPtrSet<MachineInstr*, 8> &Processed); 111 public: 112 static char ID; // Pass identification, replacement for typeid 113 TwoAddressInstructionPass() : MachineFunctionPass(&ID) {} 114 115 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 116 AU.addPreserved<LiveVariables>(); 117 AU.addPreservedID(MachineLoopInfoID); 118 AU.addPreservedID(MachineDominatorsID); 119 if (StrongPHIElim) 120 AU.addPreservedID(StrongPHIEliminationID); 121 else 122 AU.addPreservedID(PHIEliminationID); 123 MachineFunctionPass::getAnalysisUsage(AU); 124 } 125 126 /// runOnMachineFunction - Pass entry point. 127 bool runOnMachineFunction(MachineFunction&); 128 }; 129} 130 131char TwoAddressInstructionPass::ID = 0; 132static RegisterPass<TwoAddressInstructionPass> 133X("twoaddressinstruction", "Two-Address instruction pass"); 134 135const PassInfo *const llvm::TwoAddressInstructionPassID = &X; 136 137/// Sink3AddrInstruction - A two-address instruction has been converted to a 138/// three-address instruction to avoid clobbering a register. Try to sink it 139/// past the instruction that would kill the above mentioned register to reduce 140/// register pressure. 141bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 142 MachineInstr *MI, unsigned SavedReg, 143 MachineBasicBlock::iterator OldPos) { 144 // Check if it's safe to move this instruction. 145 bool SeenStore = true; // Be conservative. 146 if (!MI->isSafeToMove(TII, SeenStore)) 147 return false; 148 149 unsigned DefReg = 0; 150 SmallSet<unsigned, 4> UseRegs; 151 152 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 153 const MachineOperand &MO = MI->getOperand(i); 154 if (!MO.isReg()) 155 continue; 156 unsigned MOReg = MO.getReg(); 157 if (!MOReg) 158 continue; 159 if (MO.isUse() && MOReg != SavedReg) 160 UseRegs.insert(MO.getReg()); 161 if (!MO.isDef()) 162 continue; 163 if (MO.isImplicit()) 164 // Don't try to move it if it implicitly defines a register. 165 return false; 166 if (DefReg) 167 // For now, don't move any instructions that define multiple registers. 168 return false; 169 DefReg = MO.getReg(); 170 } 171 172 // Find the instruction that kills SavedReg. 173 MachineInstr *KillMI = NULL; 174 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg), 175 UE = MRI->use_end(); UI != UE; ++UI) { 176 MachineOperand &UseMO = UI.getOperand(); 177 if (!UseMO.isKill()) 178 continue; 179 KillMI = UseMO.getParent(); 180 break; 181 } 182 183 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI) 184 return false; 185 186 // If any of the definitions are used by another instruction between the 187 // position and the kill use, then it's not safe to sink it. 188 // 189 // FIXME: This can be sped up if there is an easy way to query whether an 190 // instruction is before or after another instruction. Then we can use 191 // MachineRegisterInfo def / use instead. 192 MachineOperand *KillMO = NULL; 193 MachineBasicBlock::iterator KillPos = KillMI; 194 ++KillPos; 195 196 unsigned NumVisited = 0; 197 for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) { 198 MachineInstr *OtherMI = I; 199 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 200 return false; 201 ++NumVisited; 202 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 203 MachineOperand &MO = OtherMI->getOperand(i); 204 if (!MO.isReg()) 205 continue; 206 unsigned MOReg = MO.getReg(); 207 if (!MOReg) 208 continue; 209 if (DefReg == MOReg) 210 return false; 211 212 if (MO.isKill()) { 213 if (OtherMI == KillMI && MOReg == SavedReg) 214 // Save the operand that kills the register. We want to unset the kill 215 // marker if we can sink MI past it. 216 KillMO = &MO; 217 else if (UseRegs.count(MOReg)) 218 // One of the uses is killed before the destination. 219 return false; 220 } 221 } 222 } 223 224 // Update kill and LV information. 225 KillMO->setIsKill(false); 226 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 227 KillMO->setIsKill(true); 228 229 if (LV) 230 LV->replaceKillInstruction(SavedReg, KillMI, MI); 231 232 // Move instruction to its destination. 233 MBB->remove(MI); 234 MBB->insert(KillPos, MI); 235 236 ++Num3AddrSunk; 237 return true; 238} 239 240/// isTwoAddrUse - Return true if the specified MI is using the specified 241/// register as a two-address operand. 242static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 243 const TargetInstrDesc &TID = UseMI->getDesc(); 244 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 245 MachineOperand &MO = UseMI->getOperand(i); 246 if (MO.isReg() && MO.getReg() == Reg && 247 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 248 // Earlier use is a two-address one. 249 return true; 250 } 251 return false; 252} 253 254/// isProfitableToReMat - Return true if the heuristics determines it is likely 255/// to be profitable to re-materialize the definition of Reg rather than copy 256/// the register. 257bool 258TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 259 const TargetRegisterClass *RC, 260 MachineInstr *MI, MachineInstr *DefMI, 261 MachineBasicBlock *MBB, unsigned Loc) { 262 bool OtherUse = false; 263 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 264 UE = MRI->use_end(); UI != UE; ++UI) { 265 MachineOperand &UseMO = UI.getOperand(); 266 MachineInstr *UseMI = UseMO.getParent(); 267 MachineBasicBlock *UseMBB = UseMI->getParent(); 268 if (UseMBB == MBB) { 269 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 270 if (DI != DistanceMap.end() && DI->second == Loc) 271 continue; // Current use. 272 OtherUse = true; 273 // There is at least one other use in the MBB that will clobber the 274 // register. 275 if (isTwoAddrUse(UseMI, Reg)) 276 return true; 277 } 278 } 279 280 // If other uses in MBB are not two-address uses, then don't remat. 281 if (OtherUse) 282 return false; 283 284 // No other uses in the same block, remat if it's defined in the same 285 // block so it does not unnecessarily extend the live range. 286 return MBB == DefMI->getParent(); 287} 288 289/// NoUseAfterLastDef - Return true if there are no intervening uses between the 290/// last instruction in the MBB that defines the specified register and the 291/// two-address instruction which is being processed. It also returns the last 292/// def location by reference 293bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 294 MachineBasicBlock *MBB, unsigned Dist, 295 unsigned &LastDef) { 296 LastDef = 0; 297 unsigned LastUse = Dist; 298 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 299 E = MRI->reg_end(); I != E; ++I) { 300 MachineOperand &MO = I.getOperand(); 301 MachineInstr *MI = MO.getParent(); 302 if (MI->getParent() != MBB) 303 continue; 304 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 305 if (DI == DistanceMap.end()) 306 continue; 307 if (MO.isUse() && DI->second < LastUse) 308 LastUse = DI->second; 309 if (MO.isDef() && DI->second > LastDef) 310 LastDef = DI->second; 311 } 312 313 return !(LastUse > LastDef && LastUse < Dist); 314} 315 316MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 317 MachineBasicBlock *MBB, 318 unsigned Dist) { 319 unsigned LastUseDist = Dist; 320 MachineInstr *LastUse = 0; 321 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 322 E = MRI->reg_end(); I != E; ++I) { 323 MachineOperand &MO = I.getOperand(); 324 MachineInstr *MI = MO.getParent(); 325 if (MI->getParent() != MBB) 326 continue; 327 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 328 if (DI == DistanceMap.end()) 329 continue; 330 if (MO.isUse() && DI->second < LastUseDist) { 331 LastUse = DI->first; 332 LastUseDist = DI->second; 333 } 334 } 335 return LastUse; 336} 337 338/// isCopyToReg - Return true if the specified MI is a copy instruction or 339/// a extract_subreg instruction. It also returns the source and destination 340/// registers and whether they are physical registers by reference. 341static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 342 unsigned &SrcReg, unsigned &DstReg, 343 bool &IsSrcPhys, bool &IsDstPhys) { 344 SrcReg = 0; 345 DstReg = 0; 346 unsigned SrcSubIdx, DstSubIdx; 347 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { 348 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { 349 DstReg = MI.getOperand(0).getReg(); 350 SrcReg = MI.getOperand(1).getReg(); 351 } else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) { 352 DstReg = MI.getOperand(0).getReg(); 353 SrcReg = MI.getOperand(2).getReg(); 354 } else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) { 355 DstReg = MI.getOperand(0).getReg(); 356 SrcReg = MI.getOperand(2).getReg(); 357 } 358 } 359 360 if (DstReg) { 361 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 362 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 363 return true; 364 } 365 return false; 366} 367 368/// isKilled - Test if the given register value, which is used by the given 369/// instruction, is killed by the given instruction. This looks through 370/// coalescable copies to see if the original value is potentially not killed. 371/// 372/// For example, in this code: 373/// 374/// %reg1034 = copy %reg1024 375/// %reg1035 = copy %reg1025<kill> 376/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 377/// 378/// %reg1034 is not considered to be killed, since it is copied from a 379/// register which is not killed. Treating it as not killed lets the 380/// normal heuristics commute the (two-address) add, which lets 381/// coalescing eliminate the extra copy. 382/// 383static bool isKilled(MachineInstr &MI, unsigned Reg, 384 const MachineRegisterInfo *MRI, 385 const TargetInstrInfo *TII) { 386 MachineInstr *DefMI = &MI; 387 for (;;) { 388 if (!DefMI->killsRegister(Reg)) 389 return false; 390 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 391 return true; 392 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 393 // If there are multiple defs, we can't do a simple analysis, so just 394 // go with what the kill flag says. 395 if (next(Begin) != MRI->def_end()) 396 return true; 397 DefMI = &*Begin; 398 bool IsSrcPhys, IsDstPhys; 399 unsigned SrcReg, DstReg; 400 // If the def is something other than a copy, then it isn't going to 401 // be coalesced, so follow the kill flag. 402 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 403 return true; 404 Reg = SrcReg; 405 } 406} 407 408/// isTwoAddrUse - Return true if the specified MI uses the specified register 409/// as a two-address use. If so, return the destination register by reference. 410static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 411 const TargetInstrDesc &TID = MI.getDesc(); 412 unsigned NumOps = (MI.getOpcode() == TargetInstrInfo::INLINEASM) 413 ? MI.getNumOperands() : TID.getNumOperands(); 414 for (unsigned i = 0; i != NumOps; ++i) { 415 const MachineOperand &MO = MI.getOperand(i); 416 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 417 continue; 418 unsigned ti; 419 if (MI.isRegTiedToDefOperand(i, &ti)) { 420 DstReg = MI.getOperand(ti).getReg(); 421 return true; 422 } 423 } 424 return false; 425} 426 427/// findOnlyInterestingUse - Given a register, if has a single in-basic block 428/// use, return the use instruction if it's a copy or a two-address use. 429static 430MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 431 MachineRegisterInfo *MRI, 432 const TargetInstrInfo *TII, 433 bool &IsCopy, 434 unsigned &DstReg, bool &IsDstPhys) { 435 MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg); 436 if (UI == MRI->use_end()) 437 return 0; 438 MachineInstr &UseMI = *UI; 439 if (++UI != MRI->use_end()) 440 // More than one use. 441 return 0; 442 if (UseMI.getParent() != MBB) 443 return 0; 444 unsigned SrcReg; 445 bool IsSrcPhys; 446 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 447 IsCopy = true; 448 return &UseMI; 449 } 450 IsDstPhys = false; 451 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 452 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 453 return &UseMI; 454 } 455 return 0; 456} 457 458/// getMappedReg - Return the physical register the specified virtual register 459/// might be mapped to. 460static unsigned 461getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 462 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 463 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 464 if (SI == RegMap.end()) 465 return 0; 466 Reg = SI->second; 467 } 468 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 469 return Reg; 470 return 0; 471} 472 473/// regsAreCompatible - Return true if the two registers are equal or aliased. 474/// 475static bool 476regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 477 if (RegA == RegB) 478 return true; 479 if (!RegA || !RegB) 480 return false; 481 return TRI->regsOverlap(RegA, RegB); 482} 483 484 485/// isProfitableToReMat - Return true if it's potentially profitable to commute 486/// the two-address instruction that's being processed. 487bool 488TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 489 MachineInstr *MI, MachineBasicBlock *MBB, 490 unsigned Dist) { 491 // Determine if it's profitable to commute this two address instruction. In 492 // general, we want no uses between this instruction and the definition of 493 // the two-address register. 494 // e.g. 495 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 496 // %reg1029<def> = MOV8rr %reg1028 497 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 498 // insert => %reg1030<def> = MOV8rr %reg1028 499 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 500 // In this case, it might not be possible to coalesce the second MOV8rr 501 // instruction if the first one is coalesced. So it would be profitable to 502 // commute it: 503 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 504 // %reg1029<def> = MOV8rr %reg1028 505 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 506 // insert => %reg1030<def> = MOV8rr %reg1029 507 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 508 509 if (!MI->killsRegister(regC)) 510 return false; 511 512 // Ok, we have something like: 513 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 514 // let's see if it's worth commuting it. 515 516 // Look for situations like this: 517 // %reg1024<def> = MOV r1 518 // %reg1025<def> = MOV r0 519 // %reg1026<def> = ADD %reg1024, %reg1025 520 // r0 = MOV %reg1026 521 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 522 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 523 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 524 unsigned ToRegB = getMappedReg(regB, DstRegMap); 525 unsigned ToRegC = getMappedReg(regC, DstRegMap); 526 if (!regsAreCompatible(FromRegB, ToRegB, TRI) && 527 (regsAreCompatible(FromRegB, ToRegC, TRI) || 528 regsAreCompatible(FromRegC, ToRegB, TRI))) 529 return true; 530 531 // If there is a use of regC between its last def (could be livein) and this 532 // instruction, then bail. 533 unsigned LastDefC = 0; 534 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 535 return false; 536 537 // If there is a use of regB between its last def (could be livein) and this 538 // instruction, then go ahead and make this transformation. 539 unsigned LastDefB = 0; 540 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 541 return true; 542 543 // Since there are no intervening uses for both registers, then commute 544 // if the def of regC is closer. Its live interval is shorter. 545 return LastDefB && LastDefC && LastDefC > LastDefB; 546} 547 548/// CommuteInstruction - Commute a two-address instruction and update the basic 549/// block, distance map, and live variables if needed. Return true if it is 550/// successful. 551bool 552TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 553 MachineFunction::iterator &mbbi, 554 unsigned RegB, unsigned RegC, unsigned Dist) { 555 MachineInstr *MI = mi; 556 DOUT << "2addr: COMMUTING : " << *MI; 557 MachineInstr *NewMI = TII->commuteInstruction(MI); 558 559 if (NewMI == 0) { 560 DOUT << "2addr: COMMUTING FAILED!\n"; 561 return false; 562 } 563 564 DOUT << "2addr: COMMUTED TO: " << *NewMI; 565 // If the instruction changed to commute it, update livevar. 566 if (NewMI != MI) { 567 if (LV) 568 // Update live variables 569 LV->replaceKillInstruction(RegC, MI, NewMI); 570 571 mbbi->insert(mi, NewMI); // Insert the new inst 572 mbbi->erase(mi); // Nuke the old inst. 573 mi = NewMI; 574 DistanceMap.insert(std::make_pair(NewMI, Dist)); 575 } 576 577 // Update source register map. 578 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 579 if (FromRegC) { 580 unsigned RegA = MI->getOperand(0).getReg(); 581 SrcRegMap[RegA] = FromRegC; 582 } 583 584 return true; 585} 586 587/// isProfitableToConv3Addr - Return true if it is profitable to convert the 588/// given 2-address instruction to a 3-address one. 589bool 590TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) { 591 // Look for situations like this: 592 // %reg1024<def> = MOV r1 593 // %reg1025<def> = MOV r0 594 // %reg1026<def> = ADD %reg1024, %reg1025 595 // r2 = MOV %reg1026 596 // Turn ADD into a 3-address instruction to avoid a copy. 597 unsigned FromRegA = getMappedReg(RegA, SrcRegMap); 598 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 599 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI)); 600} 601 602/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 603/// three address one. Return true if this transformation was successful. 604bool 605TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 606 MachineBasicBlock::iterator &nmi, 607 MachineFunction::iterator &mbbi, 608 unsigned RegB, unsigned Dist) { 609 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 610 if (NewMI) { 611 DOUT << "2addr: CONVERTING 2-ADDR: " << *mi; 612 DOUT << "2addr: TO 3-ADDR: " << *NewMI; 613 bool Sunk = false; 614 615 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 616 // FIXME: Temporary workaround. If the new instruction doesn't 617 // uses RegB, convertToThreeAddress must have created more 618 // then one instruction. 619 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 620 621 mbbi->erase(mi); // Nuke the old inst. 622 623 if (!Sunk) { 624 DistanceMap.insert(std::make_pair(NewMI, Dist)); 625 mi = NewMI; 626 nmi = next(mi); 627 } 628 return true; 629 } 630 631 return false; 632} 633 634/// ProcessCopy - If the specified instruction is not yet processed, process it 635/// if it's a copy. For a copy instruction, we find the physical registers the 636/// source and destination registers might be mapped to. These are kept in 637/// point-to maps used to determine future optimizations. e.g. 638/// v1024 = mov r0 639/// v1025 = mov r1 640/// v1026 = add v1024, v1025 641/// r1 = mov r1026 642/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 643/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 644/// potentially joined with r1 on the output side. It's worthwhile to commute 645/// 'add' to eliminate a copy. 646void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 647 MachineBasicBlock *MBB, 648 SmallPtrSet<MachineInstr*, 8> &Processed) { 649 if (Processed.count(MI)) 650 return; 651 652 bool IsSrcPhys, IsDstPhys; 653 unsigned SrcReg, DstReg; 654 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 655 return; 656 657 if (IsDstPhys && !IsSrcPhys) 658 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 659 else if (!IsDstPhys && IsSrcPhys) { 660 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 661 if (!isNew) 662 assert(SrcRegMap[DstReg] == SrcReg && 663 "Can't map to two src physical registers!"); 664 665 SmallVector<unsigned, 4> VirtRegPairs; 666 bool IsCopy = false; 667 unsigned NewReg = 0; 668 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII, 669 IsCopy, NewReg, IsDstPhys)) { 670 if (IsCopy) { 671 if (!Processed.insert(UseMI)) 672 break; 673 } 674 675 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 676 if (DI != DistanceMap.end()) 677 // Earlier in the same MBB.Reached via a back edge. 678 break; 679 680 if (IsDstPhys) { 681 VirtRegPairs.push_back(NewReg); 682 break; 683 } 684 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second; 685 if (!isNew) 686 assert(SrcRegMap[NewReg] == DstReg && 687 "Can't map to two src physical registers!"); 688 VirtRegPairs.push_back(NewReg); 689 DstReg = NewReg; 690 } 691 692 if (!VirtRegPairs.empty()) { 693 unsigned ToReg = VirtRegPairs.back(); 694 VirtRegPairs.pop_back(); 695 while (!VirtRegPairs.empty()) { 696 unsigned FromReg = VirtRegPairs.back(); 697 VirtRegPairs.pop_back(); 698 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 699 if (!isNew) 700 assert(DstRegMap[FromReg] == ToReg && 701 "Can't map to two dst physical registers!"); 702 ToReg = FromReg; 703 } 704 } 705 } 706 707 Processed.insert(MI); 708} 709 710/// isSafeToDelete - If the specified instruction does not produce any side 711/// effects and all of its defs are dead, then it's safe to delete. 712static bool isSafeToDelete(MachineInstr *MI, unsigned Reg, 713 const TargetInstrInfo *TII, 714 SmallVector<unsigned, 4> &Kills) { 715 const TargetInstrDesc &TID = MI->getDesc(); 716 if (TID.mayStore() || TID.isCall()) 717 return false; 718 if (TID.isTerminator() || TID.hasUnmodeledSideEffects()) 719 return false; 720 721 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 722 MachineOperand &MO = MI->getOperand(i); 723 if (!MO.isReg()) 724 continue; 725 if (MO.isDef() && !MO.isDead()) 726 return false; 727 if (MO.isUse() && MO.getReg() != Reg && MO.isKill()) 728 Kills.push_back(MO.getReg()); 729 } 730 731 return true; 732} 733 734/// runOnMachineFunction - Reduce two-address instructions to two operands. 735/// 736bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 737 DOUT << "Machine Function\n"; 738 const TargetMachine &TM = MF.getTarget(); 739 MRI = &MF.getRegInfo(); 740 TII = TM.getInstrInfo(); 741 TRI = TM.getRegisterInfo(); 742 LV = getAnalysisIfAvailable<LiveVariables>(); 743 744 bool MadeChange = false; 745 746 DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n"; 747 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 748 749 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 750 BitVector ReMatRegs; 751 ReMatRegs.resize(MRI->getLastVirtReg()+1); 752 753 SmallPtrSet<MachineInstr*, 8> Processed; 754 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 755 mbbi != mbbe; ++mbbi) { 756 unsigned Dist = 0; 757 DistanceMap.clear(); 758 SrcRegMap.clear(); 759 DstRegMap.clear(); 760 Processed.clear(); 761 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 762 mi != me; ) { 763 MachineBasicBlock::iterator nmi = next(mi); 764 const TargetInstrDesc &TID = mi->getDesc(); 765 bool FirstTied = true; 766 767 DistanceMap.insert(std::make_pair(mi, ++Dist)); 768 769 ProcessCopy(&*mi, &*mbbi, Processed); 770 771 unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM) 772 ? mi->getNumOperands() : TID.getNumOperands(); 773 for (unsigned si = 0; si < NumOps; ++si) { 774 unsigned ti = 0; 775 if (!mi->isRegTiedToDefOperand(si, &ti)) 776 continue; 777 778 if (FirstTied) { 779 ++NumTwoAddressInstrs; 780 DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM)); 781 } 782 783 FirstTied = false; 784 785 assert(mi->getOperand(si).isReg() && mi->getOperand(si).getReg() && 786 mi->getOperand(si).isUse() && "two address instruction invalid"); 787 788 // If the two operands are the same we just remove the use 789 // and mark the def as def&use, otherwise we have to insert a copy. 790 if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) { 791 // Rewrite: 792 // a = b op c 793 // to: 794 // a = b 795 // a = a op c 796 unsigned regA = mi->getOperand(ti).getReg(); 797 unsigned regB = mi->getOperand(si).getReg(); 798 799 assert(TargetRegisterInfo::isVirtualRegister(regB) && 800 "cannot update physical register live information"); 801 802#ifndef NDEBUG 803 // First, verify that we don't have a use of a in the instruction (a = 804 // b + a for example) because our transformation will not work. This 805 // should never occur because we are in SSA form. 806 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 807 assert(i == ti || 808 !mi->getOperand(i).isReg() || 809 mi->getOperand(i).getReg() != regA); 810#endif 811 812 // If this instruction is not the killing user of B, see if we can 813 // rearrange the code to make it so. Making it the killing user will 814 // allow us to coalesce A and B together, eliminating the copy we are 815 // about to insert. 816 if (!isKilled(*mi, regB, MRI, TII)) { 817 // If regA is dead and the instruction can be deleted, just delete 818 // it so it doesn't clobber regB. 819 SmallVector<unsigned, 4> Kills; 820 if (mi->getOperand(ti).isDead() && 821 isSafeToDelete(mi, regB, TII, Kills)) { 822 SmallVector<std::pair<std::pair<unsigned, bool> 823 ,MachineInstr*>, 4> NewKills; 824 bool ReallySafe = true; 825 // If this instruction kills some virtual registers, we need 826 // update the kill information. If it's not possible to do so, 827 // then bail out. 828 while (!Kills.empty()) { 829 unsigned Kill = Kills.back(); 830 Kills.pop_back(); 831 if (TargetRegisterInfo::isPhysicalRegister(Kill)) { 832 ReallySafe = false; 833 break; 834 } 835 MachineInstr *LastKill = FindLastUseInMBB(Kill, &*mbbi, Dist); 836 if (LastKill) { 837 bool isModRef = LastKill->modifiesRegister(Kill); 838 NewKills.push_back(std::make_pair(std::make_pair(Kill,isModRef), 839 LastKill)); 840 } else { 841 ReallySafe = false; 842 break; 843 } 844 } 845 846 if (ReallySafe) { 847 if (LV) { 848 while (!NewKills.empty()) { 849 MachineInstr *NewKill = NewKills.back().second; 850 unsigned Kill = NewKills.back().first.first; 851 bool isDead = NewKills.back().first.second; 852 NewKills.pop_back(); 853 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 854 if (isDead) 855 LV->addVirtualRegisterDead(Kill, NewKill); 856 else 857 LV->addVirtualRegisterKilled(Kill, NewKill); 858 } 859 } 860 } 861 862 // We're really going to nuke the old inst. If regB was marked 863 // as a kill we need to update its Kills list. 864 if (mi->getOperand(si).isKill()) 865 LV->removeVirtualRegisterKilled(regB, mi); 866 867 mbbi->erase(mi); // Nuke the old inst. 868 mi = nmi; 869 ++NumDeletes; 870 break; // Done with this instruction. 871 } 872 } 873 874 // If this instruction is commutative, check to see if C dies. If 875 // so, swap the B and C operands. This makes the live ranges of A 876 // and C joinable. 877 // FIXME: This code also works for A := B op C instructions. 878 if (TID.isCommutable() && mi->getNumOperands() >= 3) { 879 assert(mi->getOperand(3-si).isReg() && 880 "Not a proper commutative instruction!"); 881 unsigned regC = mi->getOperand(3-si).getReg(); 882 if (isKilled(*mi, regC, MRI, TII)) { 883 if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 884 ++NumCommuted; 885 regB = regC; 886 goto InstructionRearranged; 887 } 888 } 889 } 890 891 // If this instruction is potentially convertible to a true 892 // three-address instruction, 893 if (TID.isConvertibleTo3Addr()) { 894 // FIXME: This assumes there are no more operands which are tied 895 // to another register. 896#ifndef NDEBUG 897 for (unsigned i = si + 1, e = TID.getNumOperands(); i < e; ++i) 898 assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1); 899#endif 900 901 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) { 902 ++NumConvertedTo3Addr; 903 break; // Done with this instruction. 904 } 905 } 906 } 907 908 // If it's profitable to commute the instruction, do so. 909 if (TID.isCommutable() && mi->getNumOperands() >= 3) { 910 unsigned regC = mi->getOperand(3-si).getReg(); 911 if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) 912 if (CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 913 ++NumAggrCommuted; 914 ++NumCommuted; 915 regB = regC; 916 goto InstructionRearranged; 917 } 918 } 919 920 // If it's profitable to convert the 2-address instruction to a 921 // 3-address one, do so. 922 if (TID.isConvertibleTo3Addr() && isProfitableToConv3Addr(regA)) { 923 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) { 924 ++NumConvertedTo3Addr; 925 break; // Done with this instruction. 926 } 927 } 928 929 InstructionRearranged: 930 const TargetRegisterClass* rc = MRI->getRegClass(regB); 931 MachineInstr *DefMI = MRI->getVRegDef(regB); 932 // If it's safe and profitable, remat the definition instead of 933 // copying it. 934 if (DefMI && 935 DefMI->getDesc().isAsCheapAsAMove() && 936 DefMI->isSafeToReMat(TII, regB) && 937 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 938 DEBUG(cerr << "2addr: REMATTING : " << *DefMI << "\n"); 939 TII->reMaterialize(*mbbi, mi, regA, DefMI); 940 ReMatRegs.set(regB); 941 ++NumReMats; 942 } else { 943 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc); 944 (void)Emitted; 945 assert(Emitted && "Unable to issue a copy instruction!\n"); 946 } 947 948 MachineBasicBlock::iterator prevMI = prior(mi); 949 // Update DistanceMap. 950 DistanceMap.insert(std::make_pair(prevMI, Dist)); 951 DistanceMap[mi] = ++Dist; 952 953 // Update live variables for regB. 954 if (LV) { 955 LiveVariables::VarInfo& varInfoB = LV->getVarInfo(regB); 956 957 // regB is used in this BB. 958 varInfoB.UsedBlocks[mbbi->getNumber()] = true; 959 960 if (LV->removeVirtualRegisterKilled(regB, mi)) 961 LV->addVirtualRegisterKilled(regB, prevMI); 962 963 if (LV->removeVirtualRegisterDead(regB, mi)) 964 LV->addVirtualRegisterDead(regB, prevMI); 965 } 966 967 DOUT << "\t\tprepend:\t"; DEBUG(prevMI->print(*cerr.stream(), &TM)); 968 969 // Replace all occurences of regB with regA. 970 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 971 if (mi->getOperand(i).isReg() && 972 mi->getOperand(i).getReg() == regB) 973 mi->getOperand(i).setReg(regA); 974 } 975 } 976 977 assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse()); 978 mi->getOperand(ti).setReg(mi->getOperand(si).getReg()); 979 MadeChange = true; 980 981 DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM)); 982 } 983 984 mi = nmi; 985 } 986 } 987 988 // Some remat'ed instructions are dead. 989 int VReg = ReMatRegs.find_first(); 990 while (VReg != -1) { 991 if (MRI->use_empty(VReg)) { 992 MachineInstr *DefMI = MRI->getVRegDef(VReg); 993 DefMI->eraseFromParent(); 994 } 995 VReg = ReMatRegs.find_next(VReg); 996 } 997 998 return MadeChange; 999} 1000