TwoAddressInstructionPass.cpp revision f5a86f45e75ec744c203270ffa03659eb0a220c1 
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TwoAddress instruction pass which is used
11// by most register allocators. Two-Address instructions are rewritten
12// from:
13//
14//     A = B op C
15//
16// to:
17//
18//     A = B
19//     A op= C
20//
21// Note that if a register allocator chooses to use this pass, that it
22// has to be capable of handling the non-SSA nature of these rewritten
23// virtual registers.
24//
25// It is also worth noting that the duplicate operand of the two
26// address instruction is removed.
27//
28//===----------------------------------------------------------------------===//
29
30#define DEBUG_TYPE "twoaddrinstr"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/Function.h"
33#include "llvm/CodeGen/LiveVariables.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/Analysis/AliasAnalysis.h"
38#include "llvm/Target/TargetRegisterInfo.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetOptions.h"
42#include "llvm/Support/Debug.h"
43#include "llvm/ADT/BitVector.h"
44#include "llvm/ADT/DenseMap.h"
45#include "llvm/ADT/SmallSet.h"
46#include "llvm/ADT/Statistic.h"
47#include "llvm/ADT/STLExtras.h"
48using namespace llvm;
49
50STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
51STATISTIC(NumCommuted        , "Number of instructions commuted to coalesce");
52STATISTIC(NumAggrCommuted    , "Number of instructions aggressively commuted");
53STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
54STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
55STATISTIC(NumReMats,           "Number of instructions re-materialized");
56STATISTIC(NumDeletes,          "Number of dead instructions deleted");
57
58namespace {
59  class TwoAddressInstructionPass : public MachineFunctionPass {
60    const TargetInstrInfo *TII;
61    const TargetRegisterInfo *TRI;
62    MachineRegisterInfo *MRI;
63    LiveVariables *LV;
64    AliasAnalysis *AA;
65
66    // DistanceMap - Keep track the distance of a MI from the start of the
67    // current basic block.
68    DenseMap<MachineInstr*, unsigned> DistanceMap;
69
70    // SrcRegMap - A map from virtual registers to physical registers which
71    // are likely targets to be coalesced to due to copies from physical
72    // registers to virtual registers. e.g. v1024 = move r0.
73    DenseMap<unsigned, unsigned> SrcRegMap;
74
75    // DstRegMap - A map from virtual registers to physical registers which
76    // are likely targets to be coalesced to due to copies to physical
77    // registers from virtual registers. e.g. r1 = move v1024.
78    DenseMap<unsigned, unsigned> DstRegMap;
79
80    bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
81                              unsigned Reg,
82                              MachineBasicBlock::iterator OldPos);
83
84    bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
85                             MachineInstr *MI, MachineInstr *DefMI,
86                             MachineBasicBlock *MBB, unsigned Loc);
87
88    bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
89                           unsigned &LastDef);
90
91    MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
92                                   unsigned Dist);
93
94    bool isProfitableToCommute(unsigned regB, unsigned regC,
95                               MachineInstr *MI, MachineBasicBlock *MBB,
96                               unsigned Dist);
97
98    bool CommuteInstruction(MachineBasicBlock::iterator &mi,
99                            MachineFunction::iterator &mbbi,
100                            unsigned RegB, unsigned RegC, unsigned Dist);
101
102    bool isProfitableToConv3Addr(unsigned RegA);
103
104    bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
105                            MachineBasicBlock::iterator &nmi,
106                            MachineFunction::iterator &mbbi,
107                            unsigned RegB, unsigned Dist);
108
109    typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
110    bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
111                               SmallVector<NewKill, 4> &NewKills,
112                               MachineBasicBlock *MBB, unsigned Dist);
113    bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
114                           MachineBasicBlock::iterator &nmi,
115                           MachineFunction::iterator &mbbi,
116                           unsigned regB, unsigned regBIdx, unsigned Dist);
117
118    bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
119                                 MachineBasicBlock::iterator &nmi,
120                                 MachineFunction::iterator &mbbi,
121                                 unsigned SrcIdx, unsigned DstIdx,
122                                 unsigned Dist);
123
124    void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
125                     SmallPtrSet<MachineInstr*, 8> &Processed);
126
127  public:
128    static char ID; // Pass identification, replacement for typeid
129    TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
130
131    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
132      AU.setPreservesCFG();
133      AU.addRequired<AliasAnalysis>();
134      AU.addPreserved<LiveVariables>();
135      AU.addPreservedID(MachineLoopInfoID);
136      AU.addPreservedID(MachineDominatorsID);
137      if (StrongPHIElim)
138        AU.addPreservedID(StrongPHIEliminationID);
139      else
140        AU.addPreservedID(PHIEliminationID);
141      MachineFunctionPass::getAnalysisUsage(AU);
142    }
143
144    /// runOnMachineFunction - Pass entry point.
145    bool runOnMachineFunction(MachineFunction&);
146  };
147}
148
149char TwoAddressInstructionPass::ID = 0;
150static RegisterPass<TwoAddressInstructionPass>
151X("twoaddressinstruction", "Two-Address instruction pass");
152
153const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
154
155/// Sink3AddrInstruction - A two-address instruction has been converted to a
156/// three-address instruction to avoid clobbering a register. Try to sink it
157/// past the instruction that would kill the above mentioned register to reduce
158/// register pressure.
159bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
160                                           MachineInstr *MI, unsigned SavedReg,
161                                           MachineBasicBlock::iterator OldPos) {
162  // Check if it's safe to move this instruction.
163  bool SeenStore = true; // Be conservative.
164  if (!MI->isSafeToMove(TII, SeenStore, AA))
165    return false;
166
167  unsigned DefReg = 0;
168  SmallSet<unsigned, 4> UseRegs;
169
170  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
171    const MachineOperand &MO = MI->getOperand(i);
172    if (!MO.isReg())
173      continue;
174    unsigned MOReg = MO.getReg();
175    if (!MOReg)
176      continue;
177    if (MO.isUse() && MOReg != SavedReg)
178      UseRegs.insert(MO.getReg());
179    if (!MO.isDef())
180      continue;
181    if (MO.isImplicit())
182      // Don't try to move it if it implicitly defines a register.
183      return false;
184    if (DefReg)
185      // For now, don't move any instructions that define multiple registers.
186      return false;
187    DefReg = MO.getReg();
188  }
189
190  // Find the instruction that kills SavedReg.
191  MachineInstr *KillMI = NULL;
192  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
193         UE = MRI->use_end(); UI != UE; ++UI) {
194    MachineOperand &UseMO = UI.getOperand();
195    if (!UseMO.isKill())
196      continue;
197    KillMI = UseMO.getParent();
198    break;
199  }
200
201  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
202    return false;
203
204  // If any of the definitions are used by another instruction between the
205  // position and the kill use, then it's not safe to sink it.
206  //
207  // FIXME: This can be sped up if there is an easy way to query whether an
208  // instruction is before or after another instruction. Then we can use
209  // MachineRegisterInfo def / use instead.
210  MachineOperand *KillMO = NULL;
211  MachineBasicBlock::iterator KillPos = KillMI;
212  ++KillPos;
213
214  unsigned NumVisited = 0;
215  for (MachineBasicBlock::iterator I = next(OldPos); I != KillPos; ++I) {
216    MachineInstr *OtherMI = I;
217    if (NumVisited > 30)  // FIXME: Arbitrary limit to reduce compile time cost.
218      return false;
219    ++NumVisited;
220    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
221      MachineOperand &MO = OtherMI->getOperand(i);
222      if (!MO.isReg())
223        continue;
224      unsigned MOReg = MO.getReg();
225      if (!MOReg)
226        continue;
227      if (DefReg == MOReg)
228        return false;
229
230      if (MO.isKill()) {
231        if (OtherMI == KillMI && MOReg == SavedReg)
232          // Save the operand that kills the register. We want to unset the kill
233          // marker if we can sink MI past it.
234          KillMO = &MO;
235        else if (UseRegs.count(MOReg))
236          // One of the uses is killed before the destination.
237          return false;
238      }
239    }
240  }
241
242  // Update kill and LV information.
243  KillMO->setIsKill(false);
244  KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
245  KillMO->setIsKill(true);
246
247  if (LV)
248    LV->replaceKillInstruction(SavedReg, KillMI, MI);
249
250  // Move instruction to its destination.
251  MBB->remove(MI);
252  MBB->insert(KillPos, MI);
253
254  ++Num3AddrSunk;
255  return true;
256}
257
258/// isTwoAddrUse - Return true if the specified MI is using the specified
259/// register as a two-address operand.
260static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
261  const TargetInstrDesc &TID = UseMI->getDesc();
262  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
263    MachineOperand &MO = UseMI->getOperand(i);
264    if (MO.isReg() && MO.getReg() == Reg &&
265        (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
266      // Earlier use is a two-address one.
267      return true;
268  }
269  return false;
270}
271
272/// isProfitableToReMat - Return true if the heuristics determines it is likely
273/// to be profitable to re-materialize the definition of Reg rather than copy
274/// the register.
275bool
276TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
277                                         const TargetRegisterClass *RC,
278                                         MachineInstr *MI, MachineInstr *DefMI,
279                                         MachineBasicBlock *MBB, unsigned Loc) {
280  bool OtherUse = false;
281  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
282         UE = MRI->use_end(); UI != UE; ++UI) {
283    MachineOperand &UseMO = UI.getOperand();
284    MachineInstr *UseMI = UseMO.getParent();
285    MachineBasicBlock *UseMBB = UseMI->getParent();
286    if (UseMBB == MBB) {
287      DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
288      if (DI != DistanceMap.end() && DI->second == Loc)
289        continue;  // Current use.
290      OtherUse = true;
291      // There is at least one other use in the MBB that will clobber the
292      // register.
293      if (isTwoAddrUse(UseMI, Reg))
294        return true;
295    }
296  }
297
298  // If other uses in MBB are not two-address uses, then don't remat.
299  if (OtherUse)
300    return false;
301
302  // No other uses in the same block, remat if it's defined in the same
303  // block so it does not unnecessarily extend the live range.
304  return MBB == DefMI->getParent();
305}
306
307/// NoUseAfterLastDef - Return true if there are no intervening uses between the
308/// last instruction in the MBB that defines the specified register and the
309/// two-address instruction which is being processed. It also returns the last
310/// def location by reference
311bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
312                                           MachineBasicBlock *MBB, unsigned Dist,
313                                           unsigned &LastDef) {
314  LastDef = 0;
315  unsigned LastUse = Dist;
316  for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
317         E = MRI->reg_end(); I != E; ++I) {
318    MachineOperand &MO = I.getOperand();
319    MachineInstr *MI = MO.getParent();
320    if (MI->getParent() != MBB)
321      continue;
322    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
323    if (DI == DistanceMap.end())
324      continue;
325    if (MO.isUse() && DI->second < LastUse)
326      LastUse = DI->second;
327    if (MO.isDef() && DI->second > LastDef)
328      LastDef = DI->second;
329  }
330
331  return !(LastUse > LastDef && LastUse < Dist);
332}
333
334MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
335                                                         MachineBasicBlock *MBB,
336                                                         unsigned Dist) {
337  unsigned LastUseDist = 0;
338  MachineInstr *LastUse = 0;
339  for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
340         E = MRI->reg_end(); I != E; ++I) {
341    MachineOperand &MO = I.getOperand();
342    MachineInstr *MI = MO.getParent();
343    if (MI->getParent() != MBB)
344      continue;
345    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
346    if (DI == DistanceMap.end())
347      continue;
348    if (DI->second >= Dist)
349      continue;
350
351    if (MO.isUse() && DI->second > LastUseDist) {
352      LastUse = DI->first;
353      LastUseDist = DI->second;
354    }
355  }
356  return LastUse;
357}
358
359/// isCopyToReg - Return true if the specified MI is a copy instruction or
360/// a extract_subreg instruction. It also returns the source and destination
361/// registers and whether they are physical registers by reference.
362static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
363                        unsigned &SrcReg, unsigned &DstReg,
364                        bool &IsSrcPhys, bool &IsDstPhys) {
365  SrcReg = 0;
366  DstReg = 0;
367  unsigned SrcSubIdx, DstSubIdx;
368  if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
369    if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
370      DstReg = MI.getOperand(0).getReg();
371      SrcReg = MI.getOperand(1).getReg();
372    } else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
373      DstReg = MI.getOperand(0).getReg();
374      SrcReg = MI.getOperand(2).getReg();
375    } else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
376      DstReg = MI.getOperand(0).getReg();
377      SrcReg = MI.getOperand(2).getReg();
378    }
379  }
380
381  if (DstReg) {
382    IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
383    IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
384    return true;
385  }
386  return false;
387}
388
389/// isKilled - Test if the given register value, which is used by the given
390/// instruction, is killed by the given instruction. This looks through
391/// coalescable copies to see if the original value is potentially not killed.
392///
393/// For example, in this code:
394///
395///   %reg1034 = copy %reg1024
396///   %reg1035 = copy %reg1025<kill>
397///   %reg1036 = add %reg1034<kill>, %reg1035<kill>
398///
399/// %reg1034 is not considered to be killed, since it is copied from a
400/// register which is not killed. Treating it as not killed lets the
401/// normal heuristics commute the (two-address) add, which lets
402/// coalescing eliminate the extra copy.
403///
404static bool isKilled(MachineInstr &MI, unsigned Reg,
405                     const MachineRegisterInfo *MRI,
406                     const TargetInstrInfo *TII) {
407  MachineInstr *DefMI = &MI;
408  for (;;) {
409    if (!DefMI->killsRegister(Reg))
410      return false;
411    if (TargetRegisterInfo::isPhysicalRegister(Reg))
412      return true;
413    MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
414    // If there are multiple defs, we can't do a simple analysis, so just
415    // go with what the kill flag says.
416    if (next(Begin) != MRI->def_end())
417      return true;
418    DefMI = &*Begin;
419    bool IsSrcPhys, IsDstPhys;
420    unsigned SrcReg,  DstReg;
421    // If the def is something other than a copy, then it isn't going to
422    // be coalesced, so follow the kill flag.
423    if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
424      return true;
425    Reg = SrcReg;
426  }
427}
428
429/// isTwoAddrUse - Return true if the specified MI uses the specified register
430/// as a two-address use. If so, return the destination register by reference.
431static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
432  const TargetInstrDesc &TID = MI.getDesc();
433  unsigned NumOps = (MI.getOpcode() == TargetInstrInfo::INLINEASM)
434    ? MI.getNumOperands() : TID.getNumOperands();
435  for (unsigned i = 0; i != NumOps; ++i) {
436    const MachineOperand &MO = MI.getOperand(i);
437    if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
438      continue;
439    unsigned ti;
440    if (MI.isRegTiedToDefOperand(i, &ti)) {
441      DstReg = MI.getOperand(ti).getReg();
442      return true;
443    }
444  }
445  return false;
446}
447
448/// findOnlyInterestingUse - Given a register, if has a single in-basic block
449/// use, return the use instruction if it's a copy or a two-address use.
450static
451MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
452                                     MachineRegisterInfo *MRI,
453                                     const TargetInstrInfo *TII,
454                                     bool &IsCopy,
455                                     unsigned &DstReg, bool &IsDstPhys) {
456  MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
457  if (UI == MRI->use_end())
458    return 0;
459  MachineInstr &UseMI = *UI;
460  if (++UI != MRI->use_end())
461    // More than one use.
462    return 0;
463  if (UseMI.getParent() != MBB)
464    return 0;
465  unsigned SrcReg;
466  bool IsSrcPhys;
467  if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
468    IsCopy = true;
469    return &UseMI;
470  }
471  IsDstPhys = false;
472  if (isTwoAddrUse(UseMI, Reg, DstReg)) {
473    IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
474    return &UseMI;
475  }
476  return 0;
477}
478
479/// getMappedReg - Return the physical register the specified virtual register
480/// might be mapped to.
481static unsigned
482getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
483  while (TargetRegisterInfo::isVirtualRegister(Reg))  {
484    DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
485    if (SI == RegMap.end())
486      return 0;
487    Reg = SI->second;
488  }
489  if (TargetRegisterInfo::isPhysicalRegister(Reg))
490    return Reg;
491  return 0;
492}
493
494/// regsAreCompatible - Return true if the two registers are equal or aliased.
495///
496static bool
497regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
498  if (RegA == RegB)
499    return true;
500  if (!RegA || !RegB)
501    return false;
502  return TRI->regsOverlap(RegA, RegB);
503}
504
505
506/// isProfitableToReMat - Return true if it's potentially profitable to commute
507/// the two-address instruction that's being processed.
508bool
509TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
510                                       MachineInstr *MI, MachineBasicBlock *MBB,
511                                       unsigned Dist) {
512  // Determine if it's profitable to commute this two address instruction. In
513  // general, we want no uses between this instruction and the definition of
514  // the two-address register.
515  // e.g.
516  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
517  // %reg1029<def> = MOV8rr %reg1028
518  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
519  // insert => %reg1030<def> = MOV8rr %reg1028
520  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
521  // In this case, it might not be possible to coalesce the second MOV8rr
522  // instruction if the first one is coalesced. So it would be profitable to
523  // commute it:
524  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
525  // %reg1029<def> = MOV8rr %reg1028
526  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
527  // insert => %reg1030<def> = MOV8rr %reg1029
528  // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
529
530  if (!MI->killsRegister(regC))
531    return false;
532
533  // Ok, we have something like:
534  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
535  // let's see if it's worth commuting it.
536
537  // Look for situations like this:
538  // %reg1024<def> = MOV r1
539  // %reg1025<def> = MOV r0
540  // %reg1026<def> = ADD %reg1024, %reg1025
541  // r0            = MOV %reg1026
542  // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
543  unsigned FromRegB = getMappedReg(regB, SrcRegMap);
544  unsigned FromRegC = getMappedReg(regC, SrcRegMap);
545  unsigned ToRegB = getMappedReg(regB, DstRegMap);
546  unsigned ToRegC = getMappedReg(regC, DstRegMap);
547  if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
548      (regsAreCompatible(FromRegB, ToRegC, TRI) ||
549       regsAreCompatible(FromRegC, ToRegB, TRI)))
550    return true;
551
552  // If there is a use of regC between its last def (could be livein) and this
553  // instruction, then bail.
554  unsigned LastDefC = 0;
555  if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
556    return false;
557
558  // If there is a use of regB between its last def (could be livein) and this
559  // instruction, then go ahead and make this transformation.
560  unsigned LastDefB = 0;
561  if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
562    return true;
563
564  // Since there are no intervening uses for both registers, then commute
565  // if the def of regC is closer. Its live interval is shorter.
566  return LastDefB && LastDefC && LastDefC > LastDefB;
567}
568
569/// CommuteInstruction - Commute a two-address instruction and update the basic
570/// block, distance map, and live variables if needed. Return true if it is
571/// successful.
572bool
573TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
574                               MachineFunction::iterator &mbbi,
575                               unsigned RegB, unsigned RegC, unsigned Dist) {
576  MachineInstr *MI = mi;
577  DEBUG(errs() << "2addr: COMMUTING  : " << *MI);
578  MachineInstr *NewMI = TII->commuteInstruction(MI);
579
580  if (NewMI == 0) {
581    DEBUG(errs() << "2addr: COMMUTING FAILED!\n");
582    return false;
583  }
584
585  DEBUG(errs() << "2addr: COMMUTED TO: " << *NewMI);
586  // If the instruction changed to commute it, update livevar.
587  if (NewMI != MI) {
588    if (LV)
589      // Update live variables
590      LV->replaceKillInstruction(RegC, MI, NewMI);
591
592    mbbi->insert(mi, NewMI);           // Insert the new inst
593    mbbi->erase(mi);                   // Nuke the old inst.
594    mi = NewMI;
595    DistanceMap.insert(std::make_pair(NewMI, Dist));
596  }
597
598  // Update source register map.
599  unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
600  if (FromRegC) {
601    unsigned RegA = MI->getOperand(0).getReg();
602    SrcRegMap[RegA] = FromRegC;
603  }
604
605  return true;
606}
607
608/// isProfitableToConv3Addr - Return true if it is profitable to convert the
609/// given 2-address instruction to a 3-address one.
610bool
611TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
612  // Look for situations like this:
613  // %reg1024<def> = MOV r1
614  // %reg1025<def> = MOV r0
615  // %reg1026<def> = ADD %reg1024, %reg1025
616  // r2            = MOV %reg1026
617  // Turn ADD into a 3-address instruction to avoid a copy.
618  unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
619  unsigned ToRegA = getMappedReg(RegA, DstRegMap);
620  return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
621}
622
623/// ConvertInstTo3Addr - Convert the specified two-address instruction into a
624/// three address one. Return true if this transformation was successful.
625bool
626TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
627                                              MachineBasicBlock::iterator &nmi,
628                                              MachineFunction::iterator &mbbi,
629                                              unsigned RegB, unsigned Dist) {
630  MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
631  if (NewMI) {
632    DEBUG(errs() << "2addr: CONVERTING 2-ADDR: " << *mi);
633    DEBUG(errs() << "2addr:         TO 3-ADDR: " << *NewMI);
634    bool Sunk = false;
635
636    if (NewMI->findRegisterUseOperand(RegB, false, TRI))
637      // FIXME: Temporary workaround. If the new instruction doesn't
638      // uses RegB, convertToThreeAddress must have created more
639      // then one instruction.
640      Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
641
642    mbbi->erase(mi); // Nuke the old inst.
643
644    if (!Sunk) {
645      DistanceMap.insert(std::make_pair(NewMI, Dist));
646      mi = NewMI;
647      nmi = next(mi);
648    }
649    return true;
650  }
651
652  return false;
653}
654
655/// ProcessCopy - If the specified instruction is not yet processed, process it
656/// if it's a copy. For a copy instruction, we find the physical registers the
657/// source and destination registers might be mapped to. These are kept in
658/// point-to maps used to determine future optimizations. e.g.
659/// v1024 = mov r0
660/// v1025 = mov r1
661/// v1026 = add v1024, v1025
662/// r1    = mov r1026
663/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
664/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
665/// potentially joined with r1 on the output side. It's worthwhile to commute
666/// 'add' to eliminate a copy.
667void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
668                                     MachineBasicBlock *MBB,
669                                     SmallPtrSet<MachineInstr*, 8> &Processed) {
670  if (Processed.count(MI))
671    return;
672
673  bool IsSrcPhys, IsDstPhys;
674  unsigned SrcReg, DstReg;
675  if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
676    return;
677
678  if (IsDstPhys && !IsSrcPhys)
679    DstRegMap.insert(std::make_pair(SrcReg, DstReg));
680  else if (!IsDstPhys && IsSrcPhys) {
681    bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
682    if (!isNew)
683      assert(SrcRegMap[DstReg] == SrcReg &&
684             "Can't map to two src physical registers!");
685
686    SmallVector<unsigned, 4> VirtRegPairs;
687    bool IsCopy = false;
688    unsigned NewReg = 0;
689    while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
690                                                   IsCopy, NewReg, IsDstPhys)) {
691      if (IsCopy) {
692        if (!Processed.insert(UseMI))
693          break;
694      }
695
696      DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
697      if (DI != DistanceMap.end())
698        // Earlier in the same MBB.Reached via a back edge.
699        break;
700
701      if (IsDstPhys) {
702        VirtRegPairs.push_back(NewReg);
703        break;
704      }
705      bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
706      if (!isNew)
707        assert(SrcRegMap[NewReg] == DstReg &&
708               "Can't map to two src physical registers!");
709      VirtRegPairs.push_back(NewReg);
710      DstReg = NewReg;
711    }
712
713    if (!VirtRegPairs.empty()) {
714      unsigned ToReg = VirtRegPairs.back();
715      VirtRegPairs.pop_back();
716      while (!VirtRegPairs.empty()) {
717        unsigned FromReg = VirtRegPairs.back();
718        VirtRegPairs.pop_back();
719        bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
720        if (!isNew)
721          assert(DstRegMap[FromReg] == ToReg &&
722                 "Can't map to two dst physical registers!");
723        ToReg = FromReg;
724      }
725    }
726  }
727
728  Processed.insert(MI);
729}
730
731/// isSafeToDelete - If the specified instruction does not produce any side
732/// effects and all of its defs are dead, then it's safe to delete.
733static bool isSafeToDelete(MachineInstr *MI, unsigned Reg,
734                           const TargetInstrInfo *TII,
735                           SmallVector<unsigned, 4> &Kills) {
736  const TargetInstrDesc &TID = MI->getDesc();
737  if (TID.mayStore() || TID.isCall())
738    return false;
739  if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
740    return false;
741
742  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
743    MachineOperand &MO = MI->getOperand(i);
744    if (!MO.isReg())
745      continue;
746    if (MO.isDef() && !MO.isDead())
747      return false;
748    if (MO.isUse() && MO.getReg() != Reg && MO.isKill())
749      Kills.push_back(MO.getReg());
750  }
751
752  return true;
753}
754
755/// canUpdateDeletedKills - Check if all the registers listed in Kills are
756/// killed by instructions in MBB preceding the current instruction at
757/// position Dist.  If so, return true and record information about the
758/// preceding kills in NewKills.
759bool TwoAddressInstructionPass::
760canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
761                      SmallVector<NewKill, 4> &NewKills,
762                      MachineBasicBlock *MBB, unsigned Dist) {
763  while (!Kills.empty()) {
764    unsigned Kill = Kills.back();
765    Kills.pop_back();
766    if (TargetRegisterInfo::isPhysicalRegister(Kill))
767      return false;
768
769    MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
770    if (!LastKill)
771      return false;
772
773    bool isModRef = LastKill->modifiesRegister(Kill);
774    NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
775                                      LastKill));
776  }
777  return true;
778}
779
780/// DeleteUnusedInstr - If an instruction with a tied register operand can
781/// be safely deleted, just delete it.
782bool
783TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
784                                             MachineBasicBlock::iterator &nmi,
785                                             MachineFunction::iterator &mbbi,
786                                             unsigned regB, unsigned regBIdx,
787                                             unsigned Dist) {
788  // Check if the instruction has no side effects and if all its defs are dead.
789  SmallVector<unsigned, 4> Kills;
790  if (!isSafeToDelete(mi, regB, TII, Kills))
791    return false;
792
793  // If this instruction kills some virtual registers, we need to
794  // update the kill information. If it's not possible to do so,
795  // then bail out.
796  SmallVector<NewKill, 4> NewKills;
797  if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
798    return false;
799
800  if (LV) {
801    while (!NewKills.empty()) {
802      MachineInstr *NewKill = NewKills.back().second;
803      unsigned Kill = NewKills.back().first.first;
804      bool isDead = NewKills.back().first.second;
805      NewKills.pop_back();
806      if (LV->removeVirtualRegisterKilled(Kill, mi)) {
807        if (isDead)
808          LV->addVirtualRegisterDead(Kill, NewKill);
809        else
810          LV->addVirtualRegisterKilled(Kill, NewKill);
811      }
812    }
813
814    // If regB was marked as a kill, update its Kills list.
815    if (mi->getOperand(regBIdx).isKill())
816      LV->removeVirtualRegisterKilled(regB, mi);
817  }
818
819  mbbi->erase(mi); // Nuke the old inst.
820  mi = nmi;
821  return true;
822}
823
824/// TryInstructionTransform - For the case where an instruction has a single
825/// pair of tied register operands, attempt some transformations that may
826/// either eliminate the tied operands or improve the opportunities for
827/// coalescing away the register copy.  Returns true if the tied operands
828/// are eliminated altogether.
829bool TwoAddressInstructionPass::
830TryInstructionTransform(MachineBasicBlock::iterator &mi,
831                        MachineBasicBlock::iterator &nmi,
832                        MachineFunction::iterator &mbbi,
833                        unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
834  const TargetInstrDesc &TID = mi->getDesc();
835  unsigned regA = mi->getOperand(DstIdx).getReg();
836  unsigned regB = mi->getOperand(SrcIdx).getReg();
837
838  assert(TargetRegisterInfo::isVirtualRegister(regB) &&
839         "cannot make instruction into two-address form");
840
841  // If regA is dead and the instruction can be deleted, just delete
842  // it so it doesn't clobber regB.
843  bool regBKilled = isKilled(*mi, regB, MRI, TII);
844  if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
845      DeleteUnusedInstr(mi, nmi, mbbi, regB, SrcIdx, Dist)) {
846    ++NumDeletes;
847    return true; // Done with this instruction.
848  }
849
850  // Check if it is profitable to commute the operands.
851  unsigned SrcOp1, SrcOp2;
852  unsigned regC = 0;
853  unsigned regCIdx = ~0U;
854  bool TryCommute = false;
855  bool AggressiveCommute = false;
856  if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
857      TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
858    if (SrcIdx == SrcOp1)
859      regCIdx = SrcOp2;
860    else if (SrcIdx == SrcOp2)
861      regCIdx = SrcOp1;
862
863    if (regCIdx != ~0U) {
864      regC = mi->getOperand(regCIdx).getReg();
865      if (!regBKilled && isKilled(*mi, regC, MRI, TII))
866        // If C dies but B does not, swap the B and C operands.
867        // This makes the live ranges of A and C joinable.
868        TryCommute = true;
869      else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
870        TryCommute = true;
871        AggressiveCommute = true;
872      }
873    }
874  }
875
876  // If it's profitable to commute, try to do so.
877  if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
878    ++NumCommuted;
879    if (AggressiveCommute)
880      ++NumAggrCommuted;
881    return false;
882  }
883
884  if (TID.isConvertibleTo3Addr()) {
885    // This instruction is potentially convertible to a true
886    // three-address instruction.  Check if it is profitable.
887    if (!regBKilled || isProfitableToConv3Addr(regA)) {
888      // Try to convert it.
889      if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
890        ++NumConvertedTo3Addr;
891        return true; // Done with this instruction.
892      }
893    }
894  }
895  return false;
896}
897
898/// runOnMachineFunction - Reduce two-address instructions to two operands.
899///
900bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
901  DEBUG(errs() << "Machine Function\n");
902  const TargetMachine &TM = MF.getTarget();
903  MRI = &MF.getRegInfo();
904  TII = TM.getInstrInfo();
905  TRI = TM.getRegisterInfo();
906  LV = getAnalysisIfAvailable<LiveVariables>();
907  AA = &getAnalysis<AliasAnalysis>();
908
909  bool MadeChange = false;
910
911  DEBUG(errs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
912  DEBUG(errs() << "********** Function: "
913        << MF.getFunction()->getName() << '\n');
914
915  // ReMatRegs - Keep track of the registers whose def's are remat'ed.
916  BitVector ReMatRegs;
917  ReMatRegs.resize(MRI->getLastVirtReg()+1);
918
919  typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
920    TiedOperandMap;
921  TiedOperandMap TiedOperands(4);
922
923  SmallPtrSet<MachineInstr*, 8> Processed;
924  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
925       mbbi != mbbe; ++mbbi) {
926    unsigned Dist = 0;
927    DistanceMap.clear();
928    SrcRegMap.clear();
929    DstRegMap.clear();
930    Processed.clear();
931    for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
932         mi != me; ) {
933      MachineBasicBlock::iterator nmi = next(mi);
934      const TargetInstrDesc &TID = mi->getDesc();
935      bool FirstTied = true;
936
937      DistanceMap.insert(std::make_pair(mi, ++Dist));
938
939      ProcessCopy(&*mi, &*mbbi, Processed);
940
941      // First scan through all the tied register uses in this instruction
942      // and record a list of pairs of tied operands for each register.
943      unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
944        ? mi->getNumOperands() : TID.getNumOperands();
945      for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
946        unsigned DstIdx = 0;
947        if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
948          continue;
949
950        if (FirstTied) {
951          FirstTied = false;
952          ++NumTwoAddressInstrs;
953          DEBUG(errs() << '\t' << *mi);
954        }
955
956        assert(mi->getOperand(SrcIdx).isReg() &&
957               mi->getOperand(SrcIdx).getReg() &&
958               mi->getOperand(SrcIdx).isUse() &&
959               "two address instruction invalid");
960
961        unsigned regB = mi->getOperand(SrcIdx).getReg();
962        TiedOperandMap::iterator OI = TiedOperands.find(regB);
963        if (OI == TiedOperands.end()) {
964          SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
965          OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
966        }
967        OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
968      }
969
970      // Now iterate over the information collected above.
971      for (TiedOperandMap::iterator OI = TiedOperands.begin(),
972             OE = TiedOperands.end(); OI != OE; ++OI) {
973        SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
974
975        // If the instruction has a single pair of tied operands, try some
976        // transformations that may either eliminate the tied operands or
977        // improve the opportunities for coalescing away the register copy.
978        if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
979          unsigned SrcIdx = TiedPairs[0].first;
980          unsigned DstIdx = TiedPairs[0].second;
981
982          // If the registers are already equal, nothing needs to be done.
983          if (mi->getOperand(SrcIdx).getReg() ==
984              mi->getOperand(DstIdx).getReg())
985            break; // Done with this instruction.
986
987          if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
988            break; // The tied operands have been eliminated.
989        }
990
991        bool RemovedKillFlag = false;
992        bool AllUsesCopied = true;
993        unsigned LastCopiedReg = 0;
994        unsigned regB = OI->first;
995        for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
996          unsigned SrcIdx = TiedPairs[tpi].first;
997          unsigned DstIdx = TiedPairs[tpi].second;
998          unsigned regA = mi->getOperand(DstIdx).getReg();
999          // Grab regB from the instruction because it may have changed if the
1000          // instruction was commuted.
1001          regB = mi->getOperand(SrcIdx).getReg();
1002
1003          if (regA == regB) {
1004            // The register is tied to multiple destinations (or else we would
1005            // not have continued this far), but this use of the register
1006            // already matches the tied destination.  Leave it.
1007            AllUsesCopied = false;
1008            continue;
1009          }
1010          LastCopiedReg = regA;
1011
1012          assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1013                 "cannot make instruction into two-address form");
1014
1015#ifndef NDEBUG
1016          // First, verify that we don't have a use of "a" in the instruction
1017          // (a = b + a for example) because our transformation will not
1018          // work. This should never occur because we are in SSA form.
1019          for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1020            assert(i == DstIdx ||
1021                   !mi->getOperand(i).isReg() ||
1022                   mi->getOperand(i).getReg() != regA);
1023#endif
1024
1025          // Emit a copy or rematerialize the definition.
1026          const TargetRegisterClass *rc = MRI->getRegClass(regB);
1027          MachineInstr *DefMI = MRI->getVRegDef(regB);
1028          // If it's safe and profitable, remat the definition instead of
1029          // copying it.
1030          if (DefMI &&
1031              DefMI->getDesc().isAsCheapAsAMove() &&
1032              DefMI->isSafeToReMat(TII, regB, AA) &&
1033              isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1034            DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
1035            unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1036            TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
1037            ReMatRegs.set(regB);
1038            ++NumReMats;
1039          } else {
1040            bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
1041            (void)Emitted;
1042            assert(Emitted && "Unable to issue a copy instruction!\n");
1043          }
1044
1045          MachineBasicBlock::iterator prevMI = prior(mi);
1046          // Update DistanceMap.
1047          DistanceMap.insert(std::make_pair(prevMI, Dist));
1048          DistanceMap[mi] = ++Dist;
1049
1050          DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
1051
1052          MachineOperand &MO = mi->getOperand(SrcIdx);
1053          assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1054                 "inconsistent operand info for 2-reg pass");
1055          if (MO.isKill()) {
1056            MO.setIsKill(false);
1057            RemovedKillFlag = true;
1058          }
1059          MO.setReg(regA);
1060        }
1061
1062        if (AllUsesCopied) {
1063          // Replace other (un-tied) uses of regB with LastCopiedReg.
1064          for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1065            MachineOperand &MO = mi->getOperand(i);
1066            if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1067              if (MO.isKill()) {
1068                MO.setIsKill(false);
1069                RemovedKillFlag = true;
1070              }
1071              MO.setReg(LastCopiedReg);
1072            }
1073          }
1074
1075          // Update live variables for regB.
1076          if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1077            LV->addVirtualRegisterKilled(regB, prior(mi));
1078
1079        } else if (RemovedKillFlag) {
1080          // Some tied uses of regB matched their destination registers, so
1081          // regB is still used in this instruction, but a kill flag was
1082          // removed from a different tied use of regB, so now we need to add
1083          // a kill flag to one of the remaining uses of regB.
1084          for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1085            MachineOperand &MO = mi->getOperand(i);
1086            if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1087              MO.setIsKill(true);
1088              break;
1089            }
1090          }
1091        }
1092
1093        MadeChange = true;
1094
1095        DEBUG(errs() << "\t\trewrite to:\t" << *mi);
1096      }
1097
1098      // Clear TiedOperands here instead of at the top of the loop
1099      // since most instructions do not have tied operands.
1100      TiedOperands.clear();
1101      mi = nmi;
1102    }
1103  }
1104
1105  // Some remat'ed instructions are dead.
1106  int VReg = ReMatRegs.find_first();
1107  while (VReg != -1) {
1108    if (MRI->use_empty(VReg)) {
1109      MachineInstr *DefMI = MRI->getVRegDef(VReg);
1110      DefMI->eraseFromParent();
1111    }
1112    VReg = ReMatRegs.find_next(VReg);
1113  }
1114
1115  return MadeChange;
1116}
1117