VirtRegMap.cpp revision 408396014742a05cad1c91949d2226169e3f9d80
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/ADT/Statistic.h" 30#include "llvm/ADT/STLExtras.h" 31#include <algorithm> 32#include <iostream> 33using namespace llvm; 34 35namespace { 36 Statistic<> NumSpills("spiller", "Number of register spills"); 37 Statistic<> NumStores("spiller", "Number of stores added"); 38 Statistic<> NumLoads ("spiller", "Number of loads added"); 39 Statistic<> NumReused("spiller", "Number of values reused"); 40 Statistic<> NumDSE ("spiller", "Number of dead stores elided"); 41 42 enum SpillerName { simple, local }; 43 44 cl::opt<SpillerName> 45 SpillerOpt("spiller", 46 cl::desc("Spiller to use: (default: local)"), 47 cl::Prefix, 48 cl::values(clEnumVal(simple, " simple spiller"), 49 clEnumVal(local, " local spiller"), 50 clEnumValEnd), 51 cl::init(local)); 52} 53 54//===----------------------------------------------------------------------===// 55// VirtRegMap implementation 56//===----------------------------------------------------------------------===// 57 58void VirtRegMap::grow() { 59 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg()); 60 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg()); 61} 62 63int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 64 assert(MRegisterInfo::isVirtualRegister(virtReg)); 65 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 66 "attempt to assign stack slot to already spilled register"); 67 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); 68 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 69 RC->getAlignment()); 70 Virt2StackSlotMap[virtReg] = frameIndex; 71 ++NumSpills; 72 return frameIndex; 73} 74 75void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { 76 assert(MRegisterInfo::isVirtualRegister(virtReg)); 77 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 78 "attempt to assign stack slot to already spilled register"); 79 Virt2StackSlotMap[virtReg] = frameIndex; 80} 81 82void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 83 unsigned OpNo, MachineInstr *NewMI) { 84 // Move previous memory references folded to new instruction. 85 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 86 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 87 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 88 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 89 MI2VirtMap.erase(I++); 90 } 91 92 ModRef MRInfo; 93 if (!OldMI->getOperand(OpNo).isDef()) { 94 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?"); 95 MRInfo = isRef; 96 } else { 97 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod; 98 } 99 100 // add new memory reference 101 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 102} 103 104void VirtRegMap::print(std::ostream &OS) const { 105 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); 106 107 OS << "********** REGISTER MAP **********\n"; 108 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 109 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { 110 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 111 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; 112 113 } 114 115 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 116 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) 117 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 118 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 119 OS << '\n'; 120} 121 122void VirtRegMap::dump() const { print(std::cerr); } 123 124 125//===----------------------------------------------------------------------===// 126// Simple Spiller Implementation 127//===----------------------------------------------------------------------===// 128 129Spiller::~Spiller() {} 130 131namespace { 132 struct SimpleSpiller : public Spiller { 133 bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM); 134 }; 135} 136 137bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, 138 const VirtRegMap &VRM) { 139 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n"); 140 DEBUG(std::cerr << "********** Function: " 141 << MF.getFunction()->getName() << '\n'); 142 const TargetMachine &TM = MF.getTarget(); 143 const MRegisterInfo &MRI = *TM.getRegisterInfo(); 144 bool *PhysRegsUsed = MF.getUsedPhysregs(); 145 146 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 147 // each vreg once (in the case where a spilled vreg is used by multiple 148 // operands). This is always smaller than the number of operands to the 149 // current machine instr, so it should be small. 150 std::vector<unsigned> LoadedRegs; 151 152 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 153 MBBI != E; ++MBBI) { 154 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n"); 155 MachineBasicBlock &MBB = *MBBI; 156 for (MachineBasicBlock::iterator MII = MBB.begin(), 157 E = MBB.end(); MII != E; ++MII) { 158 MachineInstr &MI = *MII; 159 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 160 MachineOperand &MO = MI.getOperand(i); 161 if (MO.isRegister() && MO.getReg()) 162 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 163 unsigned VirtReg = MO.getReg(); 164 unsigned PhysReg = VRM.getPhys(VirtReg); 165 if (VRM.hasStackSlot(VirtReg)) { 166 int StackSlot = VRM.getStackSlot(VirtReg); 167 const TargetRegisterClass* RC = 168 MF.getSSARegMap()->getRegClass(VirtReg); 169 170 if (MO.isUse() && 171 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 172 == LoadedRegs.end()) { 173 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 174 LoadedRegs.push_back(VirtReg); 175 ++NumLoads; 176 DEBUG(std::cerr << '\t' << *prior(MII)); 177 } 178 179 if (MO.isDef()) { 180 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); 181 ++NumStores; 182 } 183 } 184 PhysRegsUsed[PhysReg] = true; 185 MI.SetMachineOperandReg(i, PhysReg); 186 } else { 187 PhysRegsUsed[MO.getReg()] = true; 188 } 189 } 190 191 DEBUG(std::cerr << '\t' << MI); 192 LoadedRegs.clear(); 193 } 194 } 195 return true; 196} 197 198//===----------------------------------------------------------------------===// 199// Local Spiller Implementation 200//===----------------------------------------------------------------------===// 201 202namespace { 203 /// LocalSpiller - This spiller does a simple pass over the machine basic 204 /// block to attempt to keep spills in registers as much as possible for 205 /// blocks that have low register pressure (the vreg may be spilled due to 206 /// register pressure in other blocks). 207 class LocalSpiller : public Spiller { 208 const MRegisterInfo *MRI; 209 const TargetInstrInfo *TII; 210 public: 211 bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM) { 212 MRI = MF.getTarget().getRegisterInfo(); 213 TII = MF.getTarget().getInstrInfo(); 214 DEBUG(std::cerr << "\n**** Local spiller rewriting function '" 215 << MF.getFunction()->getName() << "':\n"); 216 217 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 218 MBB != E; ++MBB) 219 RewriteMBB(*MBB, VRM); 220 return true; 221 } 222 private: 223 void RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM); 224 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots, 225 std::map<unsigned, int> &PhysRegs); 226 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots, 227 std::map<unsigned, int> &PhysRegs); 228 }; 229} 230 231void LocalSpiller::ClobberPhysRegOnly(unsigned PhysReg, 232 std::map<int, unsigned> &SpillSlots, 233 std::map<unsigned, int> &PhysRegs) { 234 std::map<unsigned, int>::iterator I = PhysRegs.find(PhysReg); 235 if (I != PhysRegs.end()) { 236 int Slot = I->second; 237 PhysRegs.erase(I); 238 assert(SpillSlots[Slot] == PhysReg && "Bidirectional map mismatch!"); 239 SpillSlots.erase(Slot); 240 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg) 241 << " clobbered, invalidating SS#" << Slot << "\n"); 242 243 } 244} 245 246void LocalSpiller::ClobberPhysReg(unsigned PhysReg, 247 std::map<int, unsigned> &SpillSlots, 248 std::map<unsigned, int> &PhysRegs) { 249 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) 250 ClobberPhysRegOnly(*AS, SpillSlots, PhysRegs); 251 ClobberPhysRegOnly(PhysReg, SpillSlots, PhysRegs); 252} 253 254 255// ReusedOp - For each reused operand, we keep track of a bit of information, in 256// case we need to rollback upon processing a new operand. See comments below. 257namespace { 258 struct ReusedOp { 259 // The MachineInstr operand that reused an available value. 260 unsigned Operand; 261 262 // StackSlot - The spill slot of the value being reused. 263 unsigned StackSlot; 264 265 // PhysRegReused - The physical register the value was available in. 266 unsigned PhysRegReused; 267 268 // AssignedPhysReg - The physreg that was assigned for use by the reload. 269 unsigned AssignedPhysReg; 270 271 // VirtReg - The virtual register itself. 272 unsigned VirtReg; 273 274 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 275 unsigned vreg) 276 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr), 277 VirtReg(vreg) {} 278 }; 279} 280 281 282/// rewriteMBB - Keep track of which spills are available even after the 283/// register allocator is done with them. If possible, avoid reloading vregs. 284void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) { 285 286 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual 287 // register values that are still available, due to being loaded to stored to, 288 // but not invalidated yet. 289 std::map<int, unsigned> SpillSlotsAvailable; 290 291 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating 292 // which physregs are in use holding a stack slot value. 293 std::map<unsigned, int> PhysRegsAvailable; 294 295 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n"); 296 297 std::vector<ReusedOp> ReusedOperands; 298 299 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track 300 // of it. ".first" is the machine operand index (should always be 0 for now), 301 // and ".second" is the virtual register that is spilled. 302 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg; 303 304 // MaybeDeadStores - When we need to write a value back into a stack slot, 305 // keep track of the inserted store. If the stack slot value is never read 306 // (because the value was used from some available register, for example), and 307 // subsequently stored to, the original store is dead. This map keeps track 308 // of inserted stores that are not used. If we see a subsequent store to the 309 // same stack slot, the original store is deleted. 310 std::map<int, MachineInstr*> MaybeDeadStores; 311 312 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs(); 313 314 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 315 MII != E; ) { 316 MachineInstr &MI = *MII; 317 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 318 319 ReusedOperands.clear(); 320 DefAndUseVReg.clear(); 321 322 // Process all of the spilled uses and all non spilled reg references. 323 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 324 MachineOperand &MO = MI.getOperand(i); 325 if (!MO.isRegister() || MO.getReg() == 0) 326 continue; // Ignore non-register operands. 327 328 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { 329 // Ignore physregs for spilling, but remember that it is used by this 330 // function. 331 PhysRegsUsed[MO.getReg()] = true; 332 continue; 333 } 334 335 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) && 336 "Not a virtual or a physical register?"); 337 338 unsigned VirtReg = MO.getReg(); 339 if (!VRM.hasStackSlot(VirtReg)) { 340 // This virtual register was assigned a physreg! 341 unsigned Phys = VRM.getPhys(VirtReg); 342 PhysRegsUsed[Phys] = true; 343 MI.SetMachineOperandReg(i, Phys); 344 continue; 345 } 346 347 // This virtual register is now known to be a spilled value. 348 if (!MO.isUse()) 349 continue; // Handle defs in the loop below (handle use&def here though) 350 351 // If this is both a def and a use, we need to emit a store to the 352 // stack slot after the instruction. Keep track of D&U operands 353 // because we are about to change it to a physreg here. 354 if (MO.isDef()) { 355 // Remember that this was a def-and-use operand, and that the 356 // stack slot is live after this instruction executes. 357 DefAndUseVReg.push_back(std::make_pair(i, VirtReg)); 358 } 359 360 int StackSlot = VRM.getStackSlot(VirtReg); 361 unsigned PhysReg; 362 363 // Check to see if this stack slot is available. 364 std::map<int, unsigned>::iterator SSI = 365 SpillSlotsAvailable.find(StackSlot); 366 if (SSI != SpillSlotsAvailable.end()) { 367 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg " 368 << MRI->getName(SSI->second) << " for vreg" 369 << VirtReg <<" instead of reloading into physreg " 370 << MRI->getName(VRM.getPhys(VirtReg)) << "\n"); 371 // If this stack slot value is already available, reuse it! 372 PhysReg = SSI->second; 373 MI.SetMachineOperandReg(i, PhysReg); 374 375 // The only technical detail we have is that we don't know that 376 // PhysReg won't be clobbered by a reloaded stack slot that occurs 377 // later in the instruction. In particular, consider 'op V1, V2'. 378 // If V1 is available in physreg R0, we would choose to reuse it 379 // here, instead of reloading it into the register the allocator 380 // indicated (say R1). However, V2 might have to be reloaded 381 // later, and it might indicate that it needs to live in R0. When 382 // this occurs, we need to have information available that 383 // indicates it is safe to use R1 for the reload instead of R0. 384 // 385 // To further complicate matters, we might conflict with an alias, 386 // or R0 and R1 might not be compatible with each other. In this 387 // case, we actually insert a reload for V1 in R1, ensuring that 388 // we can get at R0 or its alias. 389 ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg, 390 VRM.getPhys(VirtReg), VirtReg)); 391 ++NumReused; 392 continue; 393 } 394 395 // Otherwise, reload it and remember that we have it. 396 PhysReg = VRM.getPhys(VirtReg); 397 assert(PhysReg && "Must map virtreg to physreg!"); 398 const TargetRegisterClass* RC = 399 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); 400 401 RecheckRegister: 402 // Note that, if we reused a register for a previous operand, the 403 // register we want to reload into might not actually be 404 // available. If this occurs, use the register indicated by the 405 // reuser. 406 if (!ReusedOperands.empty()) // This is most often empty. 407 for (unsigned ro = 0, e = ReusedOperands.size(); ro != e; ++ro) 408 if (ReusedOperands[ro].PhysRegReused == PhysReg) { 409 // Yup, use the reload register that we didn't use before. 410 PhysReg = ReusedOperands[ro].AssignedPhysReg; 411 goto RecheckRegister; 412 } else { 413 ReusedOp &Op = ReusedOperands[ro]; 414 unsigned PRRU = Op.PhysRegReused; 415 if (MRI->areAliases(PRRU, PhysReg)) { 416 // Okay, we found out that an alias of a reused register 417 // was used. This isn't good because it means we have 418 // to undo a previous reuse. 419 const TargetRegisterClass *AliasRC = 420 MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg); 421 MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg, 422 Op.StackSlot, AliasRC); 423 ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable, 424 PhysRegsAvailable); 425 426 // Any stores to this stack slot are not dead anymore. 427 MaybeDeadStores.erase(Op.StackSlot); 428 429 MI.SetMachineOperandReg(Op.Operand, Op.AssignedPhysReg); 430 PhysRegsAvailable[Op.AssignedPhysReg] = Op.StackSlot; 431 SpillSlotsAvailable[Op.StackSlot] = Op.AssignedPhysReg; 432 PhysRegsAvailable.erase(Op.PhysRegReused); 433 DEBUG(std::cerr << "Remembering SS#" << Op.StackSlot 434 << " in physreg " 435 << MRI->getName(Op.AssignedPhysReg) << "\n"); 436 ++NumLoads; 437 DEBUG(std::cerr << '\t' << *prior(MII)); 438 439 DEBUG(std::cerr << "Reuse undone!\n"); 440 ReusedOperands.erase(ReusedOperands.begin()+ro); 441 --NumReused; 442 goto ContinueReload; 443 } 444 } 445 ContinueReload: 446 PhysRegsUsed[PhysReg] = true; 447 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 448 // This invalidates PhysReg. 449 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable); 450 451 // Any stores to this stack slot are not dead anymore. 452 MaybeDeadStores.erase(StackSlot); 453 454 MI.SetMachineOperandReg(i, PhysReg); 455 PhysRegsAvailable[PhysReg] = StackSlot; 456 SpillSlotsAvailable[StackSlot] = PhysReg; 457 DEBUG(std::cerr << "Remembering SS#" << StackSlot <<" in physreg " 458 << MRI->getName(PhysReg) << "\n"); 459 ++NumLoads; 460 DEBUG(std::cerr << '\t' << *prior(MII)); 461 } 462 463 // Loop over all of the implicit defs, clearing them from our available 464 // sets. 465 for (const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode()); 466 *ImpDef; ++ImpDef) { 467 PhysRegsUsed[*ImpDef] = true; 468 ClobberPhysReg(*ImpDef, SpillSlotsAvailable, PhysRegsAvailable); 469 } 470 471 DEBUG(std::cerr << '\t' << MI); 472 473 // If we have folded references to memory operands, make sure we clear all 474 // physical registers that may contain the value of the spilled virtual 475 // register 476 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 477 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { 478 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: " 479 << I->second.second); 480 unsigned VirtReg = I->second.first; 481 VirtRegMap::ModRef MR = I->second.second; 482 if (!VRM.hasStackSlot(VirtReg)) { 483 DEBUG(std::cerr << ": No stack slot!\n"); 484 continue; 485 } 486 int SS = VRM.getStackSlot(VirtReg); 487 DEBUG(std::cerr << " - StackSlot: " << SS << "\n"); 488 489 // If this folded instruction is just a use, check to see if it's a 490 // straight load from the virt reg slot. 491 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 492 int FrameIdx; 493 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 494 // If this spill slot is available, turn it into a copy (or nothing) 495 // instead of leaving it as a load! 496 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS); 497 if (FrameIdx == SS && It != SpillSlotsAvailable.end()) { 498 DEBUG(std::cerr << "Promoted Load To Copy: " << MI); 499 MachineFunction &MF = *MBB.getParent(); 500 if (DestReg != It->second) { 501 MRI->copyRegToReg(MBB, &MI, DestReg, It->second, 502 MF.getSSARegMap()->getRegClass(VirtReg)); 503 // Revisit the copy so we make sure to notice the effects of the 504 // operation on the destreg (either needing to RA it if it's 505 // virtual or needing to clobber any values if it's physical). 506 NextMII = &MI; 507 --NextMII; // backtrack to the copy. 508 } 509 MBB.erase(&MI); 510 goto ProcessNextInst; 511 } 512 } 513 } 514 515 // If this reference is not a use, any previous store is now dead. 516 // Otherwise, the store to this stack slot is not dead anymore. 517 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS); 518 if (MDSI != MaybeDeadStores.end()) { 519 if (MR & VirtRegMap::isRef) // Previous store is not dead. 520 MaybeDeadStores.erase(MDSI); 521 else { 522 // If we get here, the store is dead, nuke it now. 523 assert(MR == VirtRegMap::isMod && "Can't be modref!"); 524 MBB.erase(MDSI->second); 525 MaybeDeadStores.erase(MDSI); 526 ++NumDSE; 527 } 528 } 529 530 // If the spill slot value is available, and this is a new definition of 531 // the value, the value is not available anymore. 532 if (MR & VirtRegMap::isMod) { 533 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(SS); 534 if (It != SpillSlotsAvailable.end()) { 535 PhysRegsAvailable.erase(It->second); 536 SpillSlotsAvailable.erase(It); 537 } 538 } 539 } 540 541 // Process all of the spilled defs. 542 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 543 MachineOperand &MO = MI.getOperand(i); 544 if (MO.isRegister() && MO.getReg() && MO.isDef()) { 545 unsigned VirtReg = MO.getReg(); 546 547 bool TakenCareOf = false; 548 if (!MRegisterInfo::isVirtualRegister(VirtReg)) { 549 // Check to see if this is a def-and-use vreg operand that we do need 550 // to insert a store for. 551 bool OpTakenCareOf = false; 552 if (MO.isUse() && !DefAndUseVReg.empty()) { 553 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau) 554 if (DefAndUseVReg[dau].first == i) { 555 VirtReg = DefAndUseVReg[dau].second; 556 OpTakenCareOf = true; 557 break; 558 } 559 } 560 561 if (!OpTakenCareOf) { 562 ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable); 563 TakenCareOf = true; 564 } 565 } 566 567 if (!TakenCareOf) { 568 // The only vregs left are stack slot definitions. 569 int StackSlot = VRM.getStackSlot(VirtReg); 570 const TargetRegisterClass *RC = 571 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg); 572 unsigned PhysReg; 573 574 // If this is a def&use operand, and we used a different physreg for 575 // it than the one assigned, make sure to execute the store from the 576 // correct physical register. 577 if (MO.getReg() == VirtReg) 578 PhysReg = VRM.getPhys(VirtReg); 579 else 580 PhysReg = MO.getReg(); 581 582 PhysRegsUsed[PhysReg] = true; 583 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); 584 DEBUG(std::cerr << "Store:\t" << *next(MII)); 585 MI.SetMachineOperandReg(i, PhysReg); 586 587 // If there is a dead store to this stack slot, nuke it now. 588 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 589 if (LastStore) { 590 DEBUG(std::cerr << " Killed store:\t" << *LastStore); 591 ++NumDSE; 592 MBB.erase(LastStore); 593 } 594 LastStore = next(MII); 595 596 // If the stack slot value was previously available in some other 597 // register, change it now. Otherwise, make the register available, 598 // in PhysReg. 599 std::map<int, unsigned>::iterator SSA = 600 SpillSlotsAvailable.find(StackSlot); 601 if (SSA != SpillSlotsAvailable.end()) { 602 // Remove the record for physreg. 603 PhysRegsAvailable.erase(SSA->second); 604 SpillSlotsAvailable.erase(SSA); 605 } 606 ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable); 607 608 PhysRegsAvailable[PhysReg] = StackSlot; 609 SpillSlotsAvailable[StackSlot] = PhysReg; 610 DEBUG(std::cerr << "Updating SS#" << StackSlot <<" in physreg " 611 << MRI->getName(PhysReg) << " for virtreg #" 612 << VirtReg << "\n"); 613 614 ++NumStores; 615 VirtReg = PhysReg; 616 } 617 } 618 } 619 ProcessNextInst: 620 MII = NextMII; 621 } 622} 623 624 625 626llvm::Spiller* llvm::createSpiller() { 627 switch (SpillerOpt) { 628 default: assert(0 && "Unreachable!"); 629 case local: 630 return new LocalSpiller(); 631 case simple: 632 return new SimpleSpiller(); 633 } 634} 635