VirtRegMap.cpp revision aee4af68ae2016afc5b4ec0c430e539c5810a766
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/SSARegMap.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/ADT/BitVector.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/ADT/SmallSet.h" 34#include <algorithm> 35using namespace llvm; 36 37STATISTIC(NumSpills, "Number of register spills"); 38STATISTIC(NumReMats, "Number of re-materialization"); 39STATISTIC(NumDRM , "Number of re-materializable defs elided"); 40STATISTIC(NumStores, "Number of stores added"); 41STATISTIC(NumLoads , "Number of loads added"); 42STATISTIC(NumReused, "Number of values reused"); 43STATISTIC(NumDSE , "Number of dead stores elided"); 44STATISTIC(NumDCE , "Number of copies elided"); 45 46namespace { 47 enum SpillerName { simple, local }; 48 49 static cl::opt<SpillerName> 50 SpillerOpt("spiller", 51 cl::desc("Spiller to use: (default: local)"), 52 cl::Prefix, 53 cl::values(clEnumVal(simple, " simple spiller"), 54 clEnumVal(local, " local spiller"), 55 clEnumValEnd), 56 cl::init(local)); 57} 58 59//===----------------------------------------------------------------------===// 60// VirtRegMap implementation 61//===----------------------------------------------------------------------===// 62 63VirtRegMap::VirtRegMap(MachineFunction &mf) 64 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 65 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 66 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 67 ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1) { 68 grow(); 69} 70 71void VirtRegMap::grow() { 72 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg(); 73 Virt2PhysMap.grow(LastVirtReg); 74 Virt2StackSlotMap.grow(LastVirtReg); 75 Virt2ReMatIdMap.grow(LastVirtReg); 76 Virt2SplitMap.grow(LastVirtReg); 77 ReMatMap.grow(LastVirtReg); 78} 79 80int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 81 assert(MRegisterInfo::isVirtualRegister(virtReg)); 82 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 83 "attempt to assign stack slot to already spilled register"); 84 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg); 85 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 86 RC->getAlignment()); 87 Virt2StackSlotMap[virtReg] = frameIndex; 88 ++NumSpills; 89 return frameIndex; 90} 91 92void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { 93 assert(MRegisterInfo::isVirtualRegister(virtReg)); 94 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 95 "attempt to assign stack slot to already spilled register"); 96 assert((frameIndex >= 0 || 97 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) && 98 "illegal fixed frame index"); 99 Virt2StackSlotMap[virtReg] = frameIndex; 100} 101 102int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 103 assert(MRegisterInfo::isVirtualRegister(virtReg)); 104 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 105 "attempt to assign re-mat id to already spilled register"); 106 Virt2ReMatIdMap[virtReg] = ReMatId; 107 return ReMatId++; 108} 109 110void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 111 assert(MRegisterInfo::isVirtualRegister(virtReg)); 112 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 113 "attempt to assign re-mat id to already spilled register"); 114 Virt2ReMatIdMap[virtReg] = id; 115} 116 117void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 118 MachineInstr *NewMI, ModRef MRInfo) { 119 // Move previous memory references folded to new instruction. 120 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 121 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 122 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 123 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 124 MI2VirtMap.erase(I++); 125 } 126 127 // add new memory reference 128 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 129} 130 131void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 132 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 133 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 134} 135 136void VirtRegMap::print(std::ostream &OS) const { 137 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); 138 139 OS << "********** REGISTER MAP **********\n"; 140 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 141 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) { 142 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 143 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; 144 145 } 146 147 for (unsigned i = MRegisterInfo::FirstVirtualRegister, 148 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) 149 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 150 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 151 OS << '\n'; 152} 153 154void VirtRegMap::dump() const { 155 print(DOUT); 156} 157 158 159//===----------------------------------------------------------------------===// 160// Simple Spiller Implementation 161//===----------------------------------------------------------------------===// 162 163Spiller::~Spiller() {} 164 165namespace { 166 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 167 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 168 }; 169} 170 171bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 172 DOUT << "********** REWRITE MACHINE CODE **********\n"; 173 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 174 const TargetMachine &TM = MF.getTarget(); 175 const MRegisterInfo &MRI = *TM.getRegisterInfo(); 176 177 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 178 // each vreg once (in the case where a spilled vreg is used by multiple 179 // operands). This is always smaller than the number of operands to the 180 // current machine instr, so it should be small. 181 std::vector<unsigned> LoadedRegs; 182 183 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 184 MBBI != E; ++MBBI) { 185 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 186 MachineBasicBlock &MBB = *MBBI; 187 for (MachineBasicBlock::iterator MII = MBB.begin(), 188 E = MBB.end(); MII != E; ++MII) { 189 MachineInstr &MI = *MII; 190 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 191 MachineOperand &MO = MI.getOperand(i); 192 if (MO.isRegister() && MO.getReg()) 193 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 194 unsigned VirtReg = MO.getReg(); 195 unsigned PhysReg = VRM.getPhys(VirtReg); 196 if (!VRM.isAssignedReg(VirtReg)) { 197 int StackSlot = VRM.getStackSlot(VirtReg); 198 const TargetRegisterClass* RC = 199 MF.getSSARegMap()->getRegClass(VirtReg); 200 201 if (MO.isUse() && 202 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 203 == LoadedRegs.end()) { 204 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 205 LoadedRegs.push_back(VirtReg); 206 ++NumLoads; 207 DOUT << '\t' << *prior(MII); 208 } 209 210 if (MO.isDef()) { 211 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); 212 ++NumStores; 213 } 214 } 215 MF.setPhysRegUsed(PhysReg); 216 MI.getOperand(i).setReg(PhysReg); 217 } else { 218 MF.setPhysRegUsed(MO.getReg()); 219 } 220 } 221 222 DOUT << '\t' << MI; 223 LoadedRegs.clear(); 224 } 225 } 226 return true; 227} 228 229//===----------------------------------------------------------------------===// 230// Local Spiller Implementation 231//===----------------------------------------------------------------------===// 232 233namespace { 234 class AvailableSpills; 235 236 /// LocalSpiller - This spiller does a simple pass over the machine basic 237 /// block to attempt to keep spills in registers as much as possible for 238 /// blocks that have low register pressure (the vreg may be spilled due to 239 /// register pressure in other blocks). 240 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 241 SSARegMap *RegMap; 242 const MRegisterInfo *MRI; 243 const TargetInstrInfo *TII; 244 public: 245 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 246 RegMap = MF.getSSARegMap(); 247 MRI = MF.getTarget().getRegisterInfo(); 248 TII = MF.getTarget().getInstrInfo(); 249 DOUT << "\n**** Local spiller rewriting function '" 250 << MF.getFunction()->getName() << "':\n"; 251 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n"; 252 DEBUG(MF.dump()); 253 254 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 255 MBB != E; ++MBB) 256 RewriteMBB(*MBB, VRM); 257 258 DOUT << "**** Post Machine Instrs ****\n"; 259 DEBUG(MF.dump()); 260 261 return true; 262 } 263 private: 264 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 265 MachineBasicBlock::iterator &MII, 266 std::vector<MachineInstr*> &MaybeDeadStores, 267 AvailableSpills &Spills, BitVector &RegKills, 268 std::vector<MachineOperand*> &KillOps, 269 VirtRegMap &VRM); 270 void SpillRegToStackSlot(MachineBasicBlock &MBB, 271 MachineBasicBlock::iterator &MII, 272 int Idx, unsigned PhysReg, int StackSlot, 273 const TargetRegisterClass *RC, 274 MachineInstr *&LastStore, 275 AvailableSpills &Spills, 276 SmallSet<MachineInstr*, 4> &ReMatDefs, 277 BitVector &RegKills, 278 std::vector<MachineOperand*> &KillOps, 279 VirtRegMap &VRM); 280 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); 281 }; 282} 283 284/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 285/// top down, keep track of which spills slots or remat are available in each 286/// register. 287/// 288/// Note that not all physregs are created equal here. In particular, some 289/// physregs are reloads that we are allowed to clobber or ignore at any time. 290/// Other physregs are values that the register allocated program is using that 291/// we cannot CHANGE, but we can read if we like. We keep track of this on a 292/// per-stack-slot / remat id basis as the low bit in the value of the 293/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 294/// this bit and addAvailable sets it if. 295namespace { 296class VISIBILITY_HIDDEN AvailableSpills { 297 const MRegisterInfo *MRI; 298 const TargetInstrInfo *TII; 299 300 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 301 // or remat'ed virtual register values that are still available, due to being 302 // loaded or stored to, but not invalidated yet. 303 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 304 305 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 306 // indicating which stack slot values are currently held by a physreg. This 307 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 308 // physreg is modified. 309 std::multimap<unsigned, int> PhysRegsAvailable; 310 311 void disallowClobberPhysRegOnly(unsigned PhysReg); 312 313 void ClobberPhysRegOnly(unsigned PhysReg); 314public: 315 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) 316 : MRI(mri), TII(tii) { 317 } 318 319 const MRegisterInfo *getRegInfo() const { return MRI; } 320 321 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 322 /// available in a physical register, return that PhysReg, otherwise 323 /// return 0. 324 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 325 std::map<int, unsigned>::const_iterator I = 326 SpillSlotsOrReMatsAvailable.find(Slot); 327 if (I != SpillSlotsOrReMatsAvailable.end()) { 328 return I->second >> 1; // Remove the CanClobber bit. 329 } 330 return 0; 331 } 332 333 /// addAvailable - Mark that the specified stack slot / remat is available in 334 /// the specified physreg. If CanClobber is true, the physreg can be modified 335 /// at any time without changing the semantics of the program. 336 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, 337 bool CanClobber = true) { 338 // If this stack slot is thought to be available in some other physreg, 339 // remove its record. 340 ModifyStackSlotOrReMat(SlotOrReMat); 341 342 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 343 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 344 345 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 346 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 347 else 348 DOUT << "Remembering SS#" << SlotOrReMat; 349 DOUT << " in physreg " << MRI->getName(Reg) << "\n"; 350 } 351 352 /// canClobberPhysReg - Return true if the spiller is allowed to change the 353 /// value of the specified stackslot register if it desires. The specified 354 /// stack slot must be available in a physreg for this query to make sense. 355 bool canClobberPhysReg(int SlotOrReMat) const { 356 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 357 "Value not available!"); 358 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 359 } 360 361 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 362 /// stackslot register. The register is still available but is no longer 363 /// allowed to be modifed. 364 void disallowClobberPhysReg(unsigned PhysReg); 365 366 /// ClobberPhysReg - This is called when the specified physreg changes 367 /// value. We use this to invalidate any info about stuff that lives in 368 /// it and any of its aliases. 369 void ClobberPhysReg(unsigned PhysReg); 370 371 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 372 /// slot changes. This removes information about which register the previous 373 /// value for this slot lives in (as the previous value is dead now). 374 void ModifyStackSlotOrReMat(int SlotOrReMat); 375}; 376} 377 378/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 379/// stackslot register. The register is still available but is no longer 380/// allowed to be modifed. 381void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 382 std::multimap<unsigned, int>::iterator I = 383 PhysRegsAvailable.lower_bound(PhysReg); 384 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 385 int SlotOrReMat = I->second; 386 I++; 387 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 388 "Bidirectional map mismatch!"); 389 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 390 DOUT << "PhysReg " << MRI->getName(PhysReg) 391 << " copied, it is available for use but can no longer be modified\n"; 392 } 393} 394 395/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 396/// stackslot register and its aliases. The register and its aliases may 397/// still available but is no longer allowed to be modifed. 398void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 399 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) 400 disallowClobberPhysRegOnly(*AS); 401 disallowClobberPhysRegOnly(PhysReg); 402} 403 404/// ClobberPhysRegOnly - This is called when the specified physreg changes 405/// value. We use this to invalidate any info about stuff we thing lives in it. 406void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 407 std::multimap<unsigned, int>::iterator I = 408 PhysRegsAvailable.lower_bound(PhysReg); 409 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 410 int SlotOrReMat = I->second; 411 PhysRegsAvailable.erase(I++); 412 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 413 "Bidirectional map mismatch!"); 414 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 415 DOUT << "PhysReg " << MRI->getName(PhysReg) 416 << " clobbered, invalidating "; 417 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 418 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 419 else 420 DOUT << "SS#" << SlotOrReMat << "\n"; 421 } 422} 423 424/// ClobberPhysReg - This is called when the specified physreg changes 425/// value. We use this to invalidate any info about stuff we thing lives in 426/// it and any of its aliases. 427void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 428 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) 429 ClobberPhysRegOnly(*AS); 430 ClobberPhysRegOnly(PhysReg); 431} 432 433/// ModifyStackSlotOrReMat - This method is called when the value in a stack 434/// slot changes. This removes information about which register the previous 435/// value for this slot lives in (as the previous value is dead now). 436void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 437 std::map<int, unsigned>::iterator It = 438 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 439 if (It == SpillSlotsOrReMatsAvailable.end()) return; 440 unsigned Reg = It->second >> 1; 441 SpillSlotsOrReMatsAvailable.erase(It); 442 443 // This register may hold the value of multiple stack slots, only remove this 444 // stack slot from the set of values the register contains. 445 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 446 for (; ; ++I) { 447 assert(I != PhysRegsAvailable.end() && I->first == Reg && 448 "Map inverse broken!"); 449 if (I->second == SlotOrReMat) break; 450 } 451 PhysRegsAvailable.erase(I); 452} 453 454 455 456/// InvalidateKills - MI is going to be deleted. If any of its operands are 457/// marked kill, then invalidate the information. 458static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 459 std::vector<MachineOperand*> &KillOps, 460 SmallVector<unsigned, 2> *KillRegs = NULL) { 461 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 462 MachineOperand &MO = MI.getOperand(i); 463 if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) 464 continue; 465 unsigned Reg = MO.getReg(); 466 if (KillRegs) 467 KillRegs->push_back(Reg); 468 if (KillOps[Reg] == &MO) { 469 RegKills.reset(Reg); 470 KillOps[Reg] = NULL; 471 } 472 } 473} 474 475/// InvalidateRegDef - If the def operand of the specified def MI is now dead 476/// (since it's spill instruction is removed), mark it isDead. Also checks if 477/// the def MI has other definition operands that are not dead. Returns it by 478/// reference. 479static bool InvalidateRegDef(MachineBasicBlock::iterator I, 480 MachineInstr &NewDef, unsigned Reg, 481 bool &HasLiveDef) { 482 // Due to remat, it's possible this reg isn't being reused. That is, 483 // the def of this reg (by prev MI) is now dead. 484 MachineInstr *DefMI = I; 485 MachineOperand *DefOp = NULL; 486 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 487 MachineOperand &MO = DefMI->getOperand(i); 488 if (MO.isRegister() && MO.isDef()) { 489 if (MO.getReg() == Reg) 490 DefOp = &MO; 491 else if (!MO.isDead()) 492 HasLiveDef = true; 493 } 494 } 495 if (!DefOp) 496 return false; 497 498 bool FoundUse = false, Done = false; 499 MachineBasicBlock::iterator E = NewDef; 500 ++I; ++E; 501 for (; !Done && I != E; ++I) { 502 MachineInstr *NMI = I; 503 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 504 MachineOperand &MO = NMI->getOperand(j); 505 if (!MO.isRegister() || MO.getReg() != Reg) 506 continue; 507 if (MO.isUse()) 508 FoundUse = true; 509 Done = true; // Stop after scanning all the operands of this MI. 510 } 511 } 512 if (!FoundUse) { 513 // Def is dead! 514 DefOp->setIsDead(); 515 return true; 516 } 517 return false; 518} 519 520/// UpdateKills - Track and update kill info. If a MI reads a register that is 521/// marked kill, then it must be due to register reuse. Transfer the kill info 522/// over. 523static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 524 std::vector<MachineOperand*> &KillOps) { 525 const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); 526 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 527 MachineOperand &MO = MI.getOperand(i); 528 if (!MO.isRegister() || !MO.isUse()) 529 continue; 530 unsigned Reg = MO.getReg(); 531 if (Reg == 0) 532 continue; 533 534 if (RegKills[Reg]) { 535 // That can't be right. Register is killed but not re-defined and it's 536 // being reused. Let's fix that. 537 KillOps[Reg]->unsetIsKill(); 538 if (i < TID->numOperands && 539 TID->getOperandConstraint(i, TOI::TIED_TO) == -1) 540 // Unless it's a two-address operand, this is the new kill. 541 MO.setIsKill(); 542 } 543 544 if (MO.isKill()) { 545 RegKills.set(Reg); 546 KillOps[Reg] = &MO; 547 } 548 } 549 550 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 551 const MachineOperand &MO = MI.getOperand(i); 552 if (!MO.isRegister() || !MO.isDef()) 553 continue; 554 unsigned Reg = MO.getReg(); 555 RegKills.reset(Reg); 556 KillOps[Reg] = NULL; 557 } 558} 559 560 561// ReusedOp - For each reused operand, we keep track of a bit of information, in 562// case we need to rollback upon processing a new operand. See comments below. 563namespace { 564 struct ReusedOp { 565 // The MachineInstr operand that reused an available value. 566 unsigned Operand; 567 568 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 569 unsigned StackSlotOrReMat; 570 571 // PhysRegReused - The physical register the value was available in. 572 unsigned PhysRegReused; 573 574 // AssignedPhysReg - The physreg that was assigned for use by the reload. 575 unsigned AssignedPhysReg; 576 577 // VirtReg - The virtual register itself. 578 unsigned VirtReg; 579 580 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 581 unsigned vreg) 582 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 583 AssignedPhysReg(apr), VirtReg(vreg) {} 584 }; 585 586 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 587 /// is reused instead of reloaded. 588 class VISIBILITY_HIDDEN ReuseInfo { 589 MachineInstr &MI; 590 std::vector<ReusedOp> Reuses; 591 BitVector PhysRegsClobbered; 592 public: 593 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { 594 PhysRegsClobbered.resize(mri->getNumRegs()); 595 } 596 597 bool hasReuses() const { 598 return !Reuses.empty(); 599 } 600 601 /// addReuse - If we choose to reuse a virtual register that is already 602 /// available instead of reloading it, remember that we did so. 603 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 604 unsigned PhysRegReused, unsigned AssignedPhysReg, 605 unsigned VirtReg) { 606 // If the reload is to the assigned register anyway, no undo will be 607 // required. 608 if (PhysRegReused == AssignedPhysReg) return; 609 610 // Otherwise, remember this. 611 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 612 AssignedPhysReg, VirtReg)); 613 } 614 615 void markClobbered(unsigned PhysReg) { 616 PhysRegsClobbered.set(PhysReg); 617 } 618 619 bool isClobbered(unsigned PhysReg) const { 620 return PhysRegsClobbered.test(PhysReg); 621 } 622 623 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 624 /// is some other operand that is using the specified register, either pick 625 /// a new register to use, or evict the previous reload and use this reg. 626 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 627 AvailableSpills &Spills, 628 std::vector<MachineInstr*> &MaybeDeadStores, 629 SmallSet<unsigned, 8> &Rejected, 630 BitVector &RegKills, 631 std::vector<MachineOperand*> &KillOps, 632 VirtRegMap &VRM) { 633 if (Reuses.empty()) return PhysReg; // This is most often empty. 634 635 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 636 ReusedOp &Op = Reuses[ro]; 637 // If we find some other reuse that was supposed to use this register 638 // exactly for its reload, we can change this reload to use ITS reload 639 // register. That is, unless its reload register has already been 640 // considered and subsequently rejected because it has also been reused 641 // by another operand. 642 if (Op.PhysRegReused == PhysReg && 643 Rejected.count(Op.AssignedPhysReg) == 0) { 644 // Yup, use the reload register that we didn't use before. 645 unsigned NewReg = Op.AssignedPhysReg; 646 Rejected.insert(PhysReg); 647 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 648 RegKills, KillOps, VRM); 649 } else { 650 // Otherwise, we might also have a problem if a previously reused 651 // value aliases the new register. If so, codegen the previous reload 652 // and use this one. 653 unsigned PRRU = Op.PhysRegReused; 654 const MRegisterInfo *MRI = Spills.getRegInfo(); 655 if (MRI->areAliases(PRRU, PhysReg)) { 656 // Okay, we found out that an alias of a reused register 657 // was used. This isn't good because it means we have 658 // to undo a previous reuse. 659 MachineBasicBlock *MBB = MI->getParent(); 660 const TargetRegisterClass *AliasRC = 661 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg); 662 663 // Copy Op out of the vector and remove it, we're going to insert an 664 // explicit load for it. 665 ReusedOp NewOp = Op; 666 Reuses.erase(Reuses.begin()+ro); 667 668 // Ok, we're going to try to reload the assigned physreg into the 669 // slot that we were supposed to in the first place. However, that 670 // register could hold a reuse. Check to see if it conflicts or 671 // would prefer us to use a different register. 672 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 673 MI, Spills, MaybeDeadStores, 674 Rejected, RegKills, KillOps, VRM); 675 676 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 677 MRI->reMaterialize(*MBB, MI, NewPhysReg, 678 VRM.getReMaterializedMI(NewOp.VirtReg)); 679 ++NumReMats; 680 } else { 681 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg, 682 NewOp.StackSlotOrReMat, AliasRC); 683 // Any stores to this stack slot are not dead anymore. 684 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 685 ++NumLoads; 686 } 687 Spills.ClobberPhysReg(NewPhysReg); 688 Spills.ClobberPhysReg(NewOp.PhysRegReused); 689 690 MI->getOperand(NewOp.Operand).setReg(NewPhysReg); 691 692 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); 693 MachineBasicBlock::iterator MII = MI; 694 --MII; 695 UpdateKills(*MII, RegKills, KillOps); 696 DOUT << '\t' << *MII; 697 698 DOUT << "Reuse undone!\n"; 699 --NumReused; 700 701 // Finally, PhysReg is now available, go ahead and use it. 702 return PhysReg; 703 } 704 } 705 } 706 return PhysReg; 707 } 708 709 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 710 /// 'Rejected' set to remember which registers have been considered and 711 /// rejected for the reload. This avoids infinite looping in case like 712 /// this: 713 /// t1 := op t2, t3 714 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 715 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 716 /// t1 <- desires r1 717 /// sees r1 is taken by t2, tries t2's reload register r0 718 /// sees r0 is taken by t3, tries t3's reload register r1 719 /// sees r1 is taken by t2, tries t2's reload register r0 ... 720 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 721 AvailableSpills &Spills, 722 std::vector<MachineInstr*> &MaybeDeadStores, 723 BitVector &RegKills, 724 std::vector<MachineOperand*> &KillOps, 725 VirtRegMap &VRM) { 726 SmallSet<unsigned, 8> Rejected; 727 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 728 RegKills, KillOps, VRM); 729 } 730 }; 731} 732 733/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 734/// instruction. e.g. 735/// xorl %edi, %eax 736/// movl %eax, -32(%ebp) 737/// movl -36(%ebp), %eax 738/// orl %eax, -32(%ebp) 739/// ==> 740/// xorl %edi, %eax 741/// orl -36(%ebp), %eax 742/// mov %eax, -32(%ebp) 743/// This enables unfolding optimization for a subsequent instruction which will 744/// also eliminate the newly introduced store instruction. 745bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 746 MachineBasicBlock::iterator &MII, 747 std::vector<MachineInstr*> &MaybeDeadStores, 748 AvailableSpills &Spills, 749 BitVector &RegKills, 750 std::vector<MachineOperand*> &KillOps, 751 VirtRegMap &VRM) { 752 MachineFunction &MF = *MBB.getParent(); 753 MachineInstr &MI = *MII; 754 unsigned UnfoldedOpc = 0; 755 unsigned UnfoldPR = 0; 756 unsigned UnfoldVR = 0; 757 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 758 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 759 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { 760 // Only transform a MI that folds a single register. 761 if (UnfoldedOpc) 762 return false; 763 UnfoldVR = I->second.first; 764 VirtRegMap::ModRef MR = I->second.second; 765 if (VRM.isAssignedReg(UnfoldVR)) 766 continue; 767 // If this reference is not a use, any previous store is now dead. 768 // Otherwise, the store to this stack slot is not dead anymore. 769 FoldedSS = VRM.getStackSlot(UnfoldVR); 770 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 771 if (DeadStore && (MR & VirtRegMap::isModRef)) { 772 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 773 if (!PhysReg || 774 DeadStore->findRegisterUseOperandIdx(PhysReg, true) == -1) 775 continue; 776 UnfoldPR = PhysReg; 777 UnfoldedOpc = MRI->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 778 false, true); 779 } 780 } 781 782 if (!UnfoldedOpc) 783 return false; 784 785 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 786 MachineOperand &MO = MI.getOperand(i); 787 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) 788 continue; 789 unsigned VirtReg = MO.getReg(); 790 if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 791 continue; 792 if (VRM.isAssignedReg(VirtReg)) { 793 unsigned PhysReg = VRM.getPhys(VirtReg); 794 if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR)) 795 return false; 796 } else if (VRM.isReMaterialized(VirtReg)) 797 continue; 798 int SS = VRM.getStackSlot(VirtReg); 799 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 800 if (PhysReg) { 801 if (MRI->regsOverlap(PhysReg, UnfoldPR)) 802 return false; 803 continue; 804 } 805 PhysReg = VRM.getPhys(VirtReg); 806 if (!MRI->regsOverlap(PhysReg, UnfoldPR)) 807 continue; 808 809 // Ok, we'll need to reload the value into a register which makes 810 // it impossible to perform the store unfolding optimization later. 811 // Let's see if it is possible to fold the load if the store is 812 // unfolded. This allows us to perform the store unfolding 813 // optimization. 814 SmallVector<MachineInstr*, 4> NewMIs; 815 if (MRI->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 816 assert(NewMIs.size() == 1); 817 MachineInstr *NewMI = NewMIs.back(); 818 NewMIs.clear(); 819 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg); 820 assert(Idx != -1); 821 SmallVector<unsigned, 2> Ops; 822 Ops.push_back(Idx); 823 MachineInstr *FoldedMI = MRI->foldMemoryOperand(NewMI, Ops, SS); 824 if (FoldedMI) { 825 if (!VRM.hasPhys(UnfoldVR)) 826 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 827 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 828 MII = MBB.insert(MII, FoldedMI); 829 VRM.RemoveMachineInstrFromMaps(&MI); 830 MBB.erase(&MI); 831 return true; 832 } 833 delete NewMI; 834 } 835 } 836 return false; 837} 838 839/// findSuperReg - Find the SubReg's super-register of given register class 840/// where its SubIdx sub-register is SubReg. 841static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 842 unsigned SubIdx, const MRegisterInfo *MRI) { 843 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 844 I != E; ++I) { 845 unsigned Reg = *I; 846 if (MRI->getSubReg(Reg, SubIdx) == SubReg) 847 return Reg; 848 } 849 return 0; 850} 851 852/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 853/// the last store to the same slot is now dead. If so, remove the last store. 854void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 855 MachineBasicBlock::iterator &MII, 856 int Idx, unsigned PhysReg, int StackSlot, 857 const TargetRegisterClass *RC, 858 MachineInstr *&LastStore, 859 AvailableSpills &Spills, 860 SmallSet<MachineInstr*, 4> &ReMatDefs, 861 BitVector &RegKills, 862 std::vector<MachineOperand*> &KillOps, 863 VirtRegMap &VRM) { 864 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC); 865 DOUT << "Store:\t" << *next(MII); 866 867 // If there is a dead store to this stack slot, nuke it now. 868 if (LastStore) { 869 DOUT << "Removed dead store:\t" << *LastStore; 870 ++NumDSE; 871 SmallVector<unsigned, 2> KillRegs; 872 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 873 MachineBasicBlock::iterator PrevMII = LastStore; 874 bool CheckDef = PrevMII != MBB.begin(); 875 if (CheckDef) 876 --PrevMII; 877 MBB.erase(LastStore); 878 VRM.RemoveMachineInstrFromMaps(LastStore); 879 if (CheckDef) { 880 // Look at defs of killed registers on the store. Mark the defs 881 // as dead since the store has been deleted and they aren't 882 // being reused. 883 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 884 bool HasOtherDef = false; 885 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 886 MachineInstr *DeadDef = PrevMII; 887 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 888 // FIXME: This assumes a remat def does not have side 889 // effects. 890 MBB.erase(DeadDef); 891 VRM.RemoveMachineInstrFromMaps(DeadDef); 892 ++NumDRM; 893 } 894 } 895 } 896 } 897 } 898 899 LastStore = next(MII); 900 901 // If the stack slot value was previously available in some other 902 // register, change it now. Otherwise, make the register available, 903 // in PhysReg. 904 Spills.ModifyStackSlotOrReMat(StackSlot); 905 Spills.ClobberPhysReg(PhysReg); 906 Spills.addAvailable(StackSlot, LastStore, PhysReg); 907 ++NumStores; 908} 909 910/// rewriteMBB - Keep track of which spills are available even after the 911/// register allocator is done with them. If possible, avid reloading vregs. 912void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { 913 DOUT << MBB.getBasicBlock()->getName() << ":\n"; 914 915 MachineFunction &MF = *MBB.getParent(); 916 917 // Spills - Keep track of which spilled values are available in physregs so 918 // that we can choose to reuse the physregs instead of emitting reloads. 919 AvailableSpills Spills(MRI, TII); 920 921 // MaybeDeadStores - When we need to write a value back into a stack slot, 922 // keep track of the inserted store. If the stack slot value is never read 923 // (because the value was used from some available register, for example), and 924 // subsequently stored to, the original store is dead. This map keeps track 925 // of inserted stores that are not used. If we see a subsequent store to the 926 // same stack slot, the original store is deleted. 927 std::vector<MachineInstr*> MaybeDeadStores; 928 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 929 930 // ReMatDefs - These are rematerializable def MIs which are not deleted. 931 SmallSet<MachineInstr*, 4> ReMatDefs; 932 933 // Keep track of kill information. 934 BitVector RegKills(MRI->getNumRegs()); 935 std::vector<MachineOperand*> KillOps; 936 KillOps.resize(MRI->getNumRegs(), NULL); 937 938 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 939 MII != E; ) { 940 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 941 942 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 943 bool Erased = false; 944 bool BackTracked = false; 945 if (PrepForUnfoldOpti(MBB, MII, 946 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 947 NextMII = next(MII); 948 949 MachineInstr &MI = *MII; 950 const TargetInstrDescriptor *TID = MI.getInstrDescriptor(); 951 952 // Insert restores here if asked to. 953 if (VRM.isRestorePt(&MI)) { 954 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 955 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 956 unsigned VirtReg = RestoreRegs[i]; 957 if (!VRM.getPreSplitReg(VirtReg)) 958 continue; // Split interval spilled again. 959 unsigned Phys = VRM.getPhys(VirtReg); 960 MF.setPhysRegUsed(Phys); 961 if (VRM.isReMaterialized(VirtReg)) { 962 MRI->reMaterialize(MBB, &MI, Phys, 963 VRM.getReMaterializedMI(VirtReg)); 964 ++NumReMats; 965 } else { 966 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); 967 MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC); 968 ++NumLoads; 969 } 970 // This invalidates Phys. 971 Spills.ClobberPhysReg(Phys); 972 UpdateKills(*prior(MII), RegKills, KillOps); 973 DOUT << '\t' << *prior(MII); 974 } 975 } 976 977 // Insert spills here if asked to. 978 if (VRM.isSpillPt(&MI)) { 979 std::vector<unsigned> &SpillRegs = VRM.getSpillPtSpills(&MI); 980 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 981 unsigned VirtReg = SpillRegs[i]; 982 if (!VRM.getPreSplitReg(VirtReg)) 983 continue; // Split interval spilled again. 984 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); 985 unsigned Phys = VRM.getPhys(VirtReg); 986 int StackSlot = VRM.getStackSlot(VirtReg); 987 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 988 SpillRegToStackSlot(MBB, MII, i, Phys, StackSlot, RC, 989 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 990 } 991 } 992 993 /// ReusedOperands - Keep track of operand reuse in case we need to undo 994 /// reuse. 995 ReuseInfo ReusedOperands(MI, MRI); 996 // Process all of the spilled uses and all non spilled reg references. 997 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 998 MachineOperand &MO = MI.getOperand(i); 999 if (!MO.isRegister() || MO.getReg() == 0) 1000 continue; // Ignore non-register operands. 1001 1002 unsigned VirtReg = MO.getReg(); 1003 if (MRegisterInfo::isPhysicalRegister(VirtReg)) { 1004 // Ignore physregs for spilling, but remember that it is used by this 1005 // function. 1006 MF.setPhysRegUsed(VirtReg); 1007 continue; 1008 } 1009 1010 assert(MRegisterInfo::isVirtualRegister(VirtReg) && 1011 "Not a virtual or a physical register?"); 1012 1013 unsigned SubIdx = MO.getSubReg(); 1014 if (VRM.isAssignedReg(VirtReg)) { 1015 // This virtual register was assigned a physreg! 1016 unsigned Phys = VRM.getPhys(VirtReg); 1017 MF.setPhysRegUsed(Phys); 1018 if (MO.isDef()) 1019 ReusedOperands.markClobbered(Phys); 1020 unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; 1021 MI.getOperand(i).setReg(RReg); 1022 continue; 1023 } 1024 1025 // This virtual register is now known to be a spilled value. 1026 if (!MO.isUse()) 1027 continue; // Handle defs in the loop below (handle use&def here though) 1028 1029 bool DoReMat = VRM.isReMaterialized(VirtReg); 1030 int SSorRMId = DoReMat 1031 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1032 int ReuseSlot = SSorRMId; 1033 1034 // Check to see if this stack slot is available. 1035 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1036 if (!PhysReg && DoReMat) { 1037 // This use is rematerializable. But perhaps the value is available in 1038 // a register if the definition is not deleted. If so, check if we can 1039 // reuse the value. 1040 ReuseSlot = VRM.getStackSlot(VirtReg); 1041 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT) 1042 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot); 1043 } 1044 1045 // If this is a sub-register use, make sure the reuse register is in the 1046 // right register class. For example, for x86 not all of the 32-bit 1047 // registers have accessible sub-registers. 1048 // Similarly so for EXTRACT_SUBREG. Consider this: 1049 // EDI = op 1050 // MOV32_mr fi#1, EDI 1051 // ... 1052 // = EXTRACT_SUBREG fi#1 1053 // fi#1 is available in EDI, but it cannot be reused because it's not in 1054 // the right register file. 1055 if (PhysReg && 1056 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1057 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); 1058 if (!RC->contains(PhysReg)) 1059 PhysReg = 0; 1060 } 1061 1062 if (PhysReg) { 1063 // This spilled operand might be part of a two-address operand. If this 1064 // is the case, then changing it will necessarily require changing the 1065 // def part of the instruction as well. However, in some cases, we 1066 // aren't allowed to modify the reused register. If none of these cases 1067 // apply, reuse it. 1068 bool CanReuse = true; 1069 int ti = TID->getOperandConstraint(i, TOI::TIED_TO); 1070 if (ti != -1 && 1071 MI.getOperand(ti).isRegister() && 1072 MI.getOperand(ti).getReg() == VirtReg) { 1073 // Okay, we have a two address operand. We can reuse this physreg as 1074 // long as we are allowed to clobber the value and there isn't an 1075 // earlier def that has already clobbered the physreg. 1076 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1077 !ReusedOperands.isClobbered(PhysReg); 1078 } 1079 1080 if (CanReuse) { 1081 // If this stack slot value is already available, reuse it! 1082 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1083 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1084 else 1085 DOUT << "Reusing SS#" << ReuseSlot; 1086 DOUT << " from physreg " 1087 << MRI->getName(PhysReg) << " for vreg" 1088 << VirtReg <<" instead of reloading into physreg " 1089 << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1090 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1091 MI.getOperand(i).setReg(RReg); 1092 1093 // The only technical detail we have is that we don't know that 1094 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1095 // later in the instruction. In particular, consider 'op V1, V2'. 1096 // If V1 is available in physreg R0, we would choose to reuse it 1097 // here, instead of reloading it into the register the allocator 1098 // indicated (say R1). However, V2 might have to be reloaded 1099 // later, and it might indicate that it needs to live in R0. When 1100 // this occurs, we need to have information available that 1101 // indicates it is safe to use R1 for the reload instead of R0. 1102 // 1103 // To further complicate matters, we might conflict with an alias, 1104 // or R0 and R1 might not be compatible with each other. In this 1105 // case, we actually insert a reload for V1 in R1, ensuring that 1106 // we can get at R0 or its alias. 1107 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1108 VRM.getPhys(VirtReg), VirtReg); 1109 if (ti != -1) 1110 // Only mark it clobbered if this is a use&def operand. 1111 ReusedOperands.markClobbered(PhysReg); 1112 ++NumReused; 1113 1114 if (MI.getOperand(i).isKill() && 1115 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1116 // This was the last use and the spilled value is still available 1117 // for reuse. That means the spill was unnecessary! 1118 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; 1119 if (DeadStore) { 1120 DOUT << "Removed dead store:\t" << *DeadStore; 1121 InvalidateKills(*DeadStore, RegKills, KillOps); 1122 VRM.RemoveMachineInstrFromMaps(DeadStore); 1123 MBB.erase(DeadStore); 1124 MaybeDeadStores[ReuseSlot] = NULL; 1125 ++NumDSE; 1126 } 1127 } 1128 continue; 1129 } // CanReuse 1130 1131 // Otherwise we have a situation where we have a two-address instruction 1132 // whose mod/ref operand needs to be reloaded. This reload is already 1133 // available in some register "PhysReg", but if we used PhysReg as the 1134 // operand to our 2-addr instruction, the instruction would modify 1135 // PhysReg. This isn't cool if something later uses PhysReg and expects 1136 // to get its initial value. 1137 // 1138 // To avoid this problem, and to avoid doing a load right after a store, 1139 // we emit a copy from PhysReg into the designated register for this 1140 // operand. 1141 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1142 assert(DesignatedReg && "Must map virtreg to physreg!"); 1143 1144 // Note that, if we reused a register for a previous operand, the 1145 // register we want to reload into might not actually be 1146 // available. If this occurs, use the register indicated by the 1147 // reuser. 1148 if (ReusedOperands.hasReuses()) 1149 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1150 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1151 1152 // If the mapped designated register is actually the physreg we have 1153 // incoming, we don't need to inserted a dead copy. 1154 if (DesignatedReg == PhysReg) { 1155 // If this stack slot value is already available, reuse it! 1156 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1157 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1158 else 1159 DOUT << "Reusing SS#" << ReuseSlot; 1160 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" 1161 << VirtReg 1162 << " instead of reloading into same physreg.\n"; 1163 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1164 MI.getOperand(i).setReg(RReg); 1165 ReusedOperands.markClobbered(RReg); 1166 ++NumReused; 1167 continue; 1168 } 1169 1170 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); 1171 MF.setPhysRegUsed(DesignatedReg); 1172 ReusedOperands.markClobbered(DesignatedReg); 1173 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1174 1175 MachineInstr *CopyMI = prior(MII); 1176 UpdateKills(*CopyMI, RegKills, KillOps); 1177 1178 // This invalidates DesignatedReg. 1179 Spills.ClobberPhysReg(DesignatedReg); 1180 1181 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); 1182 unsigned RReg = 1183 SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1184 MI.getOperand(i).setReg(RReg); 1185 DOUT << '\t' << *prior(MII); 1186 ++NumReused; 1187 continue; 1188 } // if (PhysReg) 1189 1190 // Otherwise, reload it and remember that we have it. 1191 PhysReg = VRM.getPhys(VirtReg); 1192 assert(PhysReg && "Must map virtreg to physreg!"); 1193 1194 // Note that, if we reused a register for a previous operand, the 1195 // register we want to reload into might not actually be 1196 // available. If this occurs, use the register indicated by the 1197 // reuser. 1198 if (ReusedOperands.hasReuses()) 1199 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1200 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1201 1202 MF.setPhysRegUsed(PhysReg); 1203 ReusedOperands.markClobbered(PhysReg); 1204 if (DoReMat) { 1205 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); 1206 ++NumReMats; 1207 } else { 1208 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg); 1209 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1210 ++NumLoads; 1211 } 1212 // This invalidates PhysReg. 1213 Spills.ClobberPhysReg(PhysReg); 1214 1215 // Any stores to this stack slot are not dead anymore. 1216 if (!DoReMat) 1217 MaybeDeadStores[SSorRMId] = NULL; 1218 Spills.addAvailable(SSorRMId, &MI, PhysReg); 1219 // Assumes this is the last use. IsKill will be unset if reg is reused 1220 // unless it's a two-address operand. 1221 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1) 1222 MI.getOperand(i).setIsKill(); 1223 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1224 MI.getOperand(i).setReg(RReg); 1225 UpdateKills(*prior(MII), RegKills, KillOps); 1226 DOUT << '\t' << *prior(MII); 1227 } 1228 1229 DOUT << '\t' << MI; 1230 1231 1232 // If we have folded references to memory operands, make sure we clear all 1233 // physical registers that may contain the value of the spilled virtual 1234 // register 1235 SmallSet<int, 2> FoldedSS; 1236 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { 1237 unsigned VirtReg = I->second.first; 1238 VirtRegMap::ModRef MR = I->second.second; 1239 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1240 1241 int SS = VRM.getStackSlot(VirtReg); 1242 if (SS == VirtRegMap::NO_STACK_SLOT) 1243 continue; 1244 FoldedSS.insert(SS); 1245 DOUT << " - StackSlot: " << SS << "\n"; 1246 1247 // If this folded instruction is just a use, check to see if it's a 1248 // straight load from the virt reg slot. 1249 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1250 int FrameIdx; 1251 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1252 if (DestReg && FrameIdx == SS) { 1253 // If this spill slot is available, turn it into a copy (or nothing) 1254 // instead of leaving it as a load! 1255 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1256 DOUT << "Promoted Load To Copy: " << MI; 1257 if (DestReg != InReg) { 1258 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); 1259 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1260 // Revisit the copy so we make sure to notice the effects of the 1261 // operation on the destreg (either needing to RA it if it's 1262 // virtual or needing to clobber any values if it's physical). 1263 NextMII = &MI; 1264 --NextMII; // backtrack to the copy. 1265 BackTracked = true; 1266 } else 1267 DOUT << "Removing now-noop copy: " << MI; 1268 1269 VRM.RemoveMachineInstrFromMaps(&MI); 1270 MBB.erase(&MI); 1271 Erased = true; 1272 goto ProcessNextInst; 1273 } 1274 } else { 1275 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1276 SmallVector<MachineInstr*, 4> NewMIs; 1277 if (PhysReg && 1278 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1279 MBB.insert(MII, NewMIs[0]); 1280 VRM.RemoveMachineInstrFromMaps(&MI); 1281 MBB.erase(&MI); 1282 Erased = true; 1283 --NextMII; // backtrack to the unfolded instruction. 1284 BackTracked = true; 1285 goto ProcessNextInst; 1286 } 1287 } 1288 } 1289 1290 // If this reference is not a use, any previous store is now dead. 1291 // Otherwise, the store to this stack slot is not dead anymore. 1292 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1293 if (DeadStore) { 1294 bool isDead = !(MR & VirtRegMap::isRef); 1295 MachineInstr *NewStore = NULL; 1296 if (MR & VirtRegMap::isModRef) { 1297 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1298 SmallVector<MachineInstr*, 4> NewMIs; 1299 if (PhysReg && 1300 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 && 1301 MRI->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) { 1302 MBB.insert(MII, NewMIs[0]); 1303 NewStore = NewMIs[1]; 1304 MBB.insert(MII, NewStore); 1305 VRM.RemoveMachineInstrFromMaps(&MI); 1306 MBB.erase(&MI); 1307 Erased = true; 1308 --NextMII; 1309 --NextMII; // backtrack to the unfolded instruction. 1310 BackTracked = true; 1311 isDead = true; 1312 } 1313 } 1314 1315 if (isDead) { // Previous store is dead. 1316 // If we get here, the store is dead, nuke it now. 1317 DOUT << "Removed dead store:\t" << *DeadStore; 1318 InvalidateKills(*DeadStore, RegKills, KillOps); 1319 VRM.RemoveMachineInstrFromMaps(DeadStore); 1320 MBB.erase(DeadStore); 1321 if (!NewStore) 1322 ++NumDSE; 1323 } 1324 1325 MaybeDeadStores[SS] = NULL; 1326 if (NewStore) { 1327 // Treat this store as a spill merged into a copy. That makes the 1328 // stack slot value available. 1329 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1330 goto ProcessNextInst; 1331 } 1332 } 1333 1334 // If the spill slot value is available, and this is a new definition of 1335 // the value, the value is not available anymore. 1336 if (MR & VirtRegMap::isMod) { 1337 // Notice that the value in this stack slot has been modified. 1338 Spills.ModifyStackSlotOrReMat(SS); 1339 1340 // If this is *just* a mod of the value, check to see if this is just a 1341 // store to the spill slot (i.e. the spill got merged into the copy). If 1342 // so, realize that the vreg is available now, and add the store to the 1343 // MaybeDeadStore info. 1344 int StackSlot; 1345 if (!(MR & VirtRegMap::isRef)) { 1346 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1347 assert(MRegisterInfo::isPhysicalRegister(SrcReg) && 1348 "Src hasn't been allocated yet?"); 1349 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1350 // this as a potentially dead store in case there is a subsequent 1351 // store into the stack slot without a read from it. 1352 MaybeDeadStores[StackSlot] = &MI; 1353 1354 // If the stack slot value was previously available in some other 1355 // register, change it now. Otherwise, make the register available, 1356 // in PhysReg. 1357 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); 1358 } 1359 } 1360 } 1361 } 1362 1363 // Process all of the spilled defs. 1364 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1365 MachineOperand &MO = MI.getOperand(i); 1366 if (!(MO.isRegister() && MO.getReg() && MO.isDef())) 1367 continue; 1368 1369 unsigned VirtReg = MO.getReg(); 1370 if (!MRegisterInfo::isVirtualRegister(VirtReg)) { 1371 // Check to see if this is a noop copy. If so, eliminate the 1372 // instruction before considering the dest reg to be changed. 1373 unsigned Src, Dst; 1374 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1375 ++NumDCE; 1376 DOUT << "Removing now-noop copy: " << MI; 1377 MBB.erase(&MI); 1378 Erased = true; 1379 VRM.RemoveMachineInstrFromMaps(&MI); 1380 Spills.disallowClobberPhysReg(VirtReg); 1381 goto ProcessNextInst; 1382 } 1383 1384 // If it's not a no-op copy, it clobbers the value in the destreg. 1385 Spills.ClobberPhysReg(VirtReg); 1386 ReusedOperands.markClobbered(VirtReg); 1387 1388 // Check to see if this instruction is a load from a stack slot into 1389 // a register. If so, this provides the stack slot value in the reg. 1390 int FrameIdx; 1391 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1392 assert(DestReg == VirtReg && "Unknown load situation!"); 1393 1394 // If it is a folded reference, then it's not safe to clobber. 1395 bool Folded = FoldedSS.count(FrameIdx); 1396 // Otherwise, if it wasn't available, remember that it is now! 1397 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); 1398 goto ProcessNextInst; 1399 } 1400 1401 continue; 1402 } 1403 1404 unsigned SubIdx = MO.getSubReg(); 1405 bool DoReMat = VRM.isReMaterialized(VirtReg); 1406 if (DoReMat) 1407 ReMatDefs.insert(&MI); 1408 1409 // The only vregs left are stack slot definitions. 1410 int StackSlot = VRM.getStackSlot(VirtReg); 1411 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg); 1412 1413 // If this def is part of a two-address operand, make sure to execute 1414 // the store from the correct physical register. 1415 unsigned PhysReg; 1416 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i); 1417 if (TiedOp != -1) { 1418 PhysReg = MI.getOperand(TiedOp).getReg(); 1419 if (SubIdx) { 1420 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI); 1421 assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1422 "Can't find corresponding super-register!"); 1423 PhysReg = SuperReg; 1424 } 1425 } else { 1426 PhysReg = VRM.getPhys(VirtReg); 1427 if (ReusedOperands.isClobbered(PhysReg)) { 1428 // Another def has taken the assigned physreg. It must have been a 1429 // use&def which got it due to reuse. Undo the reuse! 1430 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1431 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1432 } 1433 } 1434 1435 MF.setPhysRegUsed(PhysReg); 1436 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1437 ReusedOperands.markClobbered(RReg); 1438 MI.getOperand(i).setReg(RReg); 1439 1440 if (!MO.isDead()) { 1441 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1442 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, LastStore, 1443 Spills, ReMatDefs, RegKills, KillOps, VRM); 1444 1445 // Check to see if this is a noop copy. If so, eliminate the 1446 // instruction before considering the dest reg to be changed. 1447 { 1448 unsigned Src, Dst; 1449 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1450 ++NumDCE; 1451 DOUT << "Removing now-noop copy: " << MI; 1452 MBB.erase(&MI); 1453 Erased = true; 1454 VRM.RemoveMachineInstrFromMaps(&MI); 1455 UpdateKills(*LastStore, RegKills, KillOps); 1456 goto ProcessNextInst; 1457 } 1458 } 1459 } 1460 } 1461 ProcessNextInst: 1462 if (!Erased && !BackTracked) 1463 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) 1464 UpdateKills(*II, RegKills, KillOps); 1465 MII = NextMII; 1466 } 1467} 1468 1469llvm::Spiller* llvm::createSpiller() { 1470 switch (SpillerOpt) { 1471 default: assert(0 && "Unreachable!"); 1472 case local: 1473 return new LocalSpiller(); 1474 case simple: 1475 return new SimpleSpiller(); 1476 } 1477} 1478