VirtRegMap.cpp revision b55e91e08738b804f17109a49881e51b69e91299 
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
15// code as necessary.
16//
17//===----------------------------------------------------------------------===//
18
19#define DEBUG_TYPE "virtregmap"
20#include "VirtRegMap.h"
21#include "llvm/Function.h"
22#include "llvm/CodeGen/LiveIntervalAnalysis.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/Target/TargetMachine.h"
28#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetRegisterInfo.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/ADT/BitVector.h"
35#include "llvm/ADT/DenseMap.h"
36#include "llvm/ADT/DepthFirstIterator.h"
37#include "llvm/ADT/Statistic.h"
38#include "llvm/ADT/STLExtras.h"
39#include "llvm/ADT/SmallSet.h"
40#include <algorithm>
41using namespace llvm;
42
43STATISTIC(NumSpills  , "Number of register spills");
44
45//===----------------------------------------------------------------------===//
46//  VirtRegMap implementation
47//===----------------------------------------------------------------------===//
48
49char VirtRegMap::ID = 0;
50
51INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
52
53bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
54  MRI = &mf.getRegInfo();
55  TII = mf.getTarget().getInstrInfo();
56  TRI = mf.getTarget().getRegisterInfo();
57  MF = &mf;
58
59  ReMatId = MAX_STACK_SLOT+1;
60  LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
61
62  Virt2PhysMap.clear();
63  Virt2StackSlotMap.clear();
64  Virt2ReMatIdMap.clear();
65  Virt2SplitMap.clear();
66  Virt2SplitKillMap.clear();
67  ReMatMap.clear();
68  ImplicitDefed.clear();
69  SpillSlotToUsesMap.clear();
70  MI2VirtMap.clear();
71  SpillPt2VirtMap.clear();
72  RestorePt2VirtMap.clear();
73  EmergencySpillMap.clear();
74  EmergencySpillSlots.clear();
75
76  SpillSlotToUsesMap.resize(8);
77  ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
78                       TargetRegisterInfo::FirstVirtualRegister);
79
80  allocatableRCRegs.clear();
81  for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
82         E = TRI->regclass_end(); I != E; ++I)
83    allocatableRCRegs.insert(std::make_pair(*I,
84                                            TRI->getAllocatableSet(mf, *I)));
85
86  grow();
87
88  return false;
89}
90
91void VirtRegMap::grow() {
92  unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
93  Virt2PhysMap.grow(LastVirtReg);
94  Virt2StackSlotMap.grow(LastVirtReg);
95  Virt2ReMatIdMap.grow(LastVirtReg);
96  Virt2SplitMap.grow(LastVirtReg);
97  Virt2SplitKillMap.grow(LastVirtReg);
98  ReMatMap.grow(LastVirtReg);
99  ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
100}
101
102unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
103  int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
104                                                      RC->getAlignment());
105  if (LowSpillSlot == NO_STACK_SLOT)
106    LowSpillSlot = SS;
107  if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
108    HighSpillSlot = SS;
109  assert(SS >= LowSpillSlot && "Unexpected low spill slot");
110  unsigned Idx = SS-LowSpillSlot;
111  while (Idx >= SpillSlotToUsesMap.size())
112    SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
113  return SS;
114}
115
116unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
117  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
118  unsigned physReg = Hint.second;
119  if (physReg &&
120      TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
121    physReg = getPhys(physReg);
122  if (Hint.first == 0)
123    return (physReg && TargetRegisterInfo::isPhysicalRegister(physReg))
124      ? physReg : 0;
125  return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
126}
127
128int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
129  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
130  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
131         "attempt to assign stack slot to already spilled register");
132  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
133  ++NumSpills;
134  return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
135}
136
137void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
138  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
139  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
140         "attempt to assign stack slot to already spilled register");
141  assert((SS >= 0 ||
142          (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
143         "illegal fixed frame index");
144  Virt2StackSlotMap[virtReg] = SS;
145}
146
147int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
148  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
149  assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
150         "attempt to assign re-mat id to already spilled register");
151  Virt2ReMatIdMap[virtReg] = ReMatId;
152  return ReMatId++;
153}
154
155void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
156  assert(TargetRegisterInfo::isVirtualRegister(virtReg));
157  assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
158         "attempt to assign re-mat id to already spilled register");
159  Virt2ReMatIdMap[virtReg] = id;
160}
161
162int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
163  std::map<const TargetRegisterClass*, int>::iterator I =
164    EmergencySpillSlots.find(RC);
165  if (I != EmergencySpillSlots.end())
166    return I->second;
167  return EmergencySpillSlots[RC] = createSpillSlot(RC);
168}
169
170void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
171  if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
172    // If FI < LowSpillSlot, this stack reference was produced by
173    // instruction selection and is not a spill
174    if (FI >= LowSpillSlot) {
175      assert(FI >= 0 && "Spill slot index should not be negative!");
176      assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
177             && "Invalid spill slot");
178      SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
179    }
180  }
181}
182
183void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
184                            MachineInstr *NewMI, ModRef MRInfo) {
185  // Move previous memory references folded to new instruction.
186  MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
187  for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
188         E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
189    MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
190    MI2VirtMap.erase(I++);
191  }
192
193  // add new memory reference
194  MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
195}
196
197void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
198  MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
199  MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
200}
201
202void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
203  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
204    MachineOperand &MO = MI->getOperand(i);
205    if (!MO.isFI())
206      continue;
207    int FI = MO.getIndex();
208    if (MF->getFrameInfo()->isFixedObjectIndex(FI))
209      continue;
210    // This stack reference was produced by instruction selection and
211    // is not a spill
212    if (FI < LowSpillSlot)
213      continue;
214    assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
215           && "Invalid spill slot");
216    SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
217  }
218  MI2VirtMap.erase(MI);
219  SpillPt2VirtMap.erase(MI);
220  RestorePt2VirtMap.erase(MI);
221  EmergencySpillMap.erase(MI);
222}
223
224/// FindUnusedRegisters - Gather a list of allocatable registers that
225/// have not been allocated to any virtual register.
226bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
227  unsigned NumRegs = TRI->getNumRegs();
228  UnusedRegs.reset();
229  UnusedRegs.resize(NumRegs);
230
231  BitVector Used(NumRegs);
232  for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
233         e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
234    if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
235      Used.set(Virt2PhysMap[i]);
236
237  BitVector Allocatable = TRI->getAllocatableSet(*MF);
238  bool AnyUnused = false;
239  for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
240    if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
241      bool ReallyUnused = true;
242      for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
243        if (Used[*AS] || LIs->hasInterval(*AS)) {
244          ReallyUnused = false;
245          break;
246        }
247      }
248      if (ReallyUnused) {
249        AnyUnused = true;
250        UnusedRegs.set(Reg);
251      }
252    }
253  }
254
255  return AnyUnused;
256}
257
258void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
259  const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
260  const MachineRegisterInfo &MRI = MF->getRegInfo();
261
262  OS << "********** REGISTER MAP **********\n";
263  for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
264         e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) {
265    if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
266      OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
267         << "] " << MRI.getRegClass(i)->getName() << "\n";
268  }
269
270  for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
271         e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
272    if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
273      OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i]
274         << "] " << MRI.getRegClass(i)->getName() << "\n";
275  OS << '\n';
276}
277
278void VirtRegMap::dump() const {
279  print(dbgs());
280}
281