VirtRegMap.cpp revision c7e737e1ce677ae43da7767cbecddfca4df32eca
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/ADT/BitVector.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/ADT/SmallSet.h" 36#include <algorithm> 37using namespace llvm; 38 39STATISTIC(NumSpills , "Number of register spills"); 40STATISTIC(NumPSpills , "Number of physical register spills"); 41STATISTIC(NumReMats , "Number of re-materialization"); 42STATISTIC(NumDRM , "Number of re-materializable defs elided"); 43STATISTIC(NumStores , "Number of stores added"); 44STATISTIC(NumLoads , "Number of loads added"); 45STATISTIC(NumReused , "Number of values reused"); 46STATISTIC(NumDSE , "Number of dead stores elided"); 47STATISTIC(NumDCE , "Number of copies elided"); 48STATISTIC(NumDSS , "Number of dead spill slots removed"); 49STATISTIC(NumCommutes, "Number of instructions commuted"); 50 51namespace { 52 enum SpillerName { simple, local }; 53} 54 55static cl::opt<SpillerName> 56SpillerOpt("spiller", 57 cl::desc("Spiller to use: (default: local)"), 58 cl::Prefix, 59 cl::values(clEnumVal(simple, " simple spiller"), 60 clEnumVal(local, " local spiller"), 61 clEnumValEnd), 62 cl::init(local)); 63 64//===----------------------------------------------------------------------===// 65// VirtRegMap implementation 66//===----------------------------------------------------------------------===// 67 68VirtRegMap::VirtRegMap(MachineFunction &mf) 69 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 70 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 71 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 72 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), 73 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { 74 SpillSlotToUsesMap.resize(8); 75 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- 76 TargetRegisterInfo::FirstVirtualRegister); 77 grow(); 78} 79 80void VirtRegMap::grow() { 81 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); 82 Virt2PhysMap.grow(LastVirtReg); 83 Virt2StackSlotMap.grow(LastVirtReg); 84 Virt2ReMatIdMap.grow(LastVirtReg); 85 Virt2SplitMap.grow(LastVirtReg); 86 Virt2SplitKillMap.grow(LastVirtReg); 87 ReMatMap.grow(LastVirtReg); 88 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1); 89} 90 91int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 92 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 93 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 94 "attempt to assign stack slot to already spilled register"); 95 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); 96 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 97 RC->getAlignment()); 98 if (LowSpillSlot == NO_STACK_SLOT) 99 LowSpillSlot = SS; 100 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 101 HighSpillSlot = SS; 102 unsigned Idx = SS-LowSpillSlot; 103 while (Idx >= SpillSlotToUsesMap.size()) 104 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); 105 Virt2StackSlotMap[virtReg] = SS; 106 ++NumSpills; 107 return SS; 108} 109 110void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 111 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 113 "attempt to assign stack slot to already spilled register"); 114 assert((SS >= 0 || 115 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && 116 "illegal fixed frame index"); 117 Virt2StackSlotMap[virtReg] = SS; 118} 119 120int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 121 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 122 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 123 "attempt to assign re-mat id to already spilled register"); 124 Virt2ReMatIdMap[virtReg] = ReMatId; 125 return ReMatId++; 126} 127 128void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 129 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 130 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 131 "attempt to assign re-mat id to already spilled register"); 132 Virt2ReMatIdMap[virtReg] = id; 133} 134 135int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { 136 std::map<const TargetRegisterClass*, int>::iterator I = 137 EmergencySpillSlots.find(RC); 138 if (I != EmergencySpillSlots.end()) 139 return I->second; 140 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 141 RC->getAlignment()); 142 if (LowSpillSlot == NO_STACK_SLOT) 143 LowSpillSlot = SS; 144 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 145 HighSpillSlot = SS; 146 I->second = SS; 147 return SS; 148} 149 150void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { 151 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { 152 // If FI < LowSpillSlot, this stack reference was produced by 153 // instruction selection and is not a spill 154 if (FI >= LowSpillSlot) { 155 assert(FI >= 0 && "Spill slot index should not be negative!"); 156 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 157 && "Invalid spill slot"); 158 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); 159 } 160 } 161} 162 163void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 164 MachineInstr *NewMI, ModRef MRInfo) { 165 // Move previous memory references folded to new instruction. 166 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 167 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 168 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 169 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 170 MI2VirtMap.erase(I++); 171 } 172 173 // add new memory reference 174 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 175} 176 177void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 178 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 179 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 180} 181 182void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { 183 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 184 MachineOperand &MO = MI->getOperand(i); 185 if (!MO.isFrameIndex()) 186 continue; 187 int FI = MO.getIndex(); 188 if (MF.getFrameInfo()->isFixedObjectIndex(FI)) 189 continue; 190 // This stack reference was produced by instruction selection and 191 // is not a spill 192 if (FI < LowSpillSlot) 193 continue; 194 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 195 && "Invalid spill slot"); 196 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); 197 } 198 MI2VirtMap.erase(MI); 199 SpillPt2VirtMap.erase(MI); 200 RestorePt2VirtMap.erase(MI); 201 EmergencySpillMap.erase(MI); 202} 203 204void VirtRegMap::print(std::ostream &OS) const { 205 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); 206 207 OS << "********** REGISTER MAP **********\n"; 208 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 209 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { 210 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 211 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) 212 << "]\n"; 213 } 214 215 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 216 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) 217 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 218 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 219 OS << '\n'; 220} 221 222void VirtRegMap::dump() const { 223 print(cerr); 224} 225 226 227//===----------------------------------------------------------------------===// 228// Simple Spiller Implementation 229//===----------------------------------------------------------------------===// 230 231Spiller::~Spiller() {} 232 233namespace { 234 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 235 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 236 }; 237} 238 239bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 240 DOUT << "********** REWRITE MACHINE CODE **********\n"; 241 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 242 const TargetMachine &TM = MF.getTarget(); 243 const TargetInstrInfo &TII = *TM.getInstrInfo(); 244 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 245 246 247 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 248 // each vreg once (in the case where a spilled vreg is used by multiple 249 // operands). This is always smaller than the number of operands to the 250 // current machine instr, so it should be small. 251 std::vector<unsigned> LoadedRegs; 252 253 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 254 MBBI != E; ++MBBI) { 255 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 256 MachineBasicBlock &MBB = *MBBI; 257 for (MachineBasicBlock::iterator MII = MBB.begin(), 258 E = MBB.end(); MII != E; ++MII) { 259 MachineInstr &MI = *MII; 260 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 261 MachineOperand &MO = MI.getOperand(i); 262 if (MO.isRegister() && MO.getReg()) { 263 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 264 unsigned VirtReg = MO.getReg(); 265 unsigned SubIdx = MO.getSubReg(); 266 unsigned PhysReg = VRM.getPhys(VirtReg); 267 unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg; 268 if (!VRM.isAssignedReg(VirtReg)) { 269 int StackSlot = VRM.getStackSlot(VirtReg); 270 const TargetRegisterClass* RC = 271 MF.getRegInfo().getRegClass(VirtReg); 272 273 if (MO.isUse() && 274 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 275 == LoadedRegs.end()) { 276 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 277 MachineInstr *LoadMI = prior(MII); 278 VRM.addSpillSlotUse(StackSlot, LoadMI); 279 LoadedRegs.push_back(VirtReg); 280 ++NumLoads; 281 DOUT << '\t' << *LoadMI; 282 } 283 284 if (MO.isDef()) { 285 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, 286 StackSlot, RC); 287 MachineInstr *StoreMI = next(MII); 288 VRM.addSpillSlotUse(StackSlot, StoreMI); 289 ++NumStores; 290 } 291 } 292 MF.getRegInfo().setPhysRegUsed(RReg); 293 MI.getOperand(i).setReg(RReg); 294 } else { 295 MF.getRegInfo().setPhysRegUsed(MO.getReg()); 296 } 297 } 298 } 299 300 DOUT << '\t' << MI; 301 LoadedRegs.clear(); 302 } 303 } 304 return true; 305} 306 307//===----------------------------------------------------------------------===// 308// Local Spiller Implementation 309//===----------------------------------------------------------------------===// 310 311namespace { 312 class AvailableSpills; 313 314 /// LocalSpiller - This spiller does a simple pass over the machine basic 315 /// block to attempt to keep spills in registers as much as possible for 316 /// blocks that have low register pressure (the vreg may be spilled due to 317 /// register pressure in other blocks). 318 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 319 MachineRegisterInfo *RegInfo; 320 const TargetRegisterInfo *TRI; 321 const TargetInstrInfo *TII; 322 DenseMap<MachineInstr*, unsigned> DistanceMap; 323 public: 324 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 325 RegInfo = &MF.getRegInfo(); 326 TRI = MF.getTarget().getRegisterInfo(); 327 TII = MF.getTarget().getInstrInfo(); 328 DOUT << "\n**** Local spiller rewriting function '" 329 << MF.getFunction()->getName() << "':\n"; 330 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" 331 " ****\n"; 332 DEBUG(MF.dump()); 333 334 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 335 MBB != E; ++MBB) 336 RewriteMBB(*MBB, VRM); 337 338 // Mark unused spill slots. 339 MachineFrameInfo *MFI = MF.getFrameInfo(); 340 int SS = VRM.getLowSpillSlot(); 341 if (SS != VirtRegMap::NO_STACK_SLOT) 342 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) 343 if (!VRM.isSpillSlotUsed(SS)) { 344 MFI->RemoveStackObject(SS); 345 ++NumDSS; 346 } 347 348 DOUT << "**** Post Machine Instrs ****\n"; 349 DEBUG(MF.dump()); 350 351 return true; 352 } 353 private: 354 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 355 unsigned Reg, BitVector &RegKills, 356 std::vector<MachineOperand*> &KillOps); 357 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 358 MachineBasicBlock::iterator &MII, 359 std::vector<MachineInstr*> &MaybeDeadStores, 360 AvailableSpills &Spills, BitVector &RegKills, 361 std::vector<MachineOperand*> &KillOps, 362 VirtRegMap &VRM); 363 bool CommuteToFoldReload(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator &MII, 365 unsigned VirtReg, unsigned SrcReg, int SS, 366 BitVector &RegKills, 367 std::vector<MachineOperand*> &KillOps, 368 const TargetRegisterInfo *TRI, 369 VirtRegMap &VRM); 370 void SpillRegToStackSlot(MachineBasicBlock &MBB, 371 MachineBasicBlock::iterator &MII, 372 int Idx, unsigned PhysReg, int StackSlot, 373 const TargetRegisterClass *RC, 374 bool isAvailable, MachineInstr *&LastStore, 375 AvailableSpills &Spills, 376 SmallSet<MachineInstr*, 4> &ReMatDefs, 377 BitVector &RegKills, 378 std::vector<MachineOperand*> &KillOps, 379 VirtRegMap &VRM); 380 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); 381 }; 382} 383 384/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 385/// top down, keep track of which spills slots or remat are available in each 386/// register. 387/// 388/// Note that not all physregs are created equal here. In particular, some 389/// physregs are reloads that we are allowed to clobber or ignore at any time. 390/// Other physregs are values that the register allocated program is using that 391/// we cannot CHANGE, but we can read if we like. We keep track of this on a 392/// per-stack-slot / remat id basis as the low bit in the value of the 393/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 394/// this bit and addAvailable sets it if. 395namespace { 396class VISIBILITY_HIDDEN AvailableSpills { 397 const TargetRegisterInfo *TRI; 398 const TargetInstrInfo *TII; 399 400 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 401 // or remat'ed virtual register values that are still available, due to being 402 // loaded or stored to, but not invalidated yet. 403 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 404 405 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 406 // indicating which stack slot values are currently held by a physreg. This 407 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 408 // physreg is modified. 409 std::multimap<unsigned, int> PhysRegsAvailable; 410 411 void disallowClobberPhysRegOnly(unsigned PhysReg); 412 413 void ClobberPhysRegOnly(unsigned PhysReg); 414public: 415 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) 416 : TRI(tri), TII(tii) { 417 } 418 419 const TargetRegisterInfo *getRegInfo() const { return TRI; } 420 421 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 422 /// available in a physical register, return that PhysReg, otherwise 423 /// return 0. 424 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 425 std::map<int, unsigned>::const_iterator I = 426 SpillSlotsOrReMatsAvailable.find(Slot); 427 if (I != SpillSlotsOrReMatsAvailable.end()) { 428 return I->second >> 1; // Remove the CanClobber bit. 429 } 430 return 0; 431 } 432 433 /// addAvailable - Mark that the specified stack slot / remat is available in 434 /// the specified physreg. If CanClobber is true, the physreg can be modified 435 /// at any time without changing the semantics of the program. 436 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, 437 bool CanClobber = true) { 438 // If this stack slot is thought to be available in some other physreg, 439 // remove its record. 440 ModifyStackSlotOrReMat(SlotOrReMat); 441 442 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 443 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 444 445 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 446 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 447 else 448 DOUT << "Remembering SS#" << SlotOrReMat; 449 DOUT << " in physreg " << TRI->getName(Reg) << "\n"; 450 } 451 452 /// canClobberPhysReg - Return true if the spiller is allowed to change the 453 /// value of the specified stackslot register if it desires. The specified 454 /// stack slot must be available in a physreg for this query to make sense. 455 bool canClobberPhysReg(int SlotOrReMat) const { 456 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 457 "Value not available!"); 458 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 459 } 460 461 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 462 /// stackslot register. The register is still available but is no longer 463 /// allowed to be modifed. 464 void disallowClobberPhysReg(unsigned PhysReg); 465 466 /// ClobberPhysReg - This is called when the specified physreg changes 467 /// value. We use this to invalidate any info about stuff that lives in 468 /// it and any of its aliases. 469 void ClobberPhysReg(unsigned PhysReg); 470 471 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 472 /// slot changes. This removes information about which register the previous 473 /// value for this slot lives in (as the previous value is dead now). 474 void ModifyStackSlotOrReMat(int SlotOrReMat); 475}; 476} 477 478/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 479/// stackslot register. The register is still available but is no longer 480/// allowed to be modifed. 481void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 482 std::multimap<unsigned, int>::iterator I = 483 PhysRegsAvailable.lower_bound(PhysReg); 484 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 485 int SlotOrReMat = I->second; 486 I++; 487 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 488 "Bidirectional map mismatch!"); 489 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 490 DOUT << "PhysReg " << TRI->getName(PhysReg) 491 << " copied, it is available for use but can no longer be modified\n"; 492 } 493} 494 495/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 496/// stackslot register and its aliases. The register and its aliases may 497/// still available but is no longer allowed to be modifed. 498void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 499 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 500 disallowClobberPhysRegOnly(*AS); 501 disallowClobberPhysRegOnly(PhysReg); 502} 503 504/// ClobberPhysRegOnly - This is called when the specified physreg changes 505/// value. We use this to invalidate any info about stuff we thing lives in it. 506void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 507 std::multimap<unsigned, int>::iterator I = 508 PhysRegsAvailable.lower_bound(PhysReg); 509 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 510 int SlotOrReMat = I->second; 511 PhysRegsAvailable.erase(I++); 512 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 513 "Bidirectional map mismatch!"); 514 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 515 DOUT << "PhysReg " << TRI->getName(PhysReg) 516 << " clobbered, invalidating "; 517 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 518 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 519 else 520 DOUT << "SS#" << SlotOrReMat << "\n"; 521 } 522} 523 524/// ClobberPhysReg - This is called when the specified physreg changes 525/// value. We use this to invalidate any info about stuff we thing lives in 526/// it and any of its aliases. 527void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 528 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 529 ClobberPhysRegOnly(*AS); 530 ClobberPhysRegOnly(PhysReg); 531} 532 533/// ModifyStackSlotOrReMat - This method is called when the value in a stack 534/// slot changes. This removes information about which register the previous 535/// value for this slot lives in (as the previous value is dead now). 536void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 537 std::map<int, unsigned>::iterator It = 538 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 539 if (It == SpillSlotsOrReMatsAvailable.end()) return; 540 unsigned Reg = It->second >> 1; 541 SpillSlotsOrReMatsAvailable.erase(It); 542 543 // This register may hold the value of multiple stack slots, only remove this 544 // stack slot from the set of values the register contains. 545 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 546 for (; ; ++I) { 547 assert(I != PhysRegsAvailable.end() && I->first == Reg && 548 "Map inverse broken!"); 549 if (I->second == SlotOrReMat) break; 550 } 551 PhysRegsAvailable.erase(I); 552} 553 554 555 556/// InvalidateKills - MI is going to be deleted. If any of its operands are 557/// marked kill, then invalidate the information. 558static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 559 std::vector<MachineOperand*> &KillOps, 560 SmallVector<unsigned, 2> *KillRegs = NULL) { 561 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 562 MachineOperand &MO = MI.getOperand(i); 563 if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) 564 continue; 565 unsigned Reg = MO.getReg(); 566 if (TargetRegisterInfo::isVirtualRegister(Reg)) 567 continue; 568 if (KillRegs) 569 KillRegs->push_back(Reg); 570 assert(Reg < KillOps.size()); 571 if (KillOps[Reg] == &MO) { 572 RegKills.reset(Reg); 573 KillOps[Reg] = NULL; 574 } 575 } 576} 577 578/// InvalidateKill - A MI that defines the specified register is being deleted, 579/// invalidate the register kill information. 580static void InvalidateKill(unsigned Reg, BitVector &RegKills, 581 std::vector<MachineOperand*> &KillOps) { 582 if (RegKills[Reg]) { 583 KillOps[Reg]->setIsKill(false); 584 KillOps[Reg] = NULL; 585 RegKills.reset(Reg); 586 } 587} 588 589/// InvalidateRegDef - If the def operand of the specified def MI is now dead 590/// (since it's spill instruction is removed), mark it isDead. Also checks if 591/// the def MI has other definition operands that are not dead. Returns it by 592/// reference. 593static bool InvalidateRegDef(MachineBasicBlock::iterator I, 594 MachineInstr &NewDef, unsigned Reg, 595 bool &HasLiveDef) { 596 // Due to remat, it's possible this reg isn't being reused. That is, 597 // the def of this reg (by prev MI) is now dead. 598 MachineInstr *DefMI = I; 599 MachineOperand *DefOp = NULL; 600 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 601 MachineOperand &MO = DefMI->getOperand(i); 602 if (MO.isRegister() && MO.isDef()) { 603 if (MO.getReg() == Reg) 604 DefOp = &MO; 605 else if (!MO.isDead()) 606 HasLiveDef = true; 607 } 608 } 609 if (!DefOp) 610 return false; 611 612 bool FoundUse = false, Done = false; 613 MachineBasicBlock::iterator E = &NewDef; 614 ++I; ++E; 615 for (; !Done && I != E; ++I) { 616 MachineInstr *NMI = I; 617 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 618 MachineOperand &MO = NMI->getOperand(j); 619 if (!MO.isRegister() || MO.getReg() != Reg) 620 continue; 621 if (MO.isUse()) 622 FoundUse = true; 623 Done = true; // Stop after scanning all the operands of this MI. 624 } 625 } 626 if (!FoundUse) { 627 // Def is dead! 628 DefOp->setIsDead(); 629 return true; 630 } 631 return false; 632} 633 634/// UpdateKills - Track and update kill info. If a MI reads a register that is 635/// marked kill, then it must be due to register reuse. Transfer the kill info 636/// over. 637static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 638 std::vector<MachineOperand*> &KillOps) { 639 const TargetInstrDesc &TID = MI.getDesc(); 640 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 641 MachineOperand &MO = MI.getOperand(i); 642 if (!MO.isRegister() || !MO.isUse()) 643 continue; 644 unsigned Reg = MO.getReg(); 645 if (Reg == 0) 646 continue; 647 648 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { 649 // That can't be right. Register is killed but not re-defined and it's 650 // being reused. Let's fix that. 651 KillOps[Reg]->setIsKill(false); 652 KillOps[Reg] = NULL; 653 RegKills.reset(Reg); 654 if (i < TID.getNumOperands() && 655 TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 656 // Unless it's a two-address operand, this is the new kill. 657 MO.setIsKill(); 658 } 659 if (MO.isKill()) { 660 RegKills.set(Reg); 661 KillOps[Reg] = &MO; 662 } 663 } 664 665 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 666 const MachineOperand &MO = MI.getOperand(i); 667 if (!MO.isRegister() || !MO.isDef()) 668 continue; 669 unsigned Reg = MO.getReg(); 670 RegKills.reset(Reg); 671 KillOps[Reg] = NULL; 672 } 673} 674 675/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. 676/// 677static void ReMaterialize(MachineBasicBlock &MBB, 678 MachineBasicBlock::iterator &MII, 679 unsigned DestReg, unsigned Reg, 680 const TargetInstrInfo *TII, 681 const TargetRegisterInfo *TRI, 682 VirtRegMap &VRM) { 683 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); 684 MachineInstr *NewMI = prior(MII); 685 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { 686 MachineOperand &MO = NewMI->getOperand(i); 687 if (!MO.isRegister() || MO.getReg() == 0) 688 continue; 689 unsigned VirtReg = MO.getReg(); 690 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 691 continue; 692 assert(MO.isUse()); 693 unsigned SubIdx = MO.getSubReg(); 694 unsigned Phys = VRM.getPhys(VirtReg); 695 assert(Phys); 696 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 697 MO.setReg(RReg); 698 } 699 ++NumReMats; 700} 701 702 703// ReusedOp - For each reused operand, we keep track of a bit of information, in 704// case we need to rollback upon processing a new operand. See comments below. 705namespace { 706 struct ReusedOp { 707 // The MachineInstr operand that reused an available value. 708 unsigned Operand; 709 710 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 711 unsigned StackSlotOrReMat; 712 713 // PhysRegReused - The physical register the value was available in. 714 unsigned PhysRegReused; 715 716 // AssignedPhysReg - The physreg that was assigned for use by the reload. 717 unsigned AssignedPhysReg; 718 719 // VirtReg - The virtual register itself. 720 unsigned VirtReg; 721 722 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 723 unsigned vreg) 724 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 725 AssignedPhysReg(apr), VirtReg(vreg) {} 726 }; 727 728 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 729 /// is reused instead of reloaded. 730 class VISIBILITY_HIDDEN ReuseInfo { 731 MachineInstr &MI; 732 std::vector<ReusedOp> Reuses; 733 BitVector PhysRegsClobbered; 734 public: 735 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { 736 PhysRegsClobbered.resize(tri->getNumRegs()); 737 } 738 739 bool hasReuses() const { 740 return !Reuses.empty(); 741 } 742 743 /// addReuse - If we choose to reuse a virtual register that is already 744 /// available instead of reloading it, remember that we did so. 745 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 746 unsigned PhysRegReused, unsigned AssignedPhysReg, 747 unsigned VirtReg) { 748 // If the reload is to the assigned register anyway, no undo will be 749 // required. 750 if (PhysRegReused == AssignedPhysReg) return; 751 752 // Otherwise, remember this. 753 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 754 AssignedPhysReg, VirtReg)); 755 } 756 757 void markClobbered(unsigned PhysReg) { 758 PhysRegsClobbered.set(PhysReg); 759 } 760 761 bool isClobbered(unsigned PhysReg) const { 762 return PhysRegsClobbered.test(PhysReg); 763 } 764 765 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 766 /// is some other operand that is using the specified register, either pick 767 /// a new register to use, or evict the previous reload and use this reg. 768 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 769 AvailableSpills &Spills, 770 std::vector<MachineInstr*> &MaybeDeadStores, 771 SmallSet<unsigned, 8> &Rejected, 772 BitVector &RegKills, 773 std::vector<MachineOperand*> &KillOps, 774 VirtRegMap &VRM) { 775 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() 776 .getInstrInfo(); 777 778 if (Reuses.empty()) return PhysReg; // This is most often empty. 779 780 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 781 ReusedOp &Op = Reuses[ro]; 782 // If we find some other reuse that was supposed to use this register 783 // exactly for its reload, we can change this reload to use ITS reload 784 // register. That is, unless its reload register has already been 785 // considered and subsequently rejected because it has also been reused 786 // by another operand. 787 if (Op.PhysRegReused == PhysReg && 788 Rejected.count(Op.AssignedPhysReg) == 0) { 789 // Yup, use the reload register that we didn't use before. 790 unsigned NewReg = Op.AssignedPhysReg; 791 Rejected.insert(PhysReg); 792 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 793 RegKills, KillOps, VRM); 794 } else { 795 // Otherwise, we might also have a problem if a previously reused 796 // value aliases the new register. If so, codegen the previous reload 797 // and use this one. 798 unsigned PRRU = Op.PhysRegReused; 799 const TargetRegisterInfo *TRI = Spills.getRegInfo(); 800 if (TRI->areAliases(PRRU, PhysReg)) { 801 // Okay, we found out that an alias of a reused register 802 // was used. This isn't good because it means we have 803 // to undo a previous reuse. 804 MachineBasicBlock *MBB = MI->getParent(); 805 const TargetRegisterClass *AliasRC = 806 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); 807 808 // Copy Op out of the vector and remove it, we're going to insert an 809 // explicit load for it. 810 ReusedOp NewOp = Op; 811 Reuses.erase(Reuses.begin()+ro); 812 813 // Ok, we're going to try to reload the assigned physreg into the 814 // slot that we were supposed to in the first place. However, that 815 // register could hold a reuse. Check to see if it conflicts or 816 // would prefer us to use a different register. 817 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 818 MI, Spills, MaybeDeadStores, 819 Rejected, RegKills, KillOps, VRM); 820 821 MachineBasicBlock::iterator MII = MI; 822 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 823 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM); 824 } else { 825 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, 826 NewOp.StackSlotOrReMat, AliasRC); 827 MachineInstr *LoadMI = prior(MII); 828 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); 829 // Any stores to this stack slot are not dead anymore. 830 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 831 ++NumLoads; 832 } 833 Spills.ClobberPhysReg(NewPhysReg); 834 Spills.ClobberPhysReg(NewOp.PhysRegReused); 835 836 MI->getOperand(NewOp.Operand).setReg(NewPhysReg); 837 838 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); 839 --MII; 840 UpdateKills(*MII, RegKills, KillOps); 841 DOUT << '\t' << *MII; 842 843 DOUT << "Reuse undone!\n"; 844 --NumReused; 845 846 // Finally, PhysReg is now available, go ahead and use it. 847 return PhysReg; 848 } 849 } 850 } 851 return PhysReg; 852 } 853 854 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 855 /// 'Rejected' set to remember which registers have been considered and 856 /// rejected for the reload. This avoids infinite looping in case like 857 /// this: 858 /// t1 := op t2, t3 859 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 860 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 861 /// t1 <- desires r1 862 /// sees r1 is taken by t2, tries t2's reload register r0 863 /// sees r0 is taken by t3, tries t3's reload register r1 864 /// sees r1 is taken by t2, tries t2's reload register r0 ... 865 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 866 AvailableSpills &Spills, 867 std::vector<MachineInstr*> &MaybeDeadStores, 868 BitVector &RegKills, 869 std::vector<MachineOperand*> &KillOps, 870 VirtRegMap &VRM) { 871 SmallSet<unsigned, 8> Rejected; 872 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 873 RegKills, KillOps, VRM); 874 } 875 }; 876} 877 878/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 879/// instruction. e.g. 880/// xorl %edi, %eax 881/// movl %eax, -32(%ebp) 882/// movl -36(%ebp), %eax 883/// orl %eax, -32(%ebp) 884/// ==> 885/// xorl %edi, %eax 886/// orl -36(%ebp), %eax 887/// mov %eax, -32(%ebp) 888/// This enables unfolding optimization for a subsequent instruction which will 889/// also eliminate the newly introduced store instruction. 890bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 891 MachineBasicBlock::iterator &MII, 892 std::vector<MachineInstr*> &MaybeDeadStores, 893 AvailableSpills &Spills, 894 BitVector &RegKills, 895 std::vector<MachineOperand*> &KillOps, 896 VirtRegMap &VRM) { 897 MachineFunction &MF = *MBB.getParent(); 898 MachineInstr &MI = *MII; 899 unsigned UnfoldedOpc = 0; 900 unsigned UnfoldPR = 0; 901 unsigned UnfoldVR = 0; 902 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 903 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 904 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 905 // Only transform a MI that folds a single register. 906 if (UnfoldedOpc) 907 return false; 908 UnfoldVR = I->second.first; 909 VirtRegMap::ModRef MR = I->second.second; 910 // MI2VirtMap be can updated which invalidate the iterator. 911 // Increment the iterator first. 912 ++I; 913 if (VRM.isAssignedReg(UnfoldVR)) 914 continue; 915 // If this reference is not a use, any previous store is now dead. 916 // Otherwise, the store to this stack slot is not dead anymore. 917 FoldedSS = VRM.getStackSlot(UnfoldVR); 918 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 919 if (DeadStore && (MR & VirtRegMap::isModRef)) { 920 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 921 if (!PhysReg || !DeadStore->readsRegister(PhysReg)) 922 continue; 923 UnfoldPR = PhysReg; 924 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 925 false, true); 926 } 927 } 928 929 if (!UnfoldedOpc) 930 return false; 931 932 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 933 MachineOperand &MO = MI.getOperand(i); 934 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) 935 continue; 936 unsigned VirtReg = MO.getReg(); 937 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 938 continue; 939 if (VRM.isAssignedReg(VirtReg)) { 940 unsigned PhysReg = VRM.getPhys(VirtReg); 941 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) 942 return false; 943 } else if (VRM.isReMaterialized(VirtReg)) 944 continue; 945 int SS = VRM.getStackSlot(VirtReg); 946 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 947 if (PhysReg) { 948 if (TRI->regsOverlap(PhysReg, UnfoldPR)) 949 return false; 950 continue; 951 } 952 if (VRM.hasPhys(VirtReg)) { 953 PhysReg = VRM.getPhys(VirtReg); 954 if (!TRI->regsOverlap(PhysReg, UnfoldPR)) 955 continue; 956 } 957 958 // Ok, we'll need to reload the value into a register which makes 959 // it impossible to perform the store unfolding optimization later. 960 // Let's see if it is possible to fold the load if the store is 961 // unfolded. This allows us to perform the store unfolding 962 // optimization. 963 SmallVector<MachineInstr*, 4> NewMIs; 964 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 965 assert(NewMIs.size() == 1); 966 MachineInstr *NewMI = NewMIs.back(); 967 NewMIs.clear(); 968 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); 969 assert(Idx != -1); 970 SmallVector<unsigned, 2> Ops; 971 Ops.push_back(Idx); 972 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); 973 if (FoldedMI) { 974 VRM.addSpillSlotUse(SS, FoldedMI); 975 if (!VRM.hasPhys(UnfoldVR)) 976 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 977 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 978 MII = MBB.insert(MII, FoldedMI); 979 InvalidateKills(MI, RegKills, KillOps); 980 VRM.RemoveMachineInstrFromMaps(&MI); 981 MBB.erase(&MI); 982 MF.DeleteMachineInstr(NewMI); 983 return true; 984 } 985 MF.DeleteMachineInstr(NewMI); 986 } 987 } 988 return false; 989} 990 991/// CommuteToFoldReload - 992/// Look for 993/// r1 = load fi#1 994/// r1 = op r1, r2<kill> 995/// store r1, fi#1 996/// 997/// If op is commutable and r2 is killed, then we can xform these to 998/// r2 = op r2, fi#1 999/// store r2, fi#1 1000bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB, 1001 MachineBasicBlock::iterator &MII, 1002 unsigned VirtReg, unsigned SrcReg, int SS, 1003 BitVector &RegKills, 1004 std::vector<MachineOperand*> &KillOps, 1005 const TargetRegisterInfo *TRI, 1006 VirtRegMap &VRM) { 1007 if (MII == MBB.begin() || !MII->killsRegister(SrcReg)) 1008 return false; 1009 1010 MachineFunction &MF = *MBB.getParent(); 1011 MachineInstr &MI = *MII; 1012 MachineBasicBlock::iterator DefMII = prior(MII); 1013 MachineInstr *DefMI = DefMII; 1014 const TargetInstrDesc &TID = DefMI->getDesc(); 1015 unsigned NewDstIdx; 1016 if (DefMII != MBB.begin() && 1017 TID.isCommutable() && 1018 TII->CommuteChangesDestination(DefMI, NewDstIdx)) { 1019 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 1020 unsigned NewReg = NewDstMO.getReg(); 1021 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg)) 1022 return false; 1023 MachineInstr *ReloadMI = prior(DefMII); 1024 int FrameIdx; 1025 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx); 1026 if (DestReg != SrcReg || FrameIdx != SS) 1027 return false; 1028 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false); 1029 if (UseIdx == -1) 1030 return false; 1031 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO); 1032 if (DefIdx == -1) 1033 return false; 1034 assert(DefMI->getOperand(DefIdx).isRegister() && 1035 DefMI->getOperand(DefIdx).getReg() == SrcReg); 1036 1037 // Now commute def instruction. 1038 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true); 1039 if (!CommutedMI) 1040 return false; 1041 SmallVector<unsigned, 2> Ops; 1042 Ops.push_back(NewDstIdx); 1043 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS); 1044 // Not needed since foldMemoryOperand returns new MI. 1045 MF.DeleteMachineInstr(CommutedMI); 1046 if (!FoldedMI) 1047 return false; 1048 1049 VRM.addSpillSlotUse(SS, FoldedMI); 1050 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 1051 // Insert new def MI and spill MI. 1052 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); 1053 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC); 1054 MII = prior(MII); 1055 MachineInstr *StoreMI = MII; 1056 VRM.addSpillSlotUse(SS, StoreMI); 1057 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1058 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack. 1059 1060 // Delete all 3 old instructions. 1061 InvalidateKills(*ReloadMI, RegKills, KillOps); 1062 VRM.RemoveMachineInstrFromMaps(ReloadMI); 1063 MBB.erase(ReloadMI); 1064 InvalidateKills(*DefMI, RegKills, KillOps); 1065 VRM.RemoveMachineInstrFromMaps(DefMI); 1066 MBB.erase(DefMI); 1067 InvalidateKills(MI, RegKills, KillOps); 1068 VRM.RemoveMachineInstrFromMaps(&MI); 1069 MBB.erase(&MI); 1070 1071 ++NumCommutes; 1072 return true; 1073 } 1074 1075 return false; 1076} 1077 1078/// findSuperReg - Find the SubReg's super-register of given register class 1079/// where its SubIdx sub-register is SubReg. 1080static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 1081 unsigned SubIdx, const TargetRegisterInfo *TRI) { 1082 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1083 I != E; ++I) { 1084 unsigned Reg = *I; 1085 if (TRI->getSubReg(Reg, SubIdx) == SubReg) 1086 return Reg; 1087 } 1088 return 0; 1089} 1090 1091/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 1092/// the last store to the same slot is now dead. If so, remove the last store. 1093void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 1094 MachineBasicBlock::iterator &MII, 1095 int Idx, unsigned PhysReg, int StackSlot, 1096 const TargetRegisterClass *RC, 1097 bool isAvailable, MachineInstr *&LastStore, 1098 AvailableSpills &Spills, 1099 SmallSet<MachineInstr*, 4> &ReMatDefs, 1100 BitVector &RegKills, 1101 std::vector<MachineOperand*> &KillOps, 1102 VirtRegMap &VRM) { 1103 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); 1104 MachineInstr *StoreMI = next(MII); 1105 VRM.addSpillSlotUse(StackSlot, StoreMI); 1106 DOUT << "Store:\t" << *StoreMI; 1107 1108 // If there is a dead store to this stack slot, nuke it now. 1109 if (LastStore) { 1110 DOUT << "Removed dead store:\t" << *LastStore; 1111 ++NumDSE; 1112 SmallVector<unsigned, 2> KillRegs; 1113 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 1114 MachineBasicBlock::iterator PrevMII = LastStore; 1115 bool CheckDef = PrevMII != MBB.begin(); 1116 if (CheckDef) 1117 --PrevMII; 1118 VRM.RemoveMachineInstrFromMaps(LastStore); 1119 MBB.erase(LastStore); 1120 if (CheckDef) { 1121 // Look at defs of killed registers on the store. Mark the defs 1122 // as dead since the store has been deleted and they aren't 1123 // being reused. 1124 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 1125 bool HasOtherDef = false; 1126 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 1127 MachineInstr *DeadDef = PrevMII; 1128 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 1129 // FIXME: This assumes a remat def does not have side 1130 // effects. 1131 VRM.RemoveMachineInstrFromMaps(DeadDef); 1132 MBB.erase(DeadDef); 1133 ++NumDRM; 1134 } 1135 } 1136 } 1137 } 1138 } 1139 1140 LastStore = next(MII); 1141 1142 // If the stack slot value was previously available in some other 1143 // register, change it now. Otherwise, make the register available, 1144 // in PhysReg. 1145 Spills.ModifyStackSlotOrReMat(StackSlot); 1146 Spills.ClobberPhysReg(PhysReg); 1147 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); 1148 ++NumStores; 1149} 1150 1151/// TransferDeadness - A identity copy definition is dead and it's being 1152/// removed. Find the last def or use and mark it as dead / kill. 1153void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 1154 unsigned Reg, BitVector &RegKills, 1155 std::vector<MachineOperand*> &KillOps) { 1156 int LastUDDist = -1; 1157 MachineInstr *LastUDMI = NULL; 1158 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg), 1159 RE = RegInfo->reg_end(); RI != RE; ++RI) { 1160 MachineInstr *UDMI = &*RI; 1161 if (UDMI->getParent() != MBB) 1162 continue; 1163 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI); 1164 if (DI == DistanceMap.end() || DI->second > CurDist) 1165 continue; 1166 if ((int)DI->second < LastUDDist) 1167 continue; 1168 LastUDDist = DI->second; 1169 LastUDMI = UDMI; 1170 } 1171 1172 if (LastUDMI) { 1173 const TargetInstrDesc &TID = LastUDMI->getDesc(); 1174 MachineOperand *LastUD = NULL; 1175 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { 1176 MachineOperand &MO = LastUDMI->getOperand(i); 1177 if (!MO.isRegister() || MO.getReg() != Reg) 1178 continue; 1179 if (!LastUD || (LastUD->isUse() && MO.isDef())) 1180 LastUD = &MO; 1181 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) 1182 return; 1183 } 1184 if (LastUD->isDef()) 1185 LastUD->setIsDead(); 1186 else { 1187 LastUD->setIsKill(); 1188 RegKills.set(Reg); 1189 KillOps[Reg] = LastUD; 1190 } 1191 } 1192} 1193 1194/// rewriteMBB - Keep track of which spills are available even after the 1195/// register allocator is done with them. If possible, avid reloading vregs. 1196void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { 1197 DOUT << MBB.getBasicBlock()->getName() << ":\n"; 1198 1199 MachineFunction &MF = *MBB.getParent(); 1200 1201 // Spills - Keep track of which spilled values are available in physregs so 1202 // that we can choose to reuse the physregs instead of emitting reloads. 1203 AvailableSpills Spills(TRI, TII); 1204 1205 // MaybeDeadStores - When we need to write a value back into a stack slot, 1206 // keep track of the inserted store. If the stack slot value is never read 1207 // (because the value was used from some available register, for example), and 1208 // subsequently stored to, the original store is dead. This map keeps track 1209 // of inserted stores that are not used. If we see a subsequent store to the 1210 // same stack slot, the original store is deleted. 1211 std::vector<MachineInstr*> MaybeDeadStores; 1212 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 1213 1214 // ReMatDefs - These are rematerializable def MIs which are not deleted. 1215 SmallSet<MachineInstr*, 4> ReMatDefs; 1216 1217 // Keep track of kill information. 1218 BitVector RegKills(TRI->getNumRegs()); 1219 std::vector<MachineOperand*> KillOps; 1220 KillOps.resize(TRI->getNumRegs(), NULL); 1221 1222 unsigned Dist = 0; 1223 DistanceMap.clear(); 1224 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 1225 MII != E; ) { 1226 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 1227 1228 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 1229 bool Erased = false; 1230 bool BackTracked = false; 1231 if (PrepForUnfoldOpti(MBB, MII, 1232 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 1233 NextMII = next(MII); 1234 1235 MachineInstr &MI = *MII; 1236 const TargetInstrDesc &TID = MI.getDesc(); 1237 1238 if (VRM.hasEmergencySpills(&MI)) { 1239 // Spill physical register(s) in the rare case the allocator has run out 1240 // of registers to allocate. 1241 SmallSet<int, 4> UsedSS; 1242 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI); 1243 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { 1244 unsigned PhysReg = EmSpills[i]; 1245 const TargetRegisterClass *RC = 1246 TRI->getPhysicalRegisterRegClass(PhysReg); 1247 assert(RC && "Unable to determine register class!"); 1248 int SS = VRM.getEmergencySpillSlot(RC); 1249 if (UsedSS.count(SS)) 1250 assert(0 && "Need to spill more than one physical registers!"); 1251 UsedSS.insert(SS); 1252 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); 1253 MachineInstr *StoreMI = prior(MII); 1254 VRM.addSpillSlotUse(SS, StoreMI); 1255 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); 1256 MachineInstr *LoadMI = next(MII); 1257 VRM.addSpillSlotUse(SS, LoadMI); 1258 ++NumPSpills; 1259 } 1260 NextMII = next(MII); 1261 } 1262 1263 // Insert restores here if asked to. 1264 if (VRM.isRestorePt(&MI)) { 1265 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 1266 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 1267 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. 1268 if (!VRM.getPreSplitReg(VirtReg)) 1269 continue; // Split interval spilled again. 1270 unsigned Phys = VRM.getPhys(VirtReg); 1271 RegInfo->setPhysRegUsed(Phys); 1272 if (VRM.isReMaterialized(VirtReg)) { 1273 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); 1274 } else { 1275 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1276 int SS = VRM.getStackSlot(VirtReg); 1277 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); 1278 MachineInstr *LoadMI = prior(MII); 1279 VRM.addSpillSlotUse(SS, LoadMI); 1280 ++NumLoads; 1281 } 1282 // This invalidates Phys. 1283 Spills.ClobberPhysReg(Phys); 1284 UpdateKills(*prior(MII), RegKills, KillOps); 1285 DOUT << '\t' << *prior(MII); 1286 } 1287 } 1288 1289 // Insert spills here if asked to. 1290 if (VRM.isSpillPt(&MI)) { 1291 std::vector<std::pair<unsigned,bool> > &SpillRegs = 1292 VRM.getSpillPtSpills(&MI); 1293 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 1294 unsigned VirtReg = SpillRegs[i].first; 1295 bool isKill = SpillRegs[i].second; 1296 if (!VRM.getPreSplitReg(VirtReg)) 1297 continue; // Split interval spilled again. 1298 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1299 unsigned Phys = VRM.getPhys(VirtReg); 1300 int StackSlot = VRM.getStackSlot(VirtReg); 1301 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); 1302 MachineInstr *StoreMI = next(MII); 1303 VRM.addSpillSlotUse(StackSlot, StoreMI); 1304 DOUT << "Store:\t" << *StoreMI; 1305 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1306 } 1307 NextMII = next(MII); 1308 } 1309 1310 /// ReusedOperands - Keep track of operand reuse in case we need to undo 1311 /// reuse. 1312 ReuseInfo ReusedOperands(MI, TRI); 1313 SmallVector<unsigned, 4> VirtUseOps; 1314 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1315 MachineOperand &MO = MI.getOperand(i); 1316 if (!MO.isRegister() || MO.getReg() == 0) 1317 continue; // Ignore non-register operands. 1318 1319 unsigned VirtReg = MO.getReg(); 1320 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { 1321 // Ignore physregs for spilling, but remember that it is used by this 1322 // function. 1323 RegInfo->setPhysRegUsed(VirtReg); 1324 continue; 1325 } 1326 1327 // We want to process implicit virtual register uses first. 1328 if (MO.isImplicit()) 1329 // If the virtual register is implicitly defined, emit a implicit_def 1330 // before so scavenger knows it's "defined". 1331 VirtUseOps.insert(VirtUseOps.begin(), i); 1332 else 1333 VirtUseOps.push_back(i); 1334 } 1335 1336 // Process all of the spilled uses and all non spilled reg references. 1337 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { 1338 unsigned i = VirtUseOps[j]; 1339 MachineOperand &MO = MI.getOperand(i); 1340 unsigned VirtReg = MO.getReg(); 1341 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 1342 "Not a virtual register?"); 1343 1344 unsigned SubIdx = MO.getSubReg(); 1345 if (VRM.isAssignedReg(VirtReg)) { 1346 // This virtual register was assigned a physreg! 1347 unsigned Phys = VRM.getPhys(VirtReg); 1348 RegInfo->setPhysRegUsed(Phys); 1349 if (MO.isDef()) 1350 ReusedOperands.markClobbered(Phys); 1351 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 1352 MI.getOperand(i).setReg(RReg); 1353 if (VRM.isImplicitlyDefined(VirtReg)) 1354 BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); 1355 continue; 1356 } 1357 1358 // This virtual register is now known to be a spilled value. 1359 if (!MO.isUse()) 1360 continue; // Handle defs in the loop below (handle use&def here though) 1361 1362 bool DoReMat = VRM.isReMaterialized(VirtReg); 1363 int SSorRMId = DoReMat 1364 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1365 int ReuseSlot = SSorRMId; 1366 1367 // Check to see if this stack slot is available. 1368 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1369 1370 // If this is a sub-register use, make sure the reuse register is in the 1371 // right register class. For example, for x86 not all of the 32-bit 1372 // registers have accessible sub-registers. 1373 // Similarly so for EXTRACT_SUBREG. Consider this: 1374 // EDI = op 1375 // MOV32_mr fi#1, EDI 1376 // ... 1377 // = EXTRACT_SUBREG fi#1 1378 // fi#1 is available in EDI, but it cannot be reused because it's not in 1379 // the right register file. 1380 if (PhysReg && 1381 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1382 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1383 if (!RC->contains(PhysReg)) 1384 PhysReg = 0; 1385 } 1386 1387 if (PhysReg) { 1388 // This spilled operand might be part of a two-address operand. If this 1389 // is the case, then changing it will necessarily require changing the 1390 // def part of the instruction as well. However, in some cases, we 1391 // aren't allowed to modify the reused register. If none of these cases 1392 // apply, reuse it. 1393 bool CanReuse = true; 1394 int ti = TID.getOperandConstraint(i, TOI::TIED_TO); 1395 if (ti != -1 && 1396 MI.getOperand(ti).isRegister() && 1397 MI.getOperand(ti).getReg() == VirtReg) { 1398 // Okay, we have a two address operand. We can reuse this physreg as 1399 // long as we are allowed to clobber the value and there isn't an 1400 // earlier def that has already clobbered the physreg. 1401 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1402 !ReusedOperands.isClobbered(PhysReg); 1403 } 1404 1405 if (CanReuse) { 1406 // If this stack slot value is already available, reuse it! 1407 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1408 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1409 else 1410 DOUT << "Reusing SS#" << ReuseSlot; 1411 DOUT << " from physreg " 1412 << TRI->getName(PhysReg) << " for vreg" 1413 << VirtReg <<" instead of reloading into physreg " 1414 << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1415 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1416 MI.getOperand(i).setReg(RReg); 1417 1418 // The only technical detail we have is that we don't know that 1419 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1420 // later in the instruction. In particular, consider 'op V1, V2'. 1421 // If V1 is available in physreg R0, we would choose to reuse it 1422 // here, instead of reloading it into the register the allocator 1423 // indicated (say R1). However, V2 might have to be reloaded 1424 // later, and it might indicate that it needs to live in R0. When 1425 // this occurs, we need to have information available that 1426 // indicates it is safe to use R1 for the reload instead of R0. 1427 // 1428 // To further complicate matters, we might conflict with an alias, 1429 // or R0 and R1 might not be compatible with each other. In this 1430 // case, we actually insert a reload for V1 in R1, ensuring that 1431 // we can get at R0 or its alias. 1432 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1433 VRM.getPhys(VirtReg), VirtReg); 1434 if (ti != -1) 1435 // Only mark it clobbered if this is a use&def operand. 1436 ReusedOperands.markClobbered(PhysReg); 1437 ++NumReused; 1438 1439 if (MI.getOperand(i).isKill() && 1440 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1441 // This was the last use and the spilled value is still available 1442 // for reuse. That means the spill was unnecessary! 1443 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; 1444 if (DeadStore) { 1445 DOUT << "Removed dead store:\t" << *DeadStore; 1446 InvalidateKills(*DeadStore, RegKills, KillOps); 1447 VRM.RemoveMachineInstrFromMaps(DeadStore); 1448 MBB.erase(DeadStore); 1449 MaybeDeadStores[ReuseSlot] = NULL; 1450 ++NumDSE; 1451 } 1452 } 1453 continue; 1454 } // CanReuse 1455 1456 // Otherwise we have a situation where we have a two-address instruction 1457 // whose mod/ref operand needs to be reloaded. This reload is already 1458 // available in some register "PhysReg", but if we used PhysReg as the 1459 // operand to our 2-addr instruction, the instruction would modify 1460 // PhysReg. This isn't cool if something later uses PhysReg and expects 1461 // to get its initial value. 1462 // 1463 // To avoid this problem, and to avoid doing a load right after a store, 1464 // we emit a copy from PhysReg into the designated register for this 1465 // operand. 1466 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1467 assert(DesignatedReg && "Must map virtreg to physreg!"); 1468 1469 // Note that, if we reused a register for a previous operand, the 1470 // register we want to reload into might not actually be 1471 // available. If this occurs, use the register indicated by the 1472 // reuser. 1473 if (ReusedOperands.hasReuses()) 1474 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1475 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1476 1477 // If the mapped designated register is actually the physreg we have 1478 // incoming, we don't need to inserted a dead copy. 1479 if (DesignatedReg == PhysReg) { 1480 // If this stack slot value is already available, reuse it! 1481 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1482 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1483 else 1484 DOUT << "Reusing SS#" << ReuseSlot; 1485 DOUT << " from physreg " << TRI->getName(PhysReg) 1486 << " for vreg" << VirtReg 1487 << " instead of reloading into same physreg.\n"; 1488 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1489 MI.getOperand(i).setReg(RReg); 1490 ReusedOperands.markClobbered(RReg); 1491 ++NumReused; 1492 continue; 1493 } 1494 1495 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1496 RegInfo->setPhysRegUsed(DesignatedReg); 1497 ReusedOperands.markClobbered(DesignatedReg); 1498 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1499 1500 MachineInstr *CopyMI = prior(MII); 1501 UpdateKills(*CopyMI, RegKills, KillOps); 1502 1503 // This invalidates DesignatedReg. 1504 Spills.ClobberPhysReg(DesignatedReg); 1505 1506 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); 1507 unsigned RReg = 1508 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1509 MI.getOperand(i).setReg(RReg); 1510 DOUT << '\t' << *prior(MII); 1511 ++NumReused; 1512 continue; 1513 } // if (PhysReg) 1514 1515 // Otherwise, reload it and remember that we have it. 1516 PhysReg = VRM.getPhys(VirtReg); 1517 assert(PhysReg && "Must map virtreg to physreg!"); 1518 1519 // Note that, if we reused a register for a previous operand, the 1520 // register we want to reload into might not actually be 1521 // available. If this occurs, use the register indicated by the 1522 // reuser. 1523 if (ReusedOperands.hasReuses()) 1524 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1525 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1526 1527 RegInfo->setPhysRegUsed(PhysReg); 1528 ReusedOperands.markClobbered(PhysReg); 1529 if (DoReMat) { 1530 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM); 1531 } else { 1532 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1533 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1534 MachineInstr *LoadMI = prior(MII); 1535 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1536 ++NumLoads; 1537 } 1538 // This invalidates PhysReg. 1539 Spills.ClobberPhysReg(PhysReg); 1540 1541 // Any stores to this stack slot are not dead anymore. 1542 if (!DoReMat) 1543 MaybeDeadStores[SSorRMId] = NULL; 1544 Spills.addAvailable(SSorRMId, &MI, PhysReg); 1545 // Assumes this is the last use. IsKill will be unset if reg is reused 1546 // unless it's a two-address operand. 1547 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 1548 MI.getOperand(i).setIsKill(); 1549 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1550 MI.getOperand(i).setReg(RReg); 1551 UpdateKills(*prior(MII), RegKills, KillOps); 1552 DOUT << '\t' << *prior(MII); 1553 } 1554 1555 DOUT << '\t' << MI; 1556 1557 1558 // If we have folded references to memory operands, make sure we clear all 1559 // physical registers that may contain the value of the spilled virtual 1560 // register 1561 SmallSet<int, 2> FoldedSS; 1562 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 1563 unsigned VirtReg = I->second.first; 1564 VirtRegMap::ModRef MR = I->second.second; 1565 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1566 1567 // MI2VirtMap be can updated which invalidate the iterator. 1568 // Increment the iterator first. 1569 ++I; 1570 int SS = VRM.getStackSlot(VirtReg); 1571 if (SS == VirtRegMap::NO_STACK_SLOT) 1572 continue; 1573 FoldedSS.insert(SS); 1574 DOUT << " - StackSlot: " << SS << "\n"; 1575 1576 // If this folded instruction is just a use, check to see if it's a 1577 // straight load from the virt reg slot. 1578 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1579 int FrameIdx; 1580 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1581 if (DestReg && FrameIdx == SS) { 1582 // If this spill slot is available, turn it into a copy (or nothing) 1583 // instead of leaving it as a load! 1584 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1585 DOUT << "Promoted Load To Copy: " << MI; 1586 if (DestReg != InReg) { 1587 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1588 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1589 // Revisit the copy so we make sure to notice the effects of the 1590 // operation on the destreg (either needing to RA it if it's 1591 // virtual or needing to clobber any values if it's physical). 1592 NextMII = &MI; 1593 --NextMII; // backtrack to the copy. 1594 BackTracked = true; 1595 } else { 1596 DOUT << "Removing now-noop copy: " << MI; 1597 // Unset last kill since it's being reused. 1598 InvalidateKill(InReg, RegKills, KillOps); 1599 } 1600 1601 InvalidateKills(MI, RegKills, KillOps); 1602 VRM.RemoveMachineInstrFromMaps(&MI); 1603 MBB.erase(&MI); 1604 Erased = true; 1605 goto ProcessNextInst; 1606 } 1607 } else { 1608 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1609 SmallVector<MachineInstr*, 4> NewMIs; 1610 if (PhysReg && 1611 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1612 MBB.insert(MII, NewMIs[0]); 1613 InvalidateKills(MI, RegKills, KillOps); 1614 VRM.RemoveMachineInstrFromMaps(&MI); 1615 MBB.erase(&MI); 1616 Erased = true; 1617 --NextMII; // backtrack to the unfolded instruction. 1618 BackTracked = true; 1619 goto ProcessNextInst; 1620 } 1621 } 1622 } 1623 1624 // If this reference is not a use, any previous store is now dead. 1625 // Otherwise, the store to this stack slot is not dead anymore. 1626 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1627 if (DeadStore) { 1628 bool isDead = !(MR & VirtRegMap::isRef); 1629 MachineInstr *NewStore = NULL; 1630 if (MR & VirtRegMap::isModRef) { 1631 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1632 SmallVector<MachineInstr*, 4> NewMIs; 1633 // We can reuse this physreg as long as we are allowed to clobber 1634 // the value and there isn't an earlier def that has already clobbered 1635 // the physreg. 1636 if (PhysReg && 1637 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable! 1638 MachineOperand *KillOpnd = 1639 DeadStore->findRegisterUseOperand(PhysReg, true); 1640 // Note, if the store is storing a sub-register, it's possible the 1641 // super-register is needed below. 1642 if (KillOpnd && !KillOpnd->getSubReg() && 1643 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ 1644 MBB.insert(MII, NewMIs[0]); 1645 NewStore = NewMIs[1]; 1646 MBB.insert(MII, NewStore); 1647 VRM.addSpillSlotUse(SS, NewStore); 1648 InvalidateKills(MI, RegKills, KillOps); 1649 VRM.RemoveMachineInstrFromMaps(&MI); 1650 MBB.erase(&MI); 1651 Erased = true; 1652 --NextMII; 1653 --NextMII; // backtrack to the unfolded instruction. 1654 BackTracked = true; 1655 isDead = true; 1656 } 1657 } 1658 } 1659 1660 if (isDead) { // Previous store is dead. 1661 // If we get here, the store is dead, nuke it now. 1662 DOUT << "Removed dead store:\t" << *DeadStore; 1663 InvalidateKills(*DeadStore, RegKills, KillOps); 1664 VRM.RemoveMachineInstrFromMaps(DeadStore); 1665 MBB.erase(DeadStore); 1666 if (!NewStore) 1667 ++NumDSE; 1668 } 1669 1670 MaybeDeadStores[SS] = NULL; 1671 if (NewStore) { 1672 // Treat this store as a spill merged into a copy. That makes the 1673 // stack slot value available. 1674 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1675 goto ProcessNextInst; 1676 } 1677 } 1678 1679 // If the spill slot value is available, and this is a new definition of 1680 // the value, the value is not available anymore. 1681 if (MR & VirtRegMap::isMod) { 1682 // Notice that the value in this stack slot has been modified. 1683 Spills.ModifyStackSlotOrReMat(SS); 1684 1685 // If this is *just* a mod of the value, check to see if this is just a 1686 // store to the spill slot (i.e. the spill got merged into the copy). If 1687 // so, realize that the vreg is available now, and add the store to the 1688 // MaybeDeadStore info. 1689 int StackSlot; 1690 if (!(MR & VirtRegMap::isRef)) { 1691 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1692 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1693 "Src hasn't been allocated yet?"); 1694 1695 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot, 1696 RegKills, KillOps, TRI, VRM)) { 1697 NextMII = next(MII); 1698 BackTracked = true; 1699 goto ProcessNextInst; 1700 } 1701 1702 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1703 // this as a potentially dead store in case there is a subsequent 1704 // store into the stack slot without a read from it. 1705 MaybeDeadStores[StackSlot] = &MI; 1706 1707 // If the stack slot value was previously available in some other 1708 // register, change it now. Otherwise, make the register 1709 // available in PhysReg. 1710 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/); 1711 } 1712 } 1713 } 1714 } 1715 1716 // Process all of the spilled defs. 1717 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1718 MachineOperand &MO = MI.getOperand(i); 1719 if (!(MO.isRegister() && MO.getReg() && MO.isDef())) 1720 continue; 1721 1722 unsigned VirtReg = MO.getReg(); 1723 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { 1724 // Check to see if this is a noop copy. If so, eliminate the 1725 // instruction before considering the dest reg to be changed. 1726 unsigned Src, Dst; 1727 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1728 ++NumDCE; 1729 DOUT << "Removing now-noop copy: " << MI; 1730 SmallVector<unsigned, 2> KillRegs; 1731 InvalidateKills(MI, RegKills, KillOps, &KillRegs); 1732 if (MO.isDead() && !KillRegs.empty()) { 1733 // Source register or an implicit super-register use is killed. 1734 assert(KillRegs[0] == Dst || TRI->isSubRegister(KillRegs[0], Dst)); 1735 // Last def is now dead. 1736 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps); 1737 } 1738 VRM.RemoveMachineInstrFromMaps(&MI); 1739 MBB.erase(&MI); 1740 Erased = true; 1741 Spills.disallowClobberPhysReg(VirtReg); 1742 goto ProcessNextInst; 1743 } 1744 1745 // If it's not a no-op copy, it clobbers the value in the destreg. 1746 Spills.ClobberPhysReg(VirtReg); 1747 ReusedOperands.markClobbered(VirtReg); 1748 1749 // Check to see if this instruction is a load from a stack slot into 1750 // a register. If so, this provides the stack slot value in the reg. 1751 int FrameIdx; 1752 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1753 assert(DestReg == VirtReg && "Unknown load situation!"); 1754 1755 // If it is a folded reference, then it's not safe to clobber. 1756 bool Folded = FoldedSS.count(FrameIdx); 1757 // Otherwise, if it wasn't available, remember that it is now! 1758 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); 1759 goto ProcessNextInst; 1760 } 1761 1762 continue; 1763 } 1764 1765 unsigned SubIdx = MO.getSubReg(); 1766 bool DoReMat = VRM.isReMaterialized(VirtReg); 1767 if (DoReMat) 1768 ReMatDefs.insert(&MI); 1769 1770 // The only vregs left are stack slot definitions. 1771 int StackSlot = VRM.getStackSlot(VirtReg); 1772 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1773 1774 // If this def is part of a two-address operand, make sure to execute 1775 // the store from the correct physical register. 1776 unsigned PhysReg; 1777 int TiedOp = MI.getDesc().findTiedToSrcOperand(i); 1778 if (TiedOp != -1) { 1779 PhysReg = MI.getOperand(TiedOp).getReg(); 1780 if (SubIdx) { 1781 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); 1782 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1783 "Can't find corresponding super-register!"); 1784 PhysReg = SuperReg; 1785 } 1786 } else { 1787 PhysReg = VRM.getPhys(VirtReg); 1788 if (ReusedOperands.isClobbered(PhysReg)) { 1789 // Another def has taken the assigned physreg. It must have been a 1790 // use&def which got it due to reuse. Undo the reuse! 1791 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1792 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1793 } 1794 } 1795 1796 assert(PhysReg && "VR not assigned a physical register?"); 1797 RegInfo->setPhysRegUsed(PhysReg); 1798 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1799 ReusedOperands.markClobbered(RReg); 1800 MI.getOperand(i).setReg(RReg); 1801 1802 if (!MO.isDead()) { 1803 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1804 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, 1805 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 1806 NextMII = next(MII); 1807 1808 // Check to see if this is a noop copy. If so, eliminate the 1809 // instruction before considering the dest reg to be changed. 1810 { 1811 unsigned Src, Dst; 1812 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1813 ++NumDCE; 1814 DOUT << "Removing now-noop copy: " << MI; 1815 InvalidateKills(MI, RegKills, KillOps); 1816 VRM.RemoveMachineInstrFromMaps(&MI); 1817 MBB.erase(&MI); 1818 Erased = true; 1819 UpdateKills(*LastStore, RegKills, KillOps); 1820 goto ProcessNextInst; 1821 } 1822 } 1823 } 1824 } 1825 ProcessNextInst: 1826 DistanceMap.insert(std::make_pair(&MI, Dist++)); 1827 if (!Erased && !BackTracked) { 1828 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II) 1829 UpdateKills(*II, RegKills, KillOps); 1830 } 1831 MII = NextMII; 1832 } 1833} 1834 1835llvm::Spiller* llvm::createSpiller() { 1836 switch (SpillerOpt) { 1837 default: assert(0 && "Unreachable!"); 1838 case local: 1839 return new LocalSpiller(); 1840 case simple: 1841 return new SimpleSpiller(); 1842 } 1843} 1844