VirtRegMap.cpp revision ecb9ad5742b5dba1c834e0c79eff2214454e3193
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetInstrInfo.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/ADT/BitVector.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/ADT/STLExtras.h" 33#include "llvm/ADT/SmallSet.h" 34#include <algorithm> 35using namespace llvm; 36 37STATISTIC(NumSpills, "Number of register spills"); 38STATISTIC(NumPSpills,"Number of physical register spills"); 39STATISTIC(NumReMats, "Number of re-materialization"); 40STATISTIC(NumDRM , "Number of re-materializable defs elided"); 41STATISTIC(NumStores, "Number of stores added"); 42STATISTIC(NumLoads , "Number of loads added"); 43STATISTIC(NumReused, "Number of values reused"); 44STATISTIC(NumDSE , "Number of dead stores elided"); 45STATISTIC(NumDCE , "Number of copies elided"); 46STATISTIC(NumDSS , "Number of dead spill slots removed"); 47 48namespace { 49 enum SpillerName { simple, local }; 50 51 static cl::opt<SpillerName> 52 SpillerOpt("spiller", 53 cl::desc("Spiller to use: (default: local)"), 54 cl::Prefix, 55 cl::values(clEnumVal(simple, " simple spiller"), 56 clEnumVal(local, " local spiller"), 57 clEnumValEnd), 58 cl::init(local)); 59} 60 61//===----------------------------------------------------------------------===// 62// VirtRegMap implementation 63//===----------------------------------------------------------------------===// 64 65VirtRegMap::VirtRegMap(MachineFunction &mf) 66 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 67 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 68 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 69 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), 70 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { 71 SpillSlotToUsesMap.resize(8); 72 grow(); 73} 74 75void VirtRegMap::grow() { 76 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); 77 Virt2PhysMap.grow(LastVirtReg); 78 Virt2StackSlotMap.grow(LastVirtReg); 79 Virt2ReMatIdMap.grow(LastVirtReg); 80 Virt2SplitMap.grow(LastVirtReg); 81 Virt2SplitKillMap.grow(LastVirtReg); 82 ReMatMap.grow(LastVirtReg); 83} 84 85int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 86 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 87 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 88 "attempt to assign stack slot to already spilled register"); 89 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); 90 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 91 RC->getAlignment()); 92 if (LowSpillSlot == NO_STACK_SLOT) 93 LowSpillSlot = SS; 94 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 95 HighSpillSlot = SS; 96 unsigned Idx = SS-LowSpillSlot; 97 while (Idx >= SpillSlotToUsesMap.size()) 98 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); 99 Virt2StackSlotMap[virtReg] = SS; 100 ++NumSpills; 101 return SS; 102} 103 104void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 105 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 106 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 107 "attempt to assign stack slot to already spilled register"); 108 assert((SS >= 0 || 109 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && 110 "illegal fixed frame index"); 111 Virt2StackSlotMap[virtReg] = SS; 112} 113 114int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 115 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 116 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 117 "attempt to assign re-mat id to already spilled register"); 118 Virt2ReMatIdMap[virtReg] = ReMatId; 119 return ReMatId++; 120} 121 122void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 123 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 124 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 125 "attempt to assign re-mat id to already spilled register"); 126 Virt2ReMatIdMap[virtReg] = id; 127} 128 129int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { 130 std::map<const TargetRegisterClass*, int>::iterator I = 131 EmergencySpillSlots.find(RC); 132 if (I != EmergencySpillSlots.end()) 133 return I->second; 134 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 135 RC->getAlignment()); 136 if (LowSpillSlot == NO_STACK_SLOT) 137 LowSpillSlot = SS; 138 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 139 HighSpillSlot = SS; 140 I->second = SS; 141 return SS; 142} 143 144void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { 145 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { 146 assert(FI >= 0 && "Spill slot index should not be negative!"); 147 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); 148 } 149} 150 151void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 152 MachineInstr *NewMI, ModRef MRInfo) { 153 // Move previous memory references folded to new instruction. 154 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 155 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 156 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 157 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 158 MI2VirtMap.erase(I++); 159 } 160 161 // add new memory reference 162 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 163} 164 165void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 166 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 167 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 168} 169 170void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { 171 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 172 MachineOperand &MO = MI->getOperand(i); 173 if (!MO.isFrameIndex()) 174 continue; 175 int FI = MO.getIndex(); 176 if (MF.getFrameInfo()->isFixedObjectIndex(FI)) 177 continue; 178 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); 179 } 180 MI2VirtMap.erase(MI); 181 SpillPt2VirtMap.erase(MI); 182 RestorePt2VirtMap.erase(MI); 183 EmergencySpillMap.erase(MI); 184} 185 186void VirtRegMap::print(std::ostream &OS) const { 187 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); 188 189 OS << "********** REGISTER MAP **********\n"; 190 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 191 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { 192 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 193 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) 194 << "]\n"; 195 } 196 197 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 198 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) 199 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 200 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 201 OS << '\n'; 202} 203 204void VirtRegMap::dump() const { 205 print(cerr); 206} 207 208 209//===----------------------------------------------------------------------===// 210// Simple Spiller Implementation 211//===----------------------------------------------------------------------===// 212 213Spiller::~Spiller() {} 214 215namespace { 216 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 217 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 218 }; 219} 220 221bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 222 DOUT << "********** REWRITE MACHINE CODE **********\n"; 223 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 224 const TargetMachine &TM = MF.getTarget(); 225 const TargetInstrInfo &TII = *TM.getInstrInfo(); 226 227 228 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 229 // each vreg once (in the case where a spilled vreg is used by multiple 230 // operands). This is always smaller than the number of operands to the 231 // current machine instr, so it should be small. 232 std::vector<unsigned> LoadedRegs; 233 234 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 235 MBBI != E; ++MBBI) { 236 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 237 MachineBasicBlock &MBB = *MBBI; 238 for (MachineBasicBlock::iterator MII = MBB.begin(), 239 E = MBB.end(); MII != E; ++MII) { 240 MachineInstr &MI = *MII; 241 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 242 MachineOperand &MO = MI.getOperand(i); 243 if (MO.isRegister() && MO.getReg()) { 244 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 245 unsigned VirtReg = MO.getReg(); 246 unsigned PhysReg = VRM.getPhys(VirtReg); 247 if (!VRM.isAssignedReg(VirtReg)) { 248 int StackSlot = VRM.getStackSlot(VirtReg); 249 const TargetRegisterClass* RC = 250 MF.getRegInfo().getRegClass(VirtReg); 251 252 if (MO.isUse() && 253 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 254 == LoadedRegs.end()) { 255 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 256 MachineInstr *LoadMI = prior(MII); 257 VRM.addSpillSlotUse(StackSlot, LoadMI); 258 LoadedRegs.push_back(VirtReg); 259 ++NumLoads; 260 DOUT << '\t' << *LoadMI; 261 } 262 263 if (MO.isDef()) { 264 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, 265 StackSlot, RC); 266 MachineInstr *StoreMI = next(MII); 267 VRM.addSpillSlotUse(StackSlot, StoreMI); 268 ++NumStores; 269 } 270 } 271 MF.getRegInfo().setPhysRegUsed(PhysReg); 272 MI.getOperand(i).setReg(PhysReg); 273 } else { 274 MF.getRegInfo().setPhysRegUsed(MO.getReg()); 275 } 276 } 277 } 278 279 DOUT << '\t' << MI; 280 LoadedRegs.clear(); 281 } 282 } 283 return true; 284} 285 286//===----------------------------------------------------------------------===// 287// Local Spiller Implementation 288//===----------------------------------------------------------------------===// 289 290namespace { 291 class AvailableSpills; 292 293 /// LocalSpiller - This spiller does a simple pass over the machine basic 294 /// block to attempt to keep spills in registers as much as possible for 295 /// blocks that have low register pressure (the vreg may be spilled due to 296 /// register pressure in other blocks). 297 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 298 MachineRegisterInfo *RegInfo; 299 const TargetRegisterInfo *TRI; 300 const TargetInstrInfo *TII; 301 public: 302 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 303 RegInfo = &MF.getRegInfo(); 304 TRI = MF.getTarget().getRegisterInfo(); 305 TII = MF.getTarget().getInstrInfo(); 306 DOUT << "\n**** Local spiller rewriting function '" 307 << MF.getFunction()->getName() << "':\n"; 308 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" 309 " ****\n"; 310 DEBUG(MF.dump()); 311 312 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 313 MBB != E; ++MBB) 314 RewriteMBB(*MBB, VRM); 315 316 // Mark unused spill slots. 317 MachineFrameInfo *MFI = MF.getFrameInfo(); 318 int SS = VRM.getLowSpillSlot(); 319 if (SS != VirtRegMap::NO_STACK_SLOT) 320 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) 321 if (!VRM.isSpillSlotUsed(SS)) { 322 MFI->RemoveStackObject(SS); 323 ++NumDSS; 324 } 325 326 DOUT << "**** Post Machine Instrs ****\n"; 327 DEBUG(MF.dump()); 328 329 return true; 330 } 331 private: 332 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 333 MachineBasicBlock::iterator &MII, 334 std::vector<MachineInstr*> &MaybeDeadStores, 335 AvailableSpills &Spills, BitVector &RegKills, 336 std::vector<MachineOperand*> &KillOps, 337 VirtRegMap &VRM); 338 void SpillRegToStackSlot(MachineBasicBlock &MBB, 339 MachineBasicBlock::iterator &MII, 340 int Idx, unsigned PhysReg, int StackSlot, 341 const TargetRegisterClass *RC, 342 bool isAvailable, MachineInstr *&LastStore, 343 AvailableSpills &Spills, 344 SmallSet<MachineInstr*, 4> &ReMatDefs, 345 BitVector &RegKills, 346 std::vector<MachineOperand*> &KillOps, 347 VirtRegMap &VRM); 348 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM); 349 }; 350} 351 352/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 353/// top down, keep track of which spills slots or remat are available in each 354/// register. 355/// 356/// Note that not all physregs are created equal here. In particular, some 357/// physregs are reloads that we are allowed to clobber or ignore at any time. 358/// Other physregs are values that the register allocated program is using that 359/// we cannot CHANGE, but we can read if we like. We keep track of this on a 360/// per-stack-slot / remat id basis as the low bit in the value of the 361/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 362/// this bit and addAvailable sets it if. 363namespace { 364class VISIBILITY_HIDDEN AvailableSpills { 365 const TargetRegisterInfo *TRI; 366 const TargetInstrInfo *TII; 367 368 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 369 // or remat'ed virtual register values that are still available, due to being 370 // loaded or stored to, but not invalidated yet. 371 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 372 373 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 374 // indicating which stack slot values are currently held by a physreg. This 375 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 376 // physreg is modified. 377 std::multimap<unsigned, int> PhysRegsAvailable; 378 379 void disallowClobberPhysRegOnly(unsigned PhysReg); 380 381 void ClobberPhysRegOnly(unsigned PhysReg); 382public: 383 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) 384 : TRI(tri), TII(tii) { 385 } 386 387 const TargetRegisterInfo *getRegInfo() const { return TRI; } 388 389 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 390 /// available in a physical register, return that PhysReg, otherwise 391 /// return 0. 392 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 393 std::map<int, unsigned>::const_iterator I = 394 SpillSlotsOrReMatsAvailable.find(Slot); 395 if (I != SpillSlotsOrReMatsAvailable.end()) { 396 return I->second >> 1; // Remove the CanClobber bit. 397 } 398 return 0; 399 } 400 401 /// addAvailable - Mark that the specified stack slot / remat is available in 402 /// the specified physreg. If CanClobber is true, the physreg can be modified 403 /// at any time without changing the semantics of the program. 404 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg, 405 bool CanClobber = true) { 406 // If this stack slot is thought to be available in some other physreg, 407 // remove its record. 408 ModifyStackSlotOrReMat(SlotOrReMat); 409 410 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 411 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 412 413 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 414 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 415 else 416 DOUT << "Remembering SS#" << SlotOrReMat; 417 DOUT << " in physreg " << TRI->getName(Reg) << "\n"; 418 } 419 420 /// canClobberPhysReg - Return true if the spiller is allowed to change the 421 /// value of the specified stackslot register if it desires. The specified 422 /// stack slot must be available in a physreg for this query to make sense. 423 bool canClobberPhysReg(int SlotOrReMat) const { 424 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 425 "Value not available!"); 426 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 427 } 428 429 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 430 /// stackslot register. The register is still available but is no longer 431 /// allowed to be modifed. 432 void disallowClobberPhysReg(unsigned PhysReg); 433 434 /// ClobberPhysReg - This is called when the specified physreg changes 435 /// value. We use this to invalidate any info about stuff that lives in 436 /// it and any of its aliases. 437 void ClobberPhysReg(unsigned PhysReg); 438 439 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 440 /// slot changes. This removes information about which register the previous 441 /// value for this slot lives in (as the previous value is dead now). 442 void ModifyStackSlotOrReMat(int SlotOrReMat); 443}; 444} 445 446/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 447/// stackslot register. The register is still available but is no longer 448/// allowed to be modifed. 449void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 450 std::multimap<unsigned, int>::iterator I = 451 PhysRegsAvailable.lower_bound(PhysReg); 452 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 453 int SlotOrReMat = I->second; 454 I++; 455 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 456 "Bidirectional map mismatch!"); 457 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 458 DOUT << "PhysReg " << TRI->getName(PhysReg) 459 << " copied, it is available for use but can no longer be modified\n"; 460 } 461} 462 463/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 464/// stackslot register and its aliases. The register and its aliases may 465/// still available but is no longer allowed to be modifed. 466void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 467 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 468 disallowClobberPhysRegOnly(*AS); 469 disallowClobberPhysRegOnly(PhysReg); 470} 471 472/// ClobberPhysRegOnly - This is called when the specified physreg changes 473/// value. We use this to invalidate any info about stuff we thing lives in it. 474void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 475 std::multimap<unsigned, int>::iterator I = 476 PhysRegsAvailable.lower_bound(PhysReg); 477 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 478 int SlotOrReMat = I->second; 479 PhysRegsAvailable.erase(I++); 480 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 481 "Bidirectional map mismatch!"); 482 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 483 DOUT << "PhysReg " << TRI->getName(PhysReg) 484 << " clobbered, invalidating "; 485 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 486 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 487 else 488 DOUT << "SS#" << SlotOrReMat << "\n"; 489 } 490} 491 492/// ClobberPhysReg - This is called when the specified physreg changes 493/// value. We use this to invalidate any info about stuff we thing lives in 494/// it and any of its aliases. 495void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 496 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 497 ClobberPhysRegOnly(*AS); 498 ClobberPhysRegOnly(PhysReg); 499} 500 501/// ModifyStackSlotOrReMat - This method is called when the value in a stack 502/// slot changes. This removes information about which register the previous 503/// value for this slot lives in (as the previous value is dead now). 504void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 505 std::map<int, unsigned>::iterator It = 506 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 507 if (It == SpillSlotsOrReMatsAvailable.end()) return; 508 unsigned Reg = It->second >> 1; 509 SpillSlotsOrReMatsAvailable.erase(It); 510 511 // This register may hold the value of multiple stack slots, only remove this 512 // stack slot from the set of values the register contains. 513 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 514 for (; ; ++I) { 515 assert(I != PhysRegsAvailable.end() && I->first == Reg && 516 "Map inverse broken!"); 517 if (I->second == SlotOrReMat) break; 518 } 519 PhysRegsAvailable.erase(I); 520} 521 522 523 524/// InvalidateKills - MI is going to be deleted. If any of its operands are 525/// marked kill, then invalidate the information. 526static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 527 std::vector<MachineOperand*> &KillOps, 528 SmallVector<unsigned, 2> *KillRegs = NULL) { 529 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 530 MachineOperand &MO = MI.getOperand(i); 531 if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) 532 continue; 533 unsigned Reg = MO.getReg(); 534 if (KillRegs) 535 KillRegs->push_back(Reg); 536 if (KillOps[Reg] == &MO) { 537 RegKills.reset(Reg); 538 KillOps[Reg] = NULL; 539 } 540 } 541} 542 543/// InvalidateKill - A MI that defines the specified register is being deleted, 544/// invalidate the register kill information. 545static void InvalidateKill(unsigned Reg, BitVector &RegKills, 546 std::vector<MachineOperand*> &KillOps) { 547 if (RegKills[Reg]) { 548 KillOps[Reg]->setIsKill(false); 549 KillOps[Reg] = NULL; 550 RegKills.reset(Reg); 551 } 552} 553 554/// InvalidateRegDef - If the def operand of the specified def MI is now dead 555/// (since it's spill instruction is removed), mark it isDead. Also checks if 556/// the def MI has other definition operands that are not dead. Returns it by 557/// reference. 558static bool InvalidateRegDef(MachineBasicBlock::iterator I, 559 MachineInstr &NewDef, unsigned Reg, 560 bool &HasLiveDef) { 561 // Due to remat, it's possible this reg isn't being reused. That is, 562 // the def of this reg (by prev MI) is now dead. 563 MachineInstr *DefMI = I; 564 MachineOperand *DefOp = NULL; 565 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 566 MachineOperand &MO = DefMI->getOperand(i); 567 if (MO.isRegister() && MO.isDef()) { 568 if (MO.getReg() == Reg) 569 DefOp = &MO; 570 else if (!MO.isDead()) 571 HasLiveDef = true; 572 } 573 } 574 if (!DefOp) 575 return false; 576 577 bool FoundUse = false, Done = false; 578 MachineBasicBlock::iterator E = NewDef; 579 ++I; ++E; 580 for (; !Done && I != E; ++I) { 581 MachineInstr *NMI = I; 582 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 583 MachineOperand &MO = NMI->getOperand(j); 584 if (!MO.isRegister() || MO.getReg() != Reg) 585 continue; 586 if (MO.isUse()) 587 FoundUse = true; 588 Done = true; // Stop after scanning all the operands of this MI. 589 } 590 } 591 if (!FoundUse) { 592 // Def is dead! 593 DefOp->setIsDead(); 594 return true; 595 } 596 return false; 597} 598 599/// UpdateKills - Track and update kill info. If a MI reads a register that is 600/// marked kill, then it must be due to register reuse. Transfer the kill info 601/// over. 602static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 603 std::vector<MachineOperand*> &KillOps) { 604 const TargetInstrDesc &TID = MI.getDesc(); 605 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 606 MachineOperand &MO = MI.getOperand(i); 607 if (!MO.isRegister() || !MO.isUse()) 608 continue; 609 unsigned Reg = MO.getReg(); 610 if (Reg == 0) 611 continue; 612 613 if (RegKills[Reg]) { 614 // That can't be right. Register is killed but not re-defined and it's 615 // being reused. Let's fix that. 616 KillOps[Reg]->setIsKill(false); 617 KillOps[Reg] = NULL; 618 RegKills.reset(Reg); 619 if (i < TID.getNumOperands() && 620 TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 621 // Unless it's a two-address operand, this is the new kill. 622 MO.setIsKill(); 623 } 624 if (MO.isKill()) { 625 RegKills.set(Reg); 626 KillOps[Reg] = &MO; 627 } 628 } 629 630 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 631 const MachineOperand &MO = MI.getOperand(i); 632 if (!MO.isRegister() || !MO.isDef()) 633 continue; 634 unsigned Reg = MO.getReg(); 635 RegKills.reset(Reg); 636 KillOps[Reg] = NULL; 637 } 638} 639 640/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. 641/// 642static void ReMaterialize(MachineBasicBlock &MBB, 643 MachineBasicBlock::iterator &MII, 644 unsigned DestReg, unsigned Reg, 645 const TargetRegisterInfo *TRI, 646 VirtRegMap &VRM) { 647 TRI->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); 648 MachineInstr *NewMI = prior(MII); 649 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { 650 MachineOperand &MO = NewMI->getOperand(i); 651 if (!MO.isRegister() || MO.getReg() == 0) 652 continue; 653 unsigned VirtReg = MO.getReg(); 654 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 655 continue; 656 assert(MO.isUse()); 657 unsigned SubIdx = MO.getSubReg(); 658 unsigned Phys = VRM.getPhys(VirtReg); 659 assert(Phys); 660 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 661 MO.setReg(RReg); 662 } 663 ++NumReMats; 664} 665 666 667// ReusedOp - For each reused operand, we keep track of a bit of information, in 668// case we need to rollback upon processing a new operand. See comments below. 669namespace { 670 struct ReusedOp { 671 // The MachineInstr operand that reused an available value. 672 unsigned Operand; 673 674 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 675 unsigned StackSlotOrReMat; 676 677 // PhysRegReused - The physical register the value was available in. 678 unsigned PhysRegReused; 679 680 // AssignedPhysReg - The physreg that was assigned for use by the reload. 681 unsigned AssignedPhysReg; 682 683 // VirtReg - The virtual register itself. 684 unsigned VirtReg; 685 686 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 687 unsigned vreg) 688 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 689 AssignedPhysReg(apr), VirtReg(vreg) {} 690 }; 691 692 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 693 /// is reused instead of reloaded. 694 class VISIBILITY_HIDDEN ReuseInfo { 695 MachineInstr &MI; 696 std::vector<ReusedOp> Reuses; 697 BitVector PhysRegsClobbered; 698 public: 699 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { 700 PhysRegsClobbered.resize(tri->getNumRegs()); 701 } 702 703 bool hasReuses() const { 704 return !Reuses.empty(); 705 } 706 707 /// addReuse - If we choose to reuse a virtual register that is already 708 /// available instead of reloading it, remember that we did so. 709 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 710 unsigned PhysRegReused, unsigned AssignedPhysReg, 711 unsigned VirtReg) { 712 // If the reload is to the assigned register anyway, no undo will be 713 // required. 714 if (PhysRegReused == AssignedPhysReg) return; 715 716 // Otherwise, remember this. 717 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 718 AssignedPhysReg, VirtReg)); 719 } 720 721 void markClobbered(unsigned PhysReg) { 722 PhysRegsClobbered.set(PhysReg); 723 } 724 725 bool isClobbered(unsigned PhysReg) const { 726 return PhysRegsClobbered.test(PhysReg); 727 } 728 729 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 730 /// is some other operand that is using the specified register, either pick 731 /// a new register to use, or evict the previous reload and use this reg. 732 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 733 AvailableSpills &Spills, 734 std::vector<MachineInstr*> &MaybeDeadStores, 735 SmallSet<unsigned, 8> &Rejected, 736 BitVector &RegKills, 737 std::vector<MachineOperand*> &KillOps, 738 VirtRegMap &VRM) { 739 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() 740 .getInstrInfo(); 741 742 if (Reuses.empty()) return PhysReg; // This is most often empty. 743 744 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 745 ReusedOp &Op = Reuses[ro]; 746 // If we find some other reuse that was supposed to use this register 747 // exactly for its reload, we can change this reload to use ITS reload 748 // register. That is, unless its reload register has already been 749 // considered and subsequently rejected because it has also been reused 750 // by another operand. 751 if (Op.PhysRegReused == PhysReg && 752 Rejected.count(Op.AssignedPhysReg) == 0) { 753 // Yup, use the reload register that we didn't use before. 754 unsigned NewReg = Op.AssignedPhysReg; 755 Rejected.insert(PhysReg); 756 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 757 RegKills, KillOps, VRM); 758 } else { 759 // Otherwise, we might also have a problem if a previously reused 760 // value aliases the new register. If so, codegen the previous reload 761 // and use this one. 762 unsigned PRRU = Op.PhysRegReused; 763 const TargetRegisterInfo *TRI = Spills.getRegInfo(); 764 if (TRI->areAliases(PRRU, PhysReg)) { 765 // Okay, we found out that an alias of a reused register 766 // was used. This isn't good because it means we have 767 // to undo a previous reuse. 768 MachineBasicBlock *MBB = MI->getParent(); 769 const TargetRegisterClass *AliasRC = 770 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); 771 772 // Copy Op out of the vector and remove it, we're going to insert an 773 // explicit load for it. 774 ReusedOp NewOp = Op; 775 Reuses.erase(Reuses.begin()+ro); 776 777 // Ok, we're going to try to reload the assigned physreg into the 778 // slot that we were supposed to in the first place. However, that 779 // register could hold a reuse. Check to see if it conflicts or 780 // would prefer us to use a different register. 781 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 782 MI, Spills, MaybeDeadStores, 783 Rejected, RegKills, KillOps, VRM); 784 785 MachineBasicBlock::iterator MII = MI; 786 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 787 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TRI, VRM); 788 } else { 789 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, 790 NewOp.StackSlotOrReMat, AliasRC); 791 MachineInstr *LoadMI = prior(MII); 792 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); 793 // Any stores to this stack slot are not dead anymore. 794 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 795 ++NumLoads; 796 } 797 Spills.ClobberPhysReg(NewPhysReg); 798 Spills.ClobberPhysReg(NewOp.PhysRegReused); 799 800 MI->getOperand(NewOp.Operand).setReg(NewPhysReg); 801 802 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); 803 --MII; 804 UpdateKills(*MII, RegKills, KillOps); 805 DOUT << '\t' << *MII; 806 807 DOUT << "Reuse undone!\n"; 808 --NumReused; 809 810 // Finally, PhysReg is now available, go ahead and use it. 811 return PhysReg; 812 } 813 } 814 } 815 return PhysReg; 816 } 817 818 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 819 /// 'Rejected' set to remember which registers have been considered and 820 /// rejected for the reload. This avoids infinite looping in case like 821 /// this: 822 /// t1 := op t2, t3 823 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 824 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 825 /// t1 <- desires r1 826 /// sees r1 is taken by t2, tries t2's reload register r0 827 /// sees r0 is taken by t3, tries t3's reload register r1 828 /// sees r1 is taken by t2, tries t2's reload register r0 ... 829 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 830 AvailableSpills &Spills, 831 std::vector<MachineInstr*> &MaybeDeadStores, 832 BitVector &RegKills, 833 std::vector<MachineOperand*> &KillOps, 834 VirtRegMap &VRM) { 835 SmallSet<unsigned, 8> Rejected; 836 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 837 RegKills, KillOps, VRM); 838 } 839 }; 840} 841 842/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 843/// instruction. e.g. 844/// xorl %edi, %eax 845/// movl %eax, -32(%ebp) 846/// movl -36(%ebp), %eax 847/// orl %eax, -32(%ebp) 848/// ==> 849/// xorl %edi, %eax 850/// orl -36(%ebp), %eax 851/// mov %eax, -32(%ebp) 852/// This enables unfolding optimization for a subsequent instruction which will 853/// also eliminate the newly introduced store instruction. 854bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 855 MachineBasicBlock::iterator &MII, 856 std::vector<MachineInstr*> &MaybeDeadStores, 857 AvailableSpills &Spills, 858 BitVector &RegKills, 859 std::vector<MachineOperand*> &KillOps, 860 VirtRegMap &VRM) { 861 MachineFunction &MF = *MBB.getParent(); 862 MachineInstr &MI = *MII; 863 unsigned UnfoldedOpc = 0; 864 unsigned UnfoldPR = 0; 865 unsigned UnfoldVR = 0; 866 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 867 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 868 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { 869 // Only transform a MI that folds a single register. 870 if (UnfoldedOpc) 871 return false; 872 UnfoldVR = I->second.first; 873 VirtRegMap::ModRef MR = I->second.second; 874 if (VRM.isAssignedReg(UnfoldVR)) 875 continue; 876 // If this reference is not a use, any previous store is now dead. 877 // Otherwise, the store to this stack slot is not dead anymore. 878 FoldedSS = VRM.getStackSlot(UnfoldVR); 879 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 880 if (DeadStore && (MR & VirtRegMap::isModRef)) { 881 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 882 if (!PhysReg || !DeadStore->readsRegister(PhysReg)) 883 continue; 884 UnfoldPR = PhysReg; 885 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 886 false, true); 887 } 888 } 889 890 if (!UnfoldedOpc) 891 return false; 892 893 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 894 MachineOperand &MO = MI.getOperand(i); 895 if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) 896 continue; 897 unsigned VirtReg = MO.getReg(); 898 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 899 continue; 900 if (VRM.isAssignedReg(VirtReg)) { 901 unsigned PhysReg = VRM.getPhys(VirtReg); 902 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) 903 return false; 904 } else if (VRM.isReMaterialized(VirtReg)) 905 continue; 906 int SS = VRM.getStackSlot(VirtReg); 907 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 908 if (PhysReg) { 909 if (TRI->regsOverlap(PhysReg, UnfoldPR)) 910 return false; 911 continue; 912 } 913 PhysReg = VRM.getPhys(VirtReg); 914 if (!TRI->regsOverlap(PhysReg, UnfoldPR)) 915 continue; 916 917 // Ok, we'll need to reload the value into a register which makes 918 // it impossible to perform the store unfolding optimization later. 919 // Let's see if it is possible to fold the load if the store is 920 // unfolded. This allows us to perform the store unfolding 921 // optimization. 922 SmallVector<MachineInstr*, 4> NewMIs; 923 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 924 assert(NewMIs.size() == 1); 925 MachineInstr *NewMI = NewMIs.back(); 926 NewMIs.clear(); 927 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); 928 assert(Idx != -1); 929 SmallVector<unsigned, 2> Ops; 930 Ops.push_back(Idx); 931 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); 932 if (FoldedMI) { 933 VRM.addSpillSlotUse(SS, FoldedMI); 934 if (!VRM.hasPhys(UnfoldVR)) 935 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 936 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 937 MII = MBB.insert(MII, FoldedMI); 938 VRM.RemoveMachineInstrFromMaps(&MI); 939 MBB.erase(&MI); 940 return true; 941 } 942 delete NewMI; 943 } 944 } 945 return false; 946} 947 948/// findSuperReg - Find the SubReg's super-register of given register class 949/// where its SubIdx sub-register is SubReg. 950static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 951 unsigned SubIdx, const TargetRegisterInfo *TRI) { 952 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 953 I != E; ++I) { 954 unsigned Reg = *I; 955 if (TRI->getSubReg(Reg, SubIdx) == SubReg) 956 return Reg; 957 } 958 return 0; 959} 960 961/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 962/// the last store to the same slot is now dead. If so, remove the last store. 963void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 964 MachineBasicBlock::iterator &MII, 965 int Idx, unsigned PhysReg, int StackSlot, 966 const TargetRegisterClass *RC, 967 bool isAvailable, MachineInstr *&LastStore, 968 AvailableSpills &Spills, 969 SmallSet<MachineInstr*, 4> &ReMatDefs, 970 BitVector &RegKills, 971 std::vector<MachineOperand*> &KillOps, 972 VirtRegMap &VRM) { 973 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); 974 MachineInstr *StoreMI = next(MII); 975 VRM.addSpillSlotUse(StackSlot, StoreMI); 976 DOUT << "Store:\t" << *StoreMI; 977 978 // If there is a dead store to this stack slot, nuke it now. 979 if (LastStore) { 980 DOUT << "Removed dead store:\t" << *LastStore; 981 ++NumDSE; 982 SmallVector<unsigned, 2> KillRegs; 983 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 984 MachineBasicBlock::iterator PrevMII = LastStore; 985 bool CheckDef = PrevMII != MBB.begin(); 986 if (CheckDef) 987 --PrevMII; 988 VRM.RemoveMachineInstrFromMaps(LastStore); 989 MBB.erase(LastStore); 990 if (CheckDef) { 991 // Look at defs of killed registers on the store. Mark the defs 992 // as dead since the store has been deleted and they aren't 993 // being reused. 994 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 995 bool HasOtherDef = false; 996 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 997 MachineInstr *DeadDef = PrevMII; 998 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 999 // FIXME: This assumes a remat def does not have side 1000 // effects. 1001 VRM.RemoveMachineInstrFromMaps(DeadDef); 1002 MBB.erase(DeadDef); 1003 ++NumDRM; 1004 } 1005 } 1006 } 1007 } 1008 } 1009 1010 LastStore = next(MII); 1011 1012 // If the stack slot value was previously available in some other 1013 // register, change it now. Otherwise, make the register available, 1014 // in PhysReg. 1015 Spills.ModifyStackSlotOrReMat(StackSlot); 1016 Spills.ClobberPhysReg(PhysReg); 1017 Spills.addAvailable(StackSlot, LastStore, PhysReg, isAvailable); 1018 ++NumStores; 1019} 1020 1021/// rewriteMBB - Keep track of which spills are available even after the 1022/// register allocator is done with them. If possible, avid reloading vregs. 1023void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { 1024 DOUT << MBB.getBasicBlock()->getName() << ":\n"; 1025 1026 MachineFunction &MF = *MBB.getParent(); 1027 1028 // Spills - Keep track of which spilled values are available in physregs so 1029 // that we can choose to reuse the physregs instead of emitting reloads. 1030 AvailableSpills Spills(TRI, TII); 1031 1032 // MaybeDeadStores - When we need to write a value back into a stack slot, 1033 // keep track of the inserted store. If the stack slot value is never read 1034 // (because the value was used from some available register, for example), and 1035 // subsequently stored to, the original store is dead. This map keeps track 1036 // of inserted stores that are not used. If we see a subsequent store to the 1037 // same stack slot, the original store is deleted. 1038 std::vector<MachineInstr*> MaybeDeadStores; 1039 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 1040 1041 // ReMatDefs - These are rematerializable def MIs which are not deleted. 1042 SmallSet<MachineInstr*, 4> ReMatDefs; 1043 1044 // Keep track of kill information. 1045 BitVector RegKills(TRI->getNumRegs()); 1046 std::vector<MachineOperand*> KillOps; 1047 KillOps.resize(TRI->getNumRegs(), NULL); 1048 1049 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 1050 MII != E; ) { 1051 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 1052 1053 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 1054 bool Erased = false; 1055 bool BackTracked = false; 1056 if (PrepForUnfoldOpti(MBB, MII, 1057 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 1058 NextMII = next(MII); 1059 1060 MachineInstr &MI = *MII; 1061 const TargetInstrDesc &TID = MI.getDesc(); 1062 1063 if (VRM.hasEmergencySpills(&MI)) { 1064 // Spill physical register(s) in the rare case the allocator has run out 1065 // of registers to allocate. 1066 SmallSet<int, 4> UsedSS; 1067 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI); 1068 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { 1069 unsigned PhysReg = EmSpills[i]; 1070 const TargetRegisterClass *RC = 1071 TRI->getPhysicalRegisterRegClass(PhysReg); 1072 assert(RC && "Unable to determine register class!"); 1073 int SS = VRM.getEmergencySpillSlot(RC); 1074 if (UsedSS.count(SS)) 1075 assert(0 && "Need to spill more than one physical registers!"); 1076 UsedSS.insert(SS); 1077 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); 1078 MachineInstr *StoreMI = prior(MII); 1079 VRM.addSpillSlotUse(SS, StoreMI); 1080 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); 1081 MachineInstr *LoadMI = next(MII); 1082 VRM.addSpillSlotUse(SS, LoadMI); 1083 ++NumPSpills; 1084 } 1085 NextMII = next(MII); 1086 } 1087 1088 // Insert restores here if asked to. 1089 if (VRM.isRestorePt(&MI)) { 1090 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 1091 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 1092 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. 1093 if (!VRM.getPreSplitReg(VirtReg)) 1094 continue; // Split interval spilled again. 1095 unsigned Phys = VRM.getPhys(VirtReg); 1096 RegInfo->setPhysRegUsed(Phys); 1097 if (VRM.isReMaterialized(VirtReg)) { 1098 ReMaterialize(MBB, MII, Phys, VirtReg, TRI, VRM); 1099 } else { 1100 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1101 int SS = VRM.getStackSlot(VirtReg); 1102 TII->loadRegFromStackSlot(MBB, &MI, Phys, SS, RC); 1103 MachineInstr *LoadMI = prior(MII); 1104 VRM.addSpillSlotUse(SS, LoadMI); 1105 ++NumLoads; 1106 } 1107 // This invalidates Phys. 1108 Spills.ClobberPhysReg(Phys); 1109 UpdateKills(*prior(MII), RegKills, KillOps); 1110 DOUT << '\t' << *prior(MII); 1111 } 1112 } 1113 1114 // Insert spills here if asked to. 1115 if (VRM.isSpillPt(&MI)) { 1116 std::vector<std::pair<unsigned,bool> > &SpillRegs = 1117 VRM.getSpillPtSpills(&MI); 1118 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 1119 unsigned VirtReg = SpillRegs[i].first; 1120 bool isKill = SpillRegs[i].second; 1121 if (!VRM.getPreSplitReg(VirtReg)) 1122 continue; // Split interval spilled again. 1123 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1124 unsigned Phys = VRM.getPhys(VirtReg); 1125 int StackSlot = VRM.getStackSlot(VirtReg); 1126 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); 1127 MachineInstr *StoreMI = next(MII); 1128 VRM.addSpillSlotUse(StackSlot, StoreMI); 1129 DOUT << "Store:\t" << *StoreMI; 1130 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1131 } 1132 NextMII = next(MII); 1133 } 1134 1135 /// ReusedOperands - Keep track of operand reuse in case we need to undo 1136 /// reuse. 1137 ReuseInfo ReusedOperands(MI, TRI); 1138 SmallVector<unsigned, 4> VirtUseOps; 1139 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1140 MachineOperand &MO = MI.getOperand(i); 1141 if (!MO.isRegister() || MO.getReg() == 0) 1142 continue; // Ignore non-register operands. 1143 1144 unsigned VirtReg = MO.getReg(); 1145 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { 1146 // Ignore physregs for spilling, but remember that it is used by this 1147 // function. 1148 RegInfo->setPhysRegUsed(VirtReg); 1149 continue; 1150 } 1151 1152 // We want to process implicit virtual register uses first. 1153 if (MO.isImplicit()) 1154 VirtUseOps.insert(VirtUseOps.begin(), i); 1155 else 1156 VirtUseOps.push_back(i); 1157 } 1158 1159 // Process all of the spilled uses and all non spilled reg references. 1160 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { 1161 unsigned i = VirtUseOps[j]; 1162 MachineOperand &MO = MI.getOperand(i); 1163 unsigned VirtReg = MO.getReg(); 1164 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 1165 "Not a virtual register?"); 1166 1167 unsigned SubIdx = MO.getSubReg(); 1168 if (VRM.isAssignedReg(VirtReg)) { 1169 // This virtual register was assigned a physreg! 1170 unsigned Phys = VRM.getPhys(VirtReg); 1171 RegInfo->setPhysRegUsed(Phys); 1172 if (MO.isDef()) 1173 ReusedOperands.markClobbered(Phys); 1174 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 1175 MI.getOperand(i).setReg(RReg); 1176 continue; 1177 } 1178 1179 // This virtual register is now known to be a spilled value. 1180 if (!MO.isUse()) 1181 continue; // Handle defs in the loop below (handle use&def here though) 1182 1183 bool DoReMat = VRM.isReMaterialized(VirtReg); 1184 int SSorRMId = DoReMat 1185 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1186 int ReuseSlot = SSorRMId; 1187 1188 // Check to see if this stack slot is available. 1189 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1190 1191 // If this is a sub-register use, make sure the reuse register is in the 1192 // right register class. For example, for x86 not all of the 32-bit 1193 // registers have accessible sub-registers. 1194 // Similarly so for EXTRACT_SUBREG. Consider this: 1195 // EDI = op 1196 // MOV32_mr fi#1, EDI 1197 // ... 1198 // = EXTRACT_SUBREG fi#1 1199 // fi#1 is available in EDI, but it cannot be reused because it's not in 1200 // the right register file. 1201 if (PhysReg && 1202 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1203 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1204 if (!RC->contains(PhysReg)) 1205 PhysReg = 0; 1206 } 1207 1208 if (PhysReg) { 1209 // This spilled operand might be part of a two-address operand. If this 1210 // is the case, then changing it will necessarily require changing the 1211 // def part of the instruction as well. However, in some cases, we 1212 // aren't allowed to modify the reused register. If none of these cases 1213 // apply, reuse it. 1214 bool CanReuse = true; 1215 int ti = TID.getOperandConstraint(i, TOI::TIED_TO); 1216 if (ti != -1 && 1217 MI.getOperand(ti).isRegister() && 1218 MI.getOperand(ti).getReg() == VirtReg) { 1219 // Okay, we have a two address operand. We can reuse this physreg as 1220 // long as we are allowed to clobber the value and there isn't an 1221 // earlier def that has already clobbered the physreg. 1222 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1223 !ReusedOperands.isClobbered(PhysReg); 1224 } 1225 1226 if (CanReuse) { 1227 // If this stack slot value is already available, reuse it! 1228 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1229 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1230 else 1231 DOUT << "Reusing SS#" << ReuseSlot; 1232 DOUT << " from physreg " 1233 << TRI->getName(PhysReg) << " for vreg" 1234 << VirtReg <<" instead of reloading into physreg " 1235 << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1236 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1237 MI.getOperand(i).setReg(RReg); 1238 1239 // The only technical detail we have is that we don't know that 1240 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1241 // later in the instruction. In particular, consider 'op V1, V2'. 1242 // If V1 is available in physreg R0, we would choose to reuse it 1243 // here, instead of reloading it into the register the allocator 1244 // indicated (say R1). However, V2 might have to be reloaded 1245 // later, and it might indicate that it needs to live in R0. When 1246 // this occurs, we need to have information available that 1247 // indicates it is safe to use R1 for the reload instead of R0. 1248 // 1249 // To further complicate matters, we might conflict with an alias, 1250 // or R0 and R1 might not be compatible with each other. In this 1251 // case, we actually insert a reload for V1 in R1, ensuring that 1252 // we can get at R0 or its alias. 1253 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1254 VRM.getPhys(VirtReg), VirtReg); 1255 if (ti != -1) 1256 // Only mark it clobbered if this is a use&def operand. 1257 ReusedOperands.markClobbered(PhysReg); 1258 ++NumReused; 1259 1260 if (MI.getOperand(i).isKill() && 1261 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1262 // This was the last use and the spilled value is still available 1263 // for reuse. That means the spill was unnecessary! 1264 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot]; 1265 if (DeadStore) { 1266 DOUT << "Removed dead store:\t" << *DeadStore; 1267 InvalidateKills(*DeadStore, RegKills, KillOps); 1268 VRM.RemoveMachineInstrFromMaps(DeadStore); 1269 MBB.erase(DeadStore); 1270 MaybeDeadStores[ReuseSlot] = NULL; 1271 ++NumDSE; 1272 } 1273 } 1274 continue; 1275 } // CanReuse 1276 1277 // Otherwise we have a situation where we have a two-address instruction 1278 // whose mod/ref operand needs to be reloaded. This reload is already 1279 // available in some register "PhysReg", but if we used PhysReg as the 1280 // operand to our 2-addr instruction, the instruction would modify 1281 // PhysReg. This isn't cool if something later uses PhysReg and expects 1282 // to get its initial value. 1283 // 1284 // To avoid this problem, and to avoid doing a load right after a store, 1285 // we emit a copy from PhysReg into the designated register for this 1286 // operand. 1287 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1288 assert(DesignatedReg && "Must map virtreg to physreg!"); 1289 1290 // Note that, if we reused a register for a previous operand, the 1291 // register we want to reload into might not actually be 1292 // available. If this occurs, use the register indicated by the 1293 // reuser. 1294 if (ReusedOperands.hasReuses()) 1295 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1296 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1297 1298 // If the mapped designated register is actually the physreg we have 1299 // incoming, we don't need to inserted a dead copy. 1300 if (DesignatedReg == PhysReg) { 1301 // If this stack slot value is already available, reuse it! 1302 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1303 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1304 else 1305 DOUT << "Reusing SS#" << ReuseSlot; 1306 DOUT << " from physreg " << TRI->getName(PhysReg) 1307 << " for vreg" << VirtReg 1308 << " instead of reloading into same physreg.\n"; 1309 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1310 MI.getOperand(i).setReg(RReg); 1311 ReusedOperands.markClobbered(RReg); 1312 ++NumReused; 1313 continue; 1314 } 1315 1316 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1317 RegInfo->setPhysRegUsed(DesignatedReg); 1318 ReusedOperands.markClobbered(DesignatedReg); 1319 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1320 1321 MachineInstr *CopyMI = prior(MII); 1322 UpdateKills(*CopyMI, RegKills, KillOps); 1323 1324 // This invalidates DesignatedReg. 1325 Spills.ClobberPhysReg(DesignatedReg); 1326 1327 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); 1328 unsigned RReg = 1329 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1330 MI.getOperand(i).setReg(RReg); 1331 DOUT << '\t' << *prior(MII); 1332 ++NumReused; 1333 continue; 1334 } // if (PhysReg) 1335 1336 // Otherwise, reload it and remember that we have it. 1337 PhysReg = VRM.getPhys(VirtReg); 1338 assert(PhysReg && "Must map virtreg to physreg!"); 1339 1340 // Note that, if we reused a register for a previous operand, the 1341 // register we want to reload into might not actually be 1342 // available. If this occurs, use the register indicated by the 1343 // reuser. 1344 if (ReusedOperands.hasReuses()) 1345 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1346 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1347 1348 RegInfo->setPhysRegUsed(PhysReg); 1349 ReusedOperands.markClobbered(PhysReg); 1350 if (DoReMat) { 1351 ReMaterialize(MBB, MII, PhysReg, VirtReg, TRI, VRM); 1352 } else { 1353 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1354 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1355 MachineInstr *LoadMI = prior(MII); 1356 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1357 ++NumLoads; 1358 } 1359 // This invalidates PhysReg. 1360 Spills.ClobberPhysReg(PhysReg); 1361 1362 // Any stores to this stack slot are not dead anymore. 1363 if (!DoReMat) 1364 MaybeDeadStores[SSorRMId] = NULL; 1365 Spills.addAvailable(SSorRMId, &MI, PhysReg); 1366 // Assumes this is the last use. IsKill will be unset if reg is reused 1367 // unless it's a two-address operand. 1368 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 1369 MI.getOperand(i).setIsKill(); 1370 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1371 MI.getOperand(i).setReg(RReg); 1372 UpdateKills(*prior(MII), RegKills, KillOps); 1373 DOUT << '\t' << *prior(MII); 1374 } 1375 1376 DOUT << '\t' << MI; 1377 1378 1379 // If we have folded references to memory operands, make sure we clear all 1380 // physical registers that may contain the value of the spilled virtual 1381 // register 1382 SmallSet<int, 2> FoldedSS; 1383 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) { 1384 unsigned VirtReg = I->second.first; 1385 VirtRegMap::ModRef MR = I->second.second; 1386 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1387 1388 int SS = VRM.getStackSlot(VirtReg); 1389 if (SS == VirtRegMap::NO_STACK_SLOT) 1390 continue; 1391 FoldedSS.insert(SS); 1392 DOUT << " - StackSlot: " << SS << "\n"; 1393 1394 // If this folded instruction is just a use, check to see if it's a 1395 // straight load from the virt reg slot. 1396 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1397 int FrameIdx; 1398 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1399 if (DestReg && FrameIdx == SS) { 1400 // If this spill slot is available, turn it into a copy (or nothing) 1401 // instead of leaving it as a load! 1402 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1403 DOUT << "Promoted Load To Copy: " << MI; 1404 if (DestReg != InReg) { 1405 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1406 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1407 // Revisit the copy so we make sure to notice the effects of the 1408 // operation on the destreg (either needing to RA it if it's 1409 // virtual or needing to clobber any values if it's physical). 1410 NextMII = &MI; 1411 --NextMII; // backtrack to the copy. 1412 BackTracked = true; 1413 } else { 1414 DOUT << "Removing now-noop copy: " << MI; 1415 // Unset last kill since it's being reused. 1416 InvalidateKill(InReg, RegKills, KillOps); 1417 } 1418 1419 VRM.RemoveMachineInstrFromMaps(&MI); 1420 MBB.erase(&MI); 1421 Erased = true; 1422 goto ProcessNextInst; 1423 } 1424 } else { 1425 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1426 SmallVector<MachineInstr*, 4> NewMIs; 1427 if (PhysReg && 1428 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1429 MBB.insert(MII, NewMIs[0]); 1430 VRM.RemoveMachineInstrFromMaps(&MI); 1431 MBB.erase(&MI); 1432 Erased = true; 1433 --NextMII; // backtrack to the unfolded instruction. 1434 BackTracked = true; 1435 goto ProcessNextInst; 1436 } 1437 } 1438 } 1439 1440 // If this reference is not a use, any previous store is now dead. 1441 // Otherwise, the store to this stack slot is not dead anymore. 1442 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1443 if (DeadStore) { 1444 bool isDead = !(MR & VirtRegMap::isRef); 1445 MachineInstr *NewStore = NULL; 1446 if (MR & VirtRegMap::isModRef) { 1447 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1448 SmallVector<MachineInstr*, 4> NewMIs; 1449 // We can reuse this physreg as long as we are allowed to clobber 1450 // the value and there isn't an earlier def that has already clobbered 1451 // the physreg. 1452 if (PhysReg && 1453 !TII->isStoreToStackSlot(&MI, SS) && // Not profitable! 1454 DeadStore->killsRegister(PhysReg) && 1455 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true, NewMIs)) { 1456 MBB.insert(MII, NewMIs[0]); 1457 NewStore = NewMIs[1]; 1458 MBB.insert(MII, NewStore); 1459 VRM.addSpillSlotUse(SS, NewStore); 1460 VRM.RemoveMachineInstrFromMaps(&MI); 1461 MBB.erase(&MI); 1462 Erased = true; 1463 --NextMII; 1464 --NextMII; // backtrack to the unfolded instruction. 1465 BackTracked = true; 1466 isDead = true; 1467 } 1468 } 1469 1470 if (isDead) { // Previous store is dead. 1471 // If we get here, the store is dead, nuke it now. 1472 DOUT << "Removed dead store:\t" << *DeadStore; 1473 InvalidateKills(*DeadStore, RegKills, KillOps); 1474 VRM.RemoveMachineInstrFromMaps(DeadStore); 1475 MBB.erase(DeadStore); 1476 if (!NewStore) 1477 ++NumDSE; 1478 } 1479 1480 MaybeDeadStores[SS] = NULL; 1481 if (NewStore) { 1482 // Treat this store as a spill merged into a copy. That makes the 1483 // stack slot value available. 1484 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1485 goto ProcessNextInst; 1486 } 1487 } 1488 1489 // If the spill slot value is available, and this is a new definition of 1490 // the value, the value is not available anymore. 1491 if (MR & VirtRegMap::isMod) { 1492 // Notice that the value in this stack slot has been modified. 1493 Spills.ModifyStackSlotOrReMat(SS); 1494 1495 // If this is *just* a mod of the value, check to see if this is just a 1496 // store to the spill slot (i.e. the spill got merged into the copy). If 1497 // so, realize that the vreg is available now, and add the store to the 1498 // MaybeDeadStore info. 1499 int StackSlot; 1500 if (!(MR & VirtRegMap::isRef)) { 1501 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1502 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1503 "Src hasn't been allocated yet?"); 1504 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1505 // this as a potentially dead store in case there is a subsequent 1506 // store into the stack slot without a read from it. 1507 MaybeDeadStores[StackSlot] = &MI; 1508 1509 // If the stack slot value was previously available in some other 1510 // register, change it now. Otherwise, make the register available, 1511 // in PhysReg. 1512 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/); 1513 } 1514 } 1515 } 1516 } 1517 1518 // Process all of the spilled defs. 1519 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1520 MachineOperand &MO = MI.getOperand(i); 1521 if (!(MO.isRegister() && MO.getReg() && MO.isDef())) 1522 continue; 1523 1524 unsigned VirtReg = MO.getReg(); 1525 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { 1526 // Check to see if this is a noop copy. If so, eliminate the 1527 // instruction before considering the dest reg to be changed. 1528 unsigned Src, Dst; 1529 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1530 ++NumDCE; 1531 DOUT << "Removing now-noop copy: " << MI; 1532 VRM.RemoveMachineInstrFromMaps(&MI); 1533 MBB.erase(&MI); 1534 Erased = true; 1535 Spills.disallowClobberPhysReg(VirtReg); 1536 goto ProcessNextInst; 1537 } 1538 1539 // If it's not a no-op copy, it clobbers the value in the destreg. 1540 Spills.ClobberPhysReg(VirtReg); 1541 ReusedOperands.markClobbered(VirtReg); 1542 1543 // Check to see if this instruction is a load from a stack slot into 1544 // a register. If so, this provides the stack slot value in the reg. 1545 int FrameIdx; 1546 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1547 assert(DestReg == VirtReg && "Unknown load situation!"); 1548 1549 // If it is a folded reference, then it's not safe to clobber. 1550 bool Folded = FoldedSS.count(FrameIdx); 1551 // Otherwise, if it wasn't available, remember that it is now! 1552 Spills.addAvailable(FrameIdx, &MI, DestReg, !Folded); 1553 goto ProcessNextInst; 1554 } 1555 1556 continue; 1557 } 1558 1559 unsigned SubIdx = MO.getSubReg(); 1560 bool DoReMat = VRM.isReMaterialized(VirtReg); 1561 if (DoReMat) 1562 ReMatDefs.insert(&MI); 1563 1564 // The only vregs left are stack slot definitions. 1565 int StackSlot = VRM.getStackSlot(VirtReg); 1566 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1567 1568 // If this def is part of a two-address operand, make sure to execute 1569 // the store from the correct physical register. 1570 unsigned PhysReg; 1571 int TiedOp = MI.getDesc().findTiedToSrcOperand(i); 1572 if (TiedOp != -1) { 1573 PhysReg = MI.getOperand(TiedOp).getReg(); 1574 if (SubIdx) { 1575 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); 1576 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1577 "Can't find corresponding super-register!"); 1578 PhysReg = SuperReg; 1579 } 1580 } else { 1581 PhysReg = VRM.getPhys(VirtReg); 1582 if (ReusedOperands.isClobbered(PhysReg)) { 1583 // Another def has taken the assigned physreg. It must have been a 1584 // use&def which got it due to reuse. Undo the reuse! 1585 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1586 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1587 } 1588 } 1589 1590 RegInfo->setPhysRegUsed(PhysReg); 1591 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1592 ReusedOperands.markClobbered(RReg); 1593 MI.getOperand(i).setReg(RReg); 1594 1595 if (!MO.isDead()) { 1596 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1597 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, 1598 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 1599 NextMII = next(MII); 1600 1601 // Check to see if this is a noop copy. If so, eliminate the 1602 // instruction before considering the dest reg to be changed. 1603 { 1604 unsigned Src, Dst; 1605 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) { 1606 ++NumDCE; 1607 DOUT << "Removing now-noop copy: " << MI; 1608 VRM.RemoveMachineInstrFromMaps(&MI); 1609 MBB.erase(&MI); 1610 Erased = true; 1611 UpdateKills(*LastStore, RegKills, KillOps); 1612 goto ProcessNextInst; 1613 } 1614 } 1615 } 1616 } 1617 ProcessNextInst: 1618 if (!Erased && !BackTracked) { 1619 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II) 1620 UpdateKills(*II, RegKills, KillOps); 1621 } 1622 MII = NextMII; 1623 } 1624} 1625 1626llvm::Spiller* llvm::createSpiller() { 1627 switch (SpillerOpt) { 1628 default: assert(0 && "Unreachable!"); 1629 case local: 1630 return new LocalSpiller(); 1631 case simple: 1632 return new SimpleSpiller(); 1633 } 1634} 1635