VirtRegMap.cpp revision fc201f33dd4e18edd9675ed7cd36579ccead6f71
1//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the VirtRegMap class. 11// 12// It also contains implementations of the the Spiller interface, which, given a 13// virtual register map and a machine function, eliminates all virtual 14// references by replacing them with physical register references - adding spill 15// code as necessary. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "spiller" 20#include "VirtRegMap.h" 21#include "llvm/Function.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/ADT/BitVector.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/DepthFirstIterator.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/ADT/STLExtras.h" 36#include "llvm/ADT/SmallSet.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NumSpills , "Number of register spills"); 41STATISTIC(NumPSpills , "Number of physical register spills"); 42STATISTIC(NumReMats , "Number of re-materialization"); 43STATISTIC(NumDRM , "Number of re-materializable defs elided"); 44STATISTIC(NumStores , "Number of stores added"); 45STATISTIC(NumLoads , "Number of loads added"); 46STATISTIC(NumReused , "Number of values reused"); 47STATISTIC(NumDSE , "Number of dead stores elided"); 48STATISTIC(NumDCE , "Number of copies elided"); 49STATISTIC(NumDSS , "Number of dead spill slots removed"); 50STATISTIC(NumCommutes, "Number of instructions commuted"); 51STATISTIC(NumOmitted , "Number of reloads omited"); 52STATISTIC(NumCopified, "Number of available reloads turned into copies"); 53 54namespace { 55 enum SpillerName { simple, local }; 56} 57 58static cl::opt<SpillerName> 59SpillerOpt("spiller", 60 cl::desc("Spiller to use: (default: local)"), 61 cl::Prefix, 62 cl::values(clEnumVal(simple, "simple spiller"), 63 clEnumVal(local, "local spiller"), 64 clEnumValEnd), 65 cl::init(local)); 66 67//===----------------------------------------------------------------------===// 68// VirtRegMap implementation 69//===----------------------------------------------------------------------===// 70 71VirtRegMap::VirtRegMap(MachineFunction &mf) 72 : TII(*mf.getTarget().getInstrInfo()), MF(mf), 73 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), 74 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), 75 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), 76 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { 77 SpillSlotToUsesMap.resize(8); 78 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- 79 TargetRegisterInfo::FirstVirtualRegister); 80 grow(); 81} 82 83void VirtRegMap::grow() { 84 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); 85 Virt2PhysMap.grow(LastVirtReg); 86 Virt2StackSlotMap.grow(LastVirtReg); 87 Virt2ReMatIdMap.grow(LastVirtReg); 88 Virt2SplitMap.grow(LastVirtReg); 89 Virt2SplitKillMap.grow(LastVirtReg); 90 ReMatMap.grow(LastVirtReg); 91 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1); 92} 93 94int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { 95 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 96 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 97 "attempt to assign stack slot to already spilled register"); 98 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); 99 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 100 RC->getAlignment()); 101 if (LowSpillSlot == NO_STACK_SLOT) 102 LowSpillSlot = SS; 103 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 104 HighSpillSlot = SS; 105 unsigned Idx = SS-LowSpillSlot; 106 while (Idx >= SpillSlotToUsesMap.size()) 107 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2); 108 Virt2StackSlotMap[virtReg] = SS; 109 ++NumSpills; 110 return SS; 111} 112 113void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { 114 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 115 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && 116 "attempt to assign stack slot to already spilled register"); 117 assert((SS >= 0 || 118 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && 119 "illegal fixed frame index"); 120 Virt2StackSlotMap[virtReg] = SS; 121} 122 123int VirtRegMap::assignVirtReMatId(unsigned virtReg) { 124 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 125 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 126 "attempt to assign re-mat id to already spilled register"); 127 Virt2ReMatIdMap[virtReg] = ReMatId; 128 return ReMatId++; 129} 130 131void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { 132 assert(TargetRegisterInfo::isVirtualRegister(virtReg)); 133 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && 134 "attempt to assign re-mat id to already spilled register"); 135 Virt2ReMatIdMap[virtReg] = id; 136} 137 138int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { 139 std::map<const TargetRegisterClass*, int>::iterator I = 140 EmergencySpillSlots.find(RC); 141 if (I != EmergencySpillSlots.end()) 142 return I->second; 143 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 144 RC->getAlignment()); 145 if (LowSpillSlot == NO_STACK_SLOT) 146 LowSpillSlot = SS; 147 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot) 148 HighSpillSlot = SS; 149 EmergencySpillSlots[RC] = SS; 150 return SS; 151} 152 153void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { 154 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { 155 // If FI < LowSpillSlot, this stack reference was produced by 156 // instruction selection and is not a spill 157 if (FI >= LowSpillSlot) { 158 assert(FI >= 0 && "Spill slot index should not be negative!"); 159 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 160 && "Invalid spill slot"); 161 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI); 162 } 163 } 164} 165 166void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, 167 MachineInstr *NewMI, ModRef MRInfo) { 168 // Move previous memory references folded to new instruction. 169 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI); 170 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI), 171 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) { 172 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second)); 173 MI2VirtMap.erase(I++); 174 } 175 176 // add new memory reference 177 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo))); 178} 179 180void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { 181 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI); 182 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo))); 183} 184 185void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { 186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 187 MachineOperand &MO = MI->getOperand(i); 188 if (!MO.isFI()) 189 continue; 190 int FI = MO.getIndex(); 191 if (MF.getFrameInfo()->isFixedObjectIndex(FI)) 192 continue; 193 // This stack reference was produced by instruction selection and 194 // is not a spill 195 if (FI < LowSpillSlot) 196 continue; 197 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size() 198 && "Invalid spill slot"); 199 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI); 200 } 201 MI2VirtMap.erase(MI); 202 SpillPt2VirtMap.erase(MI); 203 RestorePt2VirtMap.erase(MI); 204 EmergencySpillMap.erase(MI); 205} 206 207void VirtRegMap::print(std::ostream &OS) const { 208 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); 209 210 OS << "********** REGISTER MAP **********\n"; 211 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 212 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { 213 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) 214 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) 215 << "]\n"; 216 } 217 218 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 219 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) 220 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) 221 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; 222 OS << '\n'; 223} 224 225void VirtRegMap::dump() const { 226 print(cerr); 227} 228 229 230//===----------------------------------------------------------------------===// 231// Simple Spiller Implementation 232//===----------------------------------------------------------------------===// 233 234Spiller::~Spiller() {} 235 236namespace { 237 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller { 238 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM); 239 }; 240} 241 242bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 243 DOUT << "********** REWRITE MACHINE CODE **********\n"; 244 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n'; 245 const TargetMachine &TM = MF.getTarget(); 246 const TargetInstrInfo &TII = *TM.getInstrInfo(); 247 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 248 249 250 // LoadedRegs - Keep track of which vregs are loaded, so that we only load 251 // each vreg once (in the case where a spilled vreg is used by multiple 252 // operands). This is always smaller than the number of operands to the 253 // current machine instr, so it should be small. 254 std::vector<unsigned> LoadedRegs; 255 256 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end(); 257 MBBI != E; ++MBBI) { 258 DOUT << MBBI->getBasicBlock()->getName() << ":\n"; 259 MachineBasicBlock &MBB = *MBBI; 260 for (MachineBasicBlock::iterator MII = MBB.begin(), 261 E = MBB.end(); MII != E; ++MII) { 262 MachineInstr &MI = *MII; 263 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 264 MachineOperand &MO = MI.getOperand(i); 265 if (MO.isReg() && MO.getReg()) { 266 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 267 unsigned VirtReg = MO.getReg(); 268 unsigned SubIdx = MO.getSubReg(); 269 unsigned PhysReg = VRM.getPhys(VirtReg); 270 unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg; 271 if (!VRM.isAssignedReg(VirtReg)) { 272 int StackSlot = VRM.getStackSlot(VirtReg); 273 const TargetRegisterClass* RC = 274 MF.getRegInfo().getRegClass(VirtReg); 275 276 if (MO.isUse() && 277 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg) 278 == LoadedRegs.end()) { 279 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC); 280 MachineInstr *LoadMI = prior(MII); 281 VRM.addSpillSlotUse(StackSlot, LoadMI); 282 LoadedRegs.push_back(VirtReg); 283 ++NumLoads; 284 DOUT << '\t' << *LoadMI; 285 } 286 287 if (MO.isDef()) { 288 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true, 289 StackSlot, RC); 290 MachineInstr *StoreMI = next(MII); 291 VRM.addSpillSlotUse(StackSlot, StoreMI); 292 ++NumStores; 293 } 294 } 295 MF.getRegInfo().setPhysRegUsed(RReg); 296 MI.getOperand(i).setReg(RReg); 297 } else { 298 MF.getRegInfo().setPhysRegUsed(MO.getReg()); 299 } 300 } 301 } 302 303 DOUT << '\t' << MI; 304 LoadedRegs.clear(); 305 } 306 } 307 return true; 308} 309 310//===----------------------------------------------------------------------===// 311// Local Spiller Implementation 312//===----------------------------------------------------------------------===// 313 314/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from 315/// top down, keep track of which spills slots or remat are available in each 316/// register. 317/// 318/// Note that not all physregs are created equal here. In particular, some 319/// physregs are reloads that we are allowed to clobber or ignore at any time. 320/// Other physregs are values that the register allocated program is using that 321/// we cannot CHANGE, but we can read if we like. We keep track of this on a 322/// per-stack-slot / remat id basis as the low bit in the value of the 323/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks 324/// this bit and addAvailable sets it if. 325namespace { 326class VISIBILITY_HIDDEN AvailableSpills { 327 const TargetRegisterInfo *TRI; 328 const TargetInstrInfo *TII; 329 330 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled 331 // or remat'ed virtual register values that are still available, due to being 332 // loaded or stored to, but not invalidated yet. 333 std::map<int, unsigned> SpillSlotsOrReMatsAvailable; 334 335 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable, 336 // indicating which stack slot values are currently held by a physreg. This 337 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a 338 // physreg is modified. 339 std::multimap<unsigned, int> PhysRegsAvailable; 340 341 void disallowClobberPhysRegOnly(unsigned PhysReg); 342 343 void ClobberPhysRegOnly(unsigned PhysReg); 344public: 345 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) 346 : TRI(tri), TII(tii) { 347 } 348 349 /// clear - Reset the state. 350 void clear() { 351 SpillSlotsOrReMatsAvailable.clear(); 352 PhysRegsAvailable.clear(); 353 } 354 355 const TargetRegisterInfo *getRegInfo() const { return TRI; } 356 357 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is 358 /// available in a physical register, return that PhysReg, otherwise 359 /// return 0. 360 unsigned getSpillSlotOrReMatPhysReg(int Slot) const { 361 std::map<int, unsigned>::const_iterator I = 362 SpillSlotsOrReMatsAvailable.find(Slot); 363 if (I != SpillSlotsOrReMatsAvailable.end()) { 364 return I->second >> 1; // Remove the CanClobber bit. 365 } 366 return 0; 367 } 368 369 /// addAvailable - Mark that the specified stack slot / remat is available in 370 /// the specified physreg. If CanClobber is true, the physreg can be modified 371 /// at any time without changing the semantics of the program. 372 void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) { 373 // If this stack slot is thought to be available in some other physreg, 374 // remove its record. 375 ModifyStackSlotOrReMat(SlotOrReMat); 376 377 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat)); 378 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber; 379 380 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 381 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; 382 else 383 DOUT << "Remembering SS#" << SlotOrReMat; 384 DOUT << " in physreg " << TRI->getName(Reg) << "\n"; 385 } 386 387 /// canClobberPhysReg - Return true if the spiller is allowed to change the 388 /// value of the specified stackslot register if it desires. The specified 389 /// stack slot must be available in a physreg for this query to make sense. 390 bool canClobberPhysReg(int SlotOrReMat) const { 391 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && 392 "Value not available!"); 393 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1; 394 } 395 396 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified 397 /// stackslot register. The register is still available but is no longer 398 /// allowed to be modifed. 399 void disallowClobberPhysReg(unsigned PhysReg); 400 401 /// ClobberPhysReg - This is called when the specified physreg changes 402 /// value. We use this to invalidate any info about stuff that lives in 403 /// it and any of its aliases. 404 void ClobberPhysReg(unsigned PhysReg); 405 406 /// ModifyStackSlotOrReMat - This method is called when the value in a stack 407 /// slot changes. This removes information about which register the previous 408 /// value for this slot lives in (as the previous value is dead now). 409 void ModifyStackSlotOrReMat(int SlotOrReMat); 410}; 411} 412 413/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified 414/// stackslot register. The register is still available but is no longer 415/// allowed to be modifed. 416void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { 417 std::multimap<unsigned, int>::iterator I = 418 PhysRegsAvailable.lower_bound(PhysReg); 419 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 420 int SlotOrReMat = I->second; 421 I++; 422 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 423 "Bidirectional map mismatch!"); 424 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; 425 DOUT << "PhysReg " << TRI->getName(PhysReg) 426 << " copied, it is available for use but can no longer be modified\n"; 427 } 428} 429 430/// disallowClobberPhysReg - Unset the CanClobber bit of the specified 431/// stackslot register and its aliases. The register and its aliases may 432/// still available but is no longer allowed to be modifed. 433void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { 434 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 435 disallowClobberPhysRegOnly(*AS); 436 disallowClobberPhysRegOnly(PhysReg); 437} 438 439/// ClobberPhysRegOnly - This is called when the specified physreg changes 440/// value. We use this to invalidate any info about stuff we thing lives in it. 441void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { 442 std::multimap<unsigned, int>::iterator I = 443 PhysRegsAvailable.lower_bound(PhysReg); 444 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { 445 int SlotOrReMat = I->second; 446 PhysRegsAvailable.erase(I++); 447 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && 448 "Bidirectional map mismatch!"); 449 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); 450 DOUT << "PhysReg " << TRI->getName(PhysReg) 451 << " clobbered, invalidating "; 452 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) 453 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; 454 else 455 DOUT << "SS#" << SlotOrReMat << "\n"; 456 } 457} 458 459/// ClobberPhysReg - This is called when the specified physreg changes 460/// value. We use this to invalidate any info about stuff we thing lives in 461/// it and any of its aliases. 462void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { 463 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) 464 ClobberPhysRegOnly(*AS); 465 ClobberPhysRegOnly(PhysReg); 466} 467 468/// ModifyStackSlotOrReMat - This method is called when the value in a stack 469/// slot changes. This removes information about which register the previous 470/// value for this slot lives in (as the previous value is dead now). 471void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) { 472 std::map<int, unsigned>::iterator It = 473 SpillSlotsOrReMatsAvailable.find(SlotOrReMat); 474 if (It == SpillSlotsOrReMatsAvailable.end()) return; 475 unsigned Reg = It->second >> 1; 476 SpillSlotsOrReMatsAvailable.erase(It); 477 478 // This register may hold the value of multiple stack slots, only remove this 479 // stack slot from the set of values the register contains. 480 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg); 481 for (; ; ++I) { 482 assert(I != PhysRegsAvailable.end() && I->first == Reg && 483 "Map inverse broken!"); 484 if (I->second == SlotOrReMat) break; 485 } 486 PhysRegsAvailable.erase(I); 487} 488 489static void findSinglePredSuccessor(MachineBasicBlock *MBB, 490 SmallVectorImpl<MachineBasicBlock *> &Succs) { 491 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 492 SE = MBB->succ_end(); SI != SE; ++SI) { 493 MachineBasicBlock *SuccMBB = *SI; 494 if (SuccMBB->pred_size() == 1) 495 Succs.push_back(SuccMBB); 496 } 497} 498 499namespace { 500 class AvailableSpills; 501 502 /// LocalSpiller - This spiller does a simple pass over the machine basic 503 /// block to attempt to keep spills in registers as much as possible for 504 /// blocks that have low register pressure (the vreg may be spilled due to 505 /// register pressure in other blocks). 506 class VISIBILITY_HIDDEN LocalSpiller : public Spiller { 507 MachineRegisterInfo *RegInfo; 508 const TargetRegisterInfo *TRI; 509 const TargetInstrInfo *TII; 510 DenseMap<MachineInstr*, unsigned> DistanceMap; 511 public: 512 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { 513 RegInfo = &MF.getRegInfo(); 514 TRI = MF.getTarget().getRegisterInfo(); 515 TII = MF.getTarget().getInstrInfo(); 516 DOUT << "\n**** Local spiller rewriting function '" 517 << MF.getFunction()->getName() << "':\n"; 518 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)" 519 " ****\n"; 520 DEBUG(MF.dump()); 521 522 // Spills - Keep track of which spilled values are available in physregs 523 // so that we can choose to reuse the physregs instead of emitting 524 // reloads. This is usually refreshed per basic block. 525 AvailableSpills Spills(TRI, TII); 526 527 // SingleEntrySuccs - Successor blocks which have a single predecessor. 528 SmallVector<MachineBasicBlock*, 4> SinglePredSuccs; 529 SmallPtrSet<MachineBasicBlock*,16> EarlyVisited; 530 531 // Traverse the basic blocks depth first. 532 MachineBasicBlock *Entry = MF.begin(); 533 SmallPtrSet<MachineBasicBlock*,16> Visited; 534 for (df_ext_iterator<MachineBasicBlock*, 535 SmallPtrSet<MachineBasicBlock*,16> > 536 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); 537 DFI != E; ++DFI) { 538 MachineBasicBlock *MBB = *DFI; 539 if (!EarlyVisited.count(MBB)) 540 RewriteMBB(*MBB, VRM, Spills); 541 542 // If this MBB is the only predecessor of a successor. Keep the 543 // availability information and visit it next. 544 do { 545 // Keep visiting single predecessor successor as long as possible. 546 SinglePredSuccs.clear(); 547 findSinglePredSuccessor(MBB, SinglePredSuccs); 548 if (SinglePredSuccs.empty()) 549 MBB = 0; 550 else { 551 // FIXME: More than one successors, each of which has MBB has 552 // the only predecessor. 553 MBB = SinglePredSuccs[0]; 554 if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) 555 RewriteMBB(*MBB, VRM, Spills); 556 } 557 } while (MBB); 558 559 // Clear the availability info. 560 Spills.clear(); 561 } 562 563 DOUT << "**** Post Machine Instrs ****\n"; 564 DEBUG(MF.dump()); 565 566 // Mark unused spill slots. 567 MachineFrameInfo *MFI = MF.getFrameInfo(); 568 int SS = VRM.getLowSpillSlot(); 569 if (SS != VirtRegMap::NO_STACK_SLOT) 570 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS) 571 if (!VRM.isSpillSlotUsed(SS)) { 572 MFI->RemoveStackObject(SS); 573 ++NumDSS; 574 } 575 576 return true; 577 } 578 private: 579 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 580 unsigned Reg, BitVector &RegKills, 581 std::vector<MachineOperand*> &KillOps); 582 bool PrepForUnfoldOpti(MachineBasicBlock &MBB, 583 MachineBasicBlock::iterator &MII, 584 std::vector<MachineInstr*> &MaybeDeadStores, 585 AvailableSpills &Spills, BitVector &RegKills, 586 std::vector<MachineOperand*> &KillOps, 587 VirtRegMap &VRM); 588 bool CommuteToFoldReload(MachineBasicBlock &MBB, 589 MachineBasicBlock::iterator &MII, 590 unsigned VirtReg, unsigned SrcReg, int SS, 591 BitVector &RegKills, 592 std::vector<MachineOperand*> &KillOps, 593 const TargetRegisterInfo *TRI, 594 VirtRegMap &VRM); 595 void SpillRegToStackSlot(MachineBasicBlock &MBB, 596 MachineBasicBlock::iterator &MII, 597 int Idx, unsigned PhysReg, int StackSlot, 598 const TargetRegisterClass *RC, 599 bool isAvailable, MachineInstr *&LastStore, 600 AvailableSpills &Spills, 601 SmallSet<MachineInstr*, 4> &ReMatDefs, 602 BitVector &RegKills, 603 std::vector<MachineOperand*> &KillOps, 604 VirtRegMap &VRM); 605 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, 606 AvailableSpills &Spills); 607 }; 608} 609 610/// InvalidateKills - MI is going to be deleted. If any of its operands are 611/// marked kill, then invalidate the information. 612static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, 613 std::vector<MachineOperand*> &KillOps, 614 SmallVector<unsigned, 2> *KillRegs = NULL) { 615 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 616 MachineOperand &MO = MI.getOperand(i); 617 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 618 continue; 619 unsigned Reg = MO.getReg(); 620 if (TargetRegisterInfo::isVirtualRegister(Reg)) 621 continue; 622 if (KillRegs) 623 KillRegs->push_back(Reg); 624 assert(Reg < KillOps.size()); 625 if (KillOps[Reg] == &MO) { 626 RegKills.reset(Reg); 627 KillOps[Reg] = NULL; 628 } 629 } 630} 631 632/// InvalidateKill - A MI that defines the specified register is being deleted, 633/// invalidate the register kill information. 634static void InvalidateKill(unsigned Reg, BitVector &RegKills, 635 std::vector<MachineOperand*> &KillOps) { 636 if (RegKills[Reg]) { 637 KillOps[Reg]->setIsKill(false); 638 KillOps[Reg] = NULL; 639 RegKills.reset(Reg); 640 } 641} 642 643/// InvalidateRegDef - If the def operand of the specified def MI is now dead 644/// (since it's spill instruction is removed), mark it isDead. Also checks if 645/// the def MI has other definition operands that are not dead. Returns it by 646/// reference. 647static bool InvalidateRegDef(MachineBasicBlock::iterator I, 648 MachineInstr &NewDef, unsigned Reg, 649 bool &HasLiveDef) { 650 // Due to remat, it's possible this reg isn't being reused. That is, 651 // the def of this reg (by prev MI) is now dead. 652 MachineInstr *DefMI = I; 653 MachineOperand *DefOp = NULL; 654 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { 655 MachineOperand &MO = DefMI->getOperand(i); 656 if (MO.isReg() && MO.isDef()) { 657 if (MO.getReg() == Reg) 658 DefOp = &MO; 659 else if (!MO.isDead()) 660 HasLiveDef = true; 661 } 662 } 663 if (!DefOp) 664 return false; 665 666 bool FoundUse = false, Done = false; 667 MachineBasicBlock::iterator E = &NewDef; 668 ++I; ++E; 669 for (; !Done && I != E; ++I) { 670 MachineInstr *NMI = I; 671 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) { 672 MachineOperand &MO = NMI->getOperand(j); 673 if (!MO.isReg() || MO.getReg() != Reg) 674 continue; 675 if (MO.isUse()) 676 FoundUse = true; 677 Done = true; // Stop after scanning all the operands of this MI. 678 } 679 } 680 if (!FoundUse) { 681 // Def is dead! 682 DefOp->setIsDead(); 683 return true; 684 } 685 return false; 686} 687 688/// UpdateKills - Track and update kill info. If a MI reads a register that is 689/// marked kill, then it must be due to register reuse. Transfer the kill info 690/// over. 691static void UpdateKills(MachineInstr &MI, BitVector &RegKills, 692 std::vector<MachineOperand*> &KillOps, 693 const TargetRegisterInfo* TRI) { 694 const TargetInstrDesc &TID = MI.getDesc(); 695 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 696 MachineOperand &MO = MI.getOperand(i); 697 if (!MO.isReg() || !MO.isUse()) 698 continue; 699 unsigned Reg = MO.getReg(); 700 if (Reg == 0) 701 continue; 702 703 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) { 704 // That can't be right. Register is killed but not re-defined and it's 705 // being reused. Let's fix that. 706 KillOps[Reg]->setIsKill(false); 707 KillOps[Reg] = NULL; 708 RegKills.reset(Reg); 709 if (i < TID.getNumOperands() && 710 TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 711 // Unless it's a two-address operand, this is the new kill. 712 MO.setIsKill(); 713 } 714 if (MO.isKill()) { 715 RegKills.set(Reg); 716 KillOps[Reg] = &MO; 717 } 718 } 719 720 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 721 const MachineOperand &MO = MI.getOperand(i); 722 if (!MO.isReg() || !MO.isDef()) 723 continue; 724 unsigned Reg = MO.getReg(); 725 RegKills.reset(Reg); 726 KillOps[Reg] = NULL; 727 // It also defines (or partially define) aliases. 728 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { 729 RegKills.reset(*AS); 730 KillOps[*AS] = NULL; 731 } 732 } 733} 734 735/// ReMaterialize - Re-materialize definition for Reg targetting DestReg. 736/// 737static void ReMaterialize(MachineBasicBlock &MBB, 738 MachineBasicBlock::iterator &MII, 739 unsigned DestReg, unsigned Reg, 740 const TargetInstrInfo *TII, 741 const TargetRegisterInfo *TRI, 742 VirtRegMap &VRM) { 743 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg)); 744 MachineInstr *NewMI = prior(MII); 745 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) { 746 MachineOperand &MO = NewMI->getOperand(i); 747 if (!MO.isReg() || MO.getReg() == 0) 748 continue; 749 unsigned VirtReg = MO.getReg(); 750 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) 751 continue; 752 assert(MO.isUse()); 753 unsigned SubIdx = MO.getSubReg(); 754 unsigned Phys = VRM.getPhys(VirtReg); 755 assert(Phys); 756 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 757 MO.setReg(RReg); 758 } 759 ++NumReMats; 760} 761 762 763// ReusedOp - For each reused operand, we keep track of a bit of information, in 764// case we need to rollback upon processing a new operand. See comments below. 765namespace { 766 struct ReusedOp { 767 // The MachineInstr operand that reused an available value. 768 unsigned Operand; 769 770 // StackSlotOrReMat - The spill slot or remat id of the value being reused. 771 unsigned StackSlotOrReMat; 772 773 // PhysRegReused - The physical register the value was available in. 774 unsigned PhysRegReused; 775 776 // AssignedPhysReg - The physreg that was assigned for use by the reload. 777 unsigned AssignedPhysReg; 778 779 // VirtReg - The virtual register itself. 780 unsigned VirtReg; 781 782 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr, 783 unsigned vreg) 784 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), 785 AssignedPhysReg(apr), VirtReg(vreg) {} 786 }; 787 788 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that 789 /// is reused instead of reloaded. 790 class VISIBILITY_HIDDEN ReuseInfo { 791 MachineInstr &MI; 792 std::vector<ReusedOp> Reuses; 793 BitVector PhysRegsClobbered; 794 public: 795 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { 796 PhysRegsClobbered.resize(tri->getNumRegs()); 797 } 798 799 bool hasReuses() const { 800 return !Reuses.empty(); 801 } 802 803 /// addReuse - If we choose to reuse a virtual register that is already 804 /// available instead of reloading it, remember that we did so. 805 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat, 806 unsigned PhysRegReused, unsigned AssignedPhysReg, 807 unsigned VirtReg) { 808 // If the reload is to the assigned register anyway, no undo will be 809 // required. 810 if (PhysRegReused == AssignedPhysReg) return; 811 812 // Otherwise, remember this. 813 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused, 814 AssignedPhysReg, VirtReg)); 815 } 816 817 void markClobbered(unsigned PhysReg) { 818 PhysRegsClobbered.set(PhysReg); 819 } 820 821 bool isClobbered(unsigned PhysReg) const { 822 return PhysRegsClobbered.test(PhysReg); 823 } 824 825 /// GetRegForReload - We are about to emit a reload into PhysReg. If there 826 /// is some other operand that is using the specified register, either pick 827 /// a new register to use, or evict the previous reload and use this reg. 828 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 829 AvailableSpills &Spills, 830 std::vector<MachineInstr*> &MaybeDeadStores, 831 SmallSet<unsigned, 8> &Rejected, 832 BitVector &RegKills, 833 std::vector<MachineOperand*> &KillOps, 834 VirtRegMap &VRM) { 835 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget() 836 .getInstrInfo(); 837 838 if (Reuses.empty()) return PhysReg; // This is most often empty. 839 840 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) { 841 ReusedOp &Op = Reuses[ro]; 842 // If we find some other reuse that was supposed to use this register 843 // exactly for its reload, we can change this reload to use ITS reload 844 // register. That is, unless its reload register has already been 845 // considered and subsequently rejected because it has also been reused 846 // by another operand. 847 if (Op.PhysRegReused == PhysReg && 848 Rejected.count(Op.AssignedPhysReg) == 0) { 849 // Yup, use the reload register that we didn't use before. 850 unsigned NewReg = Op.AssignedPhysReg; 851 Rejected.insert(PhysReg); 852 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected, 853 RegKills, KillOps, VRM); 854 } else { 855 // Otherwise, we might also have a problem if a previously reused 856 // value aliases the new register. If so, codegen the previous reload 857 // and use this one. 858 unsigned PRRU = Op.PhysRegReused; 859 const TargetRegisterInfo *TRI = Spills.getRegInfo(); 860 if (TRI->areAliases(PRRU, PhysReg)) { 861 // Okay, we found out that an alias of a reused register 862 // was used. This isn't good because it means we have 863 // to undo a previous reuse. 864 MachineBasicBlock *MBB = MI->getParent(); 865 const TargetRegisterClass *AliasRC = 866 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); 867 868 // Copy Op out of the vector and remove it, we're going to insert an 869 // explicit load for it. 870 ReusedOp NewOp = Op; 871 Reuses.erase(Reuses.begin()+ro); 872 873 // Ok, we're going to try to reload the assigned physreg into the 874 // slot that we were supposed to in the first place. However, that 875 // register could hold a reuse. Check to see if it conflicts or 876 // would prefer us to use a different register. 877 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg, 878 MI, Spills, MaybeDeadStores, 879 Rejected, RegKills, KillOps, VRM); 880 881 MachineBasicBlock::iterator MII = MI; 882 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { 883 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM); 884 } else { 885 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg, 886 NewOp.StackSlotOrReMat, AliasRC); 887 MachineInstr *LoadMI = prior(MII); 888 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI); 889 // Any stores to this stack slot are not dead anymore. 890 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL; 891 ++NumLoads; 892 } 893 Spills.ClobberPhysReg(NewPhysReg); 894 Spills.ClobberPhysReg(NewOp.PhysRegReused); 895 896 unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg(); 897 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg; 898 MI->getOperand(NewOp.Operand).setReg(RReg); 899 900 Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg); 901 --MII; 902 UpdateKills(*MII, RegKills, KillOps, TRI); 903 DOUT << '\t' << *MII; 904 905 DOUT << "Reuse undone!\n"; 906 --NumReused; 907 908 // Finally, PhysReg is now available, go ahead and use it. 909 return PhysReg; 910 } 911 } 912 } 913 return PhysReg; 914 } 915 916 /// GetRegForReload - Helper for the above GetRegForReload(). Add a 917 /// 'Rejected' set to remember which registers have been considered and 918 /// rejected for the reload. This avoids infinite looping in case like 919 /// this: 920 /// t1 := op t2, t3 921 /// t2 <- assigned r0 for use by the reload but ended up reuse r1 922 /// t3 <- assigned r1 for use by the reload but ended up reuse r0 923 /// t1 <- desires r1 924 /// sees r1 is taken by t2, tries t2's reload register r0 925 /// sees r0 is taken by t3, tries t3's reload register r1 926 /// sees r1 is taken by t2, tries t2's reload register r0 ... 927 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI, 928 AvailableSpills &Spills, 929 std::vector<MachineInstr*> &MaybeDeadStores, 930 BitVector &RegKills, 931 std::vector<MachineOperand*> &KillOps, 932 VirtRegMap &VRM) { 933 SmallSet<unsigned, 8> Rejected; 934 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected, 935 RegKills, KillOps, VRM); 936 } 937 }; 938} 939 940/// PrepForUnfoldOpti - Turn a store folding instruction into a load folding 941/// instruction. e.g. 942/// xorl %edi, %eax 943/// movl %eax, -32(%ebp) 944/// movl -36(%ebp), %eax 945/// orl %eax, -32(%ebp) 946/// ==> 947/// xorl %edi, %eax 948/// orl -36(%ebp), %eax 949/// mov %eax, -32(%ebp) 950/// This enables unfolding optimization for a subsequent instruction which will 951/// also eliminate the newly introduced store instruction. 952bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, 953 MachineBasicBlock::iterator &MII, 954 std::vector<MachineInstr*> &MaybeDeadStores, 955 AvailableSpills &Spills, 956 BitVector &RegKills, 957 std::vector<MachineOperand*> &KillOps, 958 VirtRegMap &VRM) { 959 MachineFunction &MF = *MBB.getParent(); 960 MachineInstr &MI = *MII; 961 unsigned UnfoldedOpc = 0; 962 unsigned UnfoldPR = 0; 963 unsigned UnfoldVR = 0; 964 int FoldedSS = VirtRegMap::NO_STACK_SLOT; 965 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 966 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 967 // Only transform a MI that folds a single register. 968 if (UnfoldedOpc) 969 return false; 970 UnfoldVR = I->second.first; 971 VirtRegMap::ModRef MR = I->second.second; 972 // MI2VirtMap be can updated which invalidate the iterator. 973 // Increment the iterator first. 974 ++I; 975 if (VRM.isAssignedReg(UnfoldVR)) 976 continue; 977 // If this reference is not a use, any previous store is now dead. 978 // Otherwise, the store to this stack slot is not dead anymore. 979 FoldedSS = VRM.getStackSlot(UnfoldVR); 980 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS]; 981 if (DeadStore && (MR & VirtRegMap::isModRef)) { 982 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS); 983 if (!PhysReg || !DeadStore->readsRegister(PhysReg)) 984 continue; 985 UnfoldPR = PhysReg; 986 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 987 false, true); 988 } 989 } 990 991 if (!UnfoldedOpc) 992 return false; 993 994 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 995 MachineOperand &MO = MI.getOperand(i); 996 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse()) 997 continue; 998 unsigned VirtReg = MO.getReg(); 999 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) 1000 continue; 1001 if (VRM.isAssignedReg(VirtReg)) { 1002 unsigned PhysReg = VRM.getPhys(VirtReg); 1003 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) 1004 return false; 1005 } else if (VRM.isReMaterialized(VirtReg)) 1006 continue; 1007 int SS = VRM.getStackSlot(VirtReg); 1008 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1009 if (PhysReg) { 1010 if (TRI->regsOverlap(PhysReg, UnfoldPR)) 1011 return false; 1012 continue; 1013 } 1014 if (VRM.hasPhys(VirtReg)) { 1015 PhysReg = VRM.getPhys(VirtReg); 1016 if (!TRI->regsOverlap(PhysReg, UnfoldPR)) 1017 continue; 1018 } 1019 1020 // Ok, we'll need to reload the value into a register which makes 1021 // it impossible to perform the store unfolding optimization later. 1022 // Let's see if it is possible to fold the load if the store is 1023 // unfolded. This allows us to perform the store unfolding 1024 // optimization. 1025 SmallVector<MachineInstr*, 4> NewMIs; 1026 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) { 1027 assert(NewMIs.size() == 1); 1028 MachineInstr *NewMI = NewMIs.back(); 1029 NewMIs.clear(); 1030 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false); 1031 assert(Idx != -1); 1032 SmallVector<unsigned, 2> Ops; 1033 Ops.push_back(Idx); 1034 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS); 1035 if (FoldedMI) { 1036 VRM.addSpillSlotUse(SS, FoldedMI); 1037 if (!VRM.hasPhys(UnfoldVR)) 1038 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR); 1039 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 1040 MII = MBB.insert(MII, FoldedMI); 1041 InvalidateKills(MI, RegKills, KillOps); 1042 VRM.RemoveMachineInstrFromMaps(&MI); 1043 MBB.erase(&MI); 1044 MF.DeleteMachineInstr(NewMI); 1045 return true; 1046 } 1047 MF.DeleteMachineInstr(NewMI); 1048 } 1049 } 1050 return false; 1051} 1052 1053/// CommuteToFoldReload - 1054/// Look for 1055/// r1 = load fi#1 1056/// r1 = op r1, r2<kill> 1057/// store r1, fi#1 1058/// 1059/// If op is commutable and r2 is killed, then we can xform these to 1060/// r2 = op r2, fi#1 1061/// store r2, fi#1 1062bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB, 1063 MachineBasicBlock::iterator &MII, 1064 unsigned VirtReg, unsigned SrcReg, int SS, 1065 BitVector &RegKills, 1066 std::vector<MachineOperand*> &KillOps, 1067 const TargetRegisterInfo *TRI, 1068 VirtRegMap &VRM) { 1069 if (MII == MBB.begin() || !MII->killsRegister(SrcReg)) 1070 return false; 1071 1072 MachineFunction &MF = *MBB.getParent(); 1073 MachineInstr &MI = *MII; 1074 MachineBasicBlock::iterator DefMII = prior(MII); 1075 MachineInstr *DefMI = DefMII; 1076 const TargetInstrDesc &TID = DefMI->getDesc(); 1077 unsigned NewDstIdx; 1078 if (DefMII != MBB.begin() && 1079 TID.isCommutable() && 1080 TII->CommuteChangesDestination(DefMI, NewDstIdx)) { 1081 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 1082 unsigned NewReg = NewDstMO.getReg(); 1083 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg)) 1084 return false; 1085 MachineInstr *ReloadMI = prior(DefMII); 1086 int FrameIdx; 1087 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx); 1088 if (DestReg != SrcReg || FrameIdx != SS) 1089 return false; 1090 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false); 1091 if (UseIdx == -1) 1092 return false; 1093 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO); 1094 if (DefIdx == -1) 1095 return false; 1096 assert(DefMI->getOperand(DefIdx).isReg() && 1097 DefMI->getOperand(DefIdx).getReg() == SrcReg); 1098 1099 // Now commute def instruction. 1100 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true); 1101 if (!CommutedMI) 1102 return false; 1103 SmallVector<unsigned, 2> Ops; 1104 Ops.push_back(NewDstIdx); 1105 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS); 1106 // Not needed since foldMemoryOperand returns new MI. 1107 MF.DeleteMachineInstr(CommutedMI); 1108 if (!FoldedMI) 1109 return false; 1110 1111 VRM.addSpillSlotUse(SS, FoldedMI); 1112 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); 1113 // Insert new def MI and spill MI. 1114 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); 1115 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC); 1116 MII = prior(MII); 1117 MachineInstr *StoreMI = MII; 1118 VRM.addSpillSlotUse(SS, StoreMI); 1119 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1120 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack. 1121 1122 // Delete all 3 old instructions. 1123 InvalidateKills(*ReloadMI, RegKills, KillOps); 1124 VRM.RemoveMachineInstrFromMaps(ReloadMI); 1125 MBB.erase(ReloadMI); 1126 InvalidateKills(*DefMI, RegKills, KillOps); 1127 VRM.RemoveMachineInstrFromMaps(DefMI); 1128 MBB.erase(DefMI); 1129 InvalidateKills(MI, RegKills, KillOps); 1130 VRM.RemoveMachineInstrFromMaps(&MI); 1131 MBB.erase(&MI); 1132 1133 ++NumCommutes; 1134 return true; 1135 } 1136 1137 return false; 1138} 1139 1140/// findSuperReg - Find the SubReg's super-register of given register class 1141/// where its SubIdx sub-register is SubReg. 1142static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, 1143 unsigned SubIdx, const TargetRegisterInfo *TRI) { 1144 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 1145 I != E; ++I) { 1146 unsigned Reg = *I; 1147 if (TRI->getSubReg(Reg, SubIdx) == SubReg) 1148 return Reg; 1149 } 1150 return 0; 1151} 1152 1153/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if 1154/// the last store to the same slot is now dead. If so, remove the last store. 1155void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB, 1156 MachineBasicBlock::iterator &MII, 1157 int Idx, unsigned PhysReg, int StackSlot, 1158 const TargetRegisterClass *RC, 1159 bool isAvailable, MachineInstr *&LastStore, 1160 AvailableSpills &Spills, 1161 SmallSet<MachineInstr*, 4> &ReMatDefs, 1162 BitVector &RegKills, 1163 std::vector<MachineOperand*> &KillOps, 1164 VirtRegMap &VRM) { 1165 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC); 1166 MachineInstr *StoreMI = next(MII); 1167 VRM.addSpillSlotUse(StackSlot, StoreMI); 1168 DOUT << "Store:\t" << *StoreMI; 1169 1170 // If there is a dead store to this stack slot, nuke it now. 1171 if (LastStore) { 1172 DOUT << "Removed dead store:\t" << *LastStore; 1173 ++NumDSE; 1174 SmallVector<unsigned, 2> KillRegs; 1175 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs); 1176 MachineBasicBlock::iterator PrevMII = LastStore; 1177 bool CheckDef = PrevMII != MBB.begin(); 1178 if (CheckDef) 1179 --PrevMII; 1180 VRM.RemoveMachineInstrFromMaps(LastStore); 1181 MBB.erase(LastStore); 1182 if (CheckDef) { 1183 // Look at defs of killed registers on the store. Mark the defs 1184 // as dead since the store has been deleted and they aren't 1185 // being reused. 1186 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) { 1187 bool HasOtherDef = false; 1188 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) { 1189 MachineInstr *DeadDef = PrevMII; 1190 if (ReMatDefs.count(DeadDef) && !HasOtherDef) { 1191 // FIXME: This assumes a remat def does not have side 1192 // effects. 1193 VRM.RemoveMachineInstrFromMaps(DeadDef); 1194 MBB.erase(DeadDef); 1195 ++NumDRM; 1196 } 1197 } 1198 } 1199 } 1200 } 1201 1202 LastStore = next(MII); 1203 1204 // If the stack slot value was previously available in some other 1205 // register, change it now. Otherwise, make the register available, 1206 // in PhysReg. 1207 Spills.ModifyStackSlotOrReMat(StackSlot); 1208 Spills.ClobberPhysReg(PhysReg); 1209 Spills.addAvailable(StackSlot, PhysReg, isAvailable); 1210 ++NumStores; 1211} 1212 1213/// TransferDeadness - A identity copy definition is dead and it's being 1214/// removed. Find the last def or use and mark it as dead / kill. 1215void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist, 1216 unsigned Reg, BitVector &RegKills, 1217 std::vector<MachineOperand*> &KillOps) { 1218 int LastUDDist = -1; 1219 MachineInstr *LastUDMI = NULL; 1220 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg), 1221 RE = RegInfo->reg_end(); RI != RE; ++RI) { 1222 MachineInstr *UDMI = &*RI; 1223 if (UDMI->getParent() != MBB) 1224 continue; 1225 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI); 1226 if (DI == DistanceMap.end() || DI->second > CurDist) 1227 continue; 1228 if ((int)DI->second < LastUDDist) 1229 continue; 1230 LastUDDist = DI->second; 1231 LastUDMI = UDMI; 1232 } 1233 1234 if (LastUDMI) { 1235 const TargetInstrDesc &TID = LastUDMI->getDesc(); 1236 MachineOperand *LastUD = NULL; 1237 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) { 1238 MachineOperand &MO = LastUDMI->getOperand(i); 1239 if (!MO.isReg() || MO.getReg() != Reg) 1240 continue; 1241 if (!LastUD || (LastUD->isUse() && MO.isDef())) 1242 LastUD = &MO; 1243 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) 1244 return; 1245 } 1246 if (LastUD->isDef()) 1247 LastUD->setIsDead(); 1248 else { 1249 LastUD->setIsKill(); 1250 RegKills.set(Reg); 1251 KillOps[Reg] = LastUD; 1252 } 1253 } 1254} 1255 1256/// rewriteMBB - Keep track of which spills are available even after the 1257/// register allocator is done with them. If possible, avid reloading vregs. 1258void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM, 1259 AvailableSpills &Spills) { 1260 DOUT << "\n**** Local spiller rewriting MBB '" 1261 << MBB.getBasicBlock()->getName() << ":\n"; 1262 1263 MachineFunction &MF = *MBB.getParent(); 1264 1265 // MaybeDeadStores - When we need to write a value back into a stack slot, 1266 // keep track of the inserted store. If the stack slot value is never read 1267 // (because the value was used from some available register, for example), and 1268 // subsequently stored to, the original store is dead. This map keeps track 1269 // of inserted stores that are not used. If we see a subsequent store to the 1270 // same stack slot, the original store is deleted. 1271 std::vector<MachineInstr*> MaybeDeadStores; 1272 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL); 1273 1274 // ReMatDefs - These are rematerializable def MIs which are not deleted. 1275 SmallSet<MachineInstr*, 4> ReMatDefs; 1276 1277 // Keep track of kill information. 1278 BitVector RegKills(TRI->getNumRegs()); 1279 std::vector<MachineOperand*> KillOps; 1280 KillOps.resize(TRI->getNumRegs(), NULL); 1281 1282 unsigned Dist = 0; 1283 DistanceMap.clear(); 1284 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 1285 MII != E; ) { 1286 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 1287 1288 VirtRegMap::MI2VirtMapTy::const_iterator I, End; 1289 bool Erased = false; 1290 bool BackTracked = false; 1291 if (PrepForUnfoldOpti(MBB, MII, 1292 MaybeDeadStores, Spills, RegKills, KillOps, VRM)) 1293 NextMII = next(MII); 1294 1295 MachineInstr &MI = *MII; 1296 const TargetInstrDesc &TID = MI.getDesc(); 1297 1298 if (VRM.hasEmergencySpills(&MI)) { 1299 // Spill physical register(s) in the rare case the allocator has run out 1300 // of registers to allocate. 1301 SmallSet<int, 4> UsedSS; 1302 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI); 1303 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) { 1304 unsigned PhysReg = EmSpills[i]; 1305 const TargetRegisterClass *RC = 1306 TRI->getPhysicalRegisterRegClass(PhysReg); 1307 assert(RC && "Unable to determine register class!"); 1308 int SS = VRM.getEmergencySpillSlot(RC); 1309 if (UsedSS.count(SS)) 1310 assert(0 && "Need to spill more than one physical registers!"); 1311 UsedSS.insert(SS); 1312 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC); 1313 MachineInstr *StoreMI = prior(MII); 1314 VRM.addSpillSlotUse(SS, StoreMI); 1315 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC); 1316 MachineInstr *LoadMI = next(MII); 1317 VRM.addSpillSlotUse(SS, LoadMI); 1318 ++NumPSpills; 1319 } 1320 NextMII = next(MII); 1321 } 1322 1323 // Insert restores here if asked to. 1324 if (VRM.isRestorePt(&MI)) { 1325 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI); 1326 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) { 1327 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. 1328 if (!VRM.getPreSplitReg(VirtReg)) 1329 continue; // Split interval spilled again. 1330 unsigned Phys = VRM.getPhys(VirtReg); 1331 RegInfo->setPhysRegUsed(Phys); 1332 1333 // Check if the value being restored if available. If so, it must be 1334 // from a predecessor BB that fallthrough into this BB. We do not 1335 // expect: 1336 // BB1: 1337 // r1 = load fi#1 1338 // ... 1339 // = r1<kill> 1340 // ... # r1 not clobbered 1341 // ... 1342 // = load fi#1 1343 bool DoReMat = VRM.isReMaterialized(VirtReg); 1344 int SSorRMId = DoReMat 1345 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1346 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1347 assert((!InReg || !RegKills[InReg]) && 1348 "Restoring a value that's previously defined in the same BB?"); 1349 if (InReg == Phys) { 1350 // If the value is already available in the expected register, save 1351 // a reload / remat. 1352 if (SSorRMId) 1353 DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; 1354 else 1355 DOUT << "Reusing SS#" << SSorRMId; 1356 DOUT << " from physreg " 1357 << TRI->getName(InReg) << " for vreg" 1358 << VirtReg <<" instead of reloading into physreg " 1359 << TRI->getName(Phys) << "\n"; 1360 ++NumOmitted; 1361 continue; 1362 } else if (InReg && InReg != Phys) { 1363 if (SSorRMId) 1364 DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1; 1365 else 1366 DOUT << "Reusing SS#" << SSorRMId; 1367 DOUT << " from physreg " 1368 << TRI->getName(InReg) << " for vreg" 1369 << VirtReg <<" by copying it into physreg " 1370 << TRI->getName(Phys) << "\n"; 1371 1372 // If the reloaded / remat value is available in another register, 1373 // copy it to the desired register. 1374 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1375 TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC); 1376 1377 // This invalidates Phys. 1378 Spills.ClobberPhysReg(Phys); 1379 // Remember it's available. 1380 Spills.addAvailable(SSorRMId, Phys); 1381 1382 // Mark is killed. 1383 MachineInstr *CopyMI = prior(MII); 1384 MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg); 1385 KillOpnd->setIsKill(); 1386 UpdateKills(*CopyMI, RegKills, KillOps, TRI); 1387 1388 DOUT << '\t' << *CopyMI; 1389 ++NumCopified; 1390 continue; 1391 } 1392 1393 if (VRM.isReMaterialized(VirtReg)) { 1394 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM); 1395 } else { 1396 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1397 TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC); 1398 MachineInstr *LoadMI = prior(MII); 1399 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1400 ++NumLoads; 1401 } 1402 1403 // This invalidates Phys. 1404 Spills.ClobberPhysReg(Phys); 1405 // Remember it's available. 1406 Spills.addAvailable(SSorRMId, Phys); 1407 1408 UpdateKills(*prior(MII), RegKills, KillOps, TRI); 1409 DOUT << '\t' << *prior(MII); 1410 } 1411 } 1412 1413 // Insert spills here if asked to. 1414 if (VRM.isSpillPt(&MI)) { 1415 std::vector<std::pair<unsigned,bool> > &SpillRegs = 1416 VRM.getSpillPtSpills(&MI); 1417 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) { 1418 unsigned VirtReg = SpillRegs[i].first; 1419 bool isKill = SpillRegs[i].second; 1420 if (!VRM.getPreSplitReg(VirtReg)) 1421 continue; // Split interval spilled again. 1422 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1423 unsigned Phys = VRM.getPhys(VirtReg); 1424 int StackSlot = VRM.getStackSlot(VirtReg); 1425 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC); 1426 MachineInstr *StoreMI = next(MII); 1427 VRM.addSpillSlotUse(StackSlot, StoreMI); 1428 DOUT << "Store:\t" << *StoreMI; 1429 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod); 1430 } 1431 NextMII = next(MII); 1432 } 1433 1434 /// ReusedOperands - Keep track of operand reuse in case we need to undo 1435 /// reuse. 1436 ReuseInfo ReusedOperands(MI, TRI); 1437 SmallVector<unsigned, 4> VirtUseOps; 1438 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1439 MachineOperand &MO = MI.getOperand(i); 1440 if (!MO.isReg() || MO.getReg() == 0) 1441 continue; // Ignore non-register operands. 1442 1443 unsigned VirtReg = MO.getReg(); 1444 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { 1445 // Ignore physregs for spilling, but remember that it is used by this 1446 // function. 1447 RegInfo->setPhysRegUsed(VirtReg); 1448 continue; 1449 } 1450 1451 // We want to process implicit virtual register uses first. 1452 if (MO.isImplicit()) 1453 // If the virtual register is implicitly defined, emit a implicit_def 1454 // before so scavenger knows it's "defined". 1455 VirtUseOps.insert(VirtUseOps.begin(), i); 1456 else 1457 VirtUseOps.push_back(i); 1458 } 1459 1460 // Process all of the spilled uses and all non spilled reg references. 1461 SmallVector<int, 2> PotentialDeadStoreSlots; 1462 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) { 1463 unsigned i = VirtUseOps[j]; 1464 MachineOperand &MO = MI.getOperand(i); 1465 unsigned VirtReg = MO.getReg(); 1466 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 1467 "Not a virtual register?"); 1468 1469 unsigned SubIdx = MO.getSubReg(); 1470 if (VRM.isAssignedReg(VirtReg)) { 1471 // This virtual register was assigned a physreg! 1472 unsigned Phys = VRM.getPhys(VirtReg); 1473 RegInfo->setPhysRegUsed(Phys); 1474 if (MO.isDef()) 1475 ReusedOperands.markClobbered(Phys); 1476 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; 1477 MI.getOperand(i).setReg(RReg); 1478 if (VRM.isImplicitlyDefined(VirtReg)) 1479 BuildMI(MBB, &MI, MI.getDebugLoc(), 1480 TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg); 1481 continue; 1482 } 1483 1484 // This virtual register is now known to be a spilled value. 1485 if (!MO.isUse()) 1486 continue; // Handle defs in the loop below (handle use&def here though) 1487 1488 bool DoReMat = VRM.isReMaterialized(VirtReg); 1489 int SSorRMId = DoReMat 1490 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg); 1491 int ReuseSlot = SSorRMId; 1492 1493 // Check to see if this stack slot is available. 1494 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId); 1495 1496 // If this is a sub-register use, make sure the reuse register is in the 1497 // right register class. For example, for x86 not all of the 32-bit 1498 // registers have accessible sub-registers. 1499 // Similarly so for EXTRACT_SUBREG. Consider this: 1500 // EDI = op 1501 // MOV32_mr fi#1, EDI 1502 // ... 1503 // = EXTRACT_SUBREG fi#1 1504 // fi#1 is available in EDI, but it cannot be reused because it's not in 1505 // the right register file. 1506 if (PhysReg && 1507 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) { 1508 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1509 if (!RC->contains(PhysReg)) 1510 PhysReg = 0; 1511 } 1512 1513 if (PhysReg) { 1514 // This spilled operand might be part of a two-address operand. If this 1515 // is the case, then changing it will necessarily require changing the 1516 // def part of the instruction as well. However, in some cases, we 1517 // aren't allowed to modify the reused register. If none of these cases 1518 // apply, reuse it. 1519 bool CanReuse = true; 1520 int ti = TID.getOperandConstraint(i, TOI::TIED_TO); 1521 if (ti != -1 && 1522 MI.getOperand(ti).isReg() && 1523 MI.getOperand(ti).getReg() == VirtReg) { 1524 // Okay, we have a two address operand. We can reuse this physreg as 1525 // long as we are allowed to clobber the value and there isn't an 1526 // earlier def that has already clobbered the physreg. 1527 CanReuse = Spills.canClobberPhysReg(ReuseSlot) && 1528 !ReusedOperands.isClobbered(PhysReg); 1529 } 1530 1531 if (CanReuse) { 1532 // If this stack slot value is already available, reuse it! 1533 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1534 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1535 else 1536 DOUT << "Reusing SS#" << ReuseSlot; 1537 DOUT << " from physreg " 1538 << TRI->getName(PhysReg) << " for vreg" 1539 << VirtReg <<" instead of reloading into physreg " 1540 << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; 1541 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1542 MI.getOperand(i).setReg(RReg); 1543 1544 // The only technical detail we have is that we don't know that 1545 // PhysReg won't be clobbered by a reloaded stack slot that occurs 1546 // later in the instruction. In particular, consider 'op V1, V2'. 1547 // If V1 is available in physreg R0, we would choose to reuse it 1548 // here, instead of reloading it into the register the allocator 1549 // indicated (say R1). However, V2 might have to be reloaded 1550 // later, and it might indicate that it needs to live in R0. When 1551 // this occurs, we need to have information available that 1552 // indicates it is safe to use R1 for the reload instead of R0. 1553 // 1554 // To further complicate matters, we might conflict with an alias, 1555 // or R0 and R1 might not be compatible with each other. In this 1556 // case, we actually insert a reload for V1 in R1, ensuring that 1557 // we can get at R0 or its alias. 1558 ReusedOperands.addReuse(i, ReuseSlot, PhysReg, 1559 VRM.getPhys(VirtReg), VirtReg); 1560 if (ti != -1) 1561 // Only mark it clobbered if this is a use&def operand. 1562 ReusedOperands.markClobbered(PhysReg); 1563 ++NumReused; 1564 1565 if (MI.getOperand(i).isKill() && 1566 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) { 1567 1568 // The store of this spilled value is potentially dead, but we 1569 // won't know for certain until we've confirmed that the re-use 1570 // above is valid, which means waiting until the other operands 1571 // are processed. For now we just track the spill slot, we'll 1572 // remove it after the other operands are processed if valid. 1573 1574 PotentialDeadStoreSlots.push_back(ReuseSlot); 1575 } 1576 continue; 1577 } // CanReuse 1578 1579 // Otherwise we have a situation where we have a two-address instruction 1580 // whose mod/ref operand needs to be reloaded. This reload is already 1581 // available in some register "PhysReg", but if we used PhysReg as the 1582 // operand to our 2-addr instruction, the instruction would modify 1583 // PhysReg. This isn't cool if something later uses PhysReg and expects 1584 // to get its initial value. 1585 // 1586 // To avoid this problem, and to avoid doing a load right after a store, 1587 // we emit a copy from PhysReg into the designated register for this 1588 // operand. 1589 unsigned DesignatedReg = VRM.getPhys(VirtReg); 1590 assert(DesignatedReg && "Must map virtreg to physreg!"); 1591 1592 // Note that, if we reused a register for a previous operand, the 1593 // register we want to reload into might not actually be 1594 // available. If this occurs, use the register indicated by the 1595 // reuser. 1596 if (ReusedOperands.hasReuses()) 1597 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 1598 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1599 1600 // If the mapped designated register is actually the physreg we have 1601 // incoming, we don't need to inserted a dead copy. 1602 if (DesignatedReg == PhysReg) { 1603 // If this stack slot value is already available, reuse it! 1604 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT) 1605 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; 1606 else 1607 DOUT << "Reusing SS#" << ReuseSlot; 1608 DOUT << " from physreg " << TRI->getName(PhysReg) 1609 << " for vreg" << VirtReg 1610 << " instead of reloading into same physreg.\n"; 1611 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1612 MI.getOperand(i).setReg(RReg); 1613 ReusedOperands.markClobbered(RReg); 1614 ++NumReused; 1615 continue; 1616 } 1617 1618 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1619 RegInfo->setPhysRegUsed(DesignatedReg); 1620 ReusedOperands.markClobbered(DesignatedReg); 1621 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); 1622 1623 MachineInstr *CopyMI = prior(MII); 1624 UpdateKills(*CopyMI, RegKills, KillOps, TRI); 1625 1626 // This invalidates DesignatedReg. 1627 Spills.ClobberPhysReg(DesignatedReg); 1628 1629 Spills.addAvailable(ReuseSlot, DesignatedReg); 1630 unsigned RReg = 1631 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; 1632 MI.getOperand(i).setReg(RReg); 1633 DOUT << '\t' << *prior(MII); 1634 ++NumReused; 1635 continue; 1636 } // if (PhysReg) 1637 1638 // Otherwise, reload it and remember that we have it. 1639 PhysReg = VRM.getPhys(VirtReg); 1640 assert(PhysReg && "Must map virtreg to physreg!"); 1641 1642 // Note that, if we reused a register for a previous operand, the 1643 // register we want to reload into might not actually be 1644 // available. If this occurs, use the register indicated by the 1645 // reuser. 1646 if (ReusedOperands.hasReuses()) 1647 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1648 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1649 1650 RegInfo->setPhysRegUsed(PhysReg); 1651 ReusedOperands.markClobbered(PhysReg); 1652 if (DoReMat) { 1653 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM); 1654 } else { 1655 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); 1656 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC); 1657 MachineInstr *LoadMI = prior(MII); 1658 VRM.addSpillSlotUse(SSorRMId, LoadMI); 1659 ++NumLoads; 1660 } 1661 // This invalidates PhysReg. 1662 Spills.ClobberPhysReg(PhysReg); 1663 1664 // Any stores to this stack slot are not dead anymore. 1665 if (!DoReMat) 1666 MaybeDeadStores[SSorRMId] = NULL; 1667 Spills.addAvailable(SSorRMId, PhysReg); 1668 // Assumes this is the last use. IsKill will be unset if reg is reused 1669 // unless it's a two-address operand. 1670 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) 1671 MI.getOperand(i).setIsKill(); 1672 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1673 MI.getOperand(i).setReg(RReg); 1674 UpdateKills(*prior(MII), RegKills, KillOps, TRI); 1675 DOUT << '\t' << *prior(MII); 1676 } 1677 1678 // Ok - now we can remove stores that have been confirmed dead. 1679 for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) { 1680 // This was the last use and the spilled value is still available 1681 // for reuse. That means the spill was unnecessary! 1682 int PDSSlot = PotentialDeadStoreSlots[j]; 1683 MachineInstr* DeadStore = MaybeDeadStores[PDSSlot]; 1684 if (DeadStore) { 1685 DOUT << "Removed dead store:\t" << *DeadStore; 1686 InvalidateKills(*DeadStore, RegKills, KillOps); 1687 VRM.RemoveMachineInstrFromMaps(DeadStore); 1688 MBB.erase(DeadStore); 1689 MaybeDeadStores[PDSSlot] = NULL; 1690 ++NumDSE; 1691 } 1692 } 1693 1694 1695 DOUT << '\t' << MI; 1696 1697 1698 // If we have folded references to memory operands, make sure we clear all 1699 // physical registers that may contain the value of the spilled virtual 1700 // register 1701 SmallSet<int, 2> FoldedSS; 1702 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) { 1703 unsigned VirtReg = I->second.first; 1704 VirtRegMap::ModRef MR = I->second.second; 1705 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR; 1706 1707 // MI2VirtMap be can updated which invalidate the iterator. 1708 // Increment the iterator first. 1709 ++I; 1710 int SS = VRM.getStackSlot(VirtReg); 1711 if (SS == VirtRegMap::NO_STACK_SLOT) 1712 continue; 1713 FoldedSS.insert(SS); 1714 DOUT << " - StackSlot: " << SS << "\n"; 1715 1716 // If this folded instruction is just a use, check to see if it's a 1717 // straight load from the virt reg slot. 1718 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) { 1719 int FrameIdx; 1720 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx); 1721 if (DestReg && FrameIdx == SS) { 1722 // If this spill slot is available, turn it into a copy (or nothing) 1723 // instead of leaving it as a load! 1724 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) { 1725 DOUT << "Promoted Load To Copy: " << MI; 1726 if (DestReg != InReg) { 1727 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1728 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC); 1729 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg); 1730 unsigned SubIdx = DefMO->getSubReg(); 1731 // Revisit the copy so we make sure to notice the effects of the 1732 // operation on the destreg (either needing to RA it if it's 1733 // virtual or needing to clobber any values if it's physical). 1734 NextMII = &MI; 1735 --NextMII; // backtrack to the copy. 1736 // Propagate the sub-register index over. 1737 if (SubIdx) { 1738 DefMO = NextMII->findRegisterDefOperand(DestReg); 1739 DefMO->setSubReg(SubIdx); 1740 } 1741 BackTracked = true; 1742 } else { 1743 DOUT << "Removing now-noop copy: " << MI; 1744 // Unset last kill since it's being reused. 1745 InvalidateKill(InReg, RegKills, KillOps); 1746 } 1747 1748 InvalidateKills(MI, RegKills, KillOps); 1749 VRM.RemoveMachineInstrFromMaps(&MI); 1750 MBB.erase(&MI); 1751 Erased = true; 1752 goto ProcessNextInst; 1753 } 1754 } else { 1755 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1756 SmallVector<MachineInstr*, 4> NewMIs; 1757 if (PhysReg && 1758 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) { 1759 MBB.insert(MII, NewMIs[0]); 1760 InvalidateKills(MI, RegKills, KillOps); 1761 VRM.RemoveMachineInstrFromMaps(&MI); 1762 MBB.erase(&MI); 1763 Erased = true; 1764 --NextMII; // backtrack to the unfolded instruction. 1765 BackTracked = true; 1766 goto ProcessNextInst; 1767 } 1768 } 1769 } 1770 1771 // If this reference is not a use, any previous store is now dead. 1772 // Otherwise, the store to this stack slot is not dead anymore. 1773 MachineInstr* DeadStore = MaybeDeadStores[SS]; 1774 if (DeadStore) { 1775 bool isDead = !(MR & VirtRegMap::isRef); 1776 MachineInstr *NewStore = NULL; 1777 if (MR & VirtRegMap::isModRef) { 1778 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); 1779 SmallVector<MachineInstr*, 4> NewMIs; 1780 // We can reuse this physreg as long as we are allowed to clobber 1781 // the value and there isn't an earlier def that has already clobbered 1782 // the physreg. 1783 if (PhysReg && 1784 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable! 1785 MachineOperand *KillOpnd = 1786 DeadStore->findRegisterUseOperand(PhysReg, true); 1787 // Note, if the store is storing a sub-register, it's possible the 1788 // super-register is needed below. 1789 if (KillOpnd && !KillOpnd->getSubReg() && 1790 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ 1791 MBB.insert(MII, NewMIs[0]); 1792 NewStore = NewMIs[1]; 1793 MBB.insert(MII, NewStore); 1794 VRM.addSpillSlotUse(SS, NewStore); 1795 InvalidateKills(MI, RegKills, KillOps); 1796 VRM.RemoveMachineInstrFromMaps(&MI); 1797 MBB.erase(&MI); 1798 Erased = true; 1799 --NextMII; 1800 --NextMII; // backtrack to the unfolded instruction. 1801 BackTracked = true; 1802 isDead = true; 1803 } 1804 } 1805 } 1806 1807 if (isDead) { // Previous store is dead. 1808 // If we get here, the store is dead, nuke it now. 1809 DOUT << "Removed dead store:\t" << *DeadStore; 1810 InvalidateKills(*DeadStore, RegKills, KillOps); 1811 VRM.RemoveMachineInstrFromMaps(DeadStore); 1812 MBB.erase(DeadStore); 1813 if (!NewStore) 1814 ++NumDSE; 1815 } 1816 1817 MaybeDeadStores[SS] = NULL; 1818 if (NewStore) { 1819 // Treat this store as a spill merged into a copy. That makes the 1820 // stack slot value available. 1821 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod); 1822 goto ProcessNextInst; 1823 } 1824 } 1825 1826 // If the spill slot value is available, and this is a new definition of 1827 // the value, the value is not available anymore. 1828 if (MR & VirtRegMap::isMod) { 1829 // Notice that the value in this stack slot has been modified. 1830 Spills.ModifyStackSlotOrReMat(SS); 1831 1832 // If this is *just* a mod of the value, check to see if this is just a 1833 // store to the spill slot (i.e. the spill got merged into the copy). If 1834 // so, realize that the vreg is available now, and add the store to the 1835 // MaybeDeadStore info. 1836 int StackSlot; 1837 if (!(MR & VirtRegMap::isRef)) { 1838 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { 1839 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1840 "Src hasn't been allocated yet?"); 1841 1842 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot, 1843 RegKills, KillOps, TRI, VRM)) { 1844 NextMII = next(MII); 1845 BackTracked = true; 1846 goto ProcessNextInst; 1847 } 1848 1849 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark 1850 // this as a potentially dead store in case there is a subsequent 1851 // store into the stack slot without a read from it. 1852 MaybeDeadStores[StackSlot] = &MI; 1853 1854 // If the stack slot value was previously available in some other 1855 // register, change it now. Otherwise, make the register 1856 // available in PhysReg. 1857 Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/); 1858 } 1859 } 1860 } 1861 } 1862 1863 // Process all of the spilled defs. 1864 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1865 MachineOperand &MO = MI.getOperand(i); 1866 if (!(MO.isReg() && MO.getReg() && MO.isDef())) 1867 continue; 1868 1869 unsigned VirtReg = MO.getReg(); 1870 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { 1871 // Check to see if this is a noop copy. If so, eliminate the 1872 // instruction before considering the dest reg to be changed. 1873 unsigned Src, Dst, SrcSR, DstSR; 1874 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { 1875 ++NumDCE; 1876 DOUT << "Removing now-noop copy: " << MI; 1877 SmallVector<unsigned, 2> KillRegs; 1878 InvalidateKills(MI, RegKills, KillOps, &KillRegs); 1879 if (MO.isDead() && !KillRegs.empty()) { 1880 // Source register or an implicit super/sub-register use is killed. 1881 assert(KillRegs[0] == Dst || 1882 TRI->isSubRegister(KillRegs[0], Dst) || 1883 TRI->isSuperRegister(KillRegs[0], Dst)); 1884 // Last def is now dead. 1885 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps); 1886 } 1887 VRM.RemoveMachineInstrFromMaps(&MI); 1888 MBB.erase(&MI); 1889 Erased = true; 1890 Spills.disallowClobberPhysReg(VirtReg); 1891 goto ProcessNextInst; 1892 } 1893 1894 // If it's not a no-op copy, it clobbers the value in the destreg. 1895 Spills.ClobberPhysReg(VirtReg); 1896 ReusedOperands.markClobbered(VirtReg); 1897 1898 // Check to see if this instruction is a load from a stack slot into 1899 // a register. If so, this provides the stack slot value in the reg. 1900 int FrameIdx; 1901 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) { 1902 assert(DestReg == VirtReg && "Unknown load situation!"); 1903 1904 // If it is a folded reference, then it's not safe to clobber. 1905 bool Folded = FoldedSS.count(FrameIdx); 1906 // Otherwise, if it wasn't available, remember that it is now! 1907 Spills.addAvailable(FrameIdx, DestReg, !Folded); 1908 goto ProcessNextInst; 1909 } 1910 1911 continue; 1912 } 1913 1914 unsigned SubIdx = MO.getSubReg(); 1915 bool DoReMat = VRM.isReMaterialized(VirtReg); 1916 if (DoReMat) 1917 ReMatDefs.insert(&MI); 1918 1919 // The only vregs left are stack slot definitions. 1920 int StackSlot = VRM.getStackSlot(VirtReg); 1921 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg); 1922 1923 // If this def is part of a two-address operand, make sure to execute 1924 // the store from the correct physical register. 1925 unsigned PhysReg; 1926 int TiedOp = MI.getDesc().findTiedToSrcOperand(i); 1927 if (TiedOp != -1) { 1928 PhysReg = MI.getOperand(TiedOp).getReg(); 1929 if (SubIdx) { 1930 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); 1931 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && 1932 "Can't find corresponding super-register!"); 1933 PhysReg = SuperReg; 1934 } 1935 } else { 1936 PhysReg = VRM.getPhys(VirtReg); 1937 if (ReusedOperands.isClobbered(PhysReg)) { 1938 // Another def has taken the assigned physreg. It must have been a 1939 // use&def which got it due to reuse. Undo the reuse! 1940 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 1941 Spills, MaybeDeadStores, RegKills, KillOps, VRM); 1942 } 1943 } 1944 1945 assert(PhysReg && "VR not assigned a physical register?"); 1946 RegInfo->setPhysRegUsed(PhysReg); 1947 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; 1948 ReusedOperands.markClobbered(RReg); 1949 MI.getOperand(i).setReg(RReg); 1950 1951 if (!MO.isDead()) { 1952 MachineInstr *&LastStore = MaybeDeadStores[StackSlot]; 1953 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true, 1954 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM); 1955 NextMII = next(MII); 1956 1957 // Check to see if this is a noop copy. If so, eliminate the 1958 // instruction before considering the dest reg to be changed. 1959 { 1960 unsigned Src, Dst, SrcSR, DstSR; 1961 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { 1962 ++NumDCE; 1963 DOUT << "Removing now-noop copy: " << MI; 1964 InvalidateKills(MI, RegKills, KillOps); 1965 VRM.RemoveMachineInstrFromMaps(&MI); 1966 MBB.erase(&MI); 1967 Erased = true; 1968 UpdateKills(*LastStore, RegKills, KillOps, TRI); 1969 goto ProcessNextInst; 1970 } 1971 } 1972 } 1973 } 1974 ProcessNextInst: 1975 DistanceMap.insert(std::make_pair(&MI, Dist++)); 1976 if (!Erased && !BackTracked) { 1977 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II) 1978 UpdateKills(*II, RegKills, KillOps, TRI); 1979 } 1980 MII = NextMII; 1981 } 1982 1983} 1984 1985llvm::Spiller* llvm::createSpiller() { 1986 switch (SpillerOpt) { 1987 default: assert(0 && "Unreachable!"); 1988 case local: 1989 return new LocalSpiller(); 1990 case simple: 1991 return new SimpleSpiller(); 1992 } 1993} 1994