AArch64ISelLowering.h revision d622bef31d11a5a6429fe7fad557c9b111e96f69 
1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that AArch64 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
16#define LLVM_TARGET_AARCH64_ISELLOWERING_H
17
18#include "Utils/AArch64BaseInfo.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22#include "llvm/IR/Intrinsics.h"
23
24namespace llvm {
25namespace AArch64ISD {
26  enum NodeType {
27    // Start the numbering from where ISD NodeType finishes.
28    FIRST_NUMBER = ISD::BUILTIN_OP_END,
29
30    // This is a conditional branch which also notes the flag needed
31    // (eq/sgt/...). A64 puts this information on the branches rather than
32    // compares as LLVM does.
33    BR_CC,
34
35    // A node to be selected to an actual call operation: either BL or BLR in
36    // the absence of tail calls.
37    Call,
38
39    // Indicates a floating-point immediate which fits into the format required
40    // by the FMOV instructions. First (and only) operand is the 8-bit encoded
41    // value of that immediate.
42    FPMOV,
43
44    // Corresponds directly to an EXTR instruction. Operands are an LHS an RHS
45    // and an LSB.
46    EXTR,
47
48    // Wraps a load from the GOT, which should always be performed with a 64-bit
49    // load instruction. This prevents the DAG combiner folding a truncate to
50    // form a smaller memory access.
51    GOTLoad,
52
53    // Performs a bitfield insert. Arguments are: the value being inserted into;
54    // the value being inserted; least significant bit changed; width of the
55    // field.
56    BFI,
57
58    // Simply a convenient node inserted during ISelLowering to represent
59    // procedure return. Will almost certainly be selected to "RET".
60    Ret,
61
62    /// Extracts a field of contiguous bits from the source and sign extends
63    /// them into a single register. Arguments are: source; immr; imms. Note
64    /// these are pre-encoded since DAG matching can't cope with combining LSB
65    /// and Width into these values itself.
66    SBFX,
67
68    /// This is an A64-ification of the standard LLVM SELECT_CC operation. The
69    /// main difference is that it only has the values and an A64 condition,
70    /// which will be produced by a setcc instruction.
71    SELECT_CC,
72
73    /// This serves most of the functions of the LLVM SETCC instruction, for two
74    /// purposes. First, it prevents optimisations from fiddling with the
75    /// compare after we've moved the CondCode information onto the SELECT_CC or
76    /// BR_CC instructions. Second, it gives a legal instruction for the actual
77    /// comparison.
78    ///
79    /// It keeps a record of the condition flags asked for because certain
80    /// instructions are only valid for a subset of condition codes.
81    SETCC,
82
83    // Designates a node which is a tail call: both a call and a return
84    // instruction as far as selction is concerned. It should be selected to an
85    // unconditional branch. Has the usual plethora of call operands, but: 1st
86    // is callee, 2nd is stack adjustment required immediately before branch.
87    TC_RETURN,
88
89    // Designates a call used to support the TLS descriptor ABI. The call itself
90    // will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall
91    // var") must be attached somehow during code generation. It takes two
92    // operands: the callee and the symbol to be relocated against.
93    TLSDESCCALL,
94
95    // Leaf node which will be lowered to an appropriate MRS to obtain the
96    // thread pointer: TPIDR_EL0.
97    THREAD_POINTER,
98
99    /// Extracts a field of contiguous bits from the source and zero extends
100    /// them into a single register. Arguments are: source; immr; imms. Note
101    /// these are pre-encoded since DAG matching can't cope with combining LSB
102    /// and Width into these values itself.
103    UBFX,
104
105    // Wraps an address which the ISelLowering phase has decided should be
106    // created using the large memory model style: i.e. a sequence of four
107    // movz/movk instructions.
108    WrapperLarge,
109
110    // Wraps an address which the ISelLowering phase has decided should be
111    // created using the small memory model style: i.e. adrp/add or
112    // adrp/mem-op. This exists to prevent bare TargetAddresses which may never
113    // get selected.
114    WrapperSmall,
115
116    // Vector bitwise select
117    NEON_BSL,
118
119    // Vector move immediate
120    NEON_MOVIMM,
121
122    // Vector Move Inverted Immediate
123    NEON_MVNIMM,
124
125    // Vector FP move immediate
126    NEON_FMOVIMM,
127
128    // Vector compare
129    NEON_CMP,
130
131    // Vector compare zero
132    NEON_CMPZ,
133
134    // Vector compare bitwise test
135    NEON_TST,
136
137    // Operation for the immediate in vector shift
138    NEON_DUPIMM,
139
140    // Vector saturating shift
141    NEON_QSHLs,
142    NEON_QSHLu,
143
144    // Vector dup by lane
145    NEON_VDUPLANE
146  };
147}
148
149
150class AArch64Subtarget;
151class AArch64TargetMachine;
152
153class AArch64TargetLowering : public TargetLowering {
154public:
155  explicit AArch64TargetLowering(AArch64TargetMachine &TM);
156
157  const char *getTargetNodeName(unsigned Opcode) const;
158
159  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
160
161  SDValue LowerFormalArguments(SDValue Chain,
162                               CallingConv::ID CallConv, bool isVarArg,
163                               const SmallVectorImpl<ISD::InputArg> &Ins,
164                               SDLoc dl, SelectionDAG &DAG,
165                               SmallVectorImpl<SDValue> &InVals) const;
166
167  SDValue LowerReturn(SDValue Chain,
168                      CallingConv::ID CallConv, bool isVarArg,
169                      const SmallVectorImpl<ISD::OutputArg> &Outs,
170                      const SmallVectorImpl<SDValue> &OutVals,
171                      SDLoc dl, SelectionDAG &DAG) const;
172
173  SDValue LowerCall(CallLoweringInfo &CLI,
174                    SmallVectorImpl<SDValue> &InVals) const;
175
176  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
177                          CallingConv::ID CallConv, bool IsVarArg,
178                          const SmallVectorImpl<ISD::InputArg> &Ins,
179                          SDLoc dl, SelectionDAG &DAG,
180                          SmallVectorImpl<SDValue> &InVals) const;
181
182  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
183                            const AArch64Subtarget *ST) const;
184
185  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
186
187  void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
188                           SDValue &Chain) const;
189
190  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
191  /// for tail call optimization. Targets which want to do tail call
192  /// optimization should implement this function.
193  bool IsEligibleForTailCallOptimization(SDValue Callee,
194                                    CallingConv::ID CalleeCC,
195                                    bool IsVarArg,
196                                    bool IsCalleeStructRet,
197                                    bool IsCallerStructRet,
198                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
199                                    const SmallVectorImpl<SDValue> &OutVals,
200                                    const SmallVectorImpl<ISD::InputArg> &Ins,
201                                    SelectionDAG& DAG) const;
202
203  /// Finds the incoming stack arguments which overlap the given fixed stack
204  /// object and incorporates their load into the current chain. This prevents
205  /// an upcoming store from clobbering the stack argument before it's used.
206  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
207                              MachineFrameInfo *MFI, int ClobberedFI) const;
208
209  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
210
211  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
212
213  bool IsTailCallConvention(CallingConv::ID CallCC) const;
214
215  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
216
217  bool isLegalICmpImmediate(int64_t Val) const;
218  SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
219                         SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
220
221  virtual MachineBasicBlock *
222  EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
223
224  MachineBasicBlock *
225  emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
226                   unsigned Size, unsigned Opcode) const;
227
228  MachineBasicBlock *
229  emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
230                         unsigned Size, unsigned CmpOp,
231                         A64CC::CondCodes Cond) const;
232  MachineBasicBlock *
233  emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
234                    unsigned Size) const;
235
236  MachineBasicBlock *
237  EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
238
239  SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
240  SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
241  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
242  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
243  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
244  SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
245                          RTLIB::Libcall Call) const;
246  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
247  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
248  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
249
250  SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const;
251  SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
252  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
253
254  SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
255                           SelectionDAG &DAG) const;
256  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
257  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
258  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
259  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
260  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
261  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
262  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
263  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
264
265  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
266
267  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
268  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
269  /// expanded to FMAs when this method returns true, otherwise fmuladd is
270  /// expanded to fmul + fadd.
271  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
272
273  ConstraintType getConstraintType(const std::string &Constraint) const;
274
275  ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
276                                                  const char *Constraint) const;
277  void LowerAsmOperandForConstraint(SDValue Op,
278                                    std::string &Constraint,
279                                    std::vector<SDValue> &Ops,
280                                    SelectionDAG &DAG) const;
281
282  std::pair<unsigned, const TargetRegisterClass*>
283  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
284
285  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
286                                  unsigned Intrinsic) const LLVM_OVERRIDE;
287
288private:
289  const InstrItineraryData *Itins;
290
291  const AArch64Subtarget *getSubtarget() const {
292    return &getTargetMachine().getSubtarget<AArch64Subtarget>();
293  }
294};
295enum NeonModImmType {
296  Neon_Mov_Imm,
297  Neon_Mvn_Imm
298};
299} // namespace llvm
300
301#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H
302