| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| f04a4d74b86733b853b7445ab6d5a3bde025a30d |
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08-Dec-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r196456:
------------------------------------------------------------------------
r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines
For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 8a0ff1f236e77214878c9d493e786b30656ad2a1 |
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26-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195716:
------------------------------------------------------------------------
r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines
Refactored the implementation of AArch64 NEON instruction ZIP, UZP
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 36c7806f4eacd676932ba630246f88e0e37b1cd4 |
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19-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 97577757c6dc84233ad10cd432664257e593e76d |
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18-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| a08063a000cfc7499f08a472d85f14e7a5e90f8d |
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14-Nov-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 258115258f8fe15e9d74b5fb524f90b75bb917d1 |
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06-Nov-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 591c2f738a3e12026ff5504a486d54fc21fb3049 |
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05-Nov-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 160a14e2b1b3bfd2bd67cb03a7ae213fb35211cc |
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29-Oct-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
[AArch64] Implement FrameAddr and ReturnAddr
Fixes PR17690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 767f816b926376bd850a62a28d35343ad0559c91 |
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11-Oct-2013 |
Kevin Qin <Kevin.Qin@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (copy).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 6a5a667517160ca1b557002a29d08868ae029451 |
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10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 812ddcc50f8bc3ec6ce115863ff2263815906aaf |
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10-Oct-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| d622bef31d11a5a6429fe7fad557c9b111e96f69 |
|
10-Oct-2013 |
Hao Liu <Hao.Liu@arm.com> |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| dd518bcc9dd9e4028b2a979ced09edd5b6becd07 |
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04-Oct-2013 |
Jiangning Liu <jiangning.liu@arm.com> |
Implement aarch64 neon instruction set AdvSIMD (3V elem).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 19fdc268c316b3b0bdcb2b558449819f4f402d6a |
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04-Sep-2013 |
Hao Liu <Hao.Liu@arm.com> |
Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
and 4 convert instructions:
scvtf,ucvtf,fcvtzs,fcvtzu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| d9767021f83879429e930b068d1d6aef22285b33 |
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15-Aug-2013 |
Hao Liu <Hao.Liu@arm.com> |
Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 87773c318fcee853fb34a80a10c4347d523bdafb |
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01-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
AArch64: add initial NEON support
Patch by Ana Pazos.
- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise
- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic
- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same
- Intial implementation of instruction class:
Scalar Arithmetic
- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.
- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| e54885af9b54bfc7436a928a48d3db1ef88a2a70 |
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09-Jul-2013 |
Stephen Lin <stephenwlin@gmail.com> |
AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:
1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.
2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.
3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.
The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 5b3fca50a08865f0db55fc92ad1c037a04e12177 |
|
22-Jun-2013 |
Chad Rosier <mcrosier@apple.com> |
The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 4393f48c03300203594e22d248808f20dd59d886 |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction info and register info objects.
These objects are internal to the TargetMachine object and may change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
|
| 45db92038bf540fbbd8dfe5dff520aa8566d7cef |
|
04-May-2013 |
Tim Northover <Tim.Northover@arm.com> |
AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.
For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| dfe076af9879eb68a7b8331f9c02eecf563d85be |
|
05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
+ 80 column violations.
+ Tab characters.
+ TableGen brace placement.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 19254c49a8752fe8c6fa648a6eb29f20a1f62c8b |
|
05-Feb-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove cyclic dependency in AArch64 libraries
This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
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| 72062f5744557e270a38192554c3126ea5f97434 |
|
31-Jan-2013 |
Tim Northover <Tim.Northover@arm.com> |
Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/AArch64/AArch64ISelLowering.h
|