AArch64ISelLowering.h revision f04a4d74b86733b853b7445ab6d5a3bde025a30d 
1//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that AArch64 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
16#define LLVM_TARGET_AARCH64_ISELLOWERING_H
17
18#include "Utils/AArch64BaseInfo.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22#include "llvm/IR/Intrinsics.h"
23
24namespace llvm {
25namespace AArch64ISD {
26  enum NodeType {
27    // Start the numbering from where ISD NodeType finishes.
28    FIRST_NUMBER = ISD::BUILTIN_OP_END,
29
30    // This is a conditional branch which also notes the flag needed
31    // (eq/sgt/...). A64 puts this information on the branches rather than
32    // compares as LLVM does.
33    BR_CC,
34
35    // A node to be selected to an actual call operation: either BL or BLR in
36    // the absence of tail calls.
37    Call,
38
39    // Indicates a floating-point immediate which fits into the format required
40    // by the FMOV instructions. First (and only) operand is the 8-bit encoded
41    // value of that immediate.
42    FPMOV,
43
44    // Corresponds directly to an EXTR instruction. Operands are an LHS an RHS
45    // and an LSB.
46    EXTR,
47
48    // Wraps a load from the GOT, which should always be performed with a 64-bit
49    // load instruction. This prevents the DAG combiner folding a truncate to
50    // form a smaller memory access.
51    GOTLoad,
52
53    // Performs a bitfield insert. Arguments are: the value being inserted into;
54    // the value being inserted; least significant bit changed; width of the
55    // field.
56    BFI,
57
58    // Simply a convenient node inserted during ISelLowering to represent
59    // procedure return. Will almost certainly be selected to "RET".
60    Ret,
61
62    /// Extracts a field of contiguous bits from the source and sign extends
63    /// them into a single register. Arguments are: source; immr; imms. Note
64    /// these are pre-encoded since DAG matching can't cope with combining LSB
65    /// and Width into these values itself.
66    SBFX,
67
68    /// This is an A64-ification of the standard LLVM SELECT_CC operation. The
69    /// main difference is that it only has the values and an A64 condition,
70    /// which will be produced by a setcc instruction.
71    SELECT_CC,
72
73    /// This serves most of the functions of the LLVM SETCC instruction, for two
74    /// purposes. First, it prevents optimisations from fiddling with the
75    /// compare after we've moved the CondCode information onto the SELECT_CC or
76    /// BR_CC instructions. Second, it gives a legal instruction for the actual
77    /// comparison.
78    ///
79    /// It keeps a record of the condition flags asked for because certain
80    /// instructions are only valid for a subset of condition codes.
81    SETCC,
82
83    // Designates a node which is a tail call: both a call and a return
84    // instruction as far as selction is concerned. It should be selected to an
85    // unconditional branch. Has the usual plethora of call operands, but: 1st
86    // is callee, 2nd is stack adjustment required immediately before branch.
87    TC_RETURN,
88
89    // Designates a call used to support the TLS descriptor ABI. The call itself
90    // will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall
91    // var") must be attached somehow during code generation. It takes two
92    // operands: the callee and the symbol to be relocated against.
93    TLSDESCCALL,
94
95    // Leaf node which will be lowered to an appropriate MRS to obtain the
96    // thread pointer: TPIDR_EL0.
97    THREAD_POINTER,
98
99    /// Extracts a field of contiguous bits from the source and zero extends
100    /// them into a single register. Arguments are: source; immr; imms. Note
101    /// these are pre-encoded since DAG matching can't cope with combining LSB
102    /// and Width into these values itself.
103    UBFX,
104
105    // Wraps an address which the ISelLowering phase has decided should be
106    // created using the large memory model style: i.e. a sequence of four
107    // movz/movk instructions.
108    WrapperLarge,
109
110    // Wraps an address which the ISelLowering phase has decided should be
111    // created using the small memory model style: i.e. adrp/add or
112    // adrp/mem-op. This exists to prevent bare TargetAddresses which may never
113    // get selected.
114    WrapperSmall,
115
116    // Vector bitwise select
117    NEON_BSL,
118
119    // Vector move immediate
120    NEON_MOVIMM,
121
122    // Vector Move Inverted Immediate
123    NEON_MVNIMM,
124
125    // Vector FP move immediate
126    NEON_FMOVIMM,
127
128    // Vector permute
129    NEON_UZP1,
130    NEON_UZP2,
131    NEON_ZIP1,
132    NEON_ZIP2,
133    NEON_TRN1,
134    NEON_TRN2,
135
136    // Vector Element reverse
137    NEON_REV64,
138    NEON_REV32,
139    NEON_REV16,
140
141    // Vector compare
142    NEON_CMP,
143
144    // Vector compare zero
145    NEON_CMPZ,
146
147    // Vector compare bitwise test
148    NEON_TST,
149
150    // Vector saturating shift
151    NEON_QSHLs,
152    NEON_QSHLu,
153
154    // Vector dup
155    NEON_VDUP,
156
157    // Vector dup by lane
158    NEON_VDUPLANE,
159
160    // Vector extract
161    NEON_VEXTRACT,
162
163    // NEON duplicate lane loads
164    NEON_LD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
165    NEON_LD3DUP,
166    NEON_LD4DUP,
167
168    // NEON loads with post-increment base updates:
169    NEON_LD1_UPD,
170    NEON_LD2_UPD,
171    NEON_LD3_UPD,
172    NEON_LD4_UPD,
173    NEON_LD1x2_UPD,
174    NEON_LD1x3_UPD,
175    NEON_LD1x4_UPD,
176
177    // NEON stores with post-increment base updates:
178    NEON_ST1_UPD,
179    NEON_ST2_UPD,
180    NEON_ST3_UPD,
181    NEON_ST4_UPD,
182    NEON_ST1x2_UPD,
183    NEON_ST1x3_UPD,
184    NEON_ST1x4_UPD,
185
186    // NEON duplicate lane loads with post-increment base updates:
187    NEON_LD2DUP_UPD,
188    NEON_LD3DUP_UPD,
189    NEON_LD4DUP_UPD,
190
191    // NEON lane loads with post-increment base updates:
192    NEON_LD2LN_UPD,
193    NEON_LD3LN_UPD,
194    NEON_LD4LN_UPD,
195
196    // NEON lane store with post-increment base updates:
197    NEON_ST2LN_UPD,
198    NEON_ST3LN_UPD,
199    NEON_ST4LN_UPD
200  };
201}
202
203
204class AArch64Subtarget;
205class AArch64TargetMachine;
206
207class AArch64TargetLowering : public TargetLowering {
208public:
209  explicit AArch64TargetLowering(AArch64TargetMachine &TM);
210
211  const char *getTargetNodeName(unsigned Opcode) const;
212
213  CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
214
215  SDValue LowerFormalArguments(SDValue Chain,
216                               CallingConv::ID CallConv, bool isVarArg,
217                               const SmallVectorImpl<ISD::InputArg> &Ins,
218                               SDLoc dl, SelectionDAG &DAG,
219                               SmallVectorImpl<SDValue> &InVals) const;
220
221  SDValue LowerReturn(SDValue Chain,
222                      CallingConv::ID CallConv, bool isVarArg,
223                      const SmallVectorImpl<ISD::OutputArg> &Outs,
224                      const SmallVectorImpl<SDValue> &OutVals,
225                      SDLoc dl, SelectionDAG &DAG) const;
226
227  SDValue LowerCall(CallLoweringInfo &CLI,
228                    SmallVectorImpl<SDValue> &InVals) const;
229
230  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
231                          CallingConv::ID CallConv, bool IsVarArg,
232                          const SmallVectorImpl<ISD::InputArg> &Ins,
233                          SDLoc dl, SelectionDAG &DAG,
234                          SmallVectorImpl<SDValue> &InVals) const;
235
236  bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
237
238  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
239                            const AArch64Subtarget *ST) const;
240
241  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
242
243  void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
244                           SDValue &Chain) const;
245
246  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
247  /// for tail call optimization. Targets which want to do tail call
248  /// optimization should implement this function.
249  bool IsEligibleForTailCallOptimization(SDValue Callee,
250                                    CallingConv::ID CalleeCC,
251                                    bool IsVarArg,
252                                    bool IsCalleeStructRet,
253                                    bool IsCallerStructRet,
254                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
255                                    const SmallVectorImpl<SDValue> &OutVals,
256                                    const SmallVectorImpl<ISD::InputArg> &Ins,
257                                    SelectionDAG& DAG) const;
258
259  /// Finds the incoming stack arguments which overlap the given fixed stack
260  /// object and incorporates their load into the current chain. This prevents
261  /// an upcoming store from clobbering the stack argument before it's used.
262  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
263                              MachineFrameInfo *MFI, int ClobberedFI) const;
264
265  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
266
267  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
268
269  bool IsTailCallConvention(CallingConv::ID CallCC) const;
270
271  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
272
273  bool isLegalICmpImmediate(int64_t Val) const;
274  SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
275                         SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
276
277  virtual MachineBasicBlock *
278  EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
279
280  MachineBasicBlock *
281  emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
282                   unsigned Size, unsigned Opcode) const;
283
284  MachineBasicBlock *
285  emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
286                         unsigned Size, unsigned CmpOp,
287                         A64CC::CondCodes Cond) const;
288  MachineBasicBlock *
289  emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
290                    unsigned Size) const;
291
292  MachineBasicBlock *
293  EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
294
295  SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
296  SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
297  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
298  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
299  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
300  SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
301                          RTLIB::Libcall Call) const;
302  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
303  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
304  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
305  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
306  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
307
308  SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const;
309  SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
310  SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
311
312  SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
313                           SelectionDAG &DAG) const;
314  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
315  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
316  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
317  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
318  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
319  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
320  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
321  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
322
323  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
324
325  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
326  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
327  /// expanded to FMAs when this method returns true, otherwise fmuladd is
328  /// expanded to fmul + fadd.
329  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
330
331  ConstraintType getConstraintType(const std::string &Constraint) const;
332
333  ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
334                                                  const char *Constraint) const;
335  void LowerAsmOperandForConstraint(SDValue Op,
336                                    std::string &Constraint,
337                                    std::vector<SDValue> &Ops,
338                                    SelectionDAG &DAG) const;
339
340  std::pair<unsigned, const TargetRegisterClass*>
341  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
342
343  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
344                                  unsigned Intrinsic) const LLVM_OVERRIDE;
345
346protected:
347  std::pair<const TargetRegisterClass*, uint8_t>
348  findRepresentativeClass(MVT VT) const;
349
350private:
351  const InstrItineraryData *Itins;
352
353  const AArch64Subtarget *getSubtarget() const {
354    return &getTargetMachine().getSubtarget<AArch64Subtarget>();
355  }
356};
357enum NeonModImmType {
358  Neon_Mov_Imm,
359  Neon_Mvn_Imm
360};
361
362extern SDValue ScanBUILD_VECTOR(SDValue Op, bool &isOnlyLowElement,
363                                bool &usesOnlyOneValue, bool &hasDominantValue,
364                                bool &isConstant, bool &isUNDEF);
365} // namespace llvm
366
367#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H
368