ARMBaseRegisterInfo.cpp revision 3dab2778571b5bb00b35a0adcb7011dc85158beb
12cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMAddressingModes.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 17c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMBaseRegisterInfo.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMInstrInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 20c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 21c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Constants.h" 22c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/DerivedTypes.h" 239adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/Function.h" 249adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/LLVMContext.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineLocation.h" 30c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 31c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 323dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 33ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 34dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 35c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetFrameInfo.h" 36c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 37c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/BitVector.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/SmallVector.h" 4018ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach#include "llvm/Support/CommandLine.h" 41c140c4803dc3e10e08138670829bc0494986abe9David Goodwinusing namespace llvm; 42c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 4318ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbachstatic cl::opt<bool> 441d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim GrosbachScavengeFrameIndexVals("arm-virtual-frame-index-vals", cl::Hidden, 451d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach cl::init(false), 461d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach cl::desc("Resolve frame index values via scavenging in PEI")); 471d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach 481d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbachstatic cl::opt<bool> 493229b0bcf1fe5e9381f306ed30c37cec0377395aJim GrosbachReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(false), 5018ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach cl::desc("Reuse repeated frame index values")); 5118ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach 523dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachstatic cl::opt<bool> 533dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachARMDynamicStackAlign("arm-dynamic-stack-alignment", cl::Hidden, cl::init(false), 543dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach cl::desc("Dynamically re-align the stack as needed")); 553dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 56c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng bool *isSPVFP) { 588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = false; 60c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 61c140c4803dc3e10e08138670829bc0494986abe9David Goodwin using namespace ARM; 62c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 63c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 64c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown ARM register!"); 658295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R0: case D0: case Q0: return 0; 668295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R1: case D1: case Q1: return 1; 678295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R2: case D2: case Q2: return 2; 688295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R3: case D3: case Q3: return 3; 698295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R4: case D4: case Q4: return 4; 708295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R5: case D5: case Q5: return 5; 718295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R6: case D6: case Q6: return 6; 728295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R7: case D7: case Q7: return 7; 738295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R8: case D8: case Q8: return 8; 748295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R9: case D9: case Q9: return 9; 758295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R10: case D10: case Q10: return 10; 768295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R11: case D11: case Q11: return 11; 778295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R12: case D12: case Q12: return 12; 788295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case SP: case D13: case Q13: return 13; 798295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case LR: case D14: case Q14: return 14; 808295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case PC: case D15: case Q15: return 15; 818295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng 828295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D16: return 16; 838295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D17: return 17; 848295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D18: return 18; 858295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D19: return 19; 868295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D20: return 20; 878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D21: return 21; 888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D22: return 22; 898295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D23: return 23; 908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D24: return 24; 918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D25: return 25; 928295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D26: return 27; 938295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D27: return 27; 948295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D28: return 28; 958295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D29: return 29; 968295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D30: return 30; 978295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D31: return 31; 98c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 99c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: case S1: case S2: case S3: 100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: case S5: case S6: case S7: 101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: case S9: case S10: case S11: 102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: case S13: case S14: case S15: 103c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: case S17: case S18: case S19: 104c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: case S21: case S22: case S23: 105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: case S25: case S26: case S27: 1068295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case S28: case S29: case S30: case S31: { 1078295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 1088295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = true; 109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: return 0; // Avoid compile time warning. 111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: return 0; 112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S1: return 1; 113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S2: return 2; 114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S3: return 3; 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: return 4; 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S5: return 5; 117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S6: return 6; 118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S7: return 7; 119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: return 8; 120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S9: return 9; 121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S10: return 10; 122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S11: return 11; 123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: return 12; 124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S13: return 13; 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S14: return 14; 126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S15: return 15; 127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: return 16; 128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S17: return 17; 129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S18: return 18; 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S19: return 19; 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: return 20; 132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S21: return 21; 133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S22: return 22; 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S23: return 23; 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: return 24; 136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S25: return 25; 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S26: return 26; 138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S27: return 27; 139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S28: return 28; 140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S29: return 29; 141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S30: return 30; 142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S31: return 31; 143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 145c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 146c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 147c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 148db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 149c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 150c140c4803dc3e10e08138670829bc0494986abe9David Goodwin : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 151c140c4803dc3e10e08138670829bc0494986abe9David Goodwin TII(tii), STI(sti), 152c140c4803dc3e10e08138670829bc0494986abe9David Goodwin FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 153c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 154c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 155c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst unsigned* 156c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned CalleeSavedRegs[] = { 158c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 159c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R7, ARM::R6, ARM::R5, ARM::R4, 160c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 161c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 162c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 164c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned DarwinCalleeSavedRegs[] = { 167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 168c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register. 169c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11, ARM::R10, ARM::R8, 171c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 172c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 173c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 174c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 177c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 178c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 179c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst TargetRegisterClass* const * 180c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 18282b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 18382b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 18482b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 18682b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 18782b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 189c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 190c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 191c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 19282b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 19382b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 19482b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 195c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 19682b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 19782b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 200c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 201c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 20282b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 20382b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 20482b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, 205c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 20682b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 20782b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 208c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 209c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 210c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 211c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 21282b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 21382b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 21482b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::GPRRegClass, &ARM::GPRRegClass, 215c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 21682b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 21782b3c2e40417098f9af0c33150c4b1c66ae1747cJim Grosbach &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 218c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 219c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 220c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 221f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (STI.isThumb1Only()) { 222c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() 223c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 224c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 225c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() 226c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 227c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 228c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 229c140c4803dc3e10e08138670829bc0494986abe9David GoodwinBitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 230c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME: avoid re-calculating this everytime. 231c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 232c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 233c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 234c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) 235c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 236c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 237c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 238c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 239c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 240c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 241c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2422cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerbool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 2432cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner unsigned Reg) const { 244c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 245c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 246c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::SP: 247c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::PC: 248c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 249c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 250c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 251c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 252c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 253c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 254c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 255c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isR9Reserved(); 256c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 257c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 258c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return false; 259c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 260c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2612cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 2624f54c1293af174a8002db20faf7b4f82ba4e8514Evan ChengARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 2634f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng const TargetRegisterClass *B, 2644f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng unsigned SubIdx) const { 2654f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng switch (SubIdx) { 2664f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng default: return 0; 2674f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 1: 2684f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 2: 2694f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 3: 2704f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 4: 2714f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // S sub-registers. 2724f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A->getSize() == 8) { 2734f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A == &ARM::DPR_8RegClass) 2744f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2754f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return &ARM::DPR_VFP2RegClass; 2764f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 2774f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 2784f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng assert(A->getSize() == 16 && "Expecting a Q register class!"); 2794f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return &ARM::QPR_VFP2RegClass; 2804f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 5: 2814f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng case 6: 2824f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // D sub-registers. 2834f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2844f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 2854f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return 0; 2864f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng} 2874f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 2884f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 2892cfd52c507bd5790457a171eb9bcb39019cc6860Chris LattnerARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 290e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach return ARM::GPRRegisterClass; 291c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 292c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 293c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// getAllocationOrder - Returns the register allocation order for a specified 294c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// register class in the form of a pair of TargetRegisterClass iterators. 295c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstd::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 296c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 297c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned HintType, unsigned HintReg, 298c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 299c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Alternative register allocation orders when favoring even / odd registers 300c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of register pairs. 301c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 302c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is available. 303c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven1[] = { 304c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 305c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 306c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 307c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 308c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd1[] = { 309c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 310c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 311c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 312c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 313c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 314c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is available. 315c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven2[] = { 316c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 317c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 318c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 319c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 320c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd2[] = { 321c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 322c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 323c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 324c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 325c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 326c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is available. 327c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven3[] = { 328c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 329c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 330c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9 331c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 332c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd3[] = { 333c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 334c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 335c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8 336c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 337c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 338c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is not available. 339c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven4[] = { 340c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 341c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 342c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 343c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 344c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd4[] = { 345c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 346c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 347c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 348c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 349c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 350c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is not available. 351c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven5[] = { 352c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R10, 353c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 354c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 355c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 356c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd5[] = { 357c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R11, 358c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 359c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 360c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 361c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 362c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is not available. 363c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven6[] = { 364c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, 365c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 366c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 367c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd6[] = { 368c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, 369c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 370c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 371c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 372c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 373c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (HintType == ARMRI::RegPairEven) { 374c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 375c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 376c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 377c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 378c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 379c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 380c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin() && !hasFP(MF)) { 381c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 382c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven1, 383c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 384c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 385c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven4, 386c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 387c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 388c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 389c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven2, 390c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 391c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 392c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven5, 393c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 394c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 395c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 396c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven3, 397c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 398c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 399c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven6, 400c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 401c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 402c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (HintType == ARMRI::RegPairOdd) { 403c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 404c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 405c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 406c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 407c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 408c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 409c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin() && !hasFP(MF)) { 410c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 411c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd1, 412c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 413c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 414c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd4, 415c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 416c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 417c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 418c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd2, 419c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 420c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 421c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd5, 422c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 423c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 424c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 425c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd3, 426c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 427c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 428c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd6, 429c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 430c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 431c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 432c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 433c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 434c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 435c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 436c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// ResolveRegAllocHint - Resolves the specified register allocation hint 437c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// to a physical register. Returns the physical register if it is successful. 438c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned 439c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 440c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 441c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == 0 || !isPhysicalRegister(Reg)) 442c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 443c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Type == 0) 444c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reg; 445c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairOdd) 446c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Odd register. 447c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairOdd(Reg, MF); 448c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairEven) 449c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Even register. 450c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairEven(Reg, MF); 451c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 452c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 453c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 454c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 455c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 456c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 457c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 458c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 459c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 460c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 461c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 462c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 463c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 464c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 465c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 466c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 467c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 468c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 469c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 470c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 471c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 472c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 473c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 4743dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachstatic unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { 4753dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned MaxAlign = 0; 4763dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 4773dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach for (int i = FFI->getObjectIndexBegin(), 4783dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach e = FFI->getObjectIndexEnd(); i != e; ++i) { 4793dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (FFI->isDeadObjectIndex(i)) 4803dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach continue; 4813dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 4823dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned Align = FFI->getObjectAlignment(i); 4833dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach MaxAlign = std::max(MaxAlign, Align); 4843dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 4853dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 4863dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach return MaxAlign; 4873dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 4883dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 489c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// hasFP - Return true if the specified function should have a dedicated frame 490c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// pointer register. This is true if the function has variable sized allocas 491c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// or if frame pointer elimination is disabled. 492c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// 493c140c4803dc3e10e08138670829bc0494986abe9David Goodwinbool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 494c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 495c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (NoFramePointerElim || 4963dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach needsStackRealignment(MF) || 497c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->hasVarSizedObjects() || 498c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->isFrameAddressTaken()); 499c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 500c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 5013dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 5023dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 5033dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // Only do this for ARM if explicitly enabled 5043dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // FIXME: Once it's passing all the tests, enable by default 5053dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (!ARMDynamicStackAlign) 5063dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach return false; 5073dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 5083dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 5093dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5103dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 5113dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach return (RealignStack && 5123dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach !AFI->isThumb1OnlyFunction() && 5133dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach (MFI->getMaxAlignment() > StackAlign) && 5143dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach !MFI->hasVarSizedObjects()); 5153dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 5163dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 5173dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 518010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Chengbool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 51998a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 52098a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng if (NoFramePointerElim && MFI->hasCalls()) 52198a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 52298a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 52398a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 52498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 525542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateStackSize - Estimate and return the size of the frame. 526c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 527c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 528c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int Offset = 0; 529c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 530c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int FixedOff = -FFI->getObjectOffset(i); 531c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FixedOff > Offset) Offset = FixedOff; 532c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 533c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 534c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FFI->isDeadObjectIndex(i)) 535c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 536c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset += FFI->getObjectSize(i); 537c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Align = FFI->getObjectAlignment(i); 538c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Adjust to alignment boundary 539c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset = (Offset+Align-1)/Align*Align; 540c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 541c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (unsigned)Offset; 542c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 543c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 544542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateRSStackSizeLimit - Look at each instruction that references stack 545542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// frames and return the stack size limit beyond which some of these 546542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// instructions will require scratch register during their expansion later. 547ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Chengunsigned 548ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan ChengARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 549542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng unsigned Limit = (1 << 12) - 1; 550b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 551b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 552b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner I != E; ++I) { 553b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 554b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (!I->getOperand(i).isFI()) continue; 555764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 556b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 557b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 558b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (AddrMode == ARMII::AddrMode3 || 559b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner AddrMode == ARMII::AddrModeT2_i8) 560b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner return (1 << 8) - 1; 561764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 562b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (AddrMode == ARMII::AddrMode5 || 563b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner AddrMode == ARMII::AddrModeT2_i8s4) 564b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner Limit = std::min(Limit, ((1U << 8) - 1) * 4); 565ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng 566ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 567ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng // When the stack offset is negative, we will end up using 568ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng // the i8 instructions instead. 569ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng return (1 << 8) - 1; 570b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner break; // At most one FI per instruction 571b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner } 572542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 573542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 574542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 575542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng return Limit; 576542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng} 577542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 578c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 579c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 580c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RegScavenger *RS) const { 581c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // This tells PEI to spill the FP as if it is any other callee-save register 582c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to take advantage the eliminateFrameIndex machinery. This also ensures it 583c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // is spilled in the order specified by getCalleeSavedRegs() to make it easier 584c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to combine multiple loads / stores. 585c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CanEliminateFrame = true; 586c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CS1Spilled = false; 587c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool LRSpilled = false; 588c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumGPRSpills = 0; 589c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS1GPRs; 590c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS2GPRs; 591c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 592c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 5933dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 5943dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 5953dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // Calculate and set max stack object alignment early, so we can decide 5963dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // whether we will need stack realignment (and thus FP). 5973dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (ARMDynamicStackAlign) { 5983dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned MaxAlign = std::max(MFI->getMaxAlignment(), 5993dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach calculateMaxStackAlignment(MFI)); 6003dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach MFI->setMaxAlignment(MaxAlign); 6013dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 6023dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 603c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Don't spill FP if the frame can be eliminated. This is determined 604c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // by scanning the callee-save registers to see if any is used. 605c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 606c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 607c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0; CSRegs[i]; ++i) { 608c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = CSRegs[i]; 609c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool Spilled = false; 610c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(Reg)) { 611c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 612c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 613c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 614c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 615c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Check alias registers too. 616c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 617c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 618c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 619c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 620c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 621c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 622c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 623c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 624ec9eef4a15157fc0a05feff933848aa9283bd1afJim Grosbach if (CSRegClasses[i] == ARM::GPRRegisterClass || 625ec9eef4a15157fc0a05feff933848aa9283bd1afJim Grosbach CSRegClasses[i] == ARM::tGPRRegisterClass) { 626c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Spilled) { 627c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 628c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 629c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin()) { 630c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == ARM::LR) 631c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 632c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CS1Spilled = true; 633c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 634c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 635c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 636c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 637c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 638c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::LR: 639c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 640c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Fallthrough 641c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 642c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 643c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 644c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 645c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CS1Spilled = true; 646c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 647c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 648c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 649c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 650c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 651c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin()) { 652c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.push_back(Reg); 653c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 654c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 655c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 656c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 657c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 658c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 659c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 660c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 661c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::LR: 662c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.push_back(Reg); 663c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 664c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 665c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS2GPRs.push_back(Reg); 666c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 667c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 668c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 669c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 670c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 671c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 672c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ForceLRSpill = false; 673f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 674c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 675c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Force LR to be spilled if the Thumb function size is > 2048. This enables 676c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // use of BL to implement far jump. If it turns out that it's not needed 677c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // then the branch fix up path will undo it. 678c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FnSize >= (1 << 11)) { 679c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 680c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = true; 681c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 682c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 683c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 684c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ExtraCSSpill = false; 685010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 686c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setHasStackFrame(true); 687c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 688c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 689c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 690c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!LRSpilled && CS1Spilled) { 691c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 692c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 693c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 694c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 695c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 696c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = false; 697c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 698c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 699c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 700c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI requires FP to point to the stack slot that contains the 701c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // previous FP. 702c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) { 703c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(FramePtr); 704c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 705c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 706c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 707c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If stack and double are 8-byte aligned and we are spilling an odd number 708c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of GPRs. Spill one extra callee save GPR so we won't have to pad between 709c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // the integer and double callee save areas. 710c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 711c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (TargetAlign == 8 && (NumGPRSpills & 1)) { 712c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 713c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 714c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs[i]; 715f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin // Don't spill high register if the function is thumb1 716f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!AFI->isThumb1OnlyFunction() || 717c140c4803dc3e10e08138670829bc0494986abe9David Goodwin isARMLowRegister(Reg) || Reg == ARM::LR) { 718c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 719c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 720c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 721c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 722c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 723c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 724c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 725c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (!UnspilledCS2GPRs.empty() && 726f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin !AFI->isThumb1OnlyFunction()) { 727c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS2GPRs.front(); 728c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 729c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 730c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 731c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 732c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 733c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 734c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 735c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Estimate if we might need to scavenge a register at some point in order 736c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to materialize a stack offset. If so, either spill one additional 737c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // callee-saved register or reserve a special spill slot to facilitate 7383d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // register scavenging. Thumb1 needs a spill slot for stack pointer 7393d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // adjustments also, even when the frame itself is small. 7403d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach if (RS && !ExtraCSSpill) { 741c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 742d1a5ca6cb11763059ba1ee1c965cc69abff92e38Jim Grosbach // If any of the stack slot references may be out of range of an 743d1a5ca6cb11763059ba1ee1c965cc69abff92e38Jim Grosbach // immediate offset, make sure a register (or a spill slot) is 744d1a5ca6cb11763059ba1ee1c965cc69abff92e38Jim Grosbach // available for the register scavenger. Note that if we're indexing 745d1a5ca6cb11763059ba1ee1c965cc69abff92e38Jim Grosbach // off the frame pointer, the effective stack size is 4 bytes larger 746460c482ed38f5c2f91e29eaacf241928d3d77edfJim Grosbach // since the FP points to the stack slot of the previous FP. 747d1a5ca6cb11763059ba1ee1c965cc69abff92e38Jim Grosbach if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0) 748540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach >= estimateRSStackSizeLimit(MF)) { 749c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If any non-reserved CS register isn't spilled, just spill one or two 750c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // extra. That should take care of it! 751c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumExtras = TargetAlign / 4; 752c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 2> Extras; 753c140c4803dc3e10e08138670829bc0494986abe9David Goodwin while (NumExtras && !UnspilledCS1GPRs.empty()) { 754c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs.back(); 755c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.pop_back(); 756c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) { 757c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Extras.push_back(Reg); 758c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumExtras--; 759c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 760c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 76117487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach // For non-Thumb1 functions, also check for hi-reg CS registers 76217487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach if (!AFI->isThumb1OnlyFunction()) { 76317487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach while (NumExtras && !UnspilledCS2GPRs.empty()) { 76417487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach unsigned Reg = UnspilledCS2GPRs.back(); 76517487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach UnspilledCS2GPRs.pop_back(); 76617487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach if (!isReservedReg(MF, Reg)) { 76717487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach Extras.push_back(Reg); 76817487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach NumExtras--; 76917487ba60d171aa32b17e6c3ad6d5809e78f9868Jim Grosbach } 770c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 771c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 772c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Extras.size() && NumExtras == 0) { 773c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 774c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Extras[i]); 775c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Extras[i]); 776c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 777540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach } else if (!AFI->isThumb1OnlyFunction()) { 778540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach // note: Thumb1 functions spill to R12, not the stack. 779c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Reserve a slot closest to SP or frame pointer. 780e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach const TargetRegisterClass *RC = ARM::GPRRegisterClass; 781c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 782c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->getAlignment())); 783c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 784c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 785c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 786c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 787c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 788c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (ForceLRSpill) { 789c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 790c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 791c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setLRIsSpilledForFarJump(true); 792c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 793c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 794c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 795c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRARegister() const { 796c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::LR; 797c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 798c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 799c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { 800c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) 801c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 802c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 803c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 804c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 805c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 806c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 807c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 808c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 809c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 810c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 811c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 812c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 813c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 814c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 815c140c4803dc3e10e08138670829bc0494986abe9David Goodwinint ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 816c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 817c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 818c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 819c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 820c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 821c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 822c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 823c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 824c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 825c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R1: 826c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R0; 827c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R3: 8286009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R2; 829c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 830c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R4; 831c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 832c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 833c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 834c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 835c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 836c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 837c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 838c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S1: 839c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S0; 840c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S3: 841c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S2; 842c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S5: 843c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S4; 844c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S7: 845c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S6; 846c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S9: 847c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S8; 848c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S11: 849c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S10; 850c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S13: 851c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S12; 852c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S15: 853c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S14; 854c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S17: 855c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S16; 856c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S19: 857c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S18; 858c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S21: 859c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S20; 860c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S23: 861c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S22; 862c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S25: 863c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S24; 864c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S27: 865c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S26; 866c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S29: 867c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S28; 868c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S31: 869c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S30; 870c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 871c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D1: 872c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D0; 873c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D3: 874c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D2; 875c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D5: 876c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D4; 877c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D7: 878c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D6; 879c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D9: 880c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D8; 881c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D11: 882c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D10; 883c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D13: 884c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D12; 885c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D15: 886c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D14; 8878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D17: 8888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D16; 8898295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D19: 8908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D18; 8918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D21: 8928295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D20; 8938295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D23: 8948295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D22; 8958295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D25: 8968295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D24; 8978295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D27: 8988295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D26; 8998295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D29: 9008295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D28; 9018295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D31: 9028295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D30; 903c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 904c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 905c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 906c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 907c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 908c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 909c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 910c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 911c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 912c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 913c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 914c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R0: 915c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R1; 916c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R2: 9176009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R3; 918c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 919c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R5; 920c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 921c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 922c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R8: 923c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 924c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R10: 925c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 926c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 927c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S0: 928c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S1; 929c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S2: 930c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S3; 931c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S4: 932c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S5; 933c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S6: 934c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S7; 935c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S8: 936c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S9; 937c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S10: 938c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S11; 939c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S12: 940c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S13; 941c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S14: 942c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S15; 943c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S16: 944c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S17; 945c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S18: 946c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S19; 947c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S20: 948c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S21; 949c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S22: 950c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S23; 951c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S24: 952c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S25; 953c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S26: 954c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S27; 955c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S28: 956c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S29; 957c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S30: 958c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S31; 959c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 960c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D0: 961c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D1; 962c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D2: 963c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D3; 964c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D4: 965c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D5; 966c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D6: 967c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D7; 968c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D8: 969c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D9; 970c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D10: 971c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D11; 972c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D12: 973c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D13; 974c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D14: 975c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D15; 9768295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D16: 9778295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D17; 9788295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D18: 9798295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D19; 9808295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D20: 9818295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D21; 9828295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D22: 9838295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D23; 9848295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D24: 9858295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D25; 9868295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D26: 9878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D27; 9888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D28: 9898295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D29; 9908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D30: 9918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D31; 992c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 993c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 994c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 995c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 996c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 997db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 998db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 999db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1000db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 1001db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 100277521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 1003378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 1004db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 1005db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg) const { 1006db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 1007db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 10081d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson Constant *C = 10091d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1010db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1011db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1012378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1013378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 1014db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 1015db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1016db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1017db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1018db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 1019db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 1020db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1021db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 102241fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 10237e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 10247e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 10251d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach return ScavengeFrameIndexVals; 10267e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 1027db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1028db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1029db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// not required, we reserve argument space for call sites in the function 1030db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// immediately on entry to the current function. This eliminates the need for 1031db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// add/sub sp brackets around call sites. Returns true if the call frame is 1032db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// included as part of the stack frame. 1033db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 1034db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinhasReservedCallFrame(MachineFunction &MF) const { 1035db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 1036db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned CFSize = FFI->getMaxCallFrameSize(); 1037db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // It's not always a good idea to include the call frame as part of the 1038db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // stack frame. ARM (especially Thumb) has small immediate offset to 1039db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // address the stack frame. So a large call frame can cause poor codegen 1040db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // and may even makes it impossible to scavenge a register. 1041db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1042db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1043db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1044db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return !MF.getFrameInfo()->hasVarSizedObjects(); 1045db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1046db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1047db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void 10486495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengemitSPUpdate(bool isARM, 10496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 10506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng DebugLoc dl, const ARMBaseInstrInfo &TII, 1051db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes, 1052db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 10536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isARM) 10546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 10556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 10566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else 10576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 10586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 1059db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1060db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 10616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1062db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1063db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwineliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1064db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator I) const { 1065db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!hasReservedCallFrame(MF)) { 1066db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we have alloca, convert as follows: 1067db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1068db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKUP -> add, sp, sp, amount 1069db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstr *Old = I; 1070db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = Old->getDebugLoc(); 1071db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Amount = Old->getOperand(0).getImm(); 1072db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Amount != 0) { 1073db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // We need to keep the stack aligned properly. To do this, we round the 1074db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // amount of space needed for the outgoing arguments up to the next 1075db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // alignment boundary. 1076db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1077db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Amount = (Amount+Align-1)/Align*Align; 1078db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 10796495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 10806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 10816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This eliminateCallFramePseudoInstr does not suppor Thumb1!"); 10826495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 10836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1084db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Replace the pseudo instruction with a new instruction... 1085db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Opc = Old->getOpcode(); 1086db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 10876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN? 1088db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1089db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1090db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(2).getReg(); 10916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1092db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1093db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1094db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(3).getReg(); 1095db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 10966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1097db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1098db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1099db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1100db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBB.erase(I); 1101db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1102db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 11031d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach/// findScratchRegister - Find a 'free' ARM register. If register scavenger 11041d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach/// is not being used, R12 is available. Otherwise, try for a call-clobbered 11051d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach/// register first and then a spilled callee-saved register if that fails. 11061d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbachstatic 11071d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbachunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 11081d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach ARMFunctionInfo *AFI) { 11091d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12; 11101d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach assert(!AFI->isThumb1OnlyFunction()); 11111d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach return Reg; 11121d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach} 11131d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach 1114b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbachunsigned 11156495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1116b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbach int SPAdj, int *Value, 1117b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbach RegScavenger *RS) const { 11185ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned i = 0; 11195ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 11205ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 11215ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 1122010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 11235ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 11246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1125a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 11265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 11275ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin while (!MI.getOperand(i).isFI()) { 11285ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ++i; 11295ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 11305ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 11315ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 11325ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned FrameReg = ARM::SP; 11335ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int FrameIndex = MI.getOperand(i).getIndex(); 1134010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; 11355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 11363dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // When doing dynamic stack realignment, all of these need to change(?) 11375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 11385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getGPRCalleeSavedArea1Offset(); 11395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 11405ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getGPRCalleeSavedArea2Offset(); 11415ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 11425ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getDPRCalleeSavedAreaOffset(); 11433dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach else if (needsStackRealignment(MF)) { 11443dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // When dynamically realigning the stack, use the frame pointer for 11453dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // parameters, and the stack pointer for locals. 11463dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 11473dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (FrameIndex < 0) { 11483dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach FrameReg = getFrameRegister(MF); 11493dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach Offset -= AFI->getFramePtrSpillOffset(); 11503dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // When referencing from the frame pointer, stack pointer adjustments 11513dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // don't matter. 11523dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach SPAdj = 0; 11533dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 11543dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } else if (hasFP(MF) && AFI->hasStackFrame()) { 1155010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng assert(SPAdj == 0 && "Unexpected stack offset!"); 1156010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng // Use frame pointer to reference fixed objects unless this is a 11573dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // frameless function. 11585ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameReg = getFrameRegister(MF); 11595ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getFramePtrSpillOffset(); 11605ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 11615ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 11625ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin // modify MI as necessary to handle as much of 'Offset' as possible 1163cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 11646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 1165cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 11666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 11676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 1168cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 11696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1170cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 1171b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbach return 0; 11725ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1173db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 1174db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 1175db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 117619bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 117719bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && 1178cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 1179db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 11807e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 1181db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 1182db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 1183db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1184db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1185cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 1186cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Must be addrmode4. 1187cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 11886495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 11891d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach if (!ScavengeFrameIndexVals) { 11901d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach // Insert a set of r12 with the full address: r12 = sp + offset 11911d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach // If the offset we have is too large to fit into the instruction, we need 11921d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach // to form it with a series of ADDri's. Do this by taking 8-bit chunks 11931d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach // out of 'Offset'. 11941d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI); 11951d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach if (ScratchReg == 0) 11961d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach // No register is "free". Scavenge a register. 11971d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj); 11981d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach } else { 11991d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 12001d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach *Value = Offset; 12011d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach } 1202cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 1203cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1204cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1205cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 1206cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 1207cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1208cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1209cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 1210cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 12111d6827bbe947730cb91d68a9fd9c469f7f56a6aeJim Grosbach if (!ReuseFrameIndexVals || !ScavengeFrameIndexVals) 121218ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach ScratchReg = 0; 12136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 12147e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach return ScratchReg; 1215db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1216db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1217db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// Move iterator pass the next bunch of callee save load / store ops for 1218db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// the particular spill area (1: integer area 1, 2: integer area 2, 1219db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// 3: fp area, 0: don't care). 1220db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1221db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 12225ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int Opc1, int Opc2, unsigned Area, 1223db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const ARMSubtarget &STI) { 1224db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin while (MBBI != MBB.end() && 12255ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 12265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MBBI->getOperand(1).isFI()) { 1227db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Area != 0) { 1228db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin bool Done = false; 1229db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Category = 0; 1230db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (MBBI->getOperand(0).getReg()) { 1231db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1232db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1233db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 1; 1234db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1235db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1236db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = STI.isTargetDarwin() ? 2 : 1; 1237db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1238db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1239db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1240db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 3; 1241db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1242db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1243db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Done = true; 1244db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1245db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1246db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Done || Category != Area) 1247db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1248db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1249db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1250db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1251db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1252db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1253db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1254db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1255db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitPrologue(MachineFunction &MF) const { 1256db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock &MBB = MF.front(); 1257db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = MBB.begin(); 1258db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1259db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 12606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 12616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This emitPrologue does not suppor Thumb1!"); 12626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 1263db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1264db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned NumBytes = MFI->getStackSize(); 1265db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1266db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = (MBBI != MBB.end() ? 1267db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1268db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1269db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine the sizes of each callee-save spill areas and record which frame 1270db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // belongs to which callee-save spill areas. 1271db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1272db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FramePtrSpillFI = 0; 1273db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1274c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Allocate the vararg register save area. This is not counted in NumBytes. 1275db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 12766495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1277db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1278db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1279db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1281db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return; 1282db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1283db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1284db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1285db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Reg = CSI[i].getReg(); 1286db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FI = CSI[i].getFrameIdx(); 1287db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (Reg) { 1288db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: 1289db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R5: 1290db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R6: 1291db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R7: 1292db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1293db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1294db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1295db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1296db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1297db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1298db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: 1299db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R9: 1300db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R10: 1301db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R11: 1302db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1303db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1304db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin()) { 1305db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea2Frame(FI); 1306db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS2Size += 4; 1307db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1308db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1309db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1310db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1311db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1312db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1313db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addDPRCalleeSavedAreaFrame(FI); 1314db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DPRCSSize += 8; 1315db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1316db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1317db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1318db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 1. 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 13205732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1321db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1322c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Set FP to point to the stack slot that contains the previous FP. 1323c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // For Darwin, FP is R7, which has now been stored in spill area 1. 1324c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Otherwise, if this is not Darwin, all the callee-saved registers go 1325c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // into spill area 1, including the FP in R11. In either case, it is 1326c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // now safe to emit this assignment. 1327db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin() || hasFP(MF)) { 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1329db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstrBuilder MIB = 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1331db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addFrameIndex(FramePtrSpillFI).addImm(0); 1332db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AddDefaultCC(AddDefaultPred(MIB)); 1333db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1334db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1335db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 2. 13366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1337db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1338db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for FP callee-save spill area. 13395732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 13406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1341db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1342db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine starting offsets of spill areas. 1343db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1344db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1345db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1346db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1347db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1348db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1349db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1350db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1351db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = DPRCSOffset; 1352db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes) { 1353db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Insert it after all the callee-save spills. 1354b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI); 13556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1356db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1357db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1358db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetELF() && hasFP(MF)) { 1359db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1360db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getFramePtrSpillOffset()); 1361db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1362db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1363db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1364db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1365db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 13663dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 13673dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // If we need dynamic stack realignment, do it here. 13683dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (needsStackRealignment(MF)) { 13693dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned Opc; 13703dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 13713dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 13723dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 13733dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 13743dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP) 13753dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addReg(ARM::SP, RegState::Kill) 13763dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addImm(MaxAlign-1))); 13773dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 1378db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1379db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1380db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1381db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0; CSRegs[i]; ++i) 1382db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == CSRegs[i]) 1383db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1384db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1385db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1386db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 138777521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwinstatic bool isCSRestore(MachineInstr *MI, 1388764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach const ARMBaseInstrInfo &TII, 138977521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin const unsigned *CSRegs) { 1390b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng return ((MI->getOpcode() == (int)ARM::FLDD || 13915732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::LDR || 13925732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::t2LDRi12) && 1393db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MI->getOperand(1).isFI() && 1394db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1395db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1396db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1397db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1398293f8d9b8800ab68c64b67f38a7f76e00126715dEvan ChengemitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1399db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = prior(MBB.end()); 14005ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng assert(MBBI->getDesc().isReturn() && 1401db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin "Can only insert epilog into returning blocks"); 1402db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = MBBI->getDebugLoc(); 1403db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1404db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 14056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 14066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This emitEpilogue does not suppor Thumb1!"); 14076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 14086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1409db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1410db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes = (int)MFI->getStackSize(); 1411db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1412db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1413db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 14146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1415db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1416db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Unwind MBBI to point to first LDR / FLDD. 1417db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 1418db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (MBBI != MBB.begin()) { 1419db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin do 1420db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin --MBBI; 142177521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 142277521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin if (!isCSRestore(MBBI, TII, CSRegs)) 1423db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1424db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1425db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1426db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of FP callee save spill area. 1427db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1428db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getGPRCalleeSavedArea2Size() + 1429db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize()); 1430db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1431db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Darwin ABI requires FP to point to the stack slot that contains the 1432db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // previous FP. 1433010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng bool HasFP = hasFP(MF); 1434010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1435db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1436db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Reset SP based on frame pointer only if the stack frame extends beyond 1437db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // frame pointer stack slot or target is ELF and the function has FP. 1438010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if (HasFP || 1439010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng AFI->getGPRCalleeSavedArea2Size() || 1440db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize() || 1441010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng AFI->getDPRCalleeSavedAreaOffset()) { 14426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBytes) { 1443861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng if (isARM) 1444861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1445861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng ARMCC::AL, 0, TII); 1446861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng else 1447861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1448861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng ARMCC::AL, 0, TII); 14496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 14506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Thumb2 or ARM. 1451764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach if (isARM) 1452052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1453052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addReg(FramePtr) 1454052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1455052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng else 1456052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1457052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addReg(FramePtr); 14586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1459db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 14606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (NumBytes) 14616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1462db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1463db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 2. 1464b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI); 14656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1466db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1467db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 1. 14685732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 14696495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1470db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1471db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to SP upon entry to the function. 14725732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 14736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1474db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1475db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1476db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 14776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1478db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1479db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1480c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMGenRegisterInfo.inc" 1481