ARMBaseRegisterInfo.cpp revision d4511e947ee1e89a4f199bfac0d401976930ccfe
12cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMAddressingModes.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 17c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMBaseRegisterInfo.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMInstrInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 20c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 21c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Constants.h" 22c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/DerivedTypes.h" 239adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/Function.h" 249adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/LLVMContext.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineLocation.h" 30c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 31c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 323dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 33ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 34dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 35c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetFrameInfo.h" 36c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 37c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/BitVector.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/SmallVector.h" 4018ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach#include "llvm/Support/CommandLine.h" 41c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 428c407d45964fbba19719be555324f247e4fb14e1Dan Gohmannamespace llvm { 43a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachstatic cl::opt<bool> 443197380143cdc18837722129ac888528b9fbfc2bJim GrosbachForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), 45cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach cl::desc("Force use of virtual base registers for stack load/store")); 46a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachstatic cl::opt<bool> 47ae47c6d69e2e34bc558a302586cbc3f27a6d7334Jim GrosbachEnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, 48a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach cl::desc("Enable pre-regalloc stack frame index allocation")); 498c407d45964fbba19719be555324f247e4fb14e1Dan Gohman} 508c407d45964fbba19719be555324f247e4fb14e1Dan Gohman 518c407d45964fbba19719be555324f247e4fb14e1Dan Gohmanusing namespace llvm; 5218ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach 53c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 548295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng bool *isSPVFP) { 558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = false; 57c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 58c140c4803dc3e10e08138670829bc0494986abe9David Goodwin using namespace ARM; 59c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 60c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 61c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown ARM register!"); 628295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R0: case D0: case Q0: return 0; 638295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R1: case D1: case Q1: return 1; 648295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R2: case D2: case Q2: return 2; 658295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R3: case D3: case Q3: return 3; 668295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R4: case D4: case Q4: return 4; 678295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R5: case D5: case Q5: return 5; 688295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R6: case D6: case Q6: return 6; 698295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R7: case D7: case Q7: return 7; 708295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R8: case D8: case Q8: return 8; 718295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R9: case D9: case Q9: return 9; 728295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R10: case D10: case Q10: return 10; 738295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R11: case D11: case Q11: return 11; 748295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R12: case D12: case Q12: return 12; 758295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case SP: case D13: case Q13: return 13; 768295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case LR: case D14: case Q14: return 14; 778295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case PC: case D15: case Q15: return 15; 788295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng 798295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D16: return 16; 808295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D17: return 17; 818295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D18: return 18; 828295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D19: return 19; 838295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D20: return 20; 848295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D21: return 21; 858295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D22: return 22; 868295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D23: return 23; 878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D24: return 24; 888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D25: return 25; 8998330ff8e344d2e88c0a2166901d394e813e8162Bob Wilson case D26: return 26; 908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D27: return 27; 918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D28: return 28; 928295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D29: return 29; 938295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D30: return 30; 948295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D31: return 31; 95c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 96c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: case S1: case S2: case S3: 97c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: case S5: case S6: case S7: 98c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: case S9: case S10: case S11: 99c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: case S13: case S14: case S15: 100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: case S17: case S18: case S19: 101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: case S21: case S22: case S23: 102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: case S25: case S26: case S27: 1038295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case S28: case S29: case S30: case S31: { 1048295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 1058295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = true; 106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: return 0; // Avoid compile time warning. 108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: return 0; 109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S1: return 1; 110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S2: return 2; 111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S3: return 3; 112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: return 4; 113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S5: return 5; 114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S6: return 6; 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S7: return 7; 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: return 8; 117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S9: return 9; 118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S10: return 10; 119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S11: return 11; 120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: return 12; 121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S13: return 13; 122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S14: return 14; 123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S15: return 15; 124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: return 16; 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S17: return 17; 126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S18: return 18; 127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S19: return 19; 128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: return 20; 129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S21: return 21; 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S22: return 22; 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S23: return 23; 132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: return 24; 133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S25: return 25; 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S26: return 26; 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S27: return 27; 136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S28: return 28; 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S29: return 29; 138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S30: return 30; 139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S31: return 31; 140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 145db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 146c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 147c140c4803dc3e10e08138670829bc0494986abe9David Goodwin : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 148c140c4803dc3e10e08138670829bc0494986abe9David Goodwin TII(tii), STI(sti), 149c140c4803dc3e10e08138670829bc0494986abe9David Goodwin FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 150c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 151c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 152c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst unsigned* 153c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 154c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned CalleeSavedRegs[] = { 155c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 156c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R7, ARM::R6, ARM::R5, ARM::R4, 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 158c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 159c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 160c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 161c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 162c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned DarwinCalleeSavedRegs[] = { 164c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register. 166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11, ARM::R10, ARM::R8, 168c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 169c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 171c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 172c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 173c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 174c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1769631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 1779631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 178c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME: avoid re-calculating this everytime. 179c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 180c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 182d1fb583128c6682bb8a7c74eafa810a9270cc8dfNate Begeman Reserved.set(ARM::FPSCR); 183ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) 184c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 186c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 189c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 190c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1912cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerbool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 1922cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner unsigned Reg) const { 193c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 194c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 195c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::SP: 196c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::PC: 197c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 200ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (FramePtr == Reg && hasFP(MF)) 201c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 202c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 203c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 204c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isR9Reserved(); 205c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 206c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 207c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return false; 208c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 209c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2102cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 2114f54c1293af174a8002db20faf7b4f82ba4e8514Evan ChengARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 2124f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng const TargetRegisterClass *B, 2134f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng unsigned SubIdx) const { 2144f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng switch (SubIdx) { 2154f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng default: return 0; 216e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_0: 217e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_1: 218e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_2: 219e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_3: { 2204f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // S sub-registers. 2214f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A->getSize() == 8) { 222ba908640b3e0c1218748776e244d4b7234451155Evan Cheng if (B == &ARM::SPR_8RegClass) 223ba908640b3e0c1218748776e244d4b7234451155Evan Cheng return &ARM::DPR_8RegClass; 224ba908640b3e0c1218748776e244d4b7234451155Evan Cheng assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 2254f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A == &ARM::DPR_8RegClass) 2264f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2274f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return &ARM::DPR_VFP2RegClass; 2284f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 2294f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 230b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 231b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::SPR_8RegClass) 232b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_8RegClass; 233b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 234b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 235b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 23622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 23722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::SPR_8RegClass) 23822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 23922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 24022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 24122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 24222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 24322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 244b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 245e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_0: 246e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_1: 247e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_2: 248e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_3: { 2494f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // D sub-registers. 250b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 251b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_VFP2RegClass) 252b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 253b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_8RegClass) 25422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 255b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return A; 256b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 257b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 25822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 25922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_VFP2RegClass) 26022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 26122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_8RegClass) 26222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 26322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 26422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 26522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 26622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 26722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B != &ARM::DPRRegClass) 26822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 2694f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2704f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 271e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_4: 272e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_5: 273e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_6: 274e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_7: { 27522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // D sub-registers of QQQQ registers. 27622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::DPRRegClass) 27722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 27822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 27922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 28022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 281e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_0: 282e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_1: { 283b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng // Q sub-registers. 28422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 28522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_VFP2RegClass) 28622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 28722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_8RegClass) 28822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 28922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 29022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 29122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 29222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 29322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPRRegClass) 29422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 29522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 29622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 297e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_2: 298e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_3: { 29922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // Q sub-registers of QQQQ registers. 30022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::QPRRegClass) 30122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 30222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 303b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 304b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 3054f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return 0; 3064f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng} 3074f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 308b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengbool 30991a74da036d3a9442953ae1de3e797a50da4ccf0Bob WilsonARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, 310b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng SmallVectorImpl<unsigned> &SubIndices, 311b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned &NewSubIdx) const { 312b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 313b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned Size = RC->getSize() * 8; 314b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size < 6) 315b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 316b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 317b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng NewSubIdx = 0; // Whole register. 318b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned NumRegs = SubIndices.size(); 319b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (NumRegs == 8) { 320b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 8 D registers -> 1 QQQQ register. 321b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 322558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[0] == ARM::dsub_0 && 323558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 324558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 325558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3 && 326558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[4] == ARM::dsub_4 && 327558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[5] == ARM::dsub_5 && 328558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[6] == ARM::dsub_6 && 329558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[7] == ARM::dsub_7); 330b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 4) { 331558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 332b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 Q registers -> 1 QQQQ register. 333b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 334558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::qsub_1 && 335558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::qsub_2 && 336558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::qsub_3); 337558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 338b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register. 339b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256 && 340558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 341558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 342558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3) { 343b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 344558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 345b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 346b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 347558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 348b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register (2nd). 349b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512 && 350558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_5 && 351558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_6 && 352558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_7) { 353558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 354b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 355b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 356558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 357b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 S registers -> 1 Q register. 358b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128 && 359558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::ssub_1 && 360558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::ssub_2 && 361558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::ssub_3) { 362b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 363558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 364b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 365b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 366b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 367b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 2) { 368558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 369b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register. 370558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 371b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 372558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 373b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 374b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 375558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::qsub_2) { 376b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register (2nd). 377558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 378558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 379b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 380b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 381558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 382b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register. 383558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 384b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 385558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 386b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 387b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 388558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_2) { 389b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (2nd). 390558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 391558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_1; 392b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 393b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 394558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 395b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 396558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 397558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_2; 398b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 399b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 400558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_6) { 401b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 402558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 403558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_3; 404b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 405b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 406558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 407b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register. 408558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[1] == ARM::ssub_1) { 409b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128) 410558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_0; 411b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 412b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 413558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_2) { 414b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register (2nd). 415558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 416558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_1; 417b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 418b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 419b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 420b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 421b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return false; 422b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng} 423b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 424b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 4254f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 4262cfd52c507bd5790457a171eb9bcb39019cc6860Chris LattnerARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 427e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach return ARM::GPRRegisterClass; 428c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 429c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 430c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// getAllocationOrder - Returns the register allocation order for a specified 431c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// register class in the form of a pair of TargetRegisterClass iterators. 432c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstd::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 433c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 434c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned HintType, unsigned HintReg, 435c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 436c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Alternative register allocation orders when favoring even / odd registers 437c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of register pairs. 438c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 439c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is available. 440c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven1[] = { 441c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 442c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 443c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 444c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 445c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd1[] = { 446c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 447c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 448c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 449c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 450c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 451c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is available. 452c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven2[] = { 453c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 454c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 455c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 456c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 457c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd2[] = { 458c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 459c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 460c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 461c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 462c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 463c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is available. 464c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven3[] = { 465c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 466c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 467c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9 468c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 469c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd3[] = { 470c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 471c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 472c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8 473c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 474c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 475c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is not available. 476c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven4[] = { 477c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 478c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 479c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 480c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 481c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd4[] = { 482c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 483c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 484c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 485c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 486c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 487c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is not available. 488c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven5[] = { 489c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R10, 490c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 491c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 492c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 493c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd5[] = { 494c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R11, 495c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 496c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 497c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 498c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 499c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is not available. 500c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven6[] = { 501c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, 502c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 503c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 504c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd6[] = { 505c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, 506c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 507c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 508c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 509c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 510c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (HintType == ARMRI::RegPairEven) { 511c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 512c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 513c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 514c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 515c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 516c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 517ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!hasFP(MF)) { 518c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 519c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven1, 520c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 521c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 522c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven4, 523c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 524c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 525c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 526c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven2, 527c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 528c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 529c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven5, 530c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 531c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 532c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 533c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven3, 534c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 535c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 536c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven6, 537c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 538c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 539c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (HintType == ARMRI::RegPairOdd) { 540c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 541c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 542c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 543c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 544c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 545c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 546ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!hasFP(MF)) { 547c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 548c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd1, 549c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 550c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 551c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd4, 552c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 553c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 554c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 555c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd2, 556c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 557c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 558c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd5, 559c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 560c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 561c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 562c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd3, 563c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 564c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 565c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd6, 566c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 567c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 568c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 569c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 570c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 571c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 572c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 573c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// ResolveRegAllocHint - Resolves the specified register allocation hint 574c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// to a physical register. Returns the physical register if it is successful. 575c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned 576c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 577c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 578c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == 0 || !isPhysicalRegister(Reg)) 579c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 580c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Type == 0) 581c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reg; 582c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairOdd) 583c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Odd register. 584c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairOdd(Reg, MF); 585c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairEven) 586c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Even register. 587c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairEven(Reg, MF); 588c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 589c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 590c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 591c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 592c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 593c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 594c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 595c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 596c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 597c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 598c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 599c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 600c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 601c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 602c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 603c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 604c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 605c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 606c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 607c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 608c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 609c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 610c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 611c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// hasFP - Return true if the specified function should have a dedicated frame 612c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// pointer register. This is true if the function has variable sized allocas 613c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// or if frame pointer elimination is disabled. 614c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// 615c140c4803dc3e10e08138670829bc0494986abe9David Goodwinbool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 616ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Mac OS X requires FP not to be clobbered for backtracing purpose. 617ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (STI.isTargetDarwin()) 618ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng return true; 619ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 620c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 621b000d683c822bab7bed608937048b24b4b6db551Evan Cheng // Always eliminate non-leaf frame pointers. 622b000d683c822bab7bed608937048b24b4b6db551Evan Cheng return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || 6233dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach needsStackRealignment(MF) || 624c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->hasVarSizedObjects() || 625c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->isFrameAddressTaken()); 626c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 627c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 628e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 629e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 630e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 631e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach return (RealignStack && 632e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach !AFI->isThumb1OnlyFunction() && 633e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach !MFI->hasVarSizedObjects()); 634e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 635e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 6363dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 6373dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 6383dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 639d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 6403dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 641ad353c74adda55556f7a3969721c3e49ac16d570Jim Grosbach unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 642697cba8ec2b3f5160175fd5b4a641dbd48606e17Eric Christopher bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 643697cba8ec2b3f5160175fd5b4a641dbd48606e17Eric Christopher F->hasFnAttr(Attribute::StackAlignment)); 644d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 645d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: Currently we don't support stack realignment for functions with 646d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // variable-sized allocas. 647d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: It's more complicated than this... 648d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher if (0 && requiresRealignment && MFI->hasVarSizedObjects()) 649d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher report_fatal_error( 650d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher "Stack realignment in presense of dynamic allocas is not supported"); 651d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 652d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: This probably isn't the right place for this. 653d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) 654d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher report_fatal_error( 655d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher "Stack realignment in thumb1 functions is not supported"); 656d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 657d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 6583dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 6593dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 6609631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 6619631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 66298a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 663b92187a4103dca24c3767c380f63593d1f6161a7Bill Wendling if (DisableFramePointerElim(MF) && MFI->adjustsStack()) 66498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 66531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 66631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 66798a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 66898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 669542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateStackSize - Estimate and return the size of the frame. 670657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesenstatic unsigned estimateStackSize(MachineFunction &MF) { 671c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 672c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int Offset = 0; 673c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 674c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int FixedOff = -FFI->getObjectOffset(i); 675c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FixedOff > Offset) Offset = FixedOff; 676c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 677c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 678c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FFI->isDeadObjectIndex(i)) 679c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 680c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset += FFI->getObjectSize(i); 681c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Align = FFI->getObjectAlignment(i); 682c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Adjust to alignment boundary 683c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset = (Offset+Align-1)/Align*Align; 684c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 685c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (unsigned)Offset; 686c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 687c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 688542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateRSStackSizeLimit - Look at each instruction that references stack 689542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// frames and return the stack size limit beyond which some of these 690ce3e769c15be90463abf14bb71b5a8e1205d3661Jim Grosbach/// instructions will require a scratch register during their expansion later. 691ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Chengunsigned 692ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan ChengARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 693ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 694542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng unsigned Limit = (1 << 12) - 1; 695b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 696b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 697b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner I != E; ++I) { 698b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 699b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (!I->getOperand(i).isFI()) continue; 70052c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen 70152c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // When using ADDri to get the address of a stack object, 255 is the 70252c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // largest offset guaranteed to fit in the immediate offset. 70352c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen if (I->getOpcode() == ARM::ADDri) { 70452c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen Limit = std::min(Limit, (1U << 8) - 1); 70552c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen break; 70652c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen } 70752c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen 70852c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // Otherwise check the addressing mode. 709535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 710535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode3: 711535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i8: 712535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen Limit = std::min(Limit, (1U << 8) - 1); 713535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 714535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode5: 715535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i8s4: 716b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner Limit = std::min(Limit, ((1U << 8) - 1) * 4); 717535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 718535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i12: 719ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // i12 supports only positive offset so these will be converted to 720ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // i8 opcodes. See llvm::rewriteT2FrameIndex. 721ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF) && AFI->hasStackFrame()) 722ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng Limit = std::min(Limit, (1U << 8) - 1); 723535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 724535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode6: 725535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen // Addressing mode 6 (load/store) instructions can't encode an 726535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen // immediate offset for stack references. 727ce3e769c15be90463abf14bb71b5a8e1205d3661Jim Grosbach return 0; 728535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen default: 729535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 730535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen } 731b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner break; // At most one FI per instruction 732b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner } 733542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 734542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 735542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 736542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng return Limit; 737542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng} 738542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 7391c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattnerstatic unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 7401c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner const ARMBaseInstrInfo &TII) { 7411c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner unsigned FnSize = 0; 7421c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 7431c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner MBBI != E; ++MBBI) { 7441c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner const MachineBasicBlock &MBB = *MBBI; 7451c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 7461c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner I != E; ++I) 7471c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner FnSize += TII.GetInstSizeInBytes(I); 7481c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner } 7491c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner return FnSize; 7501c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner} 7511c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner 752c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 753c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 7549631864688c593711f82bb8d21f8b724c628d786Jim Grosbach RegScavenger *RS) const { 755c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // This tells PEI to spill the FP as if it is any other callee-save register 756c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to take advantage the eliminateFrameIndex machinery. This also ensures it 757c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // is spilled in the order specified by getCalleeSavedRegs() to make it easier 758c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to combine multiple loads / stores. 759c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CanEliminateFrame = true; 760c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CS1Spilled = false; 761c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool LRSpilled = false; 762c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumGPRSpills = 0; 763c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS1GPRs; 764c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS2GPRs; 765c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 7666c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 767c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 7687cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // Spill R4 if Thumb2 function requires stack realignment - it will be used as 7697cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // scratch register. 7707cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // FIXME: It will be better just to find spare register here. 7717cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov if (needsStackRealignment(MF) && 7727cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AFI->isThumb2Function()) 7737cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov MF.getRegInfo().setPhysRegUsed(ARM::R4); 7747cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov 775f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach // Spill LR if Thumb1 function uses variable length argument lists. 776f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) 777f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach MF.getRegInfo().setPhysRegUsed(ARM::LR); 778f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach 779c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Don't spill FP if the frame can be eliminated. This is determined 780c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // by scanning the callee-save registers to see if any is used. 781c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 782c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0; CSRegs[i]; ++i) { 783c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = CSRegs[i]; 784c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool Spilled = false; 785c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(Reg)) { 786c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 787c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 788c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 789c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 790c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Check alias registers too. 791c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 792c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 793c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 794c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 795c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 796c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 797c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 798c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 79920fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!ARM::GPRRegisterClass->contains(Reg)) 80020fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 801c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 80220fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (Spilled) { 80320fae651816916000c47b78843f22fd259ba4216Rafael Espindola NumGPRSpills++; 804c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 80520fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!STI.isTargetDarwin()) { 80620fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (Reg == ARM::LR) 807c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 80820fae651816916000c47b78843f22fd259ba4216Rafael Espindola CS1Spilled = true; 80920fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 81020fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 811c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 81220fae651816916000c47b78843f22fd259ba4216Rafael Espindola // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 81320fae651816916000c47b78843f22fd259ba4216Rafael Espindola switch (Reg) { 81420fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::LR: 81520fae651816916000c47b78843f22fd259ba4216Rafael Espindola LRSpilled = true; 81620fae651816916000c47b78843f22fd259ba4216Rafael Espindola // Fallthrough 81720fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R4: 81820fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R5: 81920fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R6: 82020fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R7: 82120fae651816916000c47b78843f22fd259ba4216Rafael Espindola CS1Spilled = true; 82220fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 82320fae651816916000c47b78843f22fd259ba4216Rafael Espindola default: 82420fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 82520fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 82620fae651816916000c47b78843f22fd259ba4216Rafael Espindola } else { 82720fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!STI.isTargetDarwin()) { 82820fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS1GPRs.push_back(Reg); 82920fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 83020fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 83120fae651816916000c47b78843f22fd259ba4216Rafael Espindola 83220fae651816916000c47b78843f22fd259ba4216Rafael Espindola switch (Reg) { 83320fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R4: 83420fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R5: 83520fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R6: 83620fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R7: 83720fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::LR: 83820fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS1GPRs.push_back(Reg); 83920fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 84020fae651816916000c47b78843f22fd259ba4216Rafael Espindola default: 84120fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS2GPRs.push_back(Reg); 84220fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 843c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 844c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 845c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 846c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 847c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ForceLRSpill = false; 848f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 8491c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 850c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Force LR to be spilled if the Thumb function size is > 2048. This enables 851c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // use of BL to implement far jump. If it turns out that it's not needed 852c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // then the branch fix up path will undo it. 853c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FnSize >= (1 << 11)) { 854c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 855c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = true; 856c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 857c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 858c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 859657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // If any of the stack slot references may be out of range of an immediate 860657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // offset, make sure a register (or a spill slot) is available for the 861657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // register scavenger. Note that if we're indexing off the frame pointer, the 862657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // effective stack size is 4 bytes larger since the FP points to the stack 8636c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // slot of the previous FP. Also, if we have variable sized objects in the 8646c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // function, stack slot references will often be negative, and some of 8656c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // our instructions are positive-offset only, so conservatively consider 866abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // that case to want a spill slot (or register) as well. Similarly, if 867abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // the function adjusts the stack pointer during execution and the 868abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // adjustments aren't already part of our stack size estimate, our offset 869abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // calculations may be off, so be conservative. 8706c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // FIXME: We could add logic to be more precise about negative offsets 8716c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // and which instructions will need a scratch register for them. Is it 8726c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // worth the effort and added fragility? 87368eec39bca280f98bef1256a5e89531ac1a77d1aChandler Carruth bool BigStack = 874ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng (RS && 875ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 876ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng estimateRSStackSizeLimit(MF))) 877a7da3ac14ab1ca6da52547baf572d29c066559ccChandler Carruth || MFI->hasVarSizedObjects() 878a7da3ac14ab1ca6da52547baf572d29c066559ccChandler Carruth || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 879657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen 880c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ExtraCSSpill = false; 881657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { 882c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setHasStackFrame(true); 883c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 884c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 885c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 886c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!LRSpilled && CS1Spilled) { 887c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 888c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 889c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 890c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 891c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 892c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = false; 893c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 894c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 895c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 896ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) { 897c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(FramePtr); 898c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 899c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 900c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 901c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If stack and double are 8-byte aligned and we are spilling an odd number 902c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of GPRs. Spill one extra callee save GPR so we won't have to pad between 903c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // the integer and double callee save areas. 904c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 905c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (TargetAlign == 8 && (NumGPRSpills & 1)) { 906c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 907c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 908c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs[i]; 909f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin // Don't spill high register if the function is thumb1 910f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!AFI->isThumb1OnlyFunction() || 911c140c4803dc3e10e08138670829bc0494986abe9David Goodwin isARMLowRegister(Reg) || Reg == ARM::LR) { 912c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 913c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 914c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 915c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 916c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 917c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 918c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 919c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (!UnspilledCS2GPRs.empty() && 920f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin !AFI->isThumb1OnlyFunction()) { 921c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS2GPRs.front(); 922c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 923c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 924c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 925c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 926c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 927c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 928c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 929c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Estimate if we might need to scavenge a register at some point in order 930c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to materialize a stack offset. If so, either spill one additional 931c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // callee-saved register or reserve a special spill slot to facilitate 9323d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // register scavenging. Thumb1 needs a spill slot for stack pointer 9333d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // adjustments also, even when the frame itself is small. 934657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (BigStack && !ExtraCSSpill) { 935657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // If any non-reserved CS register isn't spilled, just spill one or two 936657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // extra. That should take care of it! 937657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned NumExtras = TargetAlign / 4; 938657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen SmallVector<unsigned, 2> Extras; 939657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen while (NumExtras && !UnspilledCS1GPRs.empty()) { 940657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned Reg = UnspilledCS1GPRs.back(); 941657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen UnspilledCS1GPRs.pop_back(); 9421190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson if (!isReservedReg(MF, Reg) && 9431190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 9441190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson Reg == ARM::LR)) { 945657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen Extras.push_back(Reg); 946657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen NumExtras--; 947657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 948657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 949657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // For non-Thumb1 functions, also check for hi-reg CS registers 950657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (!AFI->isThumb1OnlyFunction()) { 951657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen while (NumExtras && !UnspilledCS2GPRs.empty()) { 952657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned Reg = UnspilledCS2GPRs.back(); 953657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen UnspilledCS2GPRs.pop_back(); 954c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) { 955c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Extras.push_back(Reg); 956c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumExtras--; 957c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 958c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 959657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 960657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (Extras.size() && NumExtras == 0) { 961657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 962657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen MF.getRegInfo().setPhysRegUsed(Extras[i]); 963657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen AFI->setCSRegisterIsSpilled(Extras[i]); 964c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 965657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } else if (!AFI->isThumb1OnlyFunction()) { 966657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 967657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // closest to SP or frame pointer. 968657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen const TargetRegisterClass *RC = ARM::GPRRegisterClass; 969657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 970657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen RC->getAlignment(), 971657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen false)); 972c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 973c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 974c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 975c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 976c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (ForceLRSpill) { 977c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 978c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 979c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setLRIsSpilledForFarJump(true); 980c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 981c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 982c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 983c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRARegister() const { 984c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::LR; 985c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 986c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 9873f2bf85d14759cc4b28a86805f566ac805a54d00David Greeneunsigned 9883f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 989ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) 990c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 991c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 992c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 993c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 994e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// Provide a base+offset reference to an FI slot for debug info. It's the 995e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// same as what we use for resolving the code-gen references for now. 996e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// FIXME: This can go wrong when references are SP-relative and simple call 997e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// frames aren't used. 99850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbachint 99930c6b75ac2eef548c18110a38c9798ea5314cabaChris LattnerARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, 100050f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach unsigned &FrameReg) const { 1001e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 1002e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach} 1003e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1004e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbachint 1005e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim GrosbachARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF, 1006e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int FI, 1007e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach unsigned &FrameReg, 1008e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int SPAdj) const { 100950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 101030c6b75ac2eef548c18110a38c9798ea5314cabaChris Lattner const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 101150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 1012e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 101350f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach bool isFixed = MFI->isFixedObjectIndex(FI); 101450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 1015a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach FrameReg = ARM::SP; 1016e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset += SPAdj; 101750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (AFI->isGPRCalleeSavedArea1Frame(FI)) 1018e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getGPRCalleeSavedArea1Offset(); 101950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 1020e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getGPRCalleeSavedArea2Offset(); 102150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 1022e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getDPRCalleeSavedAreaOffset(); 1023e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1024e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // When dynamically realigning the stack, use the frame pointer for 1025e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // parameters, and the stack pointer for locals. 1026e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach if (needsStackRealignment(MF)) { 102750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 102850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (isFixed) { 102950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 1030e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 103150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 1032e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset; 1033e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach } 1034e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1035e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // If there is a frame pointer, use it when we can. 1036e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach if (hasFP(MF) && AFI->hasStackFrame()) { 1037e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // Use frame pointer to reference fixed objects. Use it for locals if 1038e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // there are VLAs (and thus the SP isn't reliable as a base). 103950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (isFixed || MFI->hasVarSizedObjects()) { 104050f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 1041e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 104250f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } else if (AFI->isThumb2Function()) { 1043e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // In Thumb2 mode, the negative offset is very limited. Try to avoid 1044e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // out of range references. 104550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (FPOffset >= -255 && FPOffset < 0) { 104650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 104750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach Offset = FPOffset; 104850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 1049e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 1050e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // Otherwise, use SP or FP, whichever is closer to the stack slot. 1051e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach FrameReg = getFrameRegister(MF); 1052e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 105350f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 105450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 105550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach return Offset; 105650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach} 105750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 105850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbachint 105930c6b75ac2eef548c18110a38c9798ea5314cabaChris LattnerARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, 106030c6b75ac2eef548c18110a38c9798ea5314cabaChris Lattner int FI) const { 106150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach unsigned FrameReg; 106250f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach return getFrameIndexReference(MF, FI, FrameReg); 106350f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach} 106450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 1065c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 1066c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 1067c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1068c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1069c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1070c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 1071c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 1072c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1073c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1074c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1075c140c4803dc3e10e08138670829bc0494986abe9David Goodwinint ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1076c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1077c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1078c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1079c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 10809631864688c593711f82bb8d21f8b724c628d786Jim Grosbach const MachineFunction &MF) const { 1081c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 1082c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 1083c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 1084c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 1085c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R1: 1086c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R0; 1087c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R3: 10886009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R2; 1089c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 1090c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R4; 1091c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 1092c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 1093c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 1094c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 1095c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 1096c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 1097c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1098c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S1: 1099c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S0; 1100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S3: 1101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S2; 1102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S5: 1103c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S4; 1104c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S7: 1105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S6; 1106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S9: 1107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S8; 1108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S11: 1109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S10; 1110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S13: 1111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S12; 1112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S15: 1113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S14; 1114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S17: 1115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S16; 1116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S19: 1117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S18; 1118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S21: 1119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S20; 1120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S23: 1121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S22; 1122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S25: 1123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S24; 1124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S27: 1125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S26; 1126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S29: 1127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S28; 1128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S31: 1129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S30; 1130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D1: 1132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D0; 1133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D3: 1134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D2; 1135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D5: 1136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D4; 1137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D7: 1138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D6; 1139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D9: 1140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D8; 1141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D11: 1142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D10; 1143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D13: 1144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D12; 1145c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D15: 1146c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D14; 11478295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D17: 11488295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D16; 11498295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D19: 11508295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D18; 11518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D21: 11528295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D20; 11538295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D23: 11548295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D22; 11558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D25: 11568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D24; 11578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D27: 11588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D26; 11598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D29: 11608295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D28; 11618295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D31: 11628295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D30; 1163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 1164c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1168c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 1169c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 1170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 1171c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 1172c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 1173c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 1174c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R0: 1175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R1; 1176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R2: 11776009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R3; 1178c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 1179c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R5; 1180c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 1181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 1182c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R8: 1183c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 1184c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R10: 1185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 1186c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S0: 1188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S1; 1189c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S2: 1190c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S3; 1191c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S4: 1192c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S5; 1193c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S6: 1194c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S7; 1195c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S8: 1196c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S9; 1197c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S10: 1198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S11; 1199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S12: 1200c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S13; 1201c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S14: 1202c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S15; 1203c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S16: 1204c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S17; 1205c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S18: 1206c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S19; 1207c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S20: 1208c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S21; 1209c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S22: 1210c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S23; 1211c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S24: 1212c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S25; 1213c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S26: 1214c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S27; 1215c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S28: 1216c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S29; 1217c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S30: 1218c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S31; 1219c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1220c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D0: 1221c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D1; 1222c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D2: 1223c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D3; 1224c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D4: 1225c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D5; 1226c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D6: 1227c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D7; 1228c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D8: 1229c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D9; 1230c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D10: 1231c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D11; 1232c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D12: 1233c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D13; 1234c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D14: 1235c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D15; 12368295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D16: 12378295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D17; 12388295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D18: 12398295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D19; 12408295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D20: 12418295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D21; 12428295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D22: 12438295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D23; 12448295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D24: 12458295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D25; 12468295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D26: 12478295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D27; 12488295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D28: 12498295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D29; 12508295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D30: 12518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D31; 1252c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 1253c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1254c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1255c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1256c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1257db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 1258db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 1259db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1260db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 1261db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 126277521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 1263378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 1264db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 1265db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg) const { 1266db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 1267db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 126846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 12691d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1270db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1271db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1272378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1273378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 1274db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 1275db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1276db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1277db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1278db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 1279db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 1280db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1281db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 128241fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 12837e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 12847e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 1285ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 12867e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 1287db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1288a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 1289a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 1290a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return EnableLocalStackAlloc; 1291a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 1292a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 1293db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1294db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// not required, we reserve argument space for call sites in the function 1295db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// immediately on entry to the current function. This eliminates the need for 1296db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// add/sub sp brackets around call sites. Returns true if the call frame is 1297db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// included as part of the stack frame. 1298db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 129972852a8cfb605056d87b644d2e36b1346051413dEric ChristopherhasReservedCallFrame(const MachineFunction &MF) const { 1300db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 1301db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned CFSize = FFI->getMaxCallFrameSize(); 1302db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // It's not always a good idea to include the call frame as part of the 1303db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // stack frame. ARM (especially Thumb) has small immediate offset to 1304db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // address the stack frame. So a large call frame can cause poor codegen 1305db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // and may even makes it impossible to scavenge a register. 1306db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1307db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1308db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1309db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return !MF.getFrameInfo()->hasVarSizedObjects(); 1310db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1311db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13124642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// canSimplifyCallFramePseudos - If there is a reserved call frame, the 13134642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// call frame pseudos can be simplified. Unlike most targets, having a FP 13144642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// is not sufficient here since we still may reference some objects via SP 13154642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// even when FP is available in Thumb2 mode. 13164642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbachbool ARMBaseRegisterInfo:: 131772852a8cfb605056d87b644d2e36b1346051413dEric ChristophercanSimplifyCallFramePseudos(const MachineFunction &MF) const { 13185f366af2ff36cc65fe4964194b07bf1455828ff0Jim Grosbach return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 13194642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach} 13204642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach 1321db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengemitSPUpdate(bool isARM, 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng DebugLoc dl, const ARMBaseInstrInfo &TII, 1325db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes, 1326db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isARM) 13286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 13296495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 13306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 13326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 1333db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1334db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1336db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1337db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwineliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1338db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator I) const { 1339db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!hasReservedCallFrame(MF)) { 1340db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we have alloca, convert as follows: 1341db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1342db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKUP -> add, sp, sp, amount 1343db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstr *Old = I; 1344db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = Old->getDebugLoc(); 1345db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Amount = Old->getOperand(0).getImm(); 1346db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Amount != 0) { 1347db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // We need to keep the stack aligned properly. To do this, we round the 1348db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // amount of space needed for the outgoing arguments up to the next 1349db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // alignment boundary. 1350db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1351db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Amount = (Amount+Align-1)/Align*Align; 1352db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 13546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1355cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This eliminateCallFramePseudoInstr does not support Thumb1!"); 13566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 13576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1358db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Replace the pseudo instruction with a new instruction... 1359db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Opc = Old->getOpcode(); 13604c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach int PIdx = Old->findFirstPredOperandIdx(); 13614c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ARMCC::CondCodes Pred = (PIdx == -1) 13624c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1363db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1364db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1365db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(2).getReg(); 13666495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1367db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1368db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1369db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(3).getReg(); 1370db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 13716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1372db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1373db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1374db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1375db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBB.erase(I); 1376db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1377db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1378e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 13791ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 1380e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const TargetInstrDesc &Desc = MI->getDesc(); 1381e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1382e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t InstrOffs = 0;; 1383e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 1384e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 13851ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 1386e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 1387e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 1388e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // i8 supports only negative, and i12 supports only positive, so 1389e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // based on Offset sign, consider the appropriate instruction 1390e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 1391e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 1392e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1393e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 1394e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 1395e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 1396f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 1397e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 1398e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 1399e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 1400e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1401e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1402e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 1403e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 1404e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 1405e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1406e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 1407e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1408e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1409e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 1410e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 1411e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 1412e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1413e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 1414e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1415e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1416e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 1417e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 1418e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 1419e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 1420e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1421e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1422e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 1423e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 1424e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1425e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1426e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 1427e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 1428e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 1429e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 14308708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 14318708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 14328708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 14338708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 14348708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 14353197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 14363197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 14373197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 14383197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 14398708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 14408708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 14418708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 14428708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 14438708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 14448708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 14458708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 14468708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1447cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 1448cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 14498708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 14508708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 14518708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::LDR: case ARM::LDRH: case ARM::LDRB: 14528708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::STR: case ARM::STRH: case ARM::STRB: 14538708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2LDRi12: case ARM::t2LDRi8: 14548708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2STRi12: case ARM::t2STRi8: 14558708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 14568708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 145774d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 1458cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach if (ForceAllBaseRegAlloc) 1459cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 1460cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 14618708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 14628708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 14638708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 1464cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 1465cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 1466cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 14673197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 14683197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 14693197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 14703197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 14713197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 14723197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 14733197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 14743197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 14753197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 14763197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 14773197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 14783197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 14793197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 14803197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 14813197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 14823197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 14833197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset = -Offset; 14843197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 14853197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 14863197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 14873197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 14883197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 14893197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If there is a frame pointer, try using it. 14903197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 14913197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 14923197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 14933197380143cdc18837722129ac888528b9fbfc2bJim Grosbach unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 14943197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (hasFP(MF) && 14953197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 14963197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (isFrameOffsetLegal(MI, FPOffset)) 14973197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 14983197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 14993197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 15003197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 15013197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 15023197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 15033197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 15043197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 15053197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 1506cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 15073197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 1508cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 15098708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 15108708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1511dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach/// materializeFrameBaseRegister - Insert defining instruction(s) for 1512dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach/// BaseReg to be a pointer to FrameIdx before insertion point I. 1513dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 1514e2f556933e1a19cddf6d4f370e2770c0f763b025Jim GrosbachmaterializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg, 1515e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int FrameIdx, int64_t Offset) const { 1516dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = 1517dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach I->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 151874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 151974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 1520dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1521dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineInstrBuilder MIB = 1522dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg) 1523e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach .addFrameIndex(FrameIdx).addImm(Offset); 152474d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 152574d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach AddDefaultCC(AddDefaultPred(MIB)); 1526dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 1527dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1528dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid 1529dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim GrosbachARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 1530dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 1531dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineInstr &MI = *I; 1532dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 1533dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 1534dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1535dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 1536dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 1537dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1538dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 1539dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 1540dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1541dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 1542dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 1543dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1544dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 1545dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 1546dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 1547dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 1548dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 1549dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 1550dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 1551dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 1552dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 1553dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 15548708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1555e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1556e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 15572b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach const TargetInstrDesc &Desc = MI->getDesc(); 15582b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 15592b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 15602b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 15612b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 15622b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 15632b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 15642b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 15652b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 15662b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 15672b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 15682b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 15692b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 15702b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 15712b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 1572e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 15731ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 15742b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 15752b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 15762b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 15772b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 157874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 15792b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 15802b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 15812b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 15822b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 15832b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 15842b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 15852b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 15861ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 15872b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 15882b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 15892b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 15902b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 15911ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 15922b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 15932b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 15941ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 15952b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 15962b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 15971ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrModeT1_s: 159874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach NumBits = 5; 159974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 1600e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 160174d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 16022b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 16032b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 16042b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 16052b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 16062b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 16071ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 1608d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 1609d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 1610d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 1611d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 1612d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 1613e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 16142b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 16152b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 16162b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 16172b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 16182b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 161974d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 162074d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 162174d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 162274d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 1623fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 16246495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1625fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS) const { 16265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned i = 0; 16275ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 16285ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 16295ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 16305ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 16316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1632a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 16335ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 16345ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin while (!MI.getOperand(i).isFI()) { 16355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ++i; 16365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 16375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 16385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 16395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int FrameIndex = MI.getOperand(i).getIndex(); 1640a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 16415ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1642e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 16435ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 164462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng // Special handling of dbg_value instructions. 164562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng if (MI.isDebugValue()) { 164662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 164762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset); 1648fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 164962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng } 165062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 165148d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 1652cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 16536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 1654cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 16556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 16566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 1657cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 16586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1659cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 1660fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 16615ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1662db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 1663db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 1664db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 166519bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 1666a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1667a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1668cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 1669db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 16707e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 1671db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 1672db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 1673db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1674db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1675cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 1676a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 1677cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 16786495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 1679ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1680cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 1681cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1682cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1683cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 1684cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 1685cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1686cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1687cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 1688cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 16896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1690db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1691db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 16924371cda7f8fc21fc3192ead122ba48b0152fb0e4Jim Grosbach/// Move iterator past the next bunch of callee save load / store ops for 1693db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// the particular spill area (1: integer area 1, 2: integer area 2, 1694db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// 3: fp area, 0: don't care). 1695db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1696db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 16975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int Opc1, int Opc2, unsigned Area, 1698db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const ARMSubtarget &STI) { 1699db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin while (MBBI != MBB.end() && 17005ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 17015ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MBBI->getOperand(1).isFI()) { 1702db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Area != 0) { 1703db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin bool Done = false; 1704db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Category = 0; 1705db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (MBBI->getOperand(0).getReg()) { 1706db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1707db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1708db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 1; 1709db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1710db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1711db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = STI.isTargetDarwin() ? 2 : 1; 1712db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1713db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1714db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1715db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 3; 1716db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1717db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1718db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Done = true; 1719db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1720db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1721db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Done || Category != Area) 1722db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1723db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1724db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1725db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1726db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1727db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1728db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1729db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1730db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitPrologue(MachineFunction &MF) const { 1731db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock &MBB = MF.front(); 1732db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = MBB.begin(); 1733db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1734db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 17356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1736cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This emitPrologue does not support Thumb1!"); 17376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 1738db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1739db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned NumBytes = MFI->getStackSize(); 1740db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1741c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1742db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1743db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine the sizes of each callee-save spill areas and record which frame 1744db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // belongs to which callee-save spill areas. 1745db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1746db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FramePtrSpillFI = 0; 1747db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1748c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Allocate the vararg register save area. This is not counted in NumBytes. 1749db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 17506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1751db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1752db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1753db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 17546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1755db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return; 1756db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1757db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1758db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1759db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Reg = CSI[i].getReg(); 1760db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FI = CSI[i].getFrameIdx(); 1761db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (Reg) { 1762db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: 1763db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R5: 1764db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R6: 1765db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R7: 1766db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1767db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1768db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1769db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1770db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1771db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1772db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: 1773db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R9: 1774db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R10: 1775db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R11: 1776db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1777db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1778db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin()) { 1779db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea2Frame(FI); 1780db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS2Size += 4; 1781db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1782db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1783db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1784db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1785db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1786db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1787db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addDPRCalleeSavedAreaFrame(FI); 1788db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DPRCSSize += 8; 1789db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1790db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1791db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1792db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 1. 17936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 17945732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1795db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1796c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Set FP to point to the stack slot that contains the previous FP. 1797c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // For Darwin, FP is R7, which has now been stored in spill area 1. 1798c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Otherwise, if this is not Darwin, all the callee-saved registers go 1799c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // into spill area 1, including the FP in R11. In either case, it is 1800c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // now safe to emit this assignment. 1801ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng bool HasFP = hasFP(MF); 1802ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) { 18036495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1804db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstrBuilder MIB = 18056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1806db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addFrameIndex(FramePtrSpillFI).addImm(0); 1807db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AddDefaultCC(AddDefaultPred(MIB)); 1808db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1809db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1810db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 2. 18116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1812db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1813db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for FP callee-save spill area. 18145732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 18156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1816db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1817db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine starting offsets of spill areas. 1818db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1819db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1820db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1821ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) 1822436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912Bob Wilson AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 1823436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912Bob Wilson NumBytes); 1824db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1825db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1826db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1827db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1828e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1829db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = DPRCSOffset; 1830db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes) { 1831c5848f4ced8f9174e7141c0d2589acaafa13ff35Jim Grosbach // Adjust SP after all the callee-save spills. 18326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1833ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) 1834ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1835db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1836db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1837db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetELF() && hasFP(MF)) { 1838db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1839db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getFramePtrSpillOffset()); 1840ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1841db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1842db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1843db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1844db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1845db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 18463dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 18473dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // If we need dynamic stack realignment, do it here. 18483dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (needsStackRealignment(MF)) { 18493dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 18503dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 18517cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov if (!AFI->isThumbFunction()) { 18527cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // Emit bic sp, sp, MaxAlign 18537cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 18547cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov TII.get(ARM::BICri), ARM::SP) 18553dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addReg(ARM::SP, RegState::Kill) 18563dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addImm(MaxAlign-1))); 18577cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov } else { 18587cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // We cannot use sp as source/dest register here, thus we're emitting the 18597cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // following sequence: 18607cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // mov r4, sp 18617cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // bic r4, r4, MaxAlign 18627cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // mov sp, r4 18637cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // FIXME: It will be better just to find spare register here. 1864e9912dc553bf7e37494eb9b07e8ff880f0481a56Jakob Stoklund Olesen BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) 18657cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::SP, RegState::Kill); 18667cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 18677cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov TII.get(ARM::t2BICri), ARM::R4) 18687cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::R4, RegState::Kill) 18697cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addImm(MaxAlign-1))); 18707cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 18717cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::R4, RegState::Kill); 18727cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov } 1873ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 1874ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 18753dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 1876ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 1877ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // If the frame has variable sized objects then the epilogue must restore 1878ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // the sp from fp. 1879ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) 1880ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1881db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1882db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1883db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1884db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0; CSRegs[i]; ++i) 1885db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == CSRegs[i]) 1886db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1887db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1888db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1889db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 189077521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwinstatic bool isCSRestore(MachineInstr *MI, 1891764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach const ARMBaseInstrInfo &TII, 189277521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin const unsigned *CSRegs) { 1893e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach return ((MI->getOpcode() == (int)ARM::VLDRD || 18945732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::LDR || 18955732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::t2LDRi12) && 1896db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MI->getOperand(1).isFI() && 1897db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1898db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1899db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1900db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1901293f8d9b8800ab68c64b67f38a7f76e00126715dEvan ChengemitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1902db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = prior(MBB.end()); 19035ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng assert(MBBI->getDesc().isReturn() && 1904db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin "Can only insert epilog into returning blocks"); 190551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen unsigned RetOpcode = MBBI->getOpcode(); 1906db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = MBBI->getDebugLoc(); 1907db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1908db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 19096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1910cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This emitEpilogue does not support Thumb1!"); 19116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 19126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1913db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1914db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes = (int)MFI->getStackSize(); 1915db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1916db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1917db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 19186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1919db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1920e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach // Unwind MBBI to point to first LDR / VLDRD. 1921db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 1922db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (MBBI != MBB.begin()) { 1923db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin do 1924db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin --MBBI; 192577521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 192677521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin if (!isCSRestore(MBBI, TII, CSRegs)) 1927db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1928db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1929db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1930db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of FP callee save spill area. 1931db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1932db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getGPRCalleeSavedArea2Size() + 1933db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize()); 1934db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1935ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 1936ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // frame pointer stack slot or target is ELF and the function has FP. 1937ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (AFI->shouldRestoreSPFromFP()) { 1938db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1939ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (NumBytes) { 1940ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (isARM) 1941ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1942ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng ARMCC::AL, 0, TII); 1943ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng else 1944ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1945ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng ARMCC::AL, 0, TII); 1946ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng } else { 1947ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Thumb2 or ARM. 1948ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (isARM) 1949ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1950ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1951ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng else 1952ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1953ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng .addReg(FramePtr); 1954db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 19556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (NumBytes) 19566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1957db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1958db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 2. 1959e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 19606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1961db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1962db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 1. 19635732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 19646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1965db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1966db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to SP upon entry to the function. 19675732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 19686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1969db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1970db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 197151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 197251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 197351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Tail call return: adjust the stack pointer and jump to callee. 197451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MBBI = prior(MBB.end()); 197551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MachineOperand &JumpTarget = MBBI->getOperand(0); 197651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 197751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Jump to label or value in register. 197851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen if (RetOpcode == ARM::TCRETURNdi) { 19797835f1fcdbb58093377c9e3476f45a2638565762Dale Johannesen BuildMI(MBB, MBBI, dl, 19807835f1fcdbb58093377c9e3476f45a2638565762Dale Johannesen TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)). 198151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 198251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen JumpTarget.getTargetFlags()); 198351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNdiND) { 198410416803c1370fe1e52a7f1c431fe506be9c1ef5Dale Johannesen BuildMI(MBB, MBBI, dl, 198510416803c1370fe1e52a7f1c431fe506be9c1ef5Dale Johannesen TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)). 198651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 198751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen JumpTarget.getTargetFlags()); 198851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNri) { 19896470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). 19906470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen addReg(JumpTarget.getReg(), RegState::Kill); 199151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNriND) { 19926470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). 19936470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen addReg(JumpTarget.getReg(), RegState::Kill); 199451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } 199551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 199651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MachineInstr *NewMI = prior(MBBI); 19976470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 199851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen NewMI->addOperand(MBBI->getOperand(i)); 199951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 200051e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Delete the pseudo instruction TCRETURN. 200151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MBB.erase(MBBI); 200251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } 200351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 2004db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 20056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 2006db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 2007db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 2008c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMGenRegisterInfo.inc" 2009