ARMBaseRegisterInfo.cpp revision 21803721d538255e4d223c29b6c8d3c9e93d4d86 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMFrameLowering.h"
19#include "ARMInstrInfo.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMSubtarget.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineLocation.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RegisterScavenging.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/Target/TargetFrameLowering.h"
37#include "llvm/Target/TargetMachine.h"
38#include "llvm/Target/TargetOptions.h"
39#include "llvm/ADT/BitVector.h"
40#include "llvm/ADT/SmallVector.h"
41#include "llvm/Support/CommandLine.h"
42
43using namespace llvm;
44
45static cl::opt<bool>
46ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47          cl::desc("Force use of virtual base registers for stack load/store"));
48static cl::opt<bool>
49EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50          cl::desc("Enable pre-regalloc stack frame index allocation"));
51static cl::opt<bool>
52EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53          cl::desc("Enable use of a base pointer for complex stack frames"));
54
55ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56                                         const ARMSubtarget &sti)
57  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
58    TII(tii), STI(sti),
59    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
60    BasePtr(ARM::R6) {
61}
62
63const unsigned*
64ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65  static const unsigned CalleeSavedRegs[] = {
66    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
68
69    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
71    0
72  };
73
74  static const unsigned DarwinCalleeSavedRegs[] = {
75    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
76    // register.
77    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
78    ARM::R11, ARM::R10, ARM::R8,
79
80    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
82    0
83  };
84  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
85}
86
87BitVector ARMBaseRegisterInfo::
88getReservedRegs(const MachineFunction &MF) const {
89  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90
91  // FIXME: avoid re-calculating this every time.
92  BitVector Reserved(getNumRegs());
93  Reserved.set(ARM::SP);
94  Reserved.set(ARM::PC);
95  Reserved.set(ARM::FPSCR);
96  if (TFI->hasFP(MF))
97    Reserved.set(FramePtr);
98  if (hasBasePointer(MF))
99    Reserved.set(BasePtr);
100  // Some targets reserve R9.
101  if (STI.isR9Reserved())
102    Reserved.set(ARM::R9);
103  return Reserved;
104}
105
106bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107                                        unsigned Reg) const {
108  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
109
110  switch (Reg) {
111  default: break;
112  case ARM::SP:
113  case ARM::PC:
114    return true;
115  case ARM::R6:
116    if (hasBasePointer(MF))
117      return true;
118    break;
119  case ARM::R7:
120  case ARM::R11:
121    if (FramePtr == Reg && TFI->hasFP(MF))
122      return true;
123    break;
124  case ARM::R9:
125    return STI.isR9Reserved();
126  }
127
128  return false;
129}
130
131const TargetRegisterClass *
132ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133                                              const TargetRegisterClass *B,
134                                              unsigned SubIdx) const {
135  switch (SubIdx) {
136  default: return 0;
137  case ARM::ssub_0:
138  case ARM::ssub_1:
139  case ARM::ssub_2:
140  case ARM::ssub_3: {
141    // S sub-registers.
142    if (A->getSize() == 8) {
143      if (B == &ARM::SPR_8RegClass)
144        return &ARM::DPR_8RegClass;
145      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146      if (A == &ARM::DPR_8RegClass)
147        return A;
148      return &ARM::DPR_VFP2RegClass;
149    }
150
151    if (A->getSize() == 16) {
152      if (B == &ARM::SPR_8RegClass)
153        return &ARM::QPR_8RegClass;
154      return &ARM::QPR_VFP2RegClass;
155    }
156
157    if (A->getSize() == 32) {
158      if (B == &ARM::SPR_8RegClass)
159        return 0;  // Do not allow coalescing!
160      return &ARM::QQPR_VFP2RegClass;
161    }
162
163    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164    return 0;  // Do not allow coalescing!
165  }
166  case ARM::dsub_0:
167  case ARM::dsub_1:
168  case ARM::dsub_2:
169  case ARM::dsub_3: {
170    // D sub-registers.
171    if (A->getSize() == 16) {
172      if (B == &ARM::DPR_VFP2RegClass)
173        return &ARM::QPR_VFP2RegClass;
174      if (B == &ARM::DPR_8RegClass)
175        return 0;  // Do not allow coalescing!
176      return A;
177    }
178
179    if (A->getSize() == 32) {
180      if (B == &ARM::DPR_VFP2RegClass)
181        return &ARM::QQPR_VFP2RegClass;
182      if (B == &ARM::DPR_8RegClass)
183        return 0;  // Do not allow coalescing!
184      return A;
185    }
186
187    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188    if (B != &ARM::DPRRegClass)
189      return 0;  // Do not allow coalescing!
190    return A;
191  }
192  case ARM::dsub_4:
193  case ARM::dsub_5:
194  case ARM::dsub_6:
195  case ARM::dsub_7: {
196    // D sub-registers of QQQQ registers.
197    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
198      return A;
199    return 0;  // Do not allow coalescing!
200  }
201
202  case ARM::qsub_0:
203  case ARM::qsub_1: {
204    // Q sub-registers.
205    if (A->getSize() == 32) {
206      if (B == &ARM::QPR_VFP2RegClass)
207        return &ARM::QQPR_VFP2RegClass;
208      if (B == &ARM::QPR_8RegClass)
209        return 0;  // Do not allow coalescing!
210      return A;
211    }
212
213    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214    if (B == &ARM::QPRRegClass)
215      return A;
216    return 0;  // Do not allow coalescing!
217  }
218  case ARM::qsub_2:
219  case ARM::qsub_3: {
220    // Q sub-registers of QQQQ registers.
221    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
222      return A;
223    return 0;  // Do not allow coalescing!
224  }
225  }
226  return 0;
227}
228
229bool
230ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231                                          SmallVectorImpl<unsigned> &SubIndices,
232                                          unsigned &NewSubIdx) const {
233
234  unsigned Size = RC->getSize() * 8;
235  if (Size < 6)
236    return 0;
237
238  NewSubIdx = 0;  // Whole register.
239  unsigned NumRegs = SubIndices.size();
240  if (NumRegs == 8) {
241    // 8 D registers -> 1 QQQQ register.
242    return (Size == 512 &&
243            SubIndices[0] == ARM::dsub_0 &&
244            SubIndices[1] == ARM::dsub_1 &&
245            SubIndices[2] == ARM::dsub_2 &&
246            SubIndices[3] == ARM::dsub_3 &&
247            SubIndices[4] == ARM::dsub_4 &&
248            SubIndices[5] == ARM::dsub_5 &&
249            SubIndices[6] == ARM::dsub_6 &&
250            SubIndices[7] == ARM::dsub_7);
251  } else if (NumRegs == 4) {
252    if (SubIndices[0] == ARM::qsub_0) {
253      // 4 Q registers -> 1 QQQQ register.
254      return (Size == 512 &&
255              SubIndices[1] == ARM::qsub_1 &&
256              SubIndices[2] == ARM::qsub_2 &&
257              SubIndices[3] == ARM::qsub_3);
258    } else if (SubIndices[0] == ARM::dsub_0) {
259      // 4 D registers -> 1 QQ register.
260      if (Size >= 256 &&
261          SubIndices[1] == ARM::dsub_1 &&
262          SubIndices[2] == ARM::dsub_2 &&
263          SubIndices[3] == ARM::dsub_3) {
264        if (Size == 512)
265          NewSubIdx = ARM::qqsub_0;
266        return true;
267      }
268    } else if (SubIndices[0] == ARM::dsub_4) {
269      // 4 D registers -> 1 QQ register (2nd).
270      if (Size == 512 &&
271          SubIndices[1] == ARM::dsub_5 &&
272          SubIndices[2] == ARM::dsub_6 &&
273          SubIndices[3] == ARM::dsub_7) {
274        NewSubIdx = ARM::qqsub_1;
275        return true;
276      }
277    } else if (SubIndices[0] == ARM::ssub_0) {
278      // 4 S registers -> 1 Q register.
279      if (Size >= 128 &&
280          SubIndices[1] == ARM::ssub_1 &&
281          SubIndices[2] == ARM::ssub_2 &&
282          SubIndices[3] == ARM::ssub_3) {
283        if (Size >= 256)
284          NewSubIdx = ARM::qsub_0;
285        return true;
286      }
287    }
288  } else if (NumRegs == 2) {
289    if (SubIndices[0] == ARM::qsub_0) {
290      // 2 Q registers -> 1 QQ register.
291      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
292        if (Size == 512)
293          NewSubIdx = ARM::qqsub_0;
294        return true;
295      }
296    } else if (SubIndices[0] == ARM::qsub_2) {
297      // 2 Q registers -> 1 QQ register (2nd).
298      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299        NewSubIdx = ARM::qqsub_1;
300        return true;
301      }
302    } else if (SubIndices[0] == ARM::dsub_0) {
303      // 2 D registers -> 1 Q register.
304      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
305        if (Size >= 256)
306          NewSubIdx = ARM::qsub_0;
307        return true;
308      }
309    } else if (SubIndices[0] == ARM::dsub_2) {
310      // 2 D registers -> 1 Q register (2nd).
311      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312        NewSubIdx = ARM::qsub_1;
313        return true;
314      }
315    } else if (SubIndices[0] == ARM::dsub_4) {
316      // 2 D registers -> 1 Q register (3rd).
317      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318        NewSubIdx = ARM::qsub_2;
319        return true;
320      }
321    } else if (SubIndices[0] == ARM::dsub_6) {
322      // 2 D registers -> 1 Q register (3rd).
323      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324        NewSubIdx = ARM::qsub_3;
325        return true;
326      }
327    } else if (SubIndices[0] == ARM::ssub_0) {
328      // 2 S registers -> 1 D register.
329      if (SubIndices[1] == ARM::ssub_1) {
330        if (Size >= 128)
331          NewSubIdx = ARM::dsub_0;
332        return true;
333      }
334    } else if (SubIndices[0] == ARM::ssub_2) {
335      // 2 S registers -> 1 D register (2nd).
336      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337        NewSubIdx = ARM::dsub_1;
338        return true;
339      }
340    }
341  }
342  return false;
343}
344
345const TargetRegisterClass*
346ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
347                                                                         const {
348  const TargetRegisterClass *Super = RC;
349  TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
350  do {
351    switch (Super->getID()) {
352    case ARM::GPRRegClassID:
353    case ARM::SPRRegClassID:
354    case ARM::DPRRegClassID:
355    case ARM::QPRRegClassID:
356    case ARM::QQPRRegClassID:
357    case ARM::QQQQPRRegClassID:
358      return Super;
359    }
360    Super = *I++;
361  } while (Super);
362  return RC;
363}
364
365const TargetRegisterClass *
366ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
367  return ARM::GPRRegisterClass;
368}
369
370unsigned
371ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
372                                         MachineFunction &MF) const {
373  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
374
375  switch (RC->getID()) {
376  default:
377    return 0;
378  case ARM::tGPRRegClassID:
379    return TFI->hasFP(MF) ? 4 : 5;
380  case ARM::GPRRegClassID: {
381    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
382    return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
383  }
384  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
385  case ARM::DPRRegClassID:
386    return 32 - 10;
387  }
388}
389
390/// getAllocationOrder - Returns the register allocation order for a specified
391/// register class in the form of a pair of TargetRegisterClass iterators.
392std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
393ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
394                                        unsigned HintType, unsigned HintReg,
395                                        const MachineFunction &MF) const {
396  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
397  // Alternative register allocation orders when favoring even / odd registers
398  // of register pairs.
399
400  // No FP, R9 is available.
401  static const unsigned GPREven1[] = {
402    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
403    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
404    ARM::R9, ARM::R11
405  };
406  static const unsigned GPROdd1[] = {
407    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
408    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
409    ARM::R8, ARM::R10
410  };
411
412  // FP is R7, R9 is available.
413  static const unsigned GPREven2[] = {
414    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
415    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
416    ARM::R9, ARM::R11
417  };
418  static const unsigned GPROdd2[] = {
419    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
420    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
421    ARM::R8, ARM::R10
422  };
423
424  // FP is R11, R9 is available.
425  static const unsigned GPREven3[] = {
426    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
427    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
428    ARM::R9
429  };
430  static const unsigned GPROdd3[] = {
431    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
432    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
433    ARM::R8
434  };
435
436  // No FP, R9 is not available.
437  static const unsigned GPREven4[] = {
438    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
439    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
440    ARM::R11
441  };
442  static const unsigned GPROdd4[] = {
443    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
444    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
445    ARM::R10
446  };
447
448  // FP is R7, R9 is not available.
449  static const unsigned GPREven5[] = {
450    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
451    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
452    ARM::R11
453  };
454  static const unsigned GPROdd5[] = {
455    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
456    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
457    ARM::R10
458  };
459
460  // FP is R11, R9 is not available.
461  static const unsigned GPREven6[] = {
462    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
463    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
464  };
465  static const unsigned GPROdd6[] = {
466    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
467    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
468  };
469
470  // We only support even/odd hints for GPR and rGPR.
471  if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
472    return std::make_pair(RC->allocation_order_begin(MF),
473                          RC->allocation_order_end(MF));
474
475  if (HintType == ARMRI::RegPairEven) {
476    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
477      // It's no longer possible to fulfill this hint. Return the default
478      // allocation order.
479      return std::make_pair(RC->allocation_order_begin(MF),
480                            RC->allocation_order_end(MF));
481
482    if (!TFI->hasFP(MF)) {
483      if (!STI.isR9Reserved())
484        return std::make_pair(GPREven1,
485                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
486      else
487        return std::make_pair(GPREven4,
488                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
489    } else if (FramePtr == ARM::R7) {
490      if (!STI.isR9Reserved())
491        return std::make_pair(GPREven2,
492                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
493      else
494        return std::make_pair(GPREven5,
495                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
496    } else { // FramePtr == ARM::R11
497      if (!STI.isR9Reserved())
498        return std::make_pair(GPREven3,
499                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
500      else
501        return std::make_pair(GPREven6,
502                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
503    }
504  } else if (HintType == ARMRI::RegPairOdd) {
505    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
506      // It's no longer possible to fulfill this hint. Return the default
507      // allocation order.
508      return std::make_pair(RC->allocation_order_begin(MF),
509                            RC->allocation_order_end(MF));
510
511    if (!TFI->hasFP(MF)) {
512      if (!STI.isR9Reserved())
513        return std::make_pair(GPROdd1,
514                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
515      else
516        return std::make_pair(GPROdd4,
517                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
518    } else if (FramePtr == ARM::R7) {
519      if (!STI.isR9Reserved())
520        return std::make_pair(GPROdd2,
521                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
522      else
523        return std::make_pair(GPROdd5,
524                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
525    } else { // FramePtr == ARM::R11
526      if (!STI.isR9Reserved())
527        return std::make_pair(GPROdd3,
528                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
529      else
530        return std::make_pair(GPROdd6,
531                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
532    }
533  }
534  return std::make_pair(RC->allocation_order_begin(MF),
535                        RC->allocation_order_end(MF));
536}
537
538/// ResolveRegAllocHint - Resolves the specified register allocation hint
539/// to a physical register. Returns the physical register if it is successful.
540unsigned
541ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
542                                         const MachineFunction &MF) const {
543  if (Reg == 0 || !isPhysicalRegister(Reg))
544    return 0;
545  if (Type == 0)
546    return Reg;
547  else if (Type == (unsigned)ARMRI::RegPairOdd)
548    // Odd register.
549    return getRegisterPairOdd(Reg, MF);
550  else if (Type == (unsigned)ARMRI::RegPairEven)
551    // Even register.
552    return getRegisterPairEven(Reg, MF);
553  return 0;
554}
555
556void
557ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
558                                        MachineFunction &MF) const {
559  MachineRegisterInfo *MRI = &MF.getRegInfo();
560  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
561  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
562       Hint.first == (unsigned)ARMRI::RegPairEven) &&
563      TargetRegisterInfo::isVirtualRegister(Hint.second)) {
564    // If 'Reg' is one of the even / odd register pair and it's now changed
565    // (e.g. coalesced) into a different register. The other register of the
566    // pair allocation hint must be updated to reflect the relationship
567    // change.
568    unsigned OtherReg = Hint.second;
569    Hint = MRI->getRegAllocationHint(OtherReg);
570    if (Hint.second == Reg)
571      // Make sure the pair has not already divorced.
572      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
573  }
574}
575
576bool
577ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
578  // CortexA9 has a Write-after-write hazard for NEON registers.
579  if (!STI.isCortexA9())
580    return false;
581
582  switch (RC->getID()) {
583  case ARM::DPRRegClassID:
584  case ARM::DPR_8RegClassID:
585  case ARM::DPR_VFP2RegClassID:
586  case ARM::QPRRegClassID:
587  case ARM::QPR_8RegClassID:
588  case ARM::QPR_VFP2RegClassID:
589  case ARM::SPRRegClassID:
590  case ARM::SPR_8RegClassID:
591    // Avoid reusing S, D, and Q registers.
592    // Don't increase register pressure for QQ and QQQQ.
593    return true;
594  default:
595    return false;
596  }
597}
598
599bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
600  const MachineFrameInfo *MFI = MF.getFrameInfo();
601  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
602
603  if (!EnableBasePointer)
604    return false;
605
606  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
607    return true;
608
609  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
610  // negative range for ldr/str (255), and thumb1 is positive offsets only.
611  // It's going to be better to use the SP or Base Pointer instead. When there
612  // are variable sized objects, we can't reference off of the SP, so we
613  // reserve a Base Pointer.
614  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
615    // Conservatively estimate whether the negative offset from the frame
616    // pointer will be sufficient to reach. If a function has a smallish
617    // frame, it's less likely to have lots of spills and callee saved
618    // space, so it's all more likely to be within range of the frame pointer.
619    // If it's wrong, the scavenger will still enable access to work, it just
620    // won't be optimal.
621    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
622      return false;
623    return true;
624  }
625
626  return false;
627}
628
629bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
630  const MachineFrameInfo *MFI = MF.getFrameInfo();
631  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
632  // We can't realign the stack if:
633  // 1. Dynamic stack realignment is explicitly disabled,
634  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
635  // 3. There are VLAs in the function and the base pointer is disabled.
636  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
637          (!MFI->hasVarSizedObjects() || EnableBasePointer));
638}
639
640bool ARMBaseRegisterInfo::
641needsStackRealignment(const MachineFunction &MF) const {
642  const MachineFrameInfo *MFI = MF.getFrameInfo();
643  const Function *F = MF.getFunction();
644  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
645  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
646                               F->hasFnAttr(Attribute::StackAlignment));
647
648  return requiresRealignment && canRealignStack(MF);
649}
650
651bool ARMBaseRegisterInfo::
652cannotEliminateFrame(const MachineFunction &MF) const {
653  const MachineFrameInfo *MFI = MF.getFrameInfo();
654  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
655    return true;
656  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
657    || needsStackRealignment(MF);
658}
659
660unsigned ARMBaseRegisterInfo::getRARegister() const {
661  return ARM::LR;
662}
663
664unsigned
665ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
666  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
667
668  if (TFI->hasFP(MF))
669    return FramePtr;
670  return ARM::SP;
671}
672
673unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
674  llvm_unreachable("What is the exception register");
675  return 0;
676}
677
678unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
679  llvm_unreachable("What is the exception handler register");
680  return 0;
681}
682
683int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
684  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
685}
686
687unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
688                                              const MachineFunction &MF) const {
689  switch (Reg) {
690  default: break;
691  // Return 0 if either register of the pair is a special register.
692  // So no R12, etc.
693  case ARM::R1:
694    return ARM::R0;
695  case ARM::R3:
696    return ARM::R2;
697  case ARM::R5:
698    return ARM::R4;
699  case ARM::R7:
700    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
701      ? 0 : ARM::R6;
702  case ARM::R9:
703    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
704  case ARM::R11:
705    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
706
707  case ARM::S1:
708    return ARM::S0;
709  case ARM::S3:
710    return ARM::S2;
711  case ARM::S5:
712    return ARM::S4;
713  case ARM::S7:
714    return ARM::S6;
715  case ARM::S9:
716    return ARM::S8;
717  case ARM::S11:
718    return ARM::S10;
719  case ARM::S13:
720    return ARM::S12;
721  case ARM::S15:
722    return ARM::S14;
723  case ARM::S17:
724    return ARM::S16;
725  case ARM::S19:
726    return ARM::S18;
727  case ARM::S21:
728    return ARM::S20;
729  case ARM::S23:
730    return ARM::S22;
731  case ARM::S25:
732    return ARM::S24;
733  case ARM::S27:
734    return ARM::S26;
735  case ARM::S29:
736    return ARM::S28;
737  case ARM::S31:
738    return ARM::S30;
739
740  case ARM::D1:
741    return ARM::D0;
742  case ARM::D3:
743    return ARM::D2;
744  case ARM::D5:
745    return ARM::D4;
746  case ARM::D7:
747    return ARM::D6;
748  case ARM::D9:
749    return ARM::D8;
750  case ARM::D11:
751    return ARM::D10;
752  case ARM::D13:
753    return ARM::D12;
754  case ARM::D15:
755    return ARM::D14;
756  case ARM::D17:
757    return ARM::D16;
758  case ARM::D19:
759    return ARM::D18;
760  case ARM::D21:
761    return ARM::D20;
762  case ARM::D23:
763    return ARM::D22;
764  case ARM::D25:
765    return ARM::D24;
766  case ARM::D27:
767    return ARM::D26;
768  case ARM::D29:
769    return ARM::D28;
770  case ARM::D31:
771    return ARM::D30;
772  }
773
774  return 0;
775}
776
777unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
778                                             const MachineFunction &MF) const {
779  switch (Reg) {
780  default: break;
781  // Return 0 if either register of the pair is a special register.
782  // So no R12, etc.
783  case ARM::R0:
784    return ARM::R1;
785  case ARM::R2:
786    return ARM::R3;
787  case ARM::R4:
788    return ARM::R5;
789  case ARM::R6:
790    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
791      ? 0 : ARM::R7;
792  case ARM::R8:
793    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
794  case ARM::R10:
795    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
796
797  case ARM::S0:
798    return ARM::S1;
799  case ARM::S2:
800    return ARM::S3;
801  case ARM::S4:
802    return ARM::S5;
803  case ARM::S6:
804    return ARM::S7;
805  case ARM::S8:
806    return ARM::S9;
807  case ARM::S10:
808    return ARM::S11;
809  case ARM::S12:
810    return ARM::S13;
811  case ARM::S14:
812    return ARM::S15;
813  case ARM::S16:
814    return ARM::S17;
815  case ARM::S18:
816    return ARM::S19;
817  case ARM::S20:
818    return ARM::S21;
819  case ARM::S22:
820    return ARM::S23;
821  case ARM::S24:
822    return ARM::S25;
823  case ARM::S26:
824    return ARM::S27;
825  case ARM::S28:
826    return ARM::S29;
827  case ARM::S30:
828    return ARM::S31;
829
830  case ARM::D0:
831    return ARM::D1;
832  case ARM::D2:
833    return ARM::D3;
834  case ARM::D4:
835    return ARM::D5;
836  case ARM::D6:
837    return ARM::D7;
838  case ARM::D8:
839    return ARM::D9;
840  case ARM::D10:
841    return ARM::D11;
842  case ARM::D12:
843    return ARM::D13;
844  case ARM::D14:
845    return ARM::D15;
846  case ARM::D16:
847    return ARM::D17;
848  case ARM::D18:
849    return ARM::D19;
850  case ARM::D20:
851    return ARM::D21;
852  case ARM::D22:
853    return ARM::D23;
854  case ARM::D24:
855    return ARM::D25;
856  case ARM::D26:
857    return ARM::D27;
858  case ARM::D28:
859    return ARM::D29;
860  case ARM::D30:
861    return ARM::D31;
862  }
863
864  return 0;
865}
866
867/// emitLoadConstPool - Emits a load from constpool to materialize the
868/// specified immediate.
869void ARMBaseRegisterInfo::
870emitLoadConstPool(MachineBasicBlock &MBB,
871                  MachineBasicBlock::iterator &MBBI,
872                  DebugLoc dl,
873                  unsigned DestReg, unsigned SubIdx, int Val,
874                  ARMCC::CondCodes Pred,
875                  unsigned PredReg, unsigned MIFlags) const {
876  MachineFunction &MF = *MBB.getParent();
877  MachineConstantPool *ConstantPool = MF.getConstantPool();
878  const Constant *C =
879        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
880  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
881
882  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
883    .addReg(DestReg, getDefRegState(true), SubIdx)
884    .addConstantPoolIndex(Idx)
885    .addImm(0).addImm(Pred).addReg(PredReg)
886    .setMIFlags(MIFlags);
887}
888
889bool ARMBaseRegisterInfo::
890requiresRegisterScavenging(const MachineFunction &MF) const {
891  return true;
892}
893
894bool ARMBaseRegisterInfo::
895requiresFrameIndexScavenging(const MachineFunction &MF) const {
896  return true;
897}
898
899bool ARMBaseRegisterInfo::
900requiresVirtualBaseRegisters(const MachineFunction &MF) const {
901  return EnableLocalStackAlloc;
902}
903
904static void
905emitSPUpdate(bool isARM,
906             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
907             DebugLoc dl, const ARMBaseInstrInfo &TII,
908             int NumBytes,
909             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
910  if (isARM)
911    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
912                            Pred, PredReg, TII);
913  else
914    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
915                           Pred, PredReg, TII);
916}
917
918
919void ARMBaseRegisterInfo::
920eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
921                              MachineBasicBlock::iterator I) const {
922  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
923  if (!TFI->hasReservedCallFrame(MF)) {
924    // If we have alloca, convert as follows:
925    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
926    // ADJCALLSTACKUP   -> add, sp, sp, amount
927    MachineInstr *Old = I;
928    DebugLoc dl = Old->getDebugLoc();
929    unsigned Amount = Old->getOperand(0).getImm();
930    if (Amount != 0) {
931      // We need to keep the stack aligned properly.  To do this, we round the
932      // amount of space needed for the outgoing arguments up to the next
933      // alignment boundary.
934      unsigned Align = TFI->getStackAlignment();
935      Amount = (Amount+Align-1)/Align*Align;
936
937      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
938      assert(!AFI->isThumb1OnlyFunction() &&
939             "This eliminateCallFramePseudoInstr does not support Thumb1!");
940      bool isARM = !AFI->isThumbFunction();
941
942      // Replace the pseudo instruction with a new instruction...
943      unsigned Opc = Old->getOpcode();
944      int PIdx = Old->findFirstPredOperandIdx();
945      ARMCC::CondCodes Pred = (PIdx == -1)
946        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
947      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
948        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
949        unsigned PredReg = Old->getOperand(2).getReg();
950        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
951      } else {
952        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
953        unsigned PredReg = Old->getOperand(3).getReg();
954        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
955        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
956      }
957    }
958  }
959  MBB.erase(I);
960}
961
962int64_t ARMBaseRegisterInfo::
963getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
964  const TargetInstrDesc &Desc = MI->getDesc();
965  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
966  int64_t InstrOffs = 0;;
967  int Scale = 1;
968  unsigned ImmIdx = 0;
969  switch (AddrMode) {
970  case ARMII::AddrModeT2_i8:
971  case ARMII::AddrModeT2_i12:
972  case ARMII::AddrMode_i12:
973    InstrOffs = MI->getOperand(Idx+1).getImm();
974    Scale = 1;
975    break;
976  case ARMII::AddrMode5: {
977    // VFP address mode.
978    const MachineOperand &OffOp = MI->getOperand(Idx+1);
979    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
980    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
981      InstrOffs = -InstrOffs;
982    Scale = 4;
983    break;
984  }
985  case ARMII::AddrMode2: {
986    ImmIdx = Idx+2;
987    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
988    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
989      InstrOffs = -InstrOffs;
990    break;
991  }
992  case ARMII::AddrMode3: {
993    ImmIdx = Idx+2;
994    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
995    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
996      InstrOffs = -InstrOffs;
997    break;
998  }
999  case ARMII::AddrModeT1_s: {
1000    ImmIdx = Idx+1;
1001    InstrOffs = MI->getOperand(ImmIdx).getImm();
1002    Scale = 4;
1003    break;
1004  }
1005  default:
1006    llvm_unreachable("Unsupported addressing mode!");
1007    break;
1008  }
1009
1010  return InstrOffs * Scale;
1011}
1012
1013/// needsFrameBaseReg - Returns true if the instruction's frame index
1014/// reference would be better served by a base register other than FP
1015/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1016/// references it should create new base registers for.
1017bool ARMBaseRegisterInfo::
1018needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1019  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1020    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1021  }
1022
1023  // It's the load/store FI references that cause issues, as it can be difficult
1024  // to materialize the offset if it won't fit in the literal field. Estimate
1025  // based on the size of the local frame and some conservative assumptions
1026  // about the rest of the stack frame (note, this is pre-regalloc, so
1027  // we don't know everything for certain yet) whether this offset is likely
1028  // to be out of range of the immediate. Return true if so.
1029
1030  // We only generate virtual base registers for loads and stores, so
1031  // return false for everything else.
1032  unsigned Opc = MI->getOpcode();
1033  switch (Opc) {
1034  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1035  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1036  case ARM::t2LDRi12: case ARM::t2LDRi8:
1037  case ARM::t2STRi12: case ARM::t2STRi8:
1038  case ARM::VLDRS: case ARM::VLDRD:
1039  case ARM::VSTRS: case ARM::VSTRD:
1040  case ARM::tSTRspi: case ARM::tLDRspi:
1041    if (ForceAllBaseRegAlloc)
1042      return true;
1043    break;
1044  default:
1045    return false;
1046  }
1047
1048  // Without a virtual base register, if the function has variable sized
1049  // objects, all fixed-size local references will be via the frame pointer,
1050  // Approximate the offset and see if it's legal for the instruction.
1051  // Note that the incoming offset is based on the SP value at function entry,
1052  // so it'll be negative.
1053  MachineFunction &MF = *MI->getParent()->getParent();
1054  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1055  MachineFrameInfo *MFI = MF.getFrameInfo();
1056  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1057
1058  // Estimate an offset from the frame pointer.
1059  // Conservatively assume all callee-saved registers get pushed. R4-R6
1060  // will be earlier than the FP, so we ignore those.
1061  // R7, LR
1062  int64_t FPOffset = Offset - 8;
1063  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1064  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1065    FPOffset -= 80;
1066  // Estimate an offset from the stack pointer.
1067  // The incoming offset is relating to the SP at the start of the function,
1068  // but when we access the local it'll be relative to the SP after local
1069  // allocation, so adjust our SP-relative offset by that allocation size.
1070  Offset = -Offset;
1071  Offset += MFI->getLocalFrameSize();
1072  // Assume that we'll have at least some spill slots allocated.
1073  // FIXME: This is a total SWAG number. We should run some statistics
1074  //        and pick a real one.
1075  Offset += 128; // 128 bytes of spill slots
1076
1077  // If there is a frame pointer, try using it.
1078  // The FP is only available if there is no dynamic realignment. We
1079  // don't know for sure yet whether we'll need that, so we guess based
1080  // on whether there are any local variables that would trigger it.
1081  unsigned StackAlign = TFI->getStackAlignment();
1082  if (TFI->hasFP(MF) &&
1083      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1084    if (isFrameOffsetLegal(MI, FPOffset))
1085      return false;
1086  }
1087  // If we can reference via the stack pointer, try that.
1088  // FIXME: This (and the code that resolves the references) can be improved
1089  //        to only disallow SP relative references in the live range of
1090  //        the VLA(s). In practice, it's unclear how much difference that
1091  //        would make, but it may be worth doing.
1092  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1093    return false;
1094
1095  // The offset likely isn't legal, we want to allocate a virtual base register.
1096  return true;
1097}
1098
1099/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1100/// be a pointer to FrameIdx at the beginning of the basic block.
1101void ARMBaseRegisterInfo::
1102materializeFrameBaseRegister(MachineBasicBlock *MBB,
1103                             unsigned BaseReg, int FrameIdx,
1104                             int64_t Offset) const {
1105  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1106  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1107    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1108
1109  MachineBasicBlock::iterator Ins = MBB->begin();
1110  DebugLoc DL;                  // Defaults to "unknown"
1111  if (Ins != MBB->end())
1112    DL = Ins->getDebugLoc();
1113
1114  const TargetInstrDesc &TID = TII.get(ADDriOpc);
1115  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1116  MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this));
1117
1118  MachineInstrBuilder MIB =
1119    BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)
1120    .addFrameIndex(FrameIdx).addImm(Offset);
1121
1122  if (!AFI->isThumb1OnlyFunction())
1123    AddDefaultCC(AddDefaultPred(MIB));
1124}
1125
1126void
1127ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1128                                       unsigned BaseReg, int64_t Offset) const {
1129  MachineInstr &MI = *I;
1130  MachineBasicBlock &MBB = *MI.getParent();
1131  MachineFunction &MF = *MBB.getParent();
1132  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1133  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1134  unsigned i = 0;
1135
1136  assert(!AFI->isThumb1OnlyFunction() &&
1137         "This resolveFrameIndex does not support Thumb1!");
1138
1139  while (!MI.getOperand(i).isFI()) {
1140    ++i;
1141    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1142  }
1143  bool Done = false;
1144  if (!AFI->isThumbFunction())
1145    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1146  else {
1147    assert(AFI->isThumb2Function());
1148    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1149  }
1150  assert (Done && "Unable to resolve frame index!");
1151}
1152
1153bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1154                                             int64_t Offset) const {
1155  const TargetInstrDesc &Desc = MI->getDesc();
1156  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1157  unsigned i = 0;
1158
1159  while (!MI->getOperand(i).isFI()) {
1160    ++i;
1161    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1162  }
1163
1164  // AddrMode4 and AddrMode6 cannot handle any offset.
1165  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1166    return Offset == 0;
1167
1168  unsigned NumBits = 0;
1169  unsigned Scale = 1;
1170  bool isSigned = true;
1171  switch (AddrMode) {
1172  case ARMII::AddrModeT2_i8:
1173  case ARMII::AddrModeT2_i12:
1174    // i8 supports only negative, and i12 supports only positive, so
1175    // based on Offset sign, consider the appropriate instruction
1176    Scale = 1;
1177    if (Offset < 0) {
1178      NumBits = 8;
1179      Offset = -Offset;
1180    } else {
1181      NumBits = 12;
1182    }
1183    break;
1184  case ARMII::AddrMode5:
1185    // VFP address mode.
1186    NumBits = 8;
1187    Scale = 4;
1188    break;
1189  case ARMII::AddrMode_i12:
1190  case ARMII::AddrMode2:
1191    NumBits = 12;
1192    break;
1193  case ARMII::AddrMode3:
1194    NumBits = 8;
1195    break;
1196  case ARMII::AddrModeT1_s:
1197    NumBits = 5;
1198    Scale = 4;
1199    isSigned = false;
1200    break;
1201  default:
1202    llvm_unreachable("Unsupported addressing mode!");
1203    break;
1204  }
1205
1206  Offset += getFrameIndexInstrOffset(MI, i);
1207  // Make sure the offset is encodable for instructions that scale the
1208  // immediate.
1209  if ((Offset & (Scale-1)) != 0)
1210    return false;
1211
1212  if (isSigned && Offset < 0)
1213    Offset = -Offset;
1214
1215  unsigned Mask = (1 << NumBits) - 1;
1216  if ((unsigned)Offset <= Mask * Scale)
1217    return true;
1218
1219  return false;
1220}
1221
1222void
1223ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1224                                         int SPAdj, RegScavenger *RS) const {
1225  unsigned i = 0;
1226  MachineInstr &MI = *II;
1227  MachineBasicBlock &MBB = *MI.getParent();
1228  MachineFunction &MF = *MBB.getParent();
1229  const ARMFrameLowering *TFI =
1230    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1231  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1232  assert(!AFI->isThumb1OnlyFunction() &&
1233         "This eliminateFrameIndex does not support Thumb1!");
1234
1235  while (!MI.getOperand(i).isFI()) {
1236    ++i;
1237    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1238  }
1239
1240  int FrameIndex = MI.getOperand(i).getIndex();
1241  unsigned FrameReg;
1242
1243  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1244
1245  // Special handling of dbg_value instructions.
1246  if (MI.isDebugValue()) {
1247    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1248    MI.getOperand(i+1).ChangeToImmediate(Offset);
1249    return;
1250  }
1251
1252  // Modify MI as necessary to handle as much of 'Offset' as possible
1253  bool Done = false;
1254  if (!AFI->isThumbFunction())
1255    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1256  else {
1257    assert(AFI->isThumb2Function());
1258    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1259  }
1260  if (Done)
1261    return;
1262
1263  // If we get here, the immediate doesn't fit into the instruction.  We folded
1264  // as much as possible above, handle the rest, providing a register that is
1265  // SP+LargeImm.
1266  assert((Offset ||
1267          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1268          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1269         "This code isn't needed if offset already handled!");
1270
1271  unsigned ScratchReg = 0;
1272  int PIdx = MI.findFirstPredOperandIdx();
1273  ARMCC::CondCodes Pred = (PIdx == -1)
1274    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1275  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1276  if (Offset == 0)
1277    // Must be addrmode4/6.
1278    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1279  else {
1280    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1281    if (!AFI->isThumbFunction())
1282      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1283                              Offset, Pred, PredReg, TII);
1284    else {
1285      assert(AFI->isThumb2Function());
1286      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1287                             Offset, Pred, PredReg, TII);
1288    }
1289    // Update the original instruction to use the scratch register.
1290    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1291    if (MI.getOpcode() == ARM::t2ADDrSPi)
1292      MI.setDesc(TII.get(ARM::t2ADDri));
1293    else if (MI.getOpcode() == ARM::t2SUBrSPi)
1294      MI.setDesc(TII.get(ARM::t2SUBri));
1295  }
1296}
1297
1298#include "ARMGenRegisterInfo.inc"
1299