ARMBaseRegisterInfo.cpp revision 6db06a0866cd36fec05e6d9afb357ce8efb575e9 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47static cl::opt<bool>
48ARMDynamicStackAlign("arm-dynamic-stack-alignment", cl::Hidden, cl::init(false),
49          cl::desc("Dynamically re-align the stack as needed"));
50
51unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
52                                                   bool *isSPVFP) {
53  if (isSPVFP)
54    *isSPVFP = false;
55
56  using namespace ARM;
57  switch (RegEnum) {
58  default:
59    llvm_unreachable("Unknown ARM register!");
60  case R0:  case D0:  case Q0:  return 0;
61  case R1:  case D1:  case Q1:  return 1;
62  case R2:  case D2:  case Q2:  return 2;
63  case R3:  case D3:  case Q3:  return 3;
64  case R4:  case D4:  case Q4:  return 4;
65  case R5:  case D5:  case Q5:  return 5;
66  case R6:  case D6:  case Q6:  return 6;
67  case R7:  case D7:  case Q7:  return 7;
68  case R8:  case D8:  case Q8:  return 8;
69  case R9:  case D9:  case Q9:  return 9;
70  case R10: case D10: case Q10: return 10;
71  case R11: case D11: case Q11: return 11;
72  case R12: case D12: case Q12: return 12;
73  case SP:  case D13: case Q13: return 13;
74  case LR:  case D14: case Q14: return 14;
75  case PC:  case D15: case Q15: return 15;
76
77  case D16: return 16;
78  case D17: return 17;
79  case D18: return 18;
80  case D19: return 19;
81  case D20: return 20;
82  case D21: return 21;
83  case D22: return 22;
84  case D23: return 23;
85  case D24: return 24;
86  case D25: return 25;
87  case D26: return 27;
88  case D27: return 27;
89  case D28: return 28;
90  case D29: return 29;
91  case D30: return 30;
92  case D31: return 31;
93
94  case S0: case S1: case S2: case S3:
95  case S4: case S5: case S6: case S7:
96  case S8: case S9: case S10: case S11:
97  case S12: case S13: case S14: case S15:
98  case S16: case S17: case S18: case S19:
99  case S20: case S21: case S22: case S23:
100  case S24: case S25: case S26: case S27:
101  case S28: case S29: case S30: case S31: {
102    if (isSPVFP)
103      *isSPVFP = true;
104    switch (RegEnum) {
105    default: return 0; // Avoid compile time warning.
106    case S0: return 0;
107    case S1: return 1;
108    case S2: return 2;
109    case S3: return 3;
110    case S4: return 4;
111    case S5: return 5;
112    case S6: return 6;
113    case S7: return 7;
114    case S8: return 8;
115    case S9: return 9;
116    case S10: return 10;
117    case S11: return 11;
118    case S12: return 12;
119    case S13: return 13;
120    case S14: return 14;
121    case S15: return 15;
122    case S16: return 16;
123    case S17: return 17;
124    case S18: return 18;
125    case S19: return 19;
126    case S20: return 20;
127    case S21: return 21;
128    case S22: return 22;
129    case S23: return 23;
130    case S24: return 24;
131    case S25: return 25;
132    case S26: return 26;
133    case S27: return 27;
134    case S28: return 28;
135    case S29: return 29;
136    case S30: return 30;
137    case S31: return 31;
138    }
139  }
140  }
141}
142
143ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
144                                         const ARMSubtarget &sti)
145  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146    TII(tii), STI(sti),
147    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
148}
149
150const unsigned*
151ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152  static const unsigned CalleeSavedRegs[] = {
153    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
154    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
155
156    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
157    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
158    0
159  };
160
161  static const unsigned DarwinCalleeSavedRegs[] = {
162    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163    // register.
164    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
165    ARM::R11, ARM::R10, ARM::R8,
166
167    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
168    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
169    0
170  };
171  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
172}
173
174const TargetRegisterClass* const *
175ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
176  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
183    0
184  };
185
186  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
189    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
193    0
194  };
195
196  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
197    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
199    &ARM::GPRRegClass, &ARM::GPRRegClass,
200
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
203    0
204  };
205
206  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
207    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
208    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
209    &ARM::GPRRegClass,  &ARM::GPRRegClass,
210
211    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
213    0
214  };
215
216  if (STI.isThumb1Only()) {
217    return STI.isTargetDarwin()
218      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219  }
220  return STI.isTargetDarwin()
221    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
222}
223
224BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225  // FIXME: avoid re-calculating this everytime.
226  BitVector Reserved(getNumRegs());
227  Reserved.set(ARM::SP);
228  Reserved.set(ARM::PC);
229  if (STI.isTargetDarwin() || hasFP(MF))
230    Reserved.set(FramePtr);
231  // Some targets reserve R9.
232  if (STI.isR9Reserved())
233    Reserved.set(ARM::R9);
234  return Reserved;
235}
236
237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238                                        unsigned Reg) const {
239  switch (Reg) {
240  default: break;
241  case ARM::SP:
242  case ARM::PC:
243    return true;
244  case ARM::R7:
245  case ARM::R11:
246    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247      return true;
248    break;
249  case ARM::R9:
250    return STI.isR9Reserved();
251  }
252
253  return false;
254}
255
256const TargetRegisterClass *
257ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258                                              const TargetRegisterClass *B,
259                                              unsigned SubIdx) const {
260  switch (SubIdx) {
261  default: return 0;
262  case 1:
263  case 2:
264  case 3:
265  case 4:
266    // S sub-registers.
267    if (A->getSize() == 8) {
268      if (B == &ARM::SPR_8RegClass)
269        return &ARM::DPR_8RegClass;
270      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271      if (A == &ARM::DPR_8RegClass)
272        return A;
273      return &ARM::DPR_VFP2RegClass;
274    }
275
276    assert(A->getSize() == 16 && "Expecting a Q register class!");
277    if (B == &ARM::SPR_8RegClass)
278      return &ARM::QPR_8RegClass;
279    return &ARM::QPR_VFP2RegClass;
280  case 5:
281  case 6:
282    // D sub-registers.
283    if (B == &ARM::DPR_VFP2RegClass)
284      return &ARM::QPR_VFP2RegClass;
285    if (B == &ARM::DPR_8RegClass)
286      return &ARM::QPR_8RegClass;
287    return A;
288  }
289  return 0;
290}
291
292const TargetRegisterClass *
293ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
294  return ARM::GPRRegisterClass;
295}
296
297/// getAllocationOrder - Returns the register allocation order for a specified
298/// register class in the form of a pair of TargetRegisterClass iterators.
299std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
300ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
301                                        unsigned HintType, unsigned HintReg,
302                                        const MachineFunction &MF) const {
303  // Alternative register allocation orders when favoring even / odd registers
304  // of register pairs.
305
306  // No FP, R9 is available.
307  static const unsigned GPREven1[] = {
308    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
309    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
310    ARM::R9, ARM::R11
311  };
312  static const unsigned GPROdd1[] = {
313    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
314    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
315    ARM::R8, ARM::R10
316  };
317
318  // FP is R7, R9 is available.
319  static const unsigned GPREven2[] = {
320    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
321    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
322    ARM::R9, ARM::R11
323  };
324  static const unsigned GPROdd2[] = {
325    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
326    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
327    ARM::R8, ARM::R10
328  };
329
330  // FP is R11, R9 is available.
331  static const unsigned GPREven3[] = {
332    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
333    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
334    ARM::R9
335  };
336  static const unsigned GPROdd3[] = {
337    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
338    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
339    ARM::R8
340  };
341
342  // No FP, R9 is not available.
343  static const unsigned GPREven4[] = {
344    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
345    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
346    ARM::R11
347  };
348  static const unsigned GPROdd4[] = {
349    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
350    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
351    ARM::R10
352  };
353
354  // FP is R7, R9 is not available.
355  static const unsigned GPREven5[] = {
356    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
357    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
358    ARM::R11
359  };
360  static const unsigned GPROdd5[] = {
361    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
362    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
363    ARM::R10
364  };
365
366  // FP is R11, R9 is not available.
367  static const unsigned GPREven6[] = {
368    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
369    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
370  };
371  static const unsigned GPROdd6[] = {
372    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
373    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
374  };
375
376
377  if (HintType == ARMRI::RegPairEven) {
378    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
379      // It's no longer possible to fulfill this hint. Return the default
380      // allocation order.
381      return std::make_pair(RC->allocation_order_begin(MF),
382                            RC->allocation_order_end(MF));
383
384    if (!STI.isTargetDarwin() && !hasFP(MF)) {
385      if (!STI.isR9Reserved())
386        return std::make_pair(GPREven1,
387                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
388      else
389        return std::make_pair(GPREven4,
390                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
391    } else if (FramePtr == ARM::R7) {
392      if (!STI.isR9Reserved())
393        return std::make_pair(GPREven2,
394                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
395      else
396        return std::make_pair(GPREven5,
397                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
398    } else { // FramePtr == ARM::R11
399      if (!STI.isR9Reserved())
400        return std::make_pair(GPREven3,
401                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
402      else
403        return std::make_pair(GPREven6,
404                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
405    }
406  } else if (HintType == ARMRI::RegPairOdd) {
407    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
408      // It's no longer possible to fulfill this hint. Return the default
409      // allocation order.
410      return std::make_pair(RC->allocation_order_begin(MF),
411                            RC->allocation_order_end(MF));
412
413    if (!STI.isTargetDarwin() && !hasFP(MF)) {
414      if (!STI.isR9Reserved())
415        return std::make_pair(GPROdd1,
416                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
417      else
418        return std::make_pair(GPROdd4,
419                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
420    } else if (FramePtr == ARM::R7) {
421      if (!STI.isR9Reserved())
422        return std::make_pair(GPROdd2,
423                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
424      else
425        return std::make_pair(GPROdd5,
426                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
427    } else { // FramePtr == ARM::R11
428      if (!STI.isR9Reserved())
429        return std::make_pair(GPROdd3,
430                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
431      else
432        return std::make_pair(GPROdd6,
433                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
434    }
435  }
436  return std::make_pair(RC->allocation_order_begin(MF),
437                        RC->allocation_order_end(MF));
438}
439
440/// ResolveRegAllocHint - Resolves the specified register allocation hint
441/// to a physical register. Returns the physical register if it is successful.
442unsigned
443ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
444                                         const MachineFunction &MF) const {
445  if (Reg == 0 || !isPhysicalRegister(Reg))
446    return 0;
447  if (Type == 0)
448    return Reg;
449  else if (Type == (unsigned)ARMRI::RegPairOdd)
450    // Odd register.
451    return getRegisterPairOdd(Reg, MF);
452  else if (Type == (unsigned)ARMRI::RegPairEven)
453    // Even register.
454    return getRegisterPairEven(Reg, MF);
455  return 0;
456}
457
458void
459ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
460                                        MachineFunction &MF) const {
461  MachineRegisterInfo *MRI = &MF.getRegInfo();
462  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
463  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
464       Hint.first == (unsigned)ARMRI::RegPairEven) &&
465      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
466    // If 'Reg' is one of the even / odd register pair and it's now changed
467    // (e.g. coalesced) into a different register. The other register of the
468    // pair allocation hint must be updated to reflect the relationship
469    // change.
470    unsigned OtherReg = Hint.second;
471    Hint = MRI->getRegAllocationHint(OtherReg);
472    if (Hint.second == Reg)
473      // Make sure the pair has not already divorced.
474      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
475  }
476}
477
478static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
479  unsigned MaxAlign = 0;
480
481  for (int i = FFI->getObjectIndexBegin(),
482         e = FFI->getObjectIndexEnd(); i != e; ++i) {
483    if (FFI->isDeadObjectIndex(i))
484      continue;
485
486    unsigned Align = FFI->getObjectAlignment(i);
487    MaxAlign = std::max(MaxAlign, Align);
488  }
489
490  return MaxAlign;
491}
492
493/// hasFP - Return true if the specified function should have a dedicated frame
494/// pointer register.  This is true if the function has variable sized allocas
495/// or if frame pointer elimination is disabled.
496///
497bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
498  const MachineFrameInfo *MFI = MF.getFrameInfo();
499  return (NoFramePointerElim ||
500          needsStackRealignment(MF) ||
501          MFI->hasVarSizedObjects() ||
502          MFI->isFrameAddressTaken());
503}
504
505bool ARMBaseRegisterInfo::
506needsStackRealignment(const MachineFunction &MF) const {
507  // Only do this for ARM if explicitly enabled
508  // FIXME: Once it's passing all the tests, enable by default
509  if (!ARMDynamicStackAlign)
510    return false;
511
512  const MachineFrameInfo *MFI = MF.getFrameInfo();
513  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
514  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
515  return (RealignStack &&
516          !AFI->isThumb1OnlyFunction() &&
517          AFI->hasStackFrame() &&
518          (MFI->getMaxAlignment() > StackAlign) &&
519          !MFI->hasVarSizedObjects());
520}
521
522bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
523  const MachineFrameInfo *MFI = MF.getFrameInfo();
524  if (NoFramePointerElim && MFI->hasCalls())
525    return true;
526  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
527}
528
529/// estimateStackSize - Estimate and return the size of the frame.
530static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
531  const MachineFrameInfo *FFI = MF.getFrameInfo();
532  int Offset = 0;
533  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
534    int FixedOff = -FFI->getObjectOffset(i);
535    if (FixedOff > Offset) Offset = FixedOff;
536  }
537  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
538    if (FFI->isDeadObjectIndex(i))
539      continue;
540    Offset += FFI->getObjectSize(i);
541    unsigned Align = FFI->getObjectAlignment(i);
542    // Adjust to alignment boundary
543    Offset = (Offset+Align-1)/Align*Align;
544  }
545  return (unsigned)Offset;
546}
547
548/// estimateRSStackSizeLimit - Look at each instruction that references stack
549/// frames and return the stack size limit beyond which some of these
550/// instructions will require scratch register during their expansion later.
551unsigned
552ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
553  unsigned Limit = (1 << 12) - 1;
554  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
555    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
556         I != E; ++I) {
557      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
558        if (!I->getOperand(i).isFI()) continue;
559
560        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
561        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
562        if (AddrMode == ARMII::AddrMode3 ||
563            AddrMode == ARMII::AddrModeT2_i8)
564          return (1 << 8) - 1;
565
566        if (AddrMode == ARMII::AddrMode5 ||
567            AddrMode == ARMII::AddrModeT2_i8s4)
568          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
569
570        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
571          // When the stack offset is negative, we will end up using
572          // the i8 instructions instead.
573          return (1 << 8) - 1;
574        break; // At most one FI per instruction
575      }
576    }
577  }
578
579  return Limit;
580}
581
582void
583ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
584                                                          RegScavenger *RS) const {
585  // This tells PEI to spill the FP as if it is any other callee-save register
586  // to take advantage the eliminateFrameIndex machinery. This also ensures it
587  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
588  // to combine multiple loads / stores.
589  bool CanEliminateFrame = true;
590  bool CS1Spilled = false;
591  bool LRSpilled = false;
592  unsigned NumGPRSpills = 0;
593  SmallVector<unsigned, 4> UnspilledCS1GPRs;
594  SmallVector<unsigned, 4> UnspilledCS2GPRs;
595  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
596
597  MachineFrameInfo *MFI = MF.getFrameInfo();
598
599  // Calculate and set max stack object alignment early, so we can decide
600  // whether we will need stack realignment (and thus FP).
601  if (ARMDynamicStackAlign) {
602    unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
603                                 calculateMaxStackAlignment(MFI));
604    MFI->setMaxAlignment(MaxAlign);
605  }
606
607  // Don't spill FP if the frame can be eliminated. This is determined
608  // by scanning the callee-save registers to see if any is used.
609  const unsigned *CSRegs = getCalleeSavedRegs();
610  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
611  for (unsigned i = 0; CSRegs[i]; ++i) {
612    unsigned Reg = CSRegs[i];
613    bool Spilled = false;
614    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
615      AFI->setCSRegisterIsSpilled(Reg);
616      Spilled = true;
617      CanEliminateFrame = false;
618    } else {
619      // Check alias registers too.
620      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
621        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
622          Spilled = true;
623          CanEliminateFrame = false;
624        }
625      }
626    }
627
628    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
629        CSRegClasses[i] == ARM::tGPRRegisterClass) {
630      if (Spilled) {
631        NumGPRSpills++;
632
633        if (!STI.isTargetDarwin()) {
634          if (Reg == ARM::LR)
635            LRSpilled = true;
636          CS1Spilled = true;
637          continue;
638        }
639
640        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
641        switch (Reg) {
642        case ARM::LR:
643          LRSpilled = true;
644          // Fallthrough
645        case ARM::R4:
646        case ARM::R5:
647        case ARM::R6:
648        case ARM::R7:
649          CS1Spilled = true;
650          break;
651        default:
652          break;
653        }
654      } else {
655        if (!STI.isTargetDarwin()) {
656          UnspilledCS1GPRs.push_back(Reg);
657          continue;
658        }
659
660        switch (Reg) {
661        case ARM::R4:
662        case ARM::R5:
663        case ARM::R6:
664        case ARM::R7:
665        case ARM::LR:
666          UnspilledCS1GPRs.push_back(Reg);
667          break;
668        default:
669          UnspilledCS2GPRs.push_back(Reg);
670          break;
671        }
672      }
673    }
674  }
675
676  bool ForceLRSpill = false;
677  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
678    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
679    // Force LR to be spilled if the Thumb function size is > 2048. This enables
680    // use of BL to implement far jump. If it turns out that it's not needed
681    // then the branch fix up path will undo it.
682    if (FnSize >= (1 << 11)) {
683      CanEliminateFrame = false;
684      ForceLRSpill = true;
685    }
686  }
687
688  bool ExtraCSSpill = false;
689  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
690    AFI->setHasStackFrame(true);
691
692    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
693    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
694    if (!LRSpilled && CS1Spilled) {
695      MF.getRegInfo().setPhysRegUsed(ARM::LR);
696      AFI->setCSRegisterIsSpilled(ARM::LR);
697      NumGPRSpills++;
698      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
699                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
700      ForceLRSpill = false;
701      ExtraCSSpill = true;
702    }
703
704    // Darwin ABI requires FP to point to the stack slot that contains the
705    // previous FP.
706    if (STI.isTargetDarwin() || hasFP(MF)) {
707      MF.getRegInfo().setPhysRegUsed(FramePtr);
708      NumGPRSpills++;
709    }
710
711    // If stack and double are 8-byte aligned and we are spilling an odd number
712    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
713    // the integer and double callee save areas.
714    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
715    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
716      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
717        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
718          unsigned Reg = UnspilledCS1GPRs[i];
719          // Don't spill high register if the function is thumb1
720          if (!AFI->isThumb1OnlyFunction() ||
721              isARMLowRegister(Reg) || Reg == ARM::LR) {
722            MF.getRegInfo().setPhysRegUsed(Reg);
723            AFI->setCSRegisterIsSpilled(Reg);
724            if (!isReservedReg(MF, Reg))
725              ExtraCSSpill = true;
726            break;
727          }
728        }
729      } else if (!UnspilledCS2GPRs.empty() &&
730                 !AFI->isThumb1OnlyFunction()) {
731        unsigned Reg = UnspilledCS2GPRs.front();
732        MF.getRegInfo().setPhysRegUsed(Reg);
733        AFI->setCSRegisterIsSpilled(Reg);
734        if (!isReservedReg(MF, Reg))
735          ExtraCSSpill = true;
736      }
737    }
738
739    // Estimate if we might need to scavenge a register at some point in order
740    // to materialize a stack offset. If so, either spill one additional
741    // callee-saved register or reserve a special spill slot to facilitate
742    // register scavenging. Thumb1 needs a spill slot for stack pointer
743    // adjustments also, even when the frame itself is small.
744    if (RS && !ExtraCSSpill) {
745      MachineFrameInfo  *MFI = MF.getFrameInfo();
746      // If any of the stack slot references may be out of range of an
747      // immediate offset, make sure a register (or a spill slot) is
748      // available for the register scavenger. Note that if we're indexing
749      // off the frame pointer, the effective stack size is 4 bytes larger
750      // since the FP points to the stack slot of the previous FP.
751      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
752          >= estimateRSStackSizeLimit(MF)) {
753        // If any non-reserved CS register isn't spilled, just spill one or two
754        // extra. That should take care of it!
755        unsigned NumExtras = TargetAlign / 4;
756        SmallVector<unsigned, 2> Extras;
757        while (NumExtras && !UnspilledCS1GPRs.empty()) {
758          unsigned Reg = UnspilledCS1GPRs.back();
759          UnspilledCS1GPRs.pop_back();
760          if (!isReservedReg(MF, Reg)) {
761            Extras.push_back(Reg);
762            NumExtras--;
763          }
764        }
765        // For non-Thumb1 functions, also check for hi-reg CS registers
766        if (!AFI->isThumb1OnlyFunction()) {
767          while (NumExtras && !UnspilledCS2GPRs.empty()) {
768            unsigned Reg = UnspilledCS2GPRs.back();
769            UnspilledCS2GPRs.pop_back();
770            if (!isReservedReg(MF, Reg)) {
771              Extras.push_back(Reg);
772              NumExtras--;
773            }
774          }
775        }
776        if (Extras.size() && NumExtras == 0) {
777          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
778            MF.getRegInfo().setPhysRegUsed(Extras[i]);
779            AFI->setCSRegisterIsSpilled(Extras[i]);
780          }
781        } else if (!AFI->isThumb1OnlyFunction()) {
782          // note: Thumb1 functions spill to R12, not the stack.
783          // Reserve a slot closest to SP or frame pointer.
784          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
785          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
786                                                           RC->getAlignment()));
787        }
788      }
789    }
790  }
791
792  if (ForceLRSpill) {
793    MF.getRegInfo().setPhysRegUsed(ARM::LR);
794    AFI->setCSRegisterIsSpilled(ARM::LR);
795    AFI->setLRIsSpilledForFarJump(true);
796  }
797}
798
799unsigned ARMBaseRegisterInfo::getRARegister() const {
800  return ARM::LR;
801}
802
803unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
804  if (STI.isTargetDarwin() || hasFP(MF))
805    return FramePtr;
806  return ARM::SP;
807}
808
809unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
810  llvm_unreachable("What is the exception register");
811  return 0;
812}
813
814unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
815  llvm_unreachable("What is the exception handler register");
816  return 0;
817}
818
819int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
820  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
821}
822
823unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
824                                               const MachineFunction &MF) const {
825  switch (Reg) {
826  default: break;
827  // Return 0 if either register of the pair is a special register.
828  // So no R12, etc.
829  case ARM::R1:
830    return ARM::R0;
831  case ARM::R3:
832    return ARM::R2;
833  case ARM::R5:
834    return ARM::R4;
835  case ARM::R7:
836    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
837  case ARM::R9:
838    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
839  case ARM::R11:
840    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
841
842  case ARM::S1:
843    return ARM::S0;
844  case ARM::S3:
845    return ARM::S2;
846  case ARM::S5:
847    return ARM::S4;
848  case ARM::S7:
849    return ARM::S6;
850  case ARM::S9:
851    return ARM::S8;
852  case ARM::S11:
853    return ARM::S10;
854  case ARM::S13:
855    return ARM::S12;
856  case ARM::S15:
857    return ARM::S14;
858  case ARM::S17:
859    return ARM::S16;
860  case ARM::S19:
861    return ARM::S18;
862  case ARM::S21:
863    return ARM::S20;
864  case ARM::S23:
865    return ARM::S22;
866  case ARM::S25:
867    return ARM::S24;
868  case ARM::S27:
869    return ARM::S26;
870  case ARM::S29:
871    return ARM::S28;
872  case ARM::S31:
873    return ARM::S30;
874
875  case ARM::D1:
876    return ARM::D0;
877  case ARM::D3:
878    return ARM::D2;
879  case ARM::D5:
880    return ARM::D4;
881  case ARM::D7:
882    return ARM::D6;
883  case ARM::D9:
884    return ARM::D8;
885  case ARM::D11:
886    return ARM::D10;
887  case ARM::D13:
888    return ARM::D12;
889  case ARM::D15:
890    return ARM::D14;
891  case ARM::D17:
892    return ARM::D16;
893  case ARM::D19:
894    return ARM::D18;
895  case ARM::D21:
896    return ARM::D20;
897  case ARM::D23:
898    return ARM::D22;
899  case ARM::D25:
900    return ARM::D24;
901  case ARM::D27:
902    return ARM::D26;
903  case ARM::D29:
904    return ARM::D28;
905  case ARM::D31:
906    return ARM::D30;
907  }
908
909  return 0;
910}
911
912unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
913                                             const MachineFunction &MF) const {
914  switch (Reg) {
915  default: break;
916  // Return 0 if either register of the pair is a special register.
917  // So no R12, etc.
918  case ARM::R0:
919    return ARM::R1;
920  case ARM::R2:
921    return ARM::R3;
922  case ARM::R4:
923    return ARM::R5;
924  case ARM::R6:
925    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
926  case ARM::R8:
927    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
928  case ARM::R10:
929    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
930
931  case ARM::S0:
932    return ARM::S1;
933  case ARM::S2:
934    return ARM::S3;
935  case ARM::S4:
936    return ARM::S5;
937  case ARM::S6:
938    return ARM::S7;
939  case ARM::S8:
940    return ARM::S9;
941  case ARM::S10:
942    return ARM::S11;
943  case ARM::S12:
944    return ARM::S13;
945  case ARM::S14:
946    return ARM::S15;
947  case ARM::S16:
948    return ARM::S17;
949  case ARM::S18:
950    return ARM::S19;
951  case ARM::S20:
952    return ARM::S21;
953  case ARM::S22:
954    return ARM::S23;
955  case ARM::S24:
956    return ARM::S25;
957  case ARM::S26:
958    return ARM::S27;
959  case ARM::S28:
960    return ARM::S29;
961  case ARM::S30:
962    return ARM::S31;
963
964  case ARM::D0:
965    return ARM::D1;
966  case ARM::D2:
967    return ARM::D3;
968  case ARM::D4:
969    return ARM::D5;
970  case ARM::D6:
971    return ARM::D7;
972  case ARM::D8:
973    return ARM::D9;
974  case ARM::D10:
975    return ARM::D11;
976  case ARM::D12:
977    return ARM::D13;
978  case ARM::D14:
979    return ARM::D15;
980  case ARM::D16:
981    return ARM::D17;
982  case ARM::D18:
983    return ARM::D19;
984  case ARM::D20:
985    return ARM::D21;
986  case ARM::D22:
987    return ARM::D23;
988  case ARM::D24:
989    return ARM::D25;
990  case ARM::D26:
991    return ARM::D27;
992  case ARM::D28:
993    return ARM::D29;
994  case ARM::D30:
995    return ARM::D31;
996  }
997
998  return 0;
999}
1000
1001/// emitLoadConstPool - Emits a load from constpool to materialize the
1002/// specified immediate.
1003void ARMBaseRegisterInfo::
1004emitLoadConstPool(MachineBasicBlock &MBB,
1005                  MachineBasicBlock::iterator &MBBI,
1006                  DebugLoc dl,
1007                  unsigned DestReg, unsigned SubIdx, int Val,
1008                  ARMCC::CondCodes Pred,
1009                  unsigned PredReg) const {
1010  MachineFunction &MF = *MBB.getParent();
1011  MachineConstantPool *ConstantPool = MF.getConstantPool();
1012  Constant *C =
1013        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1014  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1015
1016  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1017    .addReg(DestReg, getDefRegState(true), SubIdx)
1018    .addConstantPoolIndex(Idx)
1019    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1020}
1021
1022bool ARMBaseRegisterInfo::
1023requiresRegisterScavenging(const MachineFunction &MF) const {
1024  return true;
1025}
1026
1027bool ARMBaseRegisterInfo::
1028requiresFrameIndexScavenging(const MachineFunction &MF) const {
1029  return true;
1030}
1031
1032// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1033// not required, we reserve argument space for call sites in the function
1034// immediately on entry to the current function. This eliminates the need for
1035// add/sub sp brackets around call sites. Returns true if the call frame is
1036// included as part of the stack frame.
1037bool ARMBaseRegisterInfo::
1038hasReservedCallFrame(MachineFunction &MF) const {
1039  const MachineFrameInfo *FFI = MF.getFrameInfo();
1040  unsigned CFSize = FFI->getMaxCallFrameSize();
1041  // It's not always a good idea to include the call frame as part of the
1042  // stack frame. ARM (especially Thumb) has small immediate offset to
1043  // address the stack frame. So a large call frame can cause poor codegen
1044  // and may even makes it impossible to scavenge a register.
1045  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1046    return false;
1047
1048  return !MF.getFrameInfo()->hasVarSizedObjects();
1049}
1050
1051static void
1052emitSPUpdate(bool isARM,
1053             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1054             DebugLoc dl, const ARMBaseInstrInfo &TII,
1055             int NumBytes,
1056             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1057  if (isARM)
1058    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1059                            Pred, PredReg, TII);
1060  else
1061    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1062                           Pred, PredReg, TII);
1063}
1064
1065
1066void ARMBaseRegisterInfo::
1067eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1068                              MachineBasicBlock::iterator I) const {
1069  if (!hasReservedCallFrame(MF)) {
1070    // If we have alloca, convert as follows:
1071    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1072    // ADJCALLSTACKUP   -> add, sp, sp, amount
1073    MachineInstr *Old = I;
1074    DebugLoc dl = Old->getDebugLoc();
1075    unsigned Amount = Old->getOperand(0).getImm();
1076    if (Amount != 0) {
1077      // We need to keep the stack aligned properly.  To do this, we round the
1078      // amount of space needed for the outgoing arguments up to the next
1079      // alignment boundary.
1080      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1081      Amount = (Amount+Align-1)/Align*Align;
1082
1083      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1084      assert(!AFI->isThumb1OnlyFunction() &&
1085             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1086      bool isARM = !AFI->isThumbFunction();
1087
1088      // Replace the pseudo instruction with a new instruction...
1089      unsigned Opc = Old->getOpcode();
1090      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1091      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1092      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1093        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1094        unsigned PredReg = Old->getOperand(2).getReg();
1095        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1096      } else {
1097        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1098        unsigned PredReg = Old->getOperand(3).getReg();
1099        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1100        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1101      }
1102    }
1103  }
1104  MBB.erase(I);
1105}
1106
1107unsigned
1108ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1109                                         int SPAdj, int *Value,
1110                                         RegScavenger *RS) const {
1111  unsigned i = 0;
1112  MachineInstr &MI = *II;
1113  MachineBasicBlock &MBB = *MI.getParent();
1114  MachineFunction &MF = *MBB.getParent();
1115  const MachineFrameInfo *MFI = MF.getFrameInfo();
1116  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1117  assert(!AFI->isThumb1OnlyFunction() &&
1118         "This eliminateFrameIndex does not support Thumb1!");
1119
1120  while (!MI.getOperand(i).isFI()) {
1121    ++i;
1122    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1123  }
1124
1125  unsigned FrameReg = ARM::SP;
1126  int FrameIndex = MI.getOperand(i).getIndex();
1127  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1128  bool isFixed = MFI->isFixedObjectIndex(FrameIndex);
1129
1130  // When doing dynamic stack realignment, all of these need to change(?)
1131  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1132    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1133  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1134    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1135  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1136    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1137  else if (needsStackRealignment(MF)) {
1138    // When dynamically realigning the stack, use the frame pointer for
1139    // parameters, and the stack pointer for locals.
1140    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1141    if (isFixed) {
1142      FrameReg = getFrameRegister(MF);
1143      Offset -= AFI->getFramePtrSpillOffset();
1144      // When referencing from the frame pointer, stack pointer adjustments
1145      // don't matter.
1146      SPAdj = 0;
1147    }
1148  } else if (hasFP(MF) && AFI->hasStackFrame()) {
1149    assert(SPAdj == 0 && "Unexpected stack offset!");
1150    if (isFixed || MFI->hasVarSizedObjects()) {
1151      // Use frame pointer to reference fixed objects unless this is a
1152      // frameless function.
1153      FrameReg = getFrameRegister(MF);
1154      Offset -= AFI->getFramePtrSpillOffset();
1155    } else if (AFI->isThumb2Function()) {
1156      // In Thumb2 mode, the negative offset is very limited.
1157      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1158      if (FPOffset >= -255 && FPOffset < 0) {
1159        FrameReg = getFrameRegister(MF);
1160        Offset = FPOffset;
1161      }
1162    }
1163  }
1164
1165  // Modify MI as necessary to handle as much of 'Offset' as possible
1166  bool Done = false;
1167  if (!AFI->isThumbFunction())
1168    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1169  else {
1170    assert(AFI->isThumb2Function());
1171    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1172  }
1173  if (Done)
1174    return 0;
1175
1176  // If we get here, the immediate doesn't fit into the instruction.  We folded
1177  // as much as possible above, handle the rest, providing a register that is
1178  // SP+LargeImm.
1179  assert((Offset ||
1180          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1181         "This code isn't needed if offset already handled!");
1182
1183  unsigned ScratchReg = 0;
1184  int PIdx = MI.findFirstPredOperandIdx();
1185  ARMCC::CondCodes Pred = (PIdx == -1)
1186    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1187  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1188  if (Offset == 0)
1189    // Must be addrmode4.
1190    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1191  else {
1192    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1193    if (Value) *Value = Offset;
1194    if (!AFI->isThumbFunction())
1195      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1196                              Offset, Pred, PredReg, TII);
1197    else {
1198      assert(AFI->isThumb2Function());
1199      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1200                             Offset, Pred, PredReg, TII);
1201    }
1202    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1203    if (!ReuseFrameIndexVals)
1204      ScratchReg = 0;
1205  }
1206  return ScratchReg;
1207}
1208
1209/// Move iterator pass the next bunch of callee save load / store ops for
1210/// the particular spill area (1: integer area 1, 2: integer area 2,
1211/// 3: fp area, 0: don't care).
1212static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1213                                   MachineBasicBlock::iterator &MBBI,
1214                                   int Opc1, int Opc2, unsigned Area,
1215                                   const ARMSubtarget &STI) {
1216  while (MBBI != MBB.end() &&
1217         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1218         MBBI->getOperand(1).isFI()) {
1219    if (Area != 0) {
1220      bool Done = false;
1221      unsigned Category = 0;
1222      switch (MBBI->getOperand(0).getReg()) {
1223      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1224      case ARM::LR:
1225        Category = 1;
1226        break;
1227      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1228        Category = STI.isTargetDarwin() ? 2 : 1;
1229        break;
1230      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1231      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1232        Category = 3;
1233        break;
1234      default:
1235        Done = true;
1236        break;
1237      }
1238      if (Done || Category != Area)
1239        break;
1240    }
1241
1242    ++MBBI;
1243  }
1244}
1245
1246void ARMBaseRegisterInfo::
1247emitPrologue(MachineFunction &MF) const {
1248  MachineBasicBlock &MBB = MF.front();
1249  MachineBasicBlock::iterator MBBI = MBB.begin();
1250  MachineFrameInfo  *MFI = MF.getFrameInfo();
1251  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1252  assert(!AFI->isThumb1OnlyFunction() &&
1253         "This emitPrologue does not suppor Thumb1!");
1254  bool isARM = !AFI->isThumbFunction();
1255  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1256  unsigned NumBytes = MFI->getStackSize();
1257  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1258  DebugLoc dl = (MBBI != MBB.end() ?
1259                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1260
1261  // Determine the sizes of each callee-save spill areas and record which frame
1262  // belongs to which callee-save spill areas.
1263  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1264  int FramePtrSpillFI = 0;
1265
1266  // Allocate the vararg register save area. This is not counted in NumBytes.
1267  if (VARegSaveSize)
1268    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1269
1270  if (!AFI->hasStackFrame()) {
1271    if (NumBytes != 0)
1272      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1273    return;
1274  }
1275
1276  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1277    unsigned Reg = CSI[i].getReg();
1278    int FI = CSI[i].getFrameIdx();
1279    switch (Reg) {
1280    case ARM::R4:
1281    case ARM::R5:
1282    case ARM::R6:
1283    case ARM::R7:
1284    case ARM::LR:
1285      if (Reg == FramePtr)
1286        FramePtrSpillFI = FI;
1287      AFI->addGPRCalleeSavedArea1Frame(FI);
1288      GPRCS1Size += 4;
1289      break;
1290    case ARM::R8:
1291    case ARM::R9:
1292    case ARM::R10:
1293    case ARM::R11:
1294      if (Reg == FramePtr)
1295        FramePtrSpillFI = FI;
1296      if (STI.isTargetDarwin()) {
1297        AFI->addGPRCalleeSavedArea2Frame(FI);
1298        GPRCS2Size += 4;
1299      } else {
1300        AFI->addGPRCalleeSavedArea1Frame(FI);
1301        GPRCS1Size += 4;
1302      }
1303      break;
1304    default:
1305      AFI->addDPRCalleeSavedAreaFrame(FI);
1306      DPRCSSize += 8;
1307    }
1308  }
1309
1310  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1311  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1312  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1313
1314  // Set FP to point to the stack slot that contains the previous FP.
1315  // For Darwin, FP is R7, which has now been stored in spill area 1.
1316  // Otherwise, if this is not Darwin, all the callee-saved registers go
1317  // into spill area 1, including the FP in R11.  In either case, it is
1318  // now safe to emit this assignment.
1319  if (STI.isTargetDarwin() || hasFP(MF)) {
1320    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1321    MachineInstrBuilder MIB =
1322      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1323      .addFrameIndex(FramePtrSpillFI).addImm(0);
1324    AddDefaultCC(AddDefaultPred(MIB));
1325  }
1326
1327  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1328  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1329
1330  // Build the new SUBri to adjust SP for FP callee-save spill area.
1331  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1332  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1333
1334  // Determine starting offsets of spill areas.
1335  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1336  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1337  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1338  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1339  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1340  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1341  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1342
1343  movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1344  NumBytes = DPRCSOffset;
1345  if (NumBytes) {
1346    // Adjust SP after all the callee-save spills.
1347    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1348  }
1349
1350  if (STI.isTargetELF() && hasFP(MF)) {
1351    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1352                             AFI->getFramePtrSpillOffset());
1353  }
1354
1355  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1356  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1357  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1358
1359  // If we need dynamic stack realignment, do it here.
1360  if (needsStackRealignment(MF)) {
1361    unsigned Opc;
1362    unsigned MaxAlign = MFI->getMaxAlignment();
1363    assert (!AFI->isThumb1OnlyFunction());
1364    Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
1365
1366    AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP)
1367                                  .addReg(ARM::SP, RegState::Kill)
1368                                  .addImm(MaxAlign-1)));
1369  }
1370}
1371
1372static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1373  for (unsigned i = 0; CSRegs[i]; ++i)
1374    if (Reg == CSRegs[i])
1375      return true;
1376  return false;
1377}
1378
1379static bool isCSRestore(MachineInstr *MI,
1380                        const ARMBaseInstrInfo &TII,
1381                        const unsigned *CSRegs) {
1382  return ((MI->getOpcode() == (int)ARM::FLDD ||
1383           MI->getOpcode() == (int)ARM::LDR ||
1384           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1385          MI->getOperand(1).isFI() &&
1386          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1387}
1388
1389void ARMBaseRegisterInfo::
1390emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1391  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1392  assert(MBBI->getDesc().isReturn() &&
1393         "Can only insert epilog into returning blocks");
1394  DebugLoc dl = MBBI->getDebugLoc();
1395  MachineFrameInfo *MFI = MF.getFrameInfo();
1396  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1397  assert(!AFI->isThumb1OnlyFunction() &&
1398         "This emitEpilogue does not suppor Thumb1!");
1399  bool isARM = !AFI->isThumbFunction();
1400
1401  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1402  int NumBytes = (int)MFI->getStackSize();
1403
1404  if (!AFI->hasStackFrame()) {
1405    if (NumBytes != 0)
1406      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1407  } else {
1408    // Unwind MBBI to point to first LDR / FLDD.
1409    const unsigned *CSRegs = getCalleeSavedRegs();
1410    if (MBBI != MBB.begin()) {
1411      do
1412        --MBBI;
1413      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1414      if (!isCSRestore(MBBI, TII, CSRegs))
1415        ++MBBI;
1416    }
1417
1418    // Move SP to start of FP callee save spill area.
1419    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1420                 AFI->getGPRCalleeSavedArea2Size() +
1421                 AFI->getDPRCalleeSavedAreaSize());
1422
1423    // Darwin ABI requires FP to point to the stack slot that contains the
1424    // previous FP.
1425    bool HasFP = hasFP(MF);
1426    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1427      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1428      // Reset SP based on frame pointer only if the stack frame extends beyond
1429      // frame pointer stack slot or target is ELF and the function has FP.
1430      if (HasFP ||
1431          AFI->getGPRCalleeSavedArea2Size() ||
1432          AFI->getDPRCalleeSavedAreaSize()  ||
1433          AFI->getDPRCalleeSavedAreaOffset()) {
1434        if (NumBytes) {
1435          if (isARM)
1436            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1437                                    ARMCC::AL, 0, TII);
1438          else
1439            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1440                                    ARMCC::AL, 0, TII);
1441        } else {
1442          // Thumb2 or ARM.
1443          if (isARM)
1444            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1445              .addReg(FramePtr)
1446              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1447          else
1448            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1449              .addReg(FramePtr);
1450        }
1451      }
1452    } else if (NumBytes)
1453      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1454
1455    // Move SP to start of integer callee save spill area 2.
1456    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1457    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1458
1459    // Move SP to start of integer callee save spill area 1.
1460    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1461    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1462
1463    // Move SP to SP upon entry to the function.
1464    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1465    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1466  }
1467
1468  if (VARegSaveSize)
1469    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1470}
1471
1472#include "ARMGenRegisterInfo.inc"
1473