ARMBaseRegisterInfo.h revision 4f54c1293af174a8002db20faf7b4f82ba4e8514 
1//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMBASEREGISTERINFO_H
15#define ARMBASEREGISTERINFO_H
16
17#include "ARM.h"
18#include "llvm/Target/TargetRegisterInfo.h"
19#include "ARMGenRegisterInfo.h.inc"
20
21namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseInstrInfo;
24  class Type;
25
26/// Register allocation hints.
27namespace ARMRI {
28  enum {
29    RegPairOdd  = 1,
30    RegPairEven = 2
31  };
32}
33
34/// isARMLowRegister - Returns true if the register is low register r0-r7.
35///
36static inline bool isARMLowRegister(unsigned Reg) {
37  using namespace ARM;
38  switch (Reg) {
39  case R0:  case R1:  case R2:  case R3:
40  case R4:  case R5:  case R6:  case R7:
41    return true;
42  default:
43    return false;
44  }
45}
46
47struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
48protected:
49  const ARMBaseInstrInfo &TII;
50  const ARMSubtarget &STI;
51
52  /// FramePtr - ARM physical register used as frame ptr.
53  unsigned FramePtr;
54
55  // Can be only subclassed.
56  explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57                               const ARMSubtarget &STI);
58
59  // Return the opcode that implements 'Op', or 0 if no opcode
60  unsigned getOpcode(int Op) const;
61
62public:
63  /// getRegisterNumbering - Given the enum value for some register, e.g.
64  /// ARM::LR, return the number that it corresponds to (e.g. 14). It
65  /// also returns true in isSPVFP if the register is a single precision
66  /// VFP register.
67  static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
68
69  /// Code Generation virtual methods...
70  const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
71
72  const TargetRegisterClass* const*
73  getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
74
75  BitVector getReservedRegs(const MachineFunction &MF) const;
76
77  /// getMatchingSuperRegClass - Return a subclass of the specified register
78  /// class A so that each register in it has a sub-register of the
79  /// specified sub-register index which is in the specified register class B.
80  virtual const TargetRegisterClass *
81  getMatchingSuperRegClass(const TargetRegisterClass *A,
82                           const TargetRegisterClass *B, unsigned Idx) const;
83
84  const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
85
86  std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
87  getAllocationOrder(const TargetRegisterClass *RC,
88                     unsigned HintType, unsigned HintReg,
89                     const MachineFunction &MF) const;
90
91  unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
92                               const MachineFunction &MF) const;
93
94  void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
95                          MachineFunction &MF) const;
96
97  bool hasFP(const MachineFunction &MF) const;
98
99  bool cannotEliminateFrame(const MachineFunction &MF) const;
100
101  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
102                                            RegScavenger *RS = NULL) const;
103
104  // Debug information queries.
105  unsigned getRARegister() const;
106  unsigned getFrameRegister(MachineFunction &MF) const;
107
108  // Exception handling queries.
109  unsigned getEHExceptionRegister() const;
110  unsigned getEHHandlerRegister() const;
111
112  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
113
114  bool isLowRegister(unsigned Reg) const;
115
116
117  /// emitLoadConstPool - Emits a load from constpool to materialize the
118  /// specified immediate.
119  virtual void emitLoadConstPool(MachineBasicBlock &MBB,
120                                 MachineBasicBlock::iterator &MBBI,
121                                 DebugLoc dl,
122                                 unsigned DestReg, unsigned SubIdx,
123                                 int Val,
124                                 ARMCC::CondCodes Pred = ARMCC::AL,
125                                 unsigned PredReg = 0) const;
126
127  /// Code Generation virtual methods...
128  virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
129
130  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
131
132  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
133
134  virtual bool hasReservedCallFrame(MachineFunction &MF) const;
135
136  virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
137                                             MachineBasicBlock &MBB,
138                                             MachineBasicBlock::iterator I) const;
139
140  virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
141                                       int SPAdj, int *Value = NULL,
142                                       RegScavenger *RS = NULL) const;
143
144  virtual void emitPrologue(MachineFunction &MF) const;
145  virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
146
147private:
148  unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
149
150  unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
151
152  unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
153};
154
155} // end namespace llvm
156
157#endif
158