ARMInstrFormats.td revision 27c016ba84f5607b3610f0ae63d36742ba0083f8
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def ArithMiscFrm : Format<11>; 37def ExtFrm : Format<12>; 38 39def VFPUnaryFrm : Format<13>; 40def VFPBinaryFrm : Format<14>; 41def VFPConv1Frm : Format<15>; 42def VFPConv2Frm : Format<16>; 43def VFPConv3Frm : Format<17>; 44def VFPConv4Frm : Format<18>; 45def VFPConv5Frm : Format<19>; 46def VFPLdStFrm : Format<20>; 47def VFPLdStMulFrm : Format<21>; 48def VFPMiscFrm : Format<22>; 49 50def ThumbFrm : Format<23>; 51 52def NEONFrm : Format<24>; 53def NEONGetLnFrm : Format<25>; 54def NEONSetLnFrm : Format<26>; 55def NEONDupFrm : Format<27>; 56 57// Misc flags. 58 59// the instruction has a Rn register operand. 60// UnaryDP - Indicates this is a unary data processing instruction, i.e. 61// it doesn't have a Rn operand. 62class UnaryDP { bit isUnaryDataProc = 1; } 63 64// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 65// a 16-bit Thumb instruction if certain conditions are met. 66class Xform16Bit { bit canXformTo16Bit = 1; } 67 68//===----------------------------------------------------------------------===// 69// ARM Instruction flags. These need to match ARMInstrInfo.h. 70// 71 72// Addressing mode. 73class AddrMode<bits<4> val> { 74 bits<4> Value = val; 75} 76def AddrModeNone : AddrMode<0>; 77def AddrMode1 : AddrMode<1>; 78def AddrMode2 : AddrMode<2>; 79def AddrMode3 : AddrMode<3>; 80def AddrMode4 : AddrMode<4>; 81def AddrMode5 : AddrMode<5>; 82def AddrMode6 : AddrMode<6>; 83def AddrModeT1_1 : AddrMode<7>; 84def AddrModeT1_2 : AddrMode<8>; 85def AddrModeT1_4 : AddrMode<9>; 86def AddrModeT1_s : AddrMode<10>; 87def AddrModeT2_i12: AddrMode<11>; 88def AddrModeT2_i8 : AddrMode<12>; 89def AddrModeT2_so : AddrMode<13>; 90def AddrModeT2_pc : AddrMode<14>; 91def AddrModeT2_i8s4 : AddrMode<15>; 92 93// Instruction size. 94class SizeFlagVal<bits<3> val> { 95 bits<3> Value = val; 96} 97def SizeInvalid : SizeFlagVal<0>; // Unset. 98def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 99def Size8Bytes : SizeFlagVal<2>; 100def Size4Bytes : SizeFlagVal<3>; 101def Size2Bytes : SizeFlagVal<4>; 102 103// Load / store index mode. 104class IndexMode<bits<2> val> { 105 bits<2> Value = val; 106} 107def IndexModeNone : IndexMode<0>; 108def IndexModePre : IndexMode<1>; 109def IndexModePost : IndexMode<2>; 110 111//===----------------------------------------------------------------------===// 112 113// ARM special operands. 114// 115 116// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 117// register whose default is 0 (no register). 118def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 119 (ops (i32 14), (i32 zero_reg))> { 120 let PrintMethod = "printPredicateOperand"; 121} 122 123// Conditional code result for instructions whose 's' bit is set, e.g. subs. 124def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 125 let PrintMethod = "printSBitModifierOperand"; 126} 127 128// Same as cc_out except it defaults to setting CPSR. 129def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 130 let PrintMethod = "printSBitModifierOperand"; 131} 132 133//===----------------------------------------------------------------------===// 134 135// ARM Instruction templates. 136// 137 138class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 139 Format f, string cstr> 140 : Instruction { 141 field bits<32> Inst; 142 143 let Namespace = "ARM"; 144 145 // TSFlagsFields 146 AddrMode AM = am; 147 bits<4> AddrModeBits = AM.Value; 148 149 SizeFlagVal SZ = sz; 150 bits<3> SizeFlag = SZ.Value; 151 152 IndexMode IM = im; 153 bits<2> IndexModeBits = IM.Value; 154 155 Format F = f; 156 bits<5> Form = F.Value; 157 158 // 159 // Attributes specific to ARM instructions... 160 // 161 bit isUnaryDataProc = 0; 162 bit canXformTo16Bit = 0; 163 164 let Constraints = cstr; 165} 166 167class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 168 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 169 let OutOperandList = oops; 170 let InOperandList = iops; 171 let AsmString = asm; 172 let Pattern = pattern; 173} 174 175// Almost all ARM instructions are predicable. 176class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 177 IndexMode im, Format f, string opc, string asm, string cstr, 178 list<dag> pattern> 179 : InstARM<am, sz, im, f, cstr> { 180 let OutOperandList = oops; 181 let InOperandList = !con(iops, (ops pred:$p)); 182 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 183 let Pattern = pattern; 184 list<Predicate> Predicates = [IsARM]; 185} 186 187// Same as I except it can optionally modify CPSR. Note it's modeled as 188// an input operand since by default it's a zero register. It will 189// become an implicit def once it's "flipped". 190class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 191 IndexMode im, Format f, string opc, string asm, string cstr, 192 list<dag> pattern> 193 : InstARM<am, sz, im, f, cstr> { 194 let OutOperandList = oops; 195 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 196 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 197 let Pattern = pattern; 198 list<Predicate> Predicates = [IsARM]; 199} 200 201// Special cases 202class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 203 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 204 : InstARM<am, sz, im, f, cstr> { 205 let OutOperandList = oops; 206 let InOperandList = iops; 207 let AsmString = asm; 208 let Pattern = pattern; 209 list<Predicate> Predicates = [IsARM]; 210} 211 212class AI<dag oops, dag iops, Format f, string opc, 213 string asm, list<dag> pattern> 214 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 215 asm, "", pattern>; 216class AsI<dag oops, dag iops, Format f, string opc, 217 string asm, list<dag> pattern> 218 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 219 asm, "", pattern>; 220class AXI<dag oops, dag iops, Format f, string asm, 221 list<dag> pattern> 222 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 223 "", pattern>; 224 225// Ctrl flow instructions 226class ABI<bits<4> opcod, dag oops, dag iops, string opc, 227 string asm, list<dag> pattern> 228 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc, 229 asm, "", pattern> { 230 let Inst{27-24} = opcod; 231} 232class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 233 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm, 234 "", pattern> { 235 let Inst{27-24} = opcod; 236} 237class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern> 238 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm, 239 "", pattern>; 240 241// BR_JT instructions 242class JTI<dag oops, dag iops, string asm, list<dag> pattern> 243 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, 244 asm, "", pattern>; 245 246// addrmode1 instructions 247class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 248 string asm, list<dag> pattern> 249 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 250 asm, "", pattern> { 251 let Inst{24-21} = opcod; 252 let Inst{27-26} = {0,0}; 253} 254class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 255 string asm, list<dag> pattern> 256 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 257 asm, "", pattern> { 258 let Inst{24-21} = opcod; 259 let Inst{27-26} = {0,0}; 260} 261class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 262 list<dag> pattern> 263 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 264 "", pattern> { 265 let Inst{24-21} = opcod; 266 let Inst{27-26} = {0,0}; 267} 268class AI1x2<dag oops, dag iops, Format f, string opc, 269 string asm, list<dag> pattern> 270 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 271 asm, "", pattern>; 272 273 274// addrmode2 loads and stores 275class AI2<dag oops, dag iops, Format f, string opc, 276 string asm, list<dag> pattern> 277 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 278 asm, "", pattern> { 279 let Inst{27-26} = {0,1}; 280} 281 282// loads 283class AI2ldw<dag oops, dag iops, Format f, string opc, 284 string asm, list<dag> pattern> 285 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 286 asm, "", pattern> { 287 let Inst{20} = 1; // L bit 288 let Inst{21} = 0; // W bit 289 let Inst{22} = 0; // B bit 290 let Inst{24} = 1; // P bit 291 let Inst{27-26} = {0,1}; 292} 293class AXI2ldw<dag oops, dag iops, Format f, string asm, 294 list<dag> pattern> 295 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 296 asm, "", pattern> { 297 let Inst{20} = 1; // L bit 298 let Inst{21} = 0; // W bit 299 let Inst{22} = 0; // B bit 300 let Inst{24} = 1; // P bit 301 let Inst{27-26} = {0,1}; 302} 303class AI2ldb<dag oops, dag iops, Format f, string opc, 304 string asm, list<dag> pattern> 305 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 306 asm, "", pattern> { 307 let Inst{20} = 1; // L bit 308 let Inst{21} = 0; // W bit 309 let Inst{22} = 1; // B bit 310 let Inst{24} = 1; // P bit 311 let Inst{27-26} = {0,1}; 312} 313class AXI2ldb<dag oops, dag iops, Format f, string asm, 314 list<dag> pattern> 315 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 316 asm, "", pattern> { 317 let Inst{20} = 1; // L bit 318 let Inst{21} = 0; // W bit 319 let Inst{22} = 1; // B bit 320 let Inst{24} = 1; // P bit 321 let Inst{27-26} = {0,1}; 322} 323 324// stores 325class AI2stw<dag oops, dag iops, Format f, string opc, 326 string asm, list<dag> pattern> 327 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 328 asm, "", pattern> { 329 let Inst{20} = 0; // L bit 330 let Inst{21} = 0; // W bit 331 let Inst{22} = 0; // B bit 332 let Inst{24} = 1; // P bit 333 let Inst{27-26} = {0,1}; 334} 335class AXI2stw<dag oops, dag iops, Format f, string asm, 336 list<dag> pattern> 337 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 338 asm, "", pattern> { 339 let Inst{20} = 0; // L bit 340 let Inst{21} = 0; // W bit 341 let Inst{22} = 0; // B bit 342 let Inst{24} = 1; // P bit 343 let Inst{27-26} = {0,1}; 344} 345class AI2stb<dag oops, dag iops, Format f, string opc, 346 string asm, list<dag> pattern> 347 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 348 asm, "", pattern> { 349 let Inst{20} = 0; // L bit 350 let Inst{21} = 0; // W bit 351 let Inst{22} = 1; // B bit 352 let Inst{24} = 1; // P bit 353 let Inst{27-26} = {0,1}; 354} 355class AXI2stb<dag oops, dag iops, Format f, string asm, 356 list<dag> pattern> 357 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 358 asm, "", pattern> { 359 let Inst{20} = 0; // L bit 360 let Inst{21} = 0; // W bit 361 let Inst{22} = 1; // B bit 362 let Inst{24} = 1; // P bit 363 let Inst{27-26} = {0,1}; 364} 365 366// Pre-indexed loads 367class AI2ldwpr<dag oops, dag iops, Format f, string opc, 368 string asm, string cstr, list<dag> pattern> 369 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 370 asm, cstr, pattern> { 371 let Inst{20} = 1; // L bit 372 let Inst{21} = 1; // W bit 373 let Inst{22} = 0; // B bit 374 let Inst{24} = 1; // P bit 375 let Inst{27-26} = {0,1}; 376} 377class AI2ldbpr<dag oops, dag iops, Format f, string opc, 378 string asm, string cstr, list<dag> pattern> 379 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 380 asm, cstr, pattern> { 381 let Inst{20} = 1; // L bit 382 let Inst{21} = 1; // W bit 383 let Inst{22} = 1; // B bit 384 let Inst{24} = 1; // P bit 385 let Inst{27-26} = {0,1}; 386} 387 388// Pre-indexed stores 389class AI2stwpr<dag oops, dag iops, Format f, string opc, 390 string asm, string cstr, list<dag> pattern> 391 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 392 asm, cstr, pattern> { 393 let Inst{20} = 0; // L bit 394 let Inst{21} = 1; // W bit 395 let Inst{22} = 0; // B bit 396 let Inst{24} = 1; // P bit 397 let Inst{27-26} = {0,1}; 398} 399class AI2stbpr<dag oops, dag iops, Format f, string opc, 400 string asm, string cstr, list<dag> pattern> 401 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 402 asm, cstr, pattern> { 403 let Inst{20} = 0; // L bit 404 let Inst{21} = 1; // W bit 405 let Inst{22} = 1; // B bit 406 let Inst{24} = 1; // P bit 407 let Inst{27-26} = {0,1}; 408} 409 410// Post-indexed loads 411class AI2ldwpo<dag oops, dag iops, Format f, string opc, 412 string asm, string cstr, list<dag> pattern> 413 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 414 asm, cstr,pattern> { 415 let Inst{20} = 1; // L bit 416 let Inst{21} = 0; // W bit 417 let Inst{22} = 0; // B bit 418 let Inst{24} = 0; // P bit 419 let Inst{27-26} = {0,1}; 420} 421class AI2ldbpo<dag oops, dag iops, Format f, string opc, 422 string asm, string cstr, list<dag> pattern> 423 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 424 asm, cstr,pattern> { 425 let Inst{20} = 1; // L bit 426 let Inst{21} = 0; // W bit 427 let Inst{22} = 1; // B bit 428 let Inst{24} = 0; // P bit 429 let Inst{27-26} = {0,1}; 430} 431 432// Post-indexed stores 433class AI2stwpo<dag oops, dag iops, Format f, string opc, 434 string asm, string cstr, list<dag> pattern> 435 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 436 asm, cstr,pattern> { 437 let Inst{20} = 0; // L bit 438 let Inst{21} = 0; // W bit 439 let Inst{22} = 0; // B bit 440 let Inst{24} = 0; // P bit 441 let Inst{27-26} = {0,1}; 442} 443class AI2stbpo<dag oops, dag iops, Format f, string opc, 444 string asm, string cstr, list<dag> pattern> 445 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 446 asm, cstr,pattern> { 447 let Inst{20} = 0; // L bit 448 let Inst{21} = 0; // W bit 449 let Inst{22} = 1; // B bit 450 let Inst{24} = 0; // P bit 451 let Inst{27-26} = {0,1}; 452} 453 454// addrmode3 instructions 455class AI3<dag oops, dag iops, Format f, string opc, 456 string asm, list<dag> pattern> 457 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 458 asm, "", pattern>; 459class AXI3<dag oops, dag iops, Format f, string asm, 460 list<dag> pattern> 461 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 462 "", pattern>; 463 464// loads 465class AI3ldh<dag oops, dag iops, Format f, string opc, 466 string asm, list<dag> pattern> 467 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 468 asm, "", pattern> { 469 let Inst{4} = 1; 470 let Inst{5} = 1; // H bit 471 let Inst{6} = 0; // S bit 472 let Inst{7} = 1; 473 let Inst{20} = 1; // L bit 474 let Inst{21} = 0; // W bit 475 let Inst{24} = 1; // P bit 476 let Inst{27-25} = 0b000; 477} 478class AXI3ldh<dag oops, dag iops, Format f, string asm, 479 list<dag> pattern> 480 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 481 asm, "", pattern> { 482 let Inst{4} = 1; 483 let Inst{5} = 1; // H bit 484 let Inst{6} = 0; // S bit 485 let Inst{7} = 1; 486 let Inst{20} = 1; // L bit 487 let Inst{21} = 0; // W bit 488 let Inst{24} = 1; // P bit 489} 490class AI3ldsh<dag oops, dag iops, Format f, string opc, 491 string asm, list<dag> pattern> 492 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 493 asm, "", pattern> { 494 let Inst{4} = 1; 495 let Inst{5} = 1; // H bit 496 let Inst{6} = 1; // S bit 497 let Inst{7} = 1; 498 let Inst{20} = 1; // L bit 499 let Inst{21} = 0; // W bit 500 let Inst{24} = 1; // P bit 501 let Inst{27-25} = 0b000; 502} 503class AXI3ldsh<dag oops, dag iops, Format f, string asm, 504 list<dag> pattern> 505 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 506 asm, "", pattern> { 507 let Inst{4} = 1; 508 let Inst{5} = 1; // H bit 509 let Inst{6} = 1; // S bit 510 let Inst{7} = 1; 511 let Inst{20} = 1; // L bit 512 let Inst{21} = 0; // W bit 513 let Inst{24} = 1; // P bit 514} 515class AI3ldsb<dag oops, dag iops, Format f, string opc, 516 string asm, list<dag> pattern> 517 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 518 asm, "", pattern> { 519 let Inst{4} = 1; 520 let Inst{5} = 0; // H bit 521 let Inst{6} = 1; // S bit 522 let Inst{7} = 1; 523 let Inst{20} = 1; // L bit 524 let Inst{21} = 0; // W bit 525 let Inst{24} = 1; // P bit 526 let Inst{27-25} = 0b000; 527} 528class AXI3ldsb<dag oops, dag iops, Format f, string asm, 529 list<dag> pattern> 530 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 531 asm, "", pattern> { 532 let Inst{4} = 1; 533 let Inst{5} = 0; // H bit 534 let Inst{6} = 1; // S bit 535 let Inst{7} = 1; 536 let Inst{20} = 1; // L bit 537 let Inst{21} = 0; // W bit 538 let Inst{24} = 1; // P bit 539} 540class AI3ldd<dag oops, dag iops, Format f, string opc, 541 string asm, list<dag> pattern> 542 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 543 asm, "", pattern> { 544 let Inst{4} = 1; 545 let Inst{5} = 0; // H bit 546 let Inst{6} = 1; // S bit 547 let Inst{7} = 1; 548 let Inst{20} = 0; // L bit 549 let Inst{21} = 0; // W bit 550 let Inst{24} = 1; // P bit 551 let Inst{27-25} = 0b000; 552} 553 554// stores 555class AI3sth<dag oops, dag iops, Format f, string opc, 556 string asm, list<dag> pattern> 557 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 558 asm, "", pattern> { 559 let Inst{4} = 1; 560 let Inst{5} = 1; // H bit 561 let Inst{6} = 0; // S bit 562 let Inst{7} = 1; 563 let Inst{20} = 0; // L bit 564 let Inst{21} = 0; // W bit 565 let Inst{24} = 1; // P bit 566 let Inst{27-25} = 0b000; 567} 568class AXI3sth<dag oops, dag iops, Format f, string asm, 569 list<dag> pattern> 570 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 571 asm, "", pattern> { 572 let Inst{4} = 1; 573 let Inst{5} = 1; // H bit 574 let Inst{6} = 0; // S bit 575 let Inst{7} = 1; 576 let Inst{20} = 0; // L bit 577 let Inst{21} = 0; // W bit 578 let Inst{24} = 1; // P bit 579} 580class AI3std<dag oops, dag iops, Format f, string opc, 581 string asm, list<dag> pattern> 582 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 583 asm, "", pattern> { 584 let Inst{4} = 1; 585 let Inst{5} = 1; // H bit 586 let Inst{6} = 1; // S bit 587 let Inst{7} = 1; 588 let Inst{20} = 0; // L bit 589 let Inst{21} = 0; // W bit 590 let Inst{24} = 1; // P bit 591 let Inst{27-25} = 0b000; 592} 593 594// Pre-indexed loads 595class AI3ldhpr<dag oops, dag iops, Format f, string opc, 596 string asm, string cstr, list<dag> pattern> 597 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 598 asm, cstr, pattern> { 599 let Inst{4} = 1; 600 let Inst{5} = 1; // H bit 601 let Inst{6} = 0; // S bit 602 let Inst{7} = 1; 603 let Inst{20} = 1; // L bit 604 let Inst{21} = 1; // W bit 605 let Inst{24} = 1; // P bit 606 let Inst{27-25} = 0b000; 607} 608class AI3ldshpr<dag oops, dag iops, Format f, string opc, 609 string asm, string cstr, list<dag> pattern> 610 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 611 asm, cstr, pattern> { 612 let Inst{4} = 1; 613 let Inst{5} = 1; // H bit 614 let Inst{6} = 1; // S bit 615 let Inst{7} = 1; 616 let Inst{20} = 1; // L bit 617 let Inst{21} = 1; // W bit 618 let Inst{24} = 1; // P bit 619 let Inst{27-25} = 0b000; 620} 621class AI3ldsbpr<dag oops, dag iops, Format f, string opc, 622 string asm, string cstr, list<dag> pattern> 623 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 624 asm, cstr, pattern> { 625 let Inst{4} = 1; 626 let Inst{5} = 0; // H bit 627 let Inst{6} = 1; // S bit 628 let Inst{7} = 1; 629 let Inst{20} = 1; // L bit 630 let Inst{21} = 1; // W bit 631 let Inst{24} = 1; // P bit 632 let Inst{27-25} = 0b000; 633} 634 635// Pre-indexed stores 636class AI3sthpr<dag oops, dag iops, Format f, string opc, 637 string asm, string cstr, list<dag> pattern> 638 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 639 asm, cstr, pattern> { 640 let Inst{4} = 1; 641 let Inst{5} = 1; // H bit 642 let Inst{6} = 0; // S bit 643 let Inst{7} = 1; 644 let Inst{20} = 0; // L bit 645 let Inst{21} = 1; // W bit 646 let Inst{24} = 1; // P bit 647 let Inst{27-25} = 0b000; 648} 649 650// Post-indexed loads 651class AI3ldhpo<dag oops, dag iops, Format f, string opc, 652 string asm, string cstr, list<dag> pattern> 653 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 654 asm, cstr,pattern> { 655 let Inst{4} = 1; 656 let Inst{5} = 1; // H bit 657 let Inst{6} = 0; // S bit 658 let Inst{7} = 1; 659 let Inst{20} = 1; // L bit 660 let Inst{21} = 1; // W bit 661 let Inst{24} = 0; // P bit 662 let Inst{27-25} = 0b000; 663} 664class AI3ldshpo<dag oops, dag iops, Format f, string opc, 665 string asm, string cstr, list<dag> pattern> 666 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 667 asm, cstr,pattern> { 668 let Inst{4} = 1; 669 let Inst{5} = 1; // H bit 670 let Inst{6} = 1; // S bit 671 let Inst{7} = 1; 672 let Inst{20} = 1; // L bit 673 let Inst{21} = 1; // W bit 674 let Inst{24} = 0; // P bit 675 let Inst{27-25} = 0b000; 676} 677class AI3ldsbpo<dag oops, dag iops, Format f, string opc, 678 string asm, string cstr, list<dag> pattern> 679 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 680 asm, cstr,pattern> { 681 let Inst{4} = 1; 682 let Inst{5} = 0; // H bit 683 let Inst{6} = 1; // S bit 684 let Inst{7} = 1; 685 let Inst{20} = 1; // L bit 686 let Inst{21} = 1; // W bit 687 let Inst{24} = 0; // P bit 688 let Inst{27-25} = 0b000; 689} 690 691// Post-indexed stores 692class AI3sthpo<dag oops, dag iops, Format f, string opc, 693 string asm, string cstr, list<dag> pattern> 694 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 695 asm, cstr,pattern> { 696 let Inst{4} = 1; 697 let Inst{5} = 1; // H bit 698 let Inst{6} = 0; // S bit 699 let Inst{7} = 1; 700 let Inst{20} = 0; // L bit 701 let Inst{21} = 1; // W bit 702 let Inst{24} = 0; // P bit 703 let Inst{27-25} = 0b000; 704} 705 706 707// addrmode4 instructions 708class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> 709 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 710 "", pattern> { 711 let Inst{20} = 1; // L bit 712 let Inst{22} = 0; // S bit 713 let Inst{27-25} = 0b100; 714} 715class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> 716 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 717 "", pattern> { 718 let Inst{20} = 0; // L bit 719 let Inst{22} = 0; // S bit 720 let Inst{27-25} = 0b100; 721} 722 723// Unsigned multiply, multiply-accumulate instructions. 724class AMul1I<bits<7> opcod, dag oops, dag iops, string opc, 725 string asm, list<dag> pattern> 726 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 727 asm, "", pattern> { 728 let Inst{7-4} = 0b1001; 729 let Inst{20} = 0; // S bit 730 let Inst{27-21} = opcod; 731} 732class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, 733 string asm, list<dag> pattern> 734 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 735 asm, "", pattern> { 736 let Inst{7-4} = 0b1001; 737 let Inst{27-21} = opcod; 738} 739 740// Most significant word multiply 741class AMul2I<bits<7> opcod, dag oops, dag iops, string opc, 742 string asm, list<dag> pattern> 743 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 744 asm, "", pattern> { 745 let Inst{7-4} = 0b1001; 746 let Inst{20} = 1; 747 let Inst{27-21} = opcod; 748} 749 750// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 751class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, 752 string asm, list<dag> pattern> 753 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 754 asm, "", pattern> { 755 let Inst{4} = 0; 756 let Inst{7} = 1; 757 let Inst{20} = 0; 758 let Inst{27-21} = opcod; 759} 760 761// Extend instructions. 762class AExtI<bits<8> opcod, dag oops, dag iops, string opc, 763 string asm, list<dag> pattern> 764 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc, 765 asm, "", pattern> { 766 let Inst{7-4} = 0b0111; 767 let Inst{27-20} = opcod; 768} 769 770// Misc Arithmetic instructions. 771class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc, 772 string asm, list<dag> pattern> 773 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc, 774 asm, "", pattern> { 775 let Inst{27-20} = opcod; 776} 777 778//===----------------------------------------------------------------------===// 779 780// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 781class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 782 list<Predicate> Predicates = [IsARM]; 783} 784class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 785 list<Predicate> Predicates = [IsARM, HasV5TE]; 786} 787class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 788 list<Predicate> Predicates = [IsARM, HasV6]; 789} 790 791//===----------------------------------------------------------------------===// 792// 793// Thumb Instruction Format Definitions. 794// 795 796// TI - Thumb instruction. 797 798class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 799 string asm, string cstr, list<dag> pattern> 800 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 801 let OutOperandList = oops; 802 let InOperandList = iops; 803 let AsmString = asm; 804 let Pattern = pattern; 805 list<Predicate> Predicates = [IsThumb]; 806} 807 808class TI<dag oops, dag iops, string asm, list<dag> pattern> 809 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, asm, "", pattern>; 810 811// BL, BLX(1) are translated by assembler into two instructions 812class TIx2<dag oops, dag iops, string asm, list<dag> pattern> 813 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>; 814 815// BR_JT instructions 816class TJTI<dag oops, dag iops, string asm, list<dag> pattern> 817 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, asm, "", pattern>; 818 819// Thumb1 only 820class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 821 string asm, string cstr, list<dag> pattern> 822 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 823 let OutOperandList = oops; 824 let InOperandList = iops; 825 let AsmString = asm; 826 let Pattern = pattern; 827 list<Predicate> Predicates = [IsThumb1Only]; 828} 829 830class T1I<dag oops, dag iops, string asm, list<dag> pattern> 831 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, asm, "", pattern>; 832class T1Ix2<dag oops, dag iops, string asm, list<dag> pattern> 833 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>; 834class T1JTI<dag oops, dag iops, string asm, list<dag> pattern> 835 : Thumb1I<oops, iops, AddrModeNone, SizeSpecial, asm, "", pattern>; 836 837// Two-address instructions 838class T1It<dag oops, dag iops, string asm, list<dag> pattern> 839 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; 840 841// Thumb1 instruction that can either be predicated or set CPSR. 842class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 843 string opc, string asm, string cstr, list<dag> pattern> 844 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 845 let OutOperandList = !con(oops, (ops s_cc_out:$s)); 846 let InOperandList = !con(iops, (ops pred:$p)); 847 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 848 let Pattern = pattern; 849 list<Predicate> Predicates = [IsThumb1Only]; 850} 851 852class T1sI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 853 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, opc, asm, "", pattern>; 854 855// Two-address instructions 856class T1sIt<dag oops, dag iops, string opc, string asm, list<dag> pattern> 857 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, opc, asm, 858 "$lhs = $dst", pattern>; 859 860// Thumb1 instruction that can be predicated. 861class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 862 string opc, string asm, string cstr, list<dag> pattern> 863 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 864 let OutOperandList = oops; 865 let InOperandList = !con(iops, (ops pred:$p)); 866 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 867 let Pattern = pattern; 868 list<Predicate> Predicates = [IsThumb1Only]; 869} 870 871class T1pI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 872 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, opc, asm, "", pattern>; 873 874// Two-address instructions 875class T1pIt<dag oops, dag iops, string opc, string asm, list<dag> pattern> 876 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, opc, asm, 877 "$lhs = $dst", pattern>; 878 879class T1pI1<dag oops, dag iops, string opc, string asm, list<dag> pattern> 880 : Thumb1pI<oops, iops, AddrModeT1_1, Size2Bytes, opc, asm, "", pattern>; 881class T1pI2<dag oops, dag iops, string opc, string asm, list<dag> pattern> 882 : Thumb1pI<oops, iops, AddrModeT1_2, Size2Bytes, opc, asm, "", pattern>; 883class T1pI4<dag oops, dag iops, string opc, string asm, list<dag> pattern> 884 : Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, opc, asm, "", pattern>; 885class T1pIs<dag oops, dag iops, string opc, string asm, list<dag> pattern> 886 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, opc, asm, "", pattern>; 887 888// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 889class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 890 string opc, string asm, string cstr, list<dag> pattern> 891 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 892 let OutOperandList = oops; 893 let InOperandList = !con(iops, (ops pred:$p)); 894 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 895 let Pattern = pattern; 896 list<Predicate> Predicates = [IsThumb2]; 897} 898 899// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as 900// an input operand since by default it's a zero register. It will 901// become an implicit def once it's "flipped". 902// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 903// more consistent. 904class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 905 string opc, string asm, string cstr, list<dag> pattern> 906 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 907 let OutOperandList = oops; 908 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 909 let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); 910 let Pattern = pattern; 911 list<Predicate> Predicates = [IsThumb2]; 912} 913 914// Special cases 915class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 916 string asm, string cstr, list<dag> pattern> 917 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 918 let OutOperandList = oops; 919 let InOperandList = iops; 920 let AsmString = asm; 921 let Pattern = pattern; 922 list<Predicate> Predicates = [IsThumb2]; 923} 924 925class T2I<dag oops, dag iops, string opc, string asm, list<dag> pattern> 926 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>; 927class T2Ii12<dag oops, dag iops, string opc, string asm, list<dag> pattern> 928 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, opc, asm, "", pattern>; 929class T2Ii8<dag oops, dag iops, string opc, string asm, list<dag> pattern> 930 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, opc, asm, "", pattern>; 931class T2Iso<dag oops, dag iops, string opc, string asm, list<dag> pattern> 932 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, opc, asm, "", pattern>; 933class T2Ipc<dag oops, dag iops, string opc, string asm, list<dag> pattern> 934 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, opc, asm, "", pattern>; 935class T2Ii8s4<dag oops, dag iops, string opc, string asm, list<dag> pattern> 936 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, opc, asm, "", pattern>; 937 938class T2sI<dag oops, dag iops, string opc, string asm, list<dag> pattern> 939 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, opc, asm, "", pattern>; 940 941class T2XI<dag oops, dag iops, string asm, list<dag> pattern> 942 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>; 943class T2JTI<dag oops, dag iops, string asm, list<dag> pattern> 944 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, asm, "", pattern>; 945 946// T2Iidxldst - Thumb2 indexed load / store instructions. 947class T2Iidxldst<dag oops, dag iops, AddrMode am, IndexMode im, 948 string opc, string asm, string cstr, list<dag> pattern> 949 : InstARM<am, Size4Bytes, im, ThumbFrm, cstr> { 950 let OutOperandList = oops; 951 let InOperandList = !con(iops, (ops pred:$p)); 952 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 953 let Pattern = pattern; 954 list<Predicate> Predicates = [IsThumb2]; 955} 956 957// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 958class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 959 list<Predicate> Predicates = [IsThumb1Only, HasV5T]; 960} 961 962// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 963class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 964 list<Predicate> Predicates = [IsThumb1Only]; 965} 966 967// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 968class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 969 list<Predicate> Predicates = [IsThumb2]; 970} 971 972//===----------------------------------------------------------------------===// 973 974//===----------------------------------------------------------------------===// 975// ARM VFP Instruction templates. 976// 977 978// Almost all VFP instructions are predicable. 979class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 980 IndexMode im, Format f, string opc, string asm, string cstr, 981 list<dag> pattern> 982 : InstARM<am, sz, im, f, cstr> { 983 let OutOperandList = oops; 984 let InOperandList = !con(iops, (ops pred:$p)); 985 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 986 let Pattern = pattern; 987 list<Predicate> Predicates = [HasVFP2]; 988} 989 990// Special cases 991class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 992 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 993 : InstARM<am, sz, im, f, cstr> { 994 let OutOperandList = oops; 995 let InOperandList = iops; 996 let AsmString = asm; 997 let Pattern = pattern; 998 list<Predicate> Predicates = [HasVFP2]; 999} 1000 1001class VFPAI<dag oops, dag iops, Format f, string opc, 1002 string asm, list<dag> pattern> 1003 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 1004 asm, "", pattern>; 1005 1006// ARM VFP addrmode5 loads and stores 1007class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1008 string opc, string asm, list<dag> pattern> 1009 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1010 VFPLdStFrm, opc, asm, "", pattern> { 1011 // TODO: Mark the instructions with the appropriate subtarget info. 1012 let Inst{27-24} = opcod1; 1013 let Inst{21-20} = opcod2; 1014 let Inst{11-8} = 0b1011; 1015} 1016 1017class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1018 string opc, string asm, list<dag> pattern> 1019 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1020 VFPLdStFrm, opc, asm, "", pattern> { 1021 // TODO: Mark the instructions with the appropriate subtarget info. 1022 let Inst{27-24} = opcod1; 1023 let Inst{21-20} = opcod2; 1024 let Inst{11-8} = 0b1010; 1025} 1026 1027// Load / store multiple 1028class AXSI5<dag oops, dag iops, string asm, list<dag> pattern> 1029 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1030 VFPLdStMulFrm, asm, "", pattern> { 1031 // TODO: Mark the instructions with the appropriate subtarget info. 1032 let Inst{27-25} = 0b110; 1033 let Inst{11-8} = 0b1011; 1034} 1035 1036class AXDI5<dag oops, dag iops, string asm, list<dag> pattern> 1037 : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone, 1038 VFPLdStMulFrm, asm, "", pattern> { 1039 // TODO: Mark the instructions with the appropriate subtarget info. 1040 let Inst{27-25} = 0b110; 1041 let Inst{11-8} = 0b1010; 1042} 1043 1044 1045// Double precision, unary 1046class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1047 string opc, string asm, list<dag> pattern> 1048 : VFPAI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 1049 let Inst{27-20} = opcod1; 1050 let Inst{19-16} = opcod2; 1051 let Inst{11-8} = 0b1011; 1052 let Inst{7-4} = opcod3; 1053} 1054 1055// Double precision, binary 1056class ADbI<bits<8> opcod, dag oops, dag iops, string opc, 1057 string asm, list<dag> pattern> 1058 : VFPAI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 1059 let Inst{27-20} = opcod; 1060 let Inst{11-8} = 0b1011; 1061} 1062 1063// Single precision, unary 1064class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops, 1065 string opc, string asm, list<dag> pattern> 1066 : VFPAI<oops, iops, VFPUnaryFrm, opc, asm, pattern> { 1067 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding. 1068 let Inst{27-20} = opcod1; 1069 let Inst{19-16} = opcod2; 1070 let Inst{11-8} = 0b1010; 1071 let Inst{7-4} = opcod3; 1072} 1073 1074// Single precision, binary 1075class ASbI<bits<8> opcod, dag oops, dag iops, string opc, 1076 string asm, list<dag> pattern> 1077 : VFPAI<oops, iops, VFPBinaryFrm, opc, asm, pattern> { 1078 // Bit 22 (D bit) can be changed during instruction encoding. 1079 let Inst{27-20} = opcod; 1080 let Inst{11-8} = 0b1010; 1081} 1082 1083// VFP conversion instructions 1084class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, 1085 dag oops, dag iops, string opc, string asm, list<dag> pattern> 1086 : VFPAI<oops, iops, VFPConv1Frm, opc, asm, pattern> { 1087 let Inst{27-20} = opcod1; 1088 let Inst{19-16} = opcod2; 1089 let Inst{11-8} = opcod3; 1090 let Inst{6} = 1; 1091} 1092 1093class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1094 string opc, string asm, list<dag> pattern> 1095 : VFPAI<oops, iops, f, opc, asm, pattern> { 1096 let Inst{27-20} = opcod1; 1097 let Inst{11-8} = opcod2; 1098 let Inst{4} = 1; 1099} 1100 1101class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1102 string asm, list<dag> pattern> 1103 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>; 1104 1105class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1106 string asm, list<dag> pattern> 1107 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>; 1108 1109class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1110 string asm, list<dag> pattern> 1111 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>; 1112 1113class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc, 1114 string asm, list<dag> pattern> 1115 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>; 1116 1117//===----------------------------------------------------------------------===// 1118 1119//===----------------------------------------------------------------------===// 1120// ARM NEON Instruction templates. 1121// 1122 1123class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, string asm, 1124 string cstr, list<dag> pattern> 1125 : InstARM<am, Size4Bytes, im, NEONFrm, cstr> { 1126 let OutOperandList = oops; 1127 let InOperandList = iops; 1128 let AsmString = asm; 1129 let Pattern = pattern; 1130 list<Predicate> Predicates = [HasNEON]; 1131} 1132 1133class NI<dag oops, dag iops, string asm, list<dag> pattern> 1134 : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, "", pattern> { 1135} 1136 1137class NLdSt<dag oops, dag iops, string asm, list<dag> pattern> 1138 : NeonI<oops, iops, AddrMode6, IndexModeNone, asm, "", pattern> { 1139 let Inst{31-24} = 0b11110100; 1140} 1141 1142class NDataI<dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1143 : NeonI<oops, iops, AddrModeNone, IndexModeNone, asm, cstr, pattern> { 1144 let Inst{31-25} = 0b1111001; 1145} 1146 1147// NEON "one register and a modified immediate" format. 1148class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1149 bit op5, bit op4, 1150 dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1151 : NDataI<oops, iops, asm, cstr, pattern> { 1152 let Inst{23} = op23; 1153 let Inst{21-19} = op21_19; 1154 let Inst{11-8} = op11_8; 1155 let Inst{7} = op7; 1156 let Inst{6} = op6; 1157 let Inst{5} = op5; 1158 let Inst{4} = op4; 1159} 1160 1161// NEON 2 vector register format. 1162class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1163 bits<5> op11_7, bit op6, bit op4, 1164 dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1165 : NDataI<oops, iops, asm, cstr, pattern> { 1166 let Inst{24-23} = op24_23; 1167 let Inst{21-20} = op21_20; 1168 let Inst{19-18} = op19_18; 1169 let Inst{17-16} = op17_16; 1170 let Inst{11-7} = op11_7; 1171 let Inst{6} = op6; 1172 let Inst{4} = op4; 1173} 1174 1175// NEON 2 vector register with immediate. 1176class N2VImm<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 1177 bit op6, bit op4, 1178 dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1179 : NDataI<oops, iops, asm, cstr, pattern> { 1180 let Inst{24} = op24; 1181 let Inst{23} = op23; 1182 let Inst{21-16} = op21_16; 1183 let Inst{11-8} = op11_8; 1184 let Inst{7} = op7; 1185 let Inst{6} = op6; 1186 let Inst{4} = op4; 1187} 1188 1189// NEON 3 vector register format. 1190class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1191 dag oops, dag iops, string asm, string cstr, list<dag> pattern> 1192 : NDataI<oops, iops, asm, cstr, pattern> { 1193 let Inst{24} = op24; 1194 let Inst{23} = op23; 1195 let Inst{21-20} = op21_20; 1196 let Inst{11-8} = op11_8; 1197 let Inst{6} = op6; 1198 let Inst{4} = op4; 1199} 1200 1201// NEON VMOVs between scalar and core registers. 1202class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1203 dag oops, dag iops, Format f, string opc, string asm, 1204 list<dag> pattern> 1205 : AI<oops, iops, f, opc, asm, pattern> { 1206 let Inst{27-20} = opcod1; 1207 let Inst{11-8} = opcod2; 1208 let Inst{6-5} = opcod3; 1209 let Inst{4} = 1; 1210 list<Predicate> Predicates = [HasNEON]; 1211} 1212class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1213 dag oops, dag iops, string opc, string asm, list<dag> pattern> 1214 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONGetLnFrm, opc, asm, 1215 pattern>; 1216class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1217 dag oops, dag iops, string opc, string asm, list<dag> pattern> 1218 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONSetLnFrm, opc, asm, 1219 pattern>; 1220class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1221 dag oops, dag iops, string opc, string asm, list<dag> pattern> 1222 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NEONDupFrm, opc, asm, pattern>; 1223