| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 44edc227c743052bd58e73a5e1402fa68ed728f0 |
|
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.
No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.
rdar://problem/15302004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5df37dab763ce377095389c4ea1cff88db369954 |
|
19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0b90c6223d9c49b5e0dc4bf4e53796b0714d7b80 |
|
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
|
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 59b3300664d062bf04159eacaeb44d6c729e6a8c |
|
18-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 19c14abf1c4ccebfa7d07bdd6ea8462a15c0b749 |
|
17-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add support for the NEON instructions vmaxnm/vminnm.
This adds a new class for non-predicable NEON instructions and a
new DecoderNamespace for v8 NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 12f45c3782c0d01bcf9973bbc23dba2b17ce54cb |
|
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9fb5a6588becc92be1d7cf503d2947b170be3c31 |
|
09-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2a9683289b78a2533b261e1b341f9ea9724465a0 |
|
06-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add MC support for the v8fp instructions: vmaxnm and vminnm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4ea250524f77a67102118747dad6ee69f9f3b3aa |
|
04-Jul-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 242c9f4615feeee2fbdd1f29cd9a8e8ffd43c075 |
|
31-May-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.
Patch by Amaury de la Vieuville.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| eb1641d54a7eda7717304bc4d55d059208d8ebed |
|
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 169e9ba2b2c78675a0fa5ad8aebb987fe9c00e23 |
|
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d8b3ed8f25c1ba76a6db875cd2d6eaa016bd4646 |
|
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 |
|
18-Apr-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3015dfb7d739f4cc0b1408555889ecea880ffac9 |
|
09-Feb-2012 |
James Molloy <james.molloy@arm.com> |
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 78d13e191e0f6bcb4bef5bc5c8c5f6e5be1f4070 |
|
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON add correct predicates for some asm aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8b31f95bdde1e3809a1c9fdb6926b1840effcf9c |
|
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c7448f8d47de96333d6854113fb9f0e7affb31cd |
|
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 485d8bf7e5537a19d3ad63e65f841bd7e63d4d06 |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM add more 'gas' compatibility aliases for NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6b044c26094a9f86da7d12945b00a47a5f07cf6d |
|
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSHR implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1ceef1a49122cec6d79c0714719d99db27ab1764 |
|
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9f3d220c632a9c18b424248592d2bc7b023956d2 |
|
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Implement ARM ARM Table A7-3 via TokenAlias.
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 253ef7a77930f6855a5bf24037e9dfbc65a1ee85 |
|
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| afb500ace12698a99daa5d7c10bfedcbfef48022 |
|
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assmebler parsing for two-operand VMUL instructions.
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 872eedbb3a46618e333db42ee9c41fda34eb1e9b |
|
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1 single lane assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 |
|
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5b2fb2083c387009607f438a2a986c3e0a2cd0be |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for data type suffices on NEON VMOV aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0530d0d5d9dfaae2e3c78a52729abcbf9fcdd21b |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Split out the plain '.{8|16|32|64}' suffix handling.
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ef448767a35148261d6c82a8e55e6e2f4be8e631 |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ffc658b056b7cc0b3f6a2626694b6a4216ed728d |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 02e3d9268fe456ebe4fe6ae277507bb7933ec3df |
|
14-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing type suffix options for VLDR/VSTR.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9588c10b69121d9746b09e868fcc8879cbd98e3a |
|
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor simple immediate asm operand render methods.
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 71810ab7c0ecd6927dde1eee0c73169642f3764d |
|
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 681460f954e9c13ffd2f02f27bba048ccf90abaf |
|
01-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD/VST assembly parsing for symbolic address operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| cb9fed665550376b7c65c7e1157a58911193e2e2 |
|
28-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 460a90540b045c102012da2492999557e6840526 |
|
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5cd5ac6ad455880395e34ac647f1e962a83763a0 |
|
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a3157b402695ef9d5f6a03e8e3afc5bddf3a3df7 |
|
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a77295db19527503d6b290e4f34f273d0a789365 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e64fb28da191bc978ab99ea397e6108a15c364f8 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR post-indexed.
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| eeec025cf5a2236ee9527a3312496a6ea42100c6 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6153a036f544beb03dfc4d58edc28cf42712743d |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8e1e60b5f8fd9c6233bdb8814ee40887555a0594 |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Reject invalid imod values in t2CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a33b31be451472e72e6dd88851061e239ad54606 |
|
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up predicates on ARM target instruction aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4ec6e888ec6d12b5255afd685b05c8fee1f7fc73 |
|
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 73a1c2cea181a4463effaab8612c78cf11b83336 |
|
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Tab character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b86e2dbf61425b195ac5c281e480d9f4414377af |
|
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 16280308ac6f20d9da06eafcc19e4a6777f49750 |
|
17-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 47a0d52b69056250a1edaca8b28f705993094542 |
|
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ef2865a8eadffd7e346b9bc70c647578010b6afd |
|
16-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 92be8ab6a410207a097a24dcbf2e2302f6634265 |
|
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Remove dead classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8757a4c6aba86111bacc49879d1f1c260f4631d4 |
|
15-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Update comment to reflect MC target machine refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 79628e92e1f903d50340d4cd3d1ea8c5fff63a87 |
|
12-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix decoding of ARM-mode STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 45251b370733b167d1d0640a027365f7208f7d10 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Remove unused template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 14605d1a679d55ff25875656e100ff455194ee17 |
|
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 26d2f0ac919f6ae868fe901fd4ad64af6f92da4d |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Continue to tighten decoding by performing more operand validation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8533ebad6f6e407215497ca50771f323058f5576 |
|
10-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add initial support for decoding NEON instructions in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8d7d2e1238fac58c01ccfb719d0cc5680a079561 |
|
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 14c903a76be7933cea746617d3f787fdf4de8203 |
|
05-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 793e79601f0fd68ba082fa2016018f80b2379460 |
|
26-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| dfdf02dbada1ff9f87fe6efef0fc182a754f13f7 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix for LDREX source register encoding.
rdar://9842203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4f6f13db1a8a491ecab6af64549fbdc23cb5ba56 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1355cf1f76abe9699cd1c2838da132ff8b25b76b |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up the ARM asm parser a bit.
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5f6c133d7d4451a78ffc39248fc69a8870b57c6a |
|
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
More simple cleanup of ARM asm operand definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 43904299b05bdf579415749041f77c4490fe5f5b |
|
25-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Make assembly parser method names more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 152d4a4bb6b75de740b4b8a9f48abb9069d50c17 |
|
22-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f6c0525d421cb48119423a96e23289b473eddbd7 |
|
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| dde038af59506c631ce181aff66e315a0c477f4d |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1769a3df4a81309ec055a8586c8ac35755fa79a2 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a0472dc4205d5f2cc4e9cc5a08c51625573a26ce |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f1a009007374d8ae1c1565f34d9cea3b83665e5f |
|
19-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 16884415db751c75f2133bd04921393c792b1158 |
|
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0d8dae292a088c3a742f655c1787782abfe7e34c |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Parameterize away the ARM T1Cop class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9bb098ad3a3c93aec50a4a63e6894472727f8d88 |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 53e3fc463e3d9ee840510b08ebd6db17694fa2c5 |
|
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d1689ae4b1ae5af191f71dcb9c59640a6dca7ebc |
|
06-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM pseudo-instructions as isPseudo.
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 33281b23616bea25decc838cb8707a2861f9d767 |
|
27-May-2011 |
Eric Christopher <echristo@apple.com> |
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
followed by a conditional and imm8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6635b04a4357caf6544cd0a7dbc4c107e7907a88 |
|
19-May-2011 |
Jim Grosbach <grosbach@apple.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 54ad87ab786cae4e5b654f4295e9697f0c72dbb1 |
|
03-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a few ARM coprocessor intrinsics. Testcases included
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a9611549fe5cd06000111851f88b951467695307 |
|
06-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ac79e4c82f201c30a06c2cd05baebd20f5b49888 |
|
04-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ae0855401b8c80f96904b6808b0bc4c89216aecd |
|
01-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b41aaab5a1769f4df04d566da37866ac91b6ee9e |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r128632 again, until I figure out what break the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| bcd3a9cd84d3bb143075d31bdf631f621f44f9e7 |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e4345c9977e65b14fa4b93d19c7e67a7b15f7f40 |
|
31-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6a7d36a32026aa366d41c457898bd2d7a539f06c |
|
31-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 40829ed6f5e449fa33a9cd7022ce6c3941dace3d |
|
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
|
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e2189144d45be78a89f0daf3df3cf12e38221d86 |
|
14-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a768c3d45f73fff46fb9bbf4368c280ee4aaca49 |
|
10-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-instructions are codegenonly by definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3116dce33840a115130c5f8ffcb9679d023496d6 |
|
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a656b63ee4d5b0e3f4d26a55dd4cc69795746684 |
|
01-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Narrow right shifts need to encode their immediates differently from a normal
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2b943566f394eba5aac0c6c94a2375ea37c9341f |
|
23-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change VFPNeonA8 definition to make the code easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6557bce3ec8d5a82b2ea299a18cb51677b299633 |
|
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
|
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5eda282cd1775afc2ec1e1b86c9e224d2db10302 |
|
16-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
|
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f922c47143d247cbae14b294a0bada139bcd35f6 |
|
12-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
AsmMatcher custom operand parser failure enhancements.
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.
Update the ARM asm parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 706d946cfe44fa93f482c3a56ed42d52ca81b257 |
|
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing dmb/dsb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6b3a999f227139a3be7df6b5aea7a7d01ce94851 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr*2 and mr*c2 support to thumb2 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| fa5bd27fbe5188ca708ac0dda4f32d90505da9f5 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr* and mr*c support to thumb targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ff12a8bd999569ce76b3a9f5e167f6e89280e9d9 |
|
18-Jan-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 41b1d4e4725b34ccf646c706757d8a557ab376e7 |
|
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ac00e9627388e31a5704bc3e3430ffd0631bb1fe |
|
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 04da9bf9f133a3e5233d10885a38e1d14199549c |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a79bd0e1e0df2358bd8d1d1d5bf30bdfc0141f67 |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| bdf714450b70509538aa5a8a676034418ce827b6 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 encoding of the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d67641b6f804110505a69aaed5479f446bbbb34e |
|
06-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
not an immediate. It stores either ARM::CPSR or reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| cf590263cd5c24ccf1d08cef612738d99cd980d9 |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Add a post encoder method to the VFP instructions to convert them to the Thumb2
encoding if we're in that mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9d63d90de5e57ad96f467b270544443a9284eb2b |
|
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 43f7b2d3703987fe964985846f8a6829a66b5d69 |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
General cleanups of comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 40062fb7479487e3bd44944b2be0b055b9ea6269 |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
s/T1pIEncode/T1pILdStEncode/g
s/T1pIEncodeImm/T1pILdStEncodeImm/g
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0b424dc6b734fc5538887d1ebbd843c3a8d3d49d |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Renaming variables to coincide with documentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3f8c110dc643847363686d543a56c23c41353ab0 |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename operands to match ARM documentation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2cbc9fe83741f9239aaf99c5b71bf3635f9af9da |
|
01-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Inline classes that were used in only one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1fd374e9c1c074c1681336bef31e65f0170b0f7e |
|
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a0d2c8a40f890345237abfa9cece16c517e1e280 |
|
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
rdar://8685712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6af50f7dd12d82f0a80f3158102180eee4c921aa |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Correct Thumb2 encodings for a much wider range of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6e4221153bf0f2b6acda93f08b08155e3628bf4c |
|
30-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize ARMPseudoInst size property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f1aa47dc1aed018e2f70ffe7d32dba51e2ac45fe |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Pseudo-ize tBR_JTr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2dc7768d73c9afa3a23b86ee7827bc8de426f459 |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a30a51b16a002dc51e206ea467f2c4ab7ca18a77 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2aeb6121a19aca7c317619f7ec37d7a770e9f03b |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 953557f445ba749e0ec95e43bc5143849d1fd99b |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e2d54af47f67f3a868f96a4d9856042c71244814 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Delete another dead class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| fc0cb4b90673eedfa36024bfee21ef6af3d50101 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
whitespace tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9ef65cbbc6f23ee8c44b065d3a4feea11c471a2f |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9558b4cdc4d12079250fe1d6302b954c7dfc0010 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9cb15b5be51b7e36f3fe0c9ee256eb9c99b9d796 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM binary encoding information for the rest of the indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0c2283a910fef6347ddc46196cf37b4ff7e87fb6 |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f1ce7cc1d19309e5cb086739471f4dc04728117b |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c884aff5f4d431b31b5f85ce8a208dba30bd72df |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for LDRH post-increment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 821752e2e601b2e4c0bb83cb341892c853f16d0a |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out the set of Thumb2 multiplication operator encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 056ab107ff8e818258c39b1f1e318b2aa1a417fc |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARMPseudoInst instructions should default to being considered a single 4-byte
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 99594eb1dec2ddccbfbc995d828ce37ad829ec87 |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
the operand to the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c6961f140ad9bb4da6554c12a4a6af4cd2dab54a |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 53694265a9e571aa53087ed0d5b770fdede12394 |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
just pretend to be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 160f8f0e6779b76c7713036c8580ae25c5aad586 |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor a few ARM load instructions to better parameterize things and re-use
common encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 89e14c7579d9351da2e39a85703882bac3a83980 |
|
17-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM encoding bits. LDRH now encodes properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6bc105a7b9282a0b5beb9d06267b31a3054fb3fa |
|
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add binary emission stuff for VLDM/VSTM. This reuses the
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7b71878d9f490dbdccd39a7f8e813cab58fe8503 |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
- Remove dead patterns.
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 99f53d13efc259b47c93dc0d90a5db763cbe371a |
|
15-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2ac190238e88b21e716e2853900b5076c9013410 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6c470b806fe8eefae1b7bf180f269a4b120173a4 |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9e0bfb58298cab01625e56c49bac23f52bf782c3 |
|
13-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
flag for the LDRT/STRT family instructions as a side effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2716e25c2cee61e95bec3d17b49ca37a48b4cfab |
|
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 529916ca4ab83ec472a2d7039a05007c4d40553a |
|
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b39e6488eef7a5ff8b4e6acf0d42d096f5be853b |
|
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Kill more unused stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a0a6a47c02d360e8a167a6a28f03a3b453c38fbb |
|
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove unused class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 80f9e6724fa98b5af0bb43f58002c1ac3e9cb30b |
|
12-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8f143913141991baaa535ca0da7c8a81606d6392 |
|
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out support for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 57dac88f775c1191a98cff89abd1f7ad33df5e29 |
|
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c7139a6f0d3acd198ab9eb536ea1ec52e61ff130 |
|
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7eab97f260ba0f56d1d4a82f3a4eb2c979452011 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 928f3325a70384ee91af5768f628cf0748879b11 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 570a9226913ebe1af04832b8fb3273c70b4ee152 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 954ffff79bf2f48ac6fd8b4406fe51e3d19440e3 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Move LDM predicate operand encoding into base clase. Add STM missing STM
encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5d5eb9e3817a2765297e6dd5649ecb9b8b03e334 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM encoding for the mode (ia, ib, da, db) operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c1235e2a4eff7ce61ab15375f6686238c39ab304 |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of non-return LDM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 866aa394ca72ca015e65fff55043bc1120b3b58d |
|
11-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix ARM encoding of LDM+Return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2f46f1f59c17040f7a2c970342f2f1dcc9b78319 |
|
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f431edae5c0c79077451adb6fb0f406f7c7e5368 |
|
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118097 to fix buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1ba6064437f7cae1d2cd1aa9c8dd50a78e8657e3 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d138d7034e8dcfbb55683116a854a1e42d6879a4 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Factor out a common encoding class for loads and stores with a lane parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c2bf50245f86805e95d01a243e7de3641c5ab7a8 |
|
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move the machine operand MC encoding patterns to the parent classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6797f89815d9e26ae6b6856273e6a96ff5e135ea |
|
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 69661191ce9f4e8a2fa00391a0708905caccf52c |
|
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 150d20e8fcadda6600bbb2e188c17a35b8ec7cbd |
|
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6b5252db2db5eeeadec4602329ac56beb6dea54a |
|
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f32ecc69e51b45bd5c0ec93b393aee535f43c66a |
|
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 86875a2463be6c0ac4df121c3319e3e1f73dcdda |
|
29-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode LDREX*/STREX* binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7e3383c007f53b3a00675af225e428cb66ddf404 |
|
28-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d2fbdb7f5c85d2191514953bdba0fae7b788e623 |
|
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f587a9352a80bc62d9d521d5051c69d1fefecca7 |
|
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3e5561247202bae994dd259a2d8dc4eff8f799f3 |
|
27-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3557d00a388585b8827d3e864cb8cd24ee42368a |
|
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a88ea03bf22ba098f1b7d3471d98f3303dcbd33f |
|
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0e9996ca94ac84c10aeddfb9b6300b2b89b08fe2 |
|
26-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
NEON vmov's are in Neon domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 162875a9f3be40bfccc07c29ea4ad19f599b9ee4 |
|
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8c71eff59439708a61a2c65919ccf9c2791d1f1b |
|
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f8da5f5dfa5e847d76bf20d0ec4940e3ca51d275 |
|
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3870b750e6d8af533926138e670f4643a5953e42 |
|
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 929a7056d8fa54a45471d2861034e3faa11e232e |
|
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize a bit of ARM encoding information, simplifying some instruction
definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9463d0e400d4bac590960ba5593d7850870f7187 |
|
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d451f888b85d01caa586b0d45bacb41836fd2c31 |
|
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| cfbece50f602c561c5eac046bcfc9a07c8c006cb |
|
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3a37866e53c6beb615300e2444e2c1b3a7647f3c |
|
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b3af5de2d97c30355b8109e149326b0664d34085 |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b35ad41fef5d1edd9495f708fb7eae1a0a94ef9d |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 08bd54987f4ae482de13436e7254ff08b23f825f |
|
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a0c14ef8f6a41184c65a7904e70efa268ab241f9 |
|
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 499e886fe6c0ad02e0079734733dd7dde03d2940 |
|
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Encoding for ARM-mode VADD.F32 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 62547267f088a060d7c1084a40d740645efe86d1 |
|
11-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7cd2729d2a2ded13ba35f85575b64383f198f976 |
|
06-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a 'pattern' arg to the ARM PseudoNeonI class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 78caacc2266e504eca315844203b3f727c27fbd0 |
|
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
replace stuff like:
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d86609fca46ac9e186557d2d7b12f029febecf0e |
|
05-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Increase the number of bits used internally by the ARM target to represent the
addressing mode from four to five.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9d4ebc0eb80c770aab5b51ca459748a6ac8f1699 |
|
16-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| bd916c54b7989ddbab373c61eb1ed2556ca44d27 |
|
14-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 72db18243839860019ab93e7c30e86228f017ea7 |
|
08-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
VFP/NEON load/store multiple instructions are addrmode4, not 5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| da2ae63206bcf6856f9d717862508b94213c2336 |
|
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Cleanup some whitespaces.
- Convert {0,1} and friends into 0b01, which is identical and more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 55c134a26188291f60c44d027a837f05d797194f |
|
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4822bce4aa395e3e96215e18f5c926c78d4a0e64 |
|
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 709d59255a3100c7d440c93069efa1f726677a27 |
|
26-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Start converting NEON load/stores to use pseudo instructions, beginning here
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8462b30548fb5969250858036638c73c16b65b43 |
|
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Add an ARMOperand class for condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9a1c189d9e7472f336f3c6d61be76bc46b25749e |
|
11-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!! Two of them were already out of sync. I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.) Add support for encoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 99ccffe87e7b2bdc8e5a477f8c1e9087758daf56 |
|
22-Jul-2010 |
Xerxes Ranby <xerxes@zafena.se> |
ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 80d9bc0336821ca2a94a7afe2daac6e8bc689ef7 |
|
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Renumber NEON instruction formats to be consecutive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 184723d9be17fa0d136b564b2dca44c5216044d6 |
|
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
"N..." instead of "NEON..." for consistency with the other NEON format names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 26532631653be91f9ccc99fca3bfb8027da7c70b |
|
26-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
Renumber MiscFrm to 25.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d303846e162e18e0f1fb02d3826dc4d38244f86a |
|
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Clean up some extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| fddb7667ca4d8fe83f96b388295849281ddaa5b4 |
|
05-Apr-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 79c4d820b46cee1e78ecdef80b3f2ed6373839b7 |
|
29-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 10bc69c7262d32321b65f21b80a57826b1a90acd |
|
27-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 897dd0c58859e10afaa36e4175eef9a703b4a794 |
|
27-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 629c25cda6af43c16ee4d1ef2301c9ff1531d041 |
|
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c6e704df8d6e96260a463dac4675ed6968e186e6 |
|
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 575c91cba78332bd9add0949e31a9c228c44cf00 |
|
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0a3dc10eba975195e8b9b028bd21a4969cd6f2de |
|
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| da9283cd57843eb21fcd4117833e165017bb9123 |
|
26-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed instruction class NI from ARMInstrFormats.td.
It doesn't seem to be used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2d2898e6e99a5a4a16352b86070fa0986b7d1efd |
|
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVDupLnFrm and change NVDupLane class to use that format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| fa80bec349b7fff9ec97b5f66795d7bafa72da62 |
|
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e4614f7e84a7219164e9992fff855dee3816a08e |
|
25-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2676737e5ed3e4b5c89b4d06b60d998e9318eb73 |
|
24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2fadd6b221893595a7a86eb4b03f5aeadb6088fc |
|
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c5f413a74c296864d54c8e1a3391e7b15c9b2f97 |
|
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
respectively, and add some more comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a271174771adce635d29219225843ddb3fb17770 |
|
24-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renamed NVdImmFrm to N1RegModImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 841e828702df6c28f2af25930cc06e23bd8fcc88 |
|
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Fix typo in the comment for N3VX class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3ae9a57c74346e8697ebd64d3139a0ee6b78118a |
|
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 927b88f771ea0c9f511fd0a92dc4a6d4024fed7e |
|
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdVmImmFrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| df9a4f0591e3f3e7ae3b3c119a0c8cf678594f6b |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 011355944bc914b556d43ca4e3b422049791de08 |
|
23-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix bad indentation, 80-column violations, and trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 785516adc5f3de0911eca1ff94283e6bc8ace7ca |
|
23-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add New NEON Format NVdImmFrm.
Ref: A7.4.6 One register and a modified immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| caa608e97c07ffe988dd7c76516b9f81ad8ffc0a |
|
20-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add NLdStFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 76a312b7d1c2b41394696510506967cd0794b831 |
|
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Revert this change, since it was causing ARM performance regressions.
--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 81f04d59f6216d0e105daa9bde2250ca6af35fa5 |
|
19-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 50622ce8cf429067540232ffabc5b53a81f53ca8 |
|
19-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Update comment to refer to the right filename.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 341ab138fb3b7b7ebe12371481641f8681cd4e9d |
|
18-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Get rid of target-specific fp <-> int nodes when still I'm here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b7d5226a4ed0d5a7ea2441791cab093741ad5e9f |
|
18-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
fix some buggy ops concatentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 6c8648b4c9f3e02b625dd2d32e0315395da88e61 |
|
18-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Revert 98745 with respect to the addition of NEONFrm subformats for disassembly.
There is a better way coming up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 89ef7b797ae949edd592f5f71dddbae6ea35c2bf |
|
17-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase format field from 5 to 6 bits. ARMII::FormMask was increased to 0x3f
in svn r74988 but the format field was never widened.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9e08876a2ae329feb7a76dbfe33666cb58033c00 |
|
17-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 49d9dc4dd205b615beb7af160ef974eaabe4d1cf |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
--- Reverse-merging r98637 into '.':
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d30a98e43ae18e1fc70a7dc748edf669d809c685 |
|
16-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| bffb5b39bea3288bc557b10f3ed1864e6c7857e0 |
|
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new
base register updating load/store-multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 815baebe1c8dc02accf128ae10dff9a1742d3244 |
|
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| dd0f3cf189c34542901178bfca0a319b74d69a05 |
|
10-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ad4df4c0da1a0e4b091321e1ffdc7973669e4273 |
|
01-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added STRHT for disassembly only and fixed a bug in AI3sthpo class where the W
bit should be set to 0 instead of 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| adc7733a64b65096cbd6066c212a9daa6e278a9a |
|
26-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 39a4bb35276206d7ef0ff51dbc984aaf50bf659d |
|
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRD_PRE/POST & STRD_PRE/POST for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| adb561d4e0a37c21159405dde90d2ef2d1a5eef9 |
|
18-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added LDRSBT, LDRHT, LDRSHT for disassembly only. And fixed encoding errors
of AI3ldsbpo, AI3ldhpo, and AI3ldshpo in ARMInstrFormats.td in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f4d81051ff40d9e4e71f0b1b84a85ed907076525 |
|
12-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 811663f799ce1af18ef704fab14afc02ac94b652 |
|
11-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
Sorry!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 69a8c7f497b5686d55798a0aa4663a6e0d5bc12b |
|
30-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Modified encoding bits specification for VFP instructions. In particular, the D
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified. For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| bbc71b2904644bfa85d8785328dc08d61c534467 |
|
16-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d68e119c0fea54f47d0f3f0b5282dcf6cd19d8b9 |
|
15-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added encoding bits for the Thumb ISA. Initial checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f6b2862e813cd75e337238bb3321d3a512b54f06 |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
ARM memory barrier instructions are not predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0291d7ed0942b218c58ddd900a8f6b3dd80ad023 |
|
11-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5278eb802fae2ee1a7b2a428596bc364d8bcd9db |
|
11-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d122874996a6faa8832569b632fd73a32ace7ae7 |
|
01-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 exception handling setjmp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f81bf15552d3df7dd341e3970a002b9e35ea4992 |
|
23-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| da1aea4d7551d05cfb28a565b9750b7965cd620a |
|
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b16ed11cb4ca0a55647335847bd69a3810290be9 |
|
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7ebd32a1b87553d98215ae159489c1407e50e34c |
|
23-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Partially revert r89377 by removing NLdStLN class definition from
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ac0869dc8a7986855c5557cc67d4709600158ef5 |
|
21-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5c376ff9f08513686293b26c86b2c116b976d6b9 |
|
19-Nov-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2e1da9fea468e33f8fedd4295ef4a73a0ccb5714 |
|
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
64-bit FP loads & stores operate on both NEON and VFP pipelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f95215f551949d5e5adfbf4753aa833b9009b77a |
|
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d9ecd3108f32b33e38b5ba0ee3963062d6ecc115 |
|
26-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 507df402b09be986b40251fb83cb0c8a2e586b68 |
|
21-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Leave some NEON instruction encoding bits unspecified instead of setting
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 1fc1dc0682b9e3648acd2e9b3b426db87d9f2dcf |
|
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Refs: A8-598.
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 780d207d1c73e53834df9eb9ff0a1b07b235dd04 |
|
20-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing encoding bits to NLdSt class of instructions.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b07c1716248cebf00b37ed5d89581369b1191a87 |
|
07-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add some instruction encoding bits for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5adb66a646e2ec32265263739f5b01c3f50c176a |
|
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 10bf734e6e0b5aba79dc199d611dcdec54a1e48e |
|
10-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix double load / store multiple encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2a9df47abd75c0337e0254f09070f90023509066 |
|
25-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Expose the instruction contraint string as an argument to the NLdSt class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 338268c67fbb7252702bf400495771068750466b |
|
11-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Use NEON for single-precision int<->FP conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| baf31088f1472f48ea5ae81f0b93636cc44ca444 |
|
08-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use VLDM / VSTM to spill/reload 128-bit Neon registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8b7d7ade85fd0103316295440d4950f39ab08419 |
|
06-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 35d6c41fde95422fb8483be0ac0af2b1425a4b13 |
|
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 53e4471adcf34cac253d2486e6b29c331e2d973e |
|
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add NEON single-precision FP support for fabs and fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 42a83f2d15cbbc08f5be19856198e3c885221e9c |
|
04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| b620724e614c6594e7b269b6ea7d8483947ea944 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| c9d138f505b515e96eb761a7b2138cd27f3f9536 |
|
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e1e52edfff9f24d1e3f308cd126ff7ffac514ed7 |
|
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix typo in addrmode definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 446c428bf394b7113b0f18cbacb5e87b4efd1e14 |
|
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3ca524e336ad0be449c080235a2d7a38516f0ca4 |
|
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| dda0f4cb798e5f482247cda4ea9b74977b4601ec |
|
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add some NEON ld / st instruction static encoding.
- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 205a5ca6cfabc6cd408634a2fa7f2529956cc2cf |
|
08-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Implement NEON vld1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 34a0fa362dde63cf9adf5917ab2ee2c2b7dd2179 |
|
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e88d5cee9d6b02bc786df806395a718464908064 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d770d9e7d1f5c65b185897dcf226b3fc64598683 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8b024a5eb5b64b482f7d92aad7a3f0e6cac93f12 |
|
02-Jul-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a new addressing mode for NEON load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5e47a9a6e46bd271eba058fb831da1a1edf8707c |
|
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f3c21b857b8449bcde35e499ef8268c0fec9514d |
|
30-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 055b0310f862b91f33699037ce67d3ab8137c20c |
|
29-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 9cb9e6778c7d458eee7f3e25d304697ad10d8d46 |
|
27-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Renaming for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0aa1d8c52d34e9ba1e731a21b16606cd6f4f924a |
|
25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 09c39fcf83952bbe0a56b950f0d90ce4eac773d0 |
|
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| f49810c7e60807c43a68ab02c936a4ee77a4d2cf |
|
23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5bafff36c798608a189c517d37527e4a38863071 |
|
23-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add support for ARM's Advanced SIMD (NEON) instruction set.
This is still a work in progress but most of the NEON instruction set
is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| ffa6d962a7d75500269ce5d2012b58249fee3d6d |
|
14-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle the rest of pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 148cad8b308c0f8fdb37b368f2c911861dd2421a |
|
13-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix pre- and post-indexed load / store encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3c4a4ffa3dba5e3c7a0900d0bafe28d7095f3ada |
|
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Consolidate formats; fix FCMPED etc. encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 80a119842da2ce2786ea476037001ab5b6c67046 |
|
12-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix VFP conversion instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0a0ab1387a3923769990e91cce8e098366c4a920 |
|
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix FMDRR encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| cd8e66a1efdb31f0514270387207fb8c63bae4ed |
|
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP load / store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 78be83d7c2a5b94e635b0227924a489b8d8937e8 |
|
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP conversion instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 96581d3633edf702b14a60472a1ec5354f327c18 |
|
11-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode VFP arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4df60f5491ff35c8a48c2cf14e18a33c9793b3bb |
|
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Jump table JIT support. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 8b59db3f2c72a642251d4f86ea61f5d27e8919a6 |
|
07-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode misc arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 97f48c39fd158ad1a701002e2d6798c4b4ae4ab8 |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode extend instructions; more clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 12c3a533c50fe3c7475c1ff7c1bb4b26e36dc6c3 |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
- Consolidate instruction formats.
- Other clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| d87293ce78ae7568477374cd83b22c84214316fb |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| eb4f52eb6287919fe2bdca62364046af800cd15d |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| fbc9d412efdfa1ed30ff4d2baedc775a5f59c638 |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 83b5cf02721cb0f755fde9bd454172bceb356532 |
|
06-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Encode pic load / store instructions; fix some encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| edda31c412d524531ee6cd3f2d21c2ef85b6afb0 |
|
05-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| e7fe6724452fc6db75be1957df79bb92f5635b28 |
|
04-Nov-2008 |
Evan Cheng <evan.cheng@apple.com> |
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0a4b9dc9b127c3fae6069f85a7858db5a06ff3a8 |
|
03-Nov-2008 |
Jim Grosbach <grosbach@apple.com> |
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 2642196a6570e95e1491ee0120f67baa5c3ea351 |
|
14-Oct-2008 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 7fd7ca4e7f775a75f648f03d956c3068c71b991d |
|
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix addrmode1 instruction encodings; fix bx_ret encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 29c57c34efcb6b8ba64e3279cdb68937c113552a |
|
17-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Specify instruction encoding using range list to avoid endianess issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 05fc9664018f867b2184589e8a04cc8f056cfa16 |
|
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 56176. All those instruction formats are still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| a964b7dffe89d22569e96f5801886ef347d01b0a |
|
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unnecessary instruction formats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 49a9f2958dadbb1fcdc707ec003a61e9ceef8a4e |
|
13-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3aac788365086260b4f8318c5563db54cd2d97fb |
|
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Control flow instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 3c2ee4939b250963fa06483b4c082b279279f4e7 |
|
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
ldm / stm instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 5d2c1cf74d2f4794883af4e90bee320a344fa9e3 |
|
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
AXI2 and AXI3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 4bbd5f8a9c39f8274219367895bcfc5d296573d7 |
|
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize instruction formats again; AXI1 encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 840917be2c58ba54d9a70204d08933f7ed107d67 |
|
01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode3 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55596 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
|
| 0d14fc8cd5cee0b8527192c6820452e96d329e05 |
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01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Reorganize some instruction format definitions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| 93912739c9afec2482ea3c824ba0e40ab9bdfc03 |
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01-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Rest of addrmode2 instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| 17222df0ecf8b0fbcf17b050dd18174ca845fbe6 |
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31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr2 word / byte load encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| b7880ac470c8d83580e9327ecb2ce8efc40ca091 |
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31-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| 612b79edc92b305bc23a23fc5ef4066ca728921f |
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29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| 130966411f83469b1d9b93df831a2f2146bd400f |
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29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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| 37f25d989a3054b4742f6c92af94a312c26ffb2b |
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29-Aug-2008 |
Evan Cheng <evan.cheng@apple.com> |
Refactor ARM instruction format definitions into a separate file. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrFormats.td
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