ARMInstrFormats.td revision 8b59db3f2c72a642251d4f86ea61f5d27e8919a6
1//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<5> val> { 19 bits<5> Value = val; 20} 21 22def Pseudo : Format<1>; 23def MulFrm : Format<2>; 24def BrFrm : Format<3>; 25def BrMiscFrm : Format<4>; 26 27def DPFrm : Format<5>; 28def DPSoRegFrm : Format<6>; 29 30def LdFrm : Format<7>; 31def StFrm : Format<8>; 32def LdMiscFrm : Format<9>; 33def StMiscFrm : Format<10>; 34def LdMulFrm : Format<11>; 35def StMulFrm : Format<12>; 36 37def ArithMiscFrm: Format<13>; 38def ExtFrm : Format<14>; 39def ThumbFrm : Format<15>; 40def VFPFrm : Format<16>; 41 42// Misc flag for data processing instructions that indicates whether 43// the instruction has a Rn register operand. 44class UnaryDP { bit isUnaryDataProc = 1; } 45 46//===----------------------------------------------------------------------===// 47 48// ARM Instruction templates. 49// 50 51class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im, 52 Format f, string cstr> 53 : Instruction { 54 field bits<32> Inst; 55 56 let Namespace = "ARM"; 57 58 // TSFlagsFields 59 AddrMode AM = am; 60 bits<4> AddrModeBits = AM.Value; 61 62 SizeFlagVal SZ = sz; 63 bits<3> SizeFlag = SZ.Value; 64 65 IndexMode IM = im; 66 bits<2> IndexModeBits = IM.Value; 67 68 Format F = f; 69 bits<5> Form = F.Value; 70 71 // 72 // Attributes specific to ARM instructions... 73 // 74 bit isUnaryDataProc = 0; 75 76 let Constraints = cstr; 77} 78 79class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> 80 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { 81 let OutOperandList = oops; 82 let InOperandList = iops; 83 let AsmString = asm; 84 let Pattern = pattern; 85} 86 87// Almost all ARM instructions are predicable. 88class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 89 IndexMode im, Format f, string opc, string asm, string cstr, 90 list<dag> pattern> 91 : InstARM<am, sz, im, f, cstr> { 92 let OutOperandList = oops; 93 let InOperandList = !con(iops, (ops pred:$p)); 94 let AsmString = !strconcat(opc, !strconcat("${p}", asm)); 95 let Pattern = pattern; 96 list<Predicate> Predicates = [IsARM]; 97} 98 99// Same as I except it can optionally modify CPSR. Note it's modeled as 100// an input operand since by default it's a zero register. It will 101// become an implicit def once it's "flipped". 102class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 103 IndexMode im, Format f, string opc, string asm, string cstr, 104 list<dag> pattern> 105 : InstARM<am, sz, im, f, cstr> { 106 let OutOperandList = oops; 107 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); 108 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); 109 let Pattern = pattern; 110 list<Predicate> Predicates = [IsARM]; 111} 112 113// Special cases 114class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, 115 IndexMode im, Format f, string asm, string cstr, list<dag> pattern> 116 : InstARM<am, sz, im, f, cstr> { 117 let OutOperandList = oops; 118 let InOperandList = iops; 119 let AsmString = asm; 120 let Pattern = pattern; 121 list<Predicate> Predicates = [IsARM]; 122} 123 124class AI<dag oops, dag iops, Format f, string opc, 125 string asm, list<dag> pattern> 126 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 127 asm, "", pattern>; 128class AsI<dag oops, dag iops, Format f, string opc, 129 string asm, list<dag> pattern> 130 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, 131 asm, "", pattern>; 132class AXI<dag oops, dag iops, Format f, string asm, 133 list<dag> pattern> 134 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, 135 "", pattern>; 136 137// Ctrl flow instructions 138class ABI<bits<4> opcod, dag oops, dag iops, string opc, 139 string asm, list<dag> pattern> 140 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc, 141 asm, "", pattern> { 142 let Inst{27-24} = opcod; 143} 144class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 145 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm, 146 "", pattern> { 147 let Inst{27-24} = opcod; 148} 149class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern> 150 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm, 151 "", pattern>; 152 153// BR_JT instructions 154// == mov pc 155class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 156 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, 157 asm, "", pattern> { 158 let Inst{20} = 0; // S Bit 159 let Inst{24-21} = opcod; 160 let Inst{27-26} = {0,0}; 161} 162// == add pc 163class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 164 : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm, 165 asm, "", pattern> { 166 let Inst{20} = 0; // S bit 167 let Inst{24-21} = opcod; 168 let Inst{27-26} = {0,0}; 169} 170// == ldr pc 171class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> 172 : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm, 173 asm, "", pattern> { 174 let Inst{20} = 1; // L bit 175 let Inst{21} = 0; // W bit 176 let Inst{22} = 0; // B bit 177 let Inst{24} = 1; // P bit 178 let Inst{27-26} = {0,1}; 179} 180 181 182// addrmode1 instructions 183class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 184 string asm, list<dag> pattern> 185 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 186 asm, "", pattern> { 187 let Inst{24-21} = opcod; 188 let Inst{27-26} = {0,0}; 189} 190class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, 191 string asm, list<dag> pattern> 192 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, 193 asm, "", pattern> { 194 let Inst{24-21} = opcod; 195 let Inst{27-26} = {0,0}; 196} 197class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, 198 list<dag> pattern> 199 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, 200 "", pattern> { 201 let Inst{24-21} = opcod; 202 let Inst{27-26} = {0,0}; 203} 204class AI1x2<dag oops, dag iops, Format f, string opc, 205 string asm, list<dag> pattern> 206 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, 207 asm, "", pattern>; 208 209 210// addrmode2 loads and stores 211class AI2<dag oops, dag iops, Format f, string opc, 212 string asm, list<dag> pattern> 213 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 214 asm, "", pattern> { 215 let Inst{27-26} = {0,1}; 216} 217 218// loads 219class AI2ldw<dag oops, dag iops, Format f, string opc, 220 string asm, list<dag> pattern> 221 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 222 asm, "", pattern> { 223 let Inst{20} = 1; // L bit 224 let Inst{21} = 0; // W bit 225 let Inst{22} = 0; // B bit 226 let Inst{24} = 1; // P bit 227 let Inst{27-26} = {0,1}; 228} 229class AXI2ldw<dag oops, dag iops, Format f, string asm, 230 list<dag> pattern> 231 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 232 asm, "", pattern> { 233 let Inst{20} = 1; // L bit 234 let Inst{21} = 0; // W bit 235 let Inst{22} = 0; // B bit 236 let Inst{24} = 1; // P bit 237 let Inst{27-26} = {0,1}; 238} 239class AI2ldb<dag oops, dag iops, Format f, string opc, 240 string asm, list<dag> pattern> 241 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 242 asm, "", pattern> { 243 let Inst{20} = 1; // L bit 244 let Inst{21} = 0; // W bit 245 let Inst{22} = 1; // B bit 246 let Inst{24} = 1; // P bit 247 let Inst{27-26} = {0,1}; 248} 249class AXI2ldb<dag oops, dag iops, Format f, string asm, 250 list<dag> pattern> 251 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 252 asm, "", pattern> { 253 let Inst{20} = 1; // L bit 254 let Inst{21} = 0; // W bit 255 let Inst{22} = 1; // B bit 256 let Inst{24} = 1; // P bit 257 let Inst{27-26} = {0,1}; 258} 259 260// stores 261class AI2stw<dag oops, dag iops, Format f, string opc, 262 string asm, list<dag> pattern> 263 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 264 asm, "", pattern> { 265 let Inst{20} = 0; // L bit 266 let Inst{21} = 0; // W bit 267 let Inst{22} = 0; // B bit 268 let Inst{24} = 1; // P bit 269 let Inst{27-26} = {0,1}; 270} 271class AXI2stw<dag oops, dag iops, Format f, string asm, 272 list<dag> pattern> 273 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 274 asm, "", pattern> { 275 let Inst{20} = 0; // L bit 276 let Inst{21} = 0; // W bit 277 let Inst{22} = 0; // B bit 278 let Inst{24} = 1; // P bit 279 let Inst{27-26} = {0,1}; 280} 281class AI2stb<dag oops, dag iops, Format f, string opc, 282 string asm, list<dag> pattern> 283 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, 284 asm, "", pattern> { 285 let Inst{20} = 0; // L bit 286 let Inst{21} = 0; // W bit 287 let Inst{22} = 1; // B bit 288 let Inst{24} = 1; // P bit 289 let Inst{27-26} = {0,1}; 290} 291class AXI2stb<dag oops, dag iops, Format f, string asm, 292 list<dag> pattern> 293 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, 294 asm, "", pattern> { 295 let Inst{20} = 0; // L bit 296 let Inst{21} = 0; // W bit 297 let Inst{22} = 1; // B bit 298 let Inst{24} = 1; // P bit 299 let Inst{27-26} = {0,1}; 300} 301 302// Pre-indexed loads 303class AI2ldwpr<dag oops, dag iops, Format f, string opc, 304 string asm, string cstr, list<dag> pattern> 305 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 306 asm, cstr, pattern> { 307 let Inst{20} = 1; // L bit 308 let Inst{21} = 1; // W bit 309 let Inst{22} = 0; // B bit 310 let Inst{24} = 1; // P bit 311 let Inst{27-26} = {0,1}; 312} 313class AI2ldbpr<dag oops, dag iops, Format f, string opc, 314 string asm, string cstr, list<dag> pattern> 315 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 316 asm, cstr, pattern> { 317 let Inst{20} = 1; // L bit 318 let Inst{21} = 1; // W bit 319 let Inst{22} = 1; // B bit 320 let Inst{24} = 1; // P bit 321 let Inst{27-26} = {0,1}; 322} 323 324// Pre-indexed stores 325class AI2stwpr<dag oops, dag iops, Format f, string opc, 326 string asm, string cstr, list<dag> pattern> 327 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 328 asm, cstr, pattern> { 329 let Inst{20} = 0; // L bit 330 let Inst{21} = 1; // W bit 331 let Inst{22} = 0; // B bit 332 let Inst{24} = 1; // P bit 333 let Inst{27-26} = {0,1}; 334} 335class AI2stbpr<dag oops, dag iops, Format f, string opc, 336 string asm, string cstr, list<dag> pattern> 337 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, 338 asm, cstr, pattern> { 339 let Inst{20} = 0; // L bit 340 let Inst{21} = 1; // W bit 341 let Inst{22} = 1; // B bit 342 let Inst{24} = 1; // P bit 343 let Inst{27-26} = {0,1}; 344} 345 346// Post-indexed loads 347class AI2ldwpo<dag oops, dag iops, Format f, string opc, 348 string asm, string cstr, list<dag> pattern> 349 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 350 asm, cstr,pattern> { 351 let Inst{20} = 1; // L bit 352 let Inst{21} = 0; // W bit 353 let Inst{22} = 0; // B bit 354 let Inst{24} = 0; // P bit 355 let Inst{27-26} = {0,1}; 356} 357class AI2ldbpo<dag oops, dag iops, Format f, string opc, 358 string asm, string cstr, list<dag> pattern> 359 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 360 asm, cstr,pattern> { 361 let Inst{20} = 1; // L bit 362 let Inst{21} = 0; // W bit 363 let Inst{22} = 1; // B bit 364 let Inst{24} = 0; // P bit 365 let Inst{27-26} = {0,1}; 366} 367 368// Post-indexed stores 369class AI2stwpo<dag oops, dag iops, Format f, string opc, 370 string asm, string cstr, list<dag> pattern> 371 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 372 asm, cstr,pattern> { 373 let Inst{20} = 0; // L bit 374 let Inst{21} = 0; // W bit 375 let Inst{22} = 0; // B bit 376 let Inst{24} = 0; // P bit 377 let Inst{27-26} = {0,1}; 378} 379class AI2stbpo<dag oops, dag iops, Format f, string opc, 380 string asm, string cstr, list<dag> pattern> 381 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, 382 asm, cstr,pattern> { 383 let Inst{20} = 0; // L bit 384 let Inst{21} = 0; // W bit 385 let Inst{22} = 1; // B bit 386 let Inst{24} = 0; // P bit 387 let Inst{27-26} = {0,1}; 388} 389 390// addrmode3 instructions 391class AI3<dag oops, dag iops, Format f, string opc, 392 string asm, list<dag> pattern> 393 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 394 asm, "", pattern>; 395class AXI3<dag oops, dag iops, Format f, string asm, 396 list<dag> pattern> 397 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, 398 "", pattern>; 399 400// loads 401class AI3ldh<dag oops, dag iops, Format f, string opc, 402 string asm, list<dag> pattern> 403 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 404 asm, "", pattern> { 405 let Inst{4} = 1; 406 let Inst{5} = 1; // H bit 407 let Inst{6} = 0; // S bit 408 let Inst{7} = 1; 409 let Inst{20} = 1; // L bit 410 let Inst{21} = 0; // W bit 411 let Inst{24} = 1; // P bit 412} 413class AXI3ldh<dag oops, dag iops, Format f, string asm, 414 list<dag> pattern> 415 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 416 asm, "", pattern> { 417 let Inst{4} = 1; 418 let Inst{5} = 1; // H bit 419 let Inst{6} = 0; // S bit 420 let Inst{7} = 1; 421 let Inst{20} = 1; // L bit 422 let Inst{21} = 0; // W bit 423 let Inst{24} = 1; // P bit 424} 425class AI3ldsh<dag oops, dag iops, Format f, string opc, 426 string asm, list<dag> pattern> 427 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 428 asm, "", pattern> { 429 let Inst{4} = 1; 430 let Inst{5} = 1; // H bit 431 let Inst{6} = 1; // S bit 432 let Inst{7} = 1; 433 let Inst{20} = 1; // L bit 434 let Inst{21} = 0; // W bit 435 let Inst{24} = 1; // P bit 436} 437class AXI3ldsh<dag oops, dag iops, Format f, string asm, 438 list<dag> pattern> 439 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 440 asm, "", pattern> { 441 let Inst{4} = 1; 442 let Inst{5} = 1; // H bit 443 let Inst{6} = 1; // S bit 444 let Inst{7} = 1; 445 let Inst{20} = 1; // L bit 446 let Inst{21} = 0; // W bit 447 let Inst{24} = 1; // P bit 448} 449class AI3ldsb<dag oops, dag iops, Format f, string opc, 450 string asm, list<dag> pattern> 451 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 452 asm, "", pattern> { 453 let Inst{4} = 1; 454 let Inst{5} = 0; // H bit 455 let Inst{6} = 1; // S bit 456 let Inst{7} = 1; 457 let Inst{20} = 1; // L bit 458 let Inst{21} = 0; // W bit 459 let Inst{24} = 1; // P bit 460} 461class AXI3ldsb<dag oops, dag iops, Format f, string asm, 462 list<dag> pattern> 463 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 464 asm, "", pattern> { 465 let Inst{4} = 1; 466 let Inst{5} = 0; // H bit 467 let Inst{6} = 1; // S bit 468 let Inst{7} = 1; 469 let Inst{20} = 1; // L bit 470 let Inst{21} = 0; // W bit 471 let Inst{24} = 1; // P bit 472} 473class AI3ldd<dag oops, dag iops, Format f, string opc, 474 string asm, list<dag> pattern> 475 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 476 asm, "", pattern> { 477 let Inst{4} = 1; 478 let Inst{5} = 0; // H bit 479 let Inst{6} = 1; // S bit 480 let Inst{7} = 1; 481 let Inst{20} = 0; // L bit 482 let Inst{21} = 0; // W bit 483 let Inst{24} = 1; // P bit 484} 485 486// stores 487class AI3sth<dag oops, dag iops, Format f, string opc, 488 string asm, list<dag> pattern> 489 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 490 asm, "", pattern> { 491 let Inst{4} = 1; 492 let Inst{5} = 1; // H bit 493 let Inst{6} = 0; // S bit 494 let Inst{7} = 1; 495 let Inst{20} = 0; // L bit 496 let Inst{21} = 0; // W bit 497 let Inst{24} = 1; // P bit 498} 499class AXI3sth<dag oops, dag iops, Format f, string asm, 500 list<dag> pattern> 501 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, 502 asm, "", pattern> { 503 let Inst{4} = 1; 504 let Inst{5} = 1; // H bit 505 let Inst{6} = 0; // S bit 506 let Inst{7} = 1; 507 let Inst{20} = 0; // L bit 508 let Inst{21} = 0; // W bit 509 let Inst{24} = 1; // P bit 510} 511class AI3std<dag oops, dag iops, Format f, string opc, 512 string asm, list<dag> pattern> 513 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, 514 asm, "", pattern> { 515 let Inst{4} = 1; 516 let Inst{5} = 1; // H bit 517 let Inst{6} = 1; // S bit 518 let Inst{7} = 1; 519 let Inst{20} = 0; // L bit 520 let Inst{21} = 0; // W bit 521 let Inst{24} = 1; // P bit 522} 523 524// Pre-indexed loads 525class AI3ldhpr<dag oops, dag iops, Format f, string opc, 526 string asm, string cstr, list<dag> pattern> 527 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 528 asm, cstr, pattern> { 529 let Inst{4} = 1; 530 let Inst{5} = 1; // H bit 531 let Inst{6} = 0; // S bit 532 let Inst{7} = 1; 533 let Inst{20} = 1; // L bit 534 let Inst{21} = 1; // W bit 535 let Inst{24} = 1; // P bit 536} 537class AI3ldshpr<dag oops, dag iops, Format f, string opc, 538 string asm, string cstr, list<dag> pattern> 539 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 540 asm, cstr, pattern> { 541 let Inst{4} = 1; 542 let Inst{5} = 1; // H bit 543 let Inst{6} = 1; // S bit 544 let Inst{7} = 1; 545 let Inst{20} = 1; // L bit 546 let Inst{21} = 1; // W bit 547 let Inst{24} = 1; // P bit 548} 549class AI3ldsbpr<dag oops, dag iops, Format f, string opc, 550 string asm, string cstr, list<dag> pattern> 551 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 552 asm, cstr, pattern> { 553 let Inst{4} = 1; 554 let Inst{5} = 0; // H bit 555 let Inst{6} = 1; // S bit 556 let Inst{7} = 1; 557 let Inst{20} = 1; // L bit 558 let Inst{21} = 1; // W bit 559 let Inst{24} = 1; // P bit 560} 561 562// Pre-indexed stores 563class AI3sthpr<dag oops, dag iops, Format f, string opc, 564 string asm, string cstr, list<dag> pattern> 565 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, 566 asm, cstr, pattern> { 567 let Inst{4} = 1; 568 let Inst{5} = 1; // H bit 569 let Inst{6} = 0; // S bit 570 let Inst{7} = 1; 571 let Inst{20} = 0; // L bit 572 let Inst{21} = 1; // W bit 573 let Inst{24} = 1; // P bit 574} 575 576// Post-indexed loads 577class AI3ldhpo<dag oops, dag iops, Format f, string opc, 578 string asm, string cstr, list<dag> pattern> 579 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 580 asm, cstr,pattern> { 581 let Inst{4} = 1; 582 let Inst{5} = 1; // H bit 583 let Inst{6} = 0; // S bit 584 let Inst{7} = 1; 585 let Inst{20} = 1; // L bit 586 let Inst{21} = 1; // W bit 587 let Inst{24} = 0; // P bit 588} 589class AI3ldshpo<dag oops, dag iops, Format f, string opc, 590 string asm, string cstr, list<dag> pattern> 591 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 592 asm, cstr,pattern> { 593 let Inst{4} = 1; 594 let Inst{5} = 1; // H bit 595 let Inst{6} = 1; // S bit 596 let Inst{7} = 1; 597 let Inst{20} = 1; // L bit 598 let Inst{21} = 1; // W bit 599 let Inst{24} = 0; // P bit 600} 601class AI3ldsbpo<dag oops, dag iops, Format f, string opc, 602 string asm, string cstr, list<dag> pattern> 603 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 604 asm, cstr,pattern> { 605 let Inst{4} = 1; 606 let Inst{5} = 0; // H bit 607 let Inst{6} = 1; // S bit 608 let Inst{7} = 1; 609 let Inst{20} = 1; // L bit 610 let Inst{21} = 1; // W bit 611 let Inst{24} = 0; // P bit 612} 613 614// Post-indexed stores 615class AI3sthpo<dag oops, dag iops, Format f, string opc, 616 string asm, string cstr, list<dag> pattern> 617 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, 618 asm, cstr,pattern> { 619 let Inst{4} = 1; 620 let Inst{5} = 1; // H bit 621 let Inst{6} = 0; // S bit 622 let Inst{7} = 1; 623 let Inst{20} = 0; // L bit 624 let Inst{21} = 1; // W bit 625 let Inst{24} = 0; // P bit 626} 627 628 629// addrmode4 instructions 630class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern> 631 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 632 "", pattern> { 633 let Inst{20} = 1; // L bit 634 let Inst{22} = 0; // S bit 635 let Inst{27-25} = 0b100; 636} 637class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern> 638 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, 639 "", pattern> { 640 let Inst{20} = 0; // L bit 641 let Inst{22} = 0; // S bit 642 let Inst{27-25} = 0b100; 643} 644 645// Unsigned multiply, multiply-accumulate instructions. 646class AMul1I<bits<7> opcod, dag oops, dag iops, string opc, 647 string asm, list<dag> pattern> 648 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 649 asm, "", pattern> { 650 let Inst{7-4} = 0b1001; 651 let Inst{20} = 0; // S bit 652 let Inst{27-21} = opcod; 653} 654class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc, 655 string asm, list<dag> pattern> 656 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 657 asm, "", pattern> { 658 let Inst{7-4} = 0b1001; 659 let Inst{27-21} = opcod; 660} 661 662// Most significant word multiply 663class AMul2I<bits<7> opcod, dag oops, dag iops, string opc, 664 string asm, list<dag> pattern> 665 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 666 asm, "", pattern> { 667 let Inst{7-4} = 0b1001; 668 let Inst{20} = 1; 669 let Inst{27-21} = opcod; 670} 671 672// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 673class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc, 674 string asm, list<dag> pattern> 675 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, 676 asm, "", pattern> { 677 let Inst{4} = 0; 678 let Inst{7} = 1; 679 let Inst{20} = 0; 680 let Inst{27-21} = opcod; 681} 682 683// Extend instructions. 684class AExtI<bits<8> opcod, dag oops, dag iops, string opc, 685 string asm, list<dag> pattern> 686 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc, 687 asm, "", pattern> { 688 let Inst{7-4} = 0b0111; 689 let Inst{27-20} = opcod; 690} 691 692// Misc Arithmetic instructions. 693class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc, 694 string asm, list<dag> pattern> 695 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc, 696 asm, "", pattern> { 697 let Inst{27-20} = opcod; 698} 699 700//===----------------------------------------------------------------------===// 701 702// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 703class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 704 list<Predicate> Predicates = [IsARM]; 705} 706class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 707 list<Predicate> Predicates = [IsARM, HasV5TE]; 708} 709class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 710 list<Predicate> Predicates = [IsARM, HasV6]; 711} 712 713//===----------------------------------------------------------------------===// 714// 715// Thumb Instruction Format Definitions. 716// 717 718 719// TI - Thumb instruction. 720 721class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, 722 string asm, string cstr, list<dag> pattern> 723 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> { 724 let OutOperandList = outs; 725 let InOperandList = ins; 726 let AsmString = asm; 727 let Pattern = pattern; 728 list<Predicate> Predicates = [IsThumb]; 729} 730 731class TI<dag outs, dag ins, string asm, list<dag> pattern> 732 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>; 733class TI1<dag outs, dag ins, string asm, list<dag> pattern> 734 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>; 735class TI2<dag outs, dag ins, string asm, list<dag> pattern> 736 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>; 737class TI4<dag outs, dag ins, string asm, list<dag> pattern> 738 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>; 739class TIs<dag outs, dag ins, string asm, list<dag> pattern> 740 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>; 741 742// Two-address instructions 743class TIt<dag outs, dag ins, string asm, list<dag> pattern> 744 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>; 745 746// BL, BLX(1) are translated by assembler into two instructions 747class TIx2<dag outs, dag ins, string asm, list<dag> pattern> 748 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>; 749 750// BR_JT instructions 751class TJTI<dag outs, dag ins, string asm, list<dag> pattern> 752 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>; 753 754 755//===----------------------------------------------------------------------===// 756 757 758// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode. 759class ThumbPat<dag pattern, dag result> : Pat<pattern, result> { 760 list<Predicate> Predicates = [IsThumb]; 761} 762 763class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> { 764 list<Predicate> Predicates = [IsThumb, HasV5T]; 765} 766