ARMInstrFormats.td revision a0472dc4205d5f2cc4e9cc5a08c51625573a26ce
1//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// ARM Instruction Format Definitions. 13// 14 15// Format specifies the encoding used by the instruction. This is part of the 16// ad-hoc solution used to emit machine instruction encodings by our machine 17// code emitter. 18class Format<bits<6> val> { 19 bits<6> Value = val; 20} 21 22def Pseudo : Format<0>; 23def MulFrm : Format<1>; 24def BrFrm : Format<2>; 25def BrMiscFrm : Format<3>; 26 27def DPFrm : Format<4>; 28def DPSoRegFrm : Format<5>; 29 30def LdFrm : Format<6>; 31def StFrm : Format<7>; 32def LdMiscFrm : Format<8>; 33def StMiscFrm : Format<9>; 34def LdStMulFrm : Format<10>; 35 36def LdStExFrm : Format<11>; 37 38def ArithMiscFrm : Format<12>; 39def SatFrm : Format<13>; 40def ExtFrm : Format<14>; 41 42def VFPUnaryFrm : Format<15>; 43def VFPBinaryFrm : Format<16>; 44def VFPConv1Frm : Format<17>; 45def VFPConv2Frm : Format<18>; 46def VFPConv3Frm : Format<19>; 47def VFPConv4Frm : Format<20>; 48def VFPConv5Frm : Format<21>; 49def VFPLdStFrm : Format<22>; 50def VFPLdStMulFrm : Format<23>; 51def VFPMiscFrm : Format<24>; 52 53def ThumbFrm : Format<25>; 54def MiscFrm : Format<26>; 55 56def NGetLnFrm : Format<27>; 57def NSetLnFrm : Format<28>; 58def NDupFrm : Format<29>; 59def NLdStFrm : Format<30>; 60def N1RegModImmFrm: Format<31>; 61def N2RegFrm : Format<32>; 62def NVCVTFrm : Format<33>; 63def NVDupLnFrm : Format<34>; 64def N2RegVShLFrm : Format<35>; 65def N2RegVShRFrm : Format<36>; 66def N3RegFrm : Format<37>; 67def N3RegVShFrm : Format<38>; 68def NVExtFrm : Format<39>; 69def NVMulSLFrm : Format<40>; 70def NVTBLFrm : Format<41>; 71 72// Misc flags. 73 74// The instruction has an Rn register operand. 75// UnaryDP - Indicates this is a unary data processing instruction, i.e. 76// it doesn't have a Rn operand. 77class UnaryDP { bit isUnaryDataProc = 1; } 78 79// Xform16Bit - Indicates this Thumb2 instruction may be transformed into 80// a 16-bit Thumb instruction if certain conditions are met. 81class Xform16Bit { bit canXformTo16Bit = 1; } 82 83//===----------------------------------------------------------------------===// 84// ARM Instruction flags. These need to match ARMBaseInstrInfo.h. 85// 86 87// FIXME: Once the JIT is MC-ized, these can go away. 88// Addressing mode. 89class AddrMode<bits<5> val> { 90 bits<5> Value = val; 91} 92def AddrModeNone : AddrMode<0>; 93def AddrMode1 : AddrMode<1>; 94def AddrMode2 : AddrMode<2>; 95def AddrMode3 : AddrMode<3>; 96def AddrMode4 : AddrMode<4>; 97def AddrMode5 : AddrMode<5>; 98def AddrMode6 : AddrMode<6>; 99def AddrModeT1_1 : AddrMode<7>; 100def AddrModeT1_2 : AddrMode<8>; 101def AddrModeT1_4 : AddrMode<9>; 102def AddrModeT1_s : AddrMode<10>; 103def AddrModeT2_i12 : AddrMode<11>; 104def AddrModeT2_i8 : AddrMode<12>; 105def AddrModeT2_so : AddrMode<13>; 106def AddrModeT2_pc : AddrMode<14>; 107def AddrModeT2_i8s4 : AddrMode<15>; 108def AddrMode_i12 : AddrMode<16>; 109 110// Load / store index mode. 111class IndexMode<bits<2> val> { 112 bits<2> Value = val; 113} 114def IndexModeNone : IndexMode<0>; 115def IndexModePre : IndexMode<1>; 116def IndexModePost : IndexMode<2>; 117def IndexModeUpd : IndexMode<3>; 118 119// Instruction execution domain. 120class Domain<bits<3> val> { 121 bits<3> Value = val; 122} 123def GenericDomain : Domain<0>; 124def VFPDomain : Domain<1>; // Instructions in VFP domain only 125def NeonDomain : Domain<2>; // Instructions in Neon domain only 126def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains 127def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8 128 129//===----------------------------------------------------------------------===// 130// ARM special operands. 131// 132 133def CondCodeOperand : AsmOperandClass { 134 let Name = "CondCode"; 135 let SuperClasses = []; 136} 137 138def CCOutOperand : AsmOperandClass { 139 let Name = "CCOut"; 140 let SuperClasses = []; 141} 142 143def MemBarrierOptOperand : AsmOperandClass { 144 let Name = "MemBarrierOpt"; 145 let SuperClasses = []; 146 let ParserMethod = "tryParseMemBarrierOptOperand"; 147} 148 149def ProcIFlagsOperand : AsmOperandClass { 150 let Name = "ProcIFlags"; 151 let SuperClasses = []; 152 let ParserMethod = "tryParseProcIFlagsOperand"; 153} 154 155def MSRMaskOperand : AsmOperandClass { 156 let Name = "MSRMask"; 157 let SuperClasses = []; 158 let ParserMethod = "tryParseMSRMaskOperand"; 159} 160 161// ARM imod and iflag operands, used only by the CPS instruction. 162def imod_op : Operand<i32> { 163 let PrintMethod = "printCPSIMod"; 164} 165 166def iflags_op : Operand<i32> { 167 let PrintMethod = "printCPSIFlag"; 168 let ParserMatchClass = ProcIFlagsOperand; 169} 170 171// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 172// register whose default is 0 (no register). 173def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 174 (ops (i32 14), (i32 zero_reg))> { 175 let PrintMethod = "printPredicateOperand"; 176 let ParserMatchClass = CondCodeOperand; 177} 178 179// Conditional code result for instructions whose 's' bit is set, e.g. subs. 180def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 181 let EncoderMethod = "getCCOutOpValue"; 182 let PrintMethod = "printSBitModifierOperand"; 183 let ParserMatchClass = CCOutOperand; 184} 185 186// Same as cc_out except it defaults to setting CPSR. 187def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { 188 let EncoderMethod = "getCCOutOpValue"; 189 let PrintMethod = "printSBitModifierOperand"; 190 let ParserMatchClass = CCOutOperand; 191} 192 193// ARM special operands for disassembly only. 194// 195def setend_op : Operand<i32> { 196 let PrintMethod = "printSetendOperand"; 197} 198 199def msr_mask : Operand<i32> { 200 let PrintMethod = "printMSRMaskOperand"; 201 let ParserMatchClass = MSRMaskOperand; 202} 203 204// Shift Right Immediate - A shift right immediate is encoded differently from 205// other shift immediates. The imm6 field is encoded like so: 206// 207// Offset Encoding 208// 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0> 209// 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0> 210// 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0> 211// 64 64 - <imm> is encoded in imm6<5:0> 212def shr_imm8 : Operand<i32> { 213 let EncoderMethod = "getShiftRight8Imm"; 214} 215def shr_imm16 : Operand<i32> { 216 let EncoderMethod = "getShiftRight16Imm"; 217} 218def shr_imm32 : Operand<i32> { 219 let EncoderMethod = "getShiftRight32Imm"; 220} 221def shr_imm64 : Operand<i32> { 222 let EncoderMethod = "getShiftRight64Imm"; 223} 224 225//===----------------------------------------------------------------------===// 226// ARM Instruction templates. 227// 228 229class InstTemplate<AddrMode am, int sz, IndexMode im, 230 Format f, Domain d, string cstr, InstrItinClass itin> 231 : Instruction { 232 let Namespace = "ARM"; 233 234 AddrMode AM = am; 235 int Size = sz; 236 IndexMode IM = im; 237 bits<2> IndexModeBits = IM.Value; 238 Format F = f; 239 bits<6> Form = F.Value; 240 Domain D = d; 241 bit isUnaryDataProc = 0; 242 bit canXformTo16Bit = 0; 243 244 // If this is a pseudo instruction, mark it isCodeGenOnly. 245 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo"); 246 247 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. 248 let TSFlags{4-0} = AM.Value; 249 let TSFlags{6-5} = IndexModeBits; 250 let TSFlags{12-7} = Form; 251 let TSFlags{13} = isUnaryDataProc; 252 let TSFlags{14} = canXformTo16Bit; 253 let TSFlags{17-15} = D.Value; 254 255 let Constraints = cstr; 256 let Itinerary = itin; 257} 258 259class Encoding { 260 field bits<32> Inst; 261} 262 263class InstARM<AddrMode am, int sz, IndexMode im, 264 Format f, Domain d, string cstr, InstrItinClass itin> 265 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding { 266 let DecoderNamespace = "ARM"; 267} 268 269// This Encoding-less class is used by Thumb1 to specify the encoding bits later 270// on by adding flavors to specific instructions. 271class InstThumb<AddrMode am, int sz, IndexMode im, 272 Format f, Domain d, string cstr, InstrItinClass itin> 273 : InstTemplate<am, sz, im, f, d, cstr, itin> { 274 let DecoderNamespace = "Thumb"; 275} 276 277class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> 278 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, 279 GenericDomain, "", itin> { 280 let OutOperandList = oops; 281 let InOperandList = iops; 282 let Pattern = pattern; 283 let isCodeGenOnly = 1; 284 let isPseudo = 1; 285} 286 287// PseudoInst that's ARM-mode only. 288class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 289 list<dag> pattern> 290 : PseudoInst<oops, iops, itin, pattern> { 291 let Size = sz; 292 list<Predicate> Predicates = [IsARM]; 293} 294 295// PseudoInst that's Thumb-mode only. 296class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 297 list<dag> pattern> 298 : PseudoInst<oops, iops, itin, pattern> { 299 let Size = sz; 300 list<Predicate> Predicates = [IsThumb]; 301} 302 303// PseudoInst that's Thumb2-mode only. 304class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin, 305 list<dag> pattern> 306 : PseudoInst<oops, iops, itin, pattern> { 307 let Size = sz; 308 list<Predicate> Predicates = [IsThumb2]; 309} 310 311class ARMPseudoExpand<dag oops, dag iops, int sz, 312 InstrItinClass itin, list<dag> pattern, 313 dag Result> 314 : ARMPseudoInst<oops, iops, sz, itin, pattern>, 315 PseudoInstExpansion<Result>; 316 317class tPseudoExpand<dag oops, dag iops, int sz, 318 InstrItinClass itin, list<dag> pattern, 319 dag Result> 320 : tPseudoInst<oops, iops, sz, itin, pattern>, 321 PseudoInstExpansion<Result>; 322 323class t2PseudoExpand<dag oops, dag iops, int sz, 324 InstrItinClass itin, list<dag> pattern, 325 dag Result> 326 : t2PseudoInst<oops, iops, sz, itin, pattern>, 327 PseudoInstExpansion<Result>; 328 329// Almost all ARM instructions are predicable. 330class I<dag oops, dag iops, AddrMode am, int sz, 331 IndexMode im, Format f, InstrItinClass itin, 332 string opc, string asm, string cstr, 333 list<dag> pattern> 334 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 335 bits<4> p; 336 let Inst{31-28} = p; 337 let OutOperandList = oops; 338 let InOperandList = !con(iops, (ins pred:$p)); 339 let AsmString = !strconcat(opc, "${p}", asm); 340 let Pattern = pattern; 341 list<Predicate> Predicates = [IsARM]; 342} 343 344// A few are not predicable 345class InoP<dag oops, dag iops, AddrMode am, int sz, 346 IndexMode im, Format f, InstrItinClass itin, 347 string opc, string asm, string cstr, 348 list<dag> pattern> 349 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 350 let OutOperandList = oops; 351 let InOperandList = iops; 352 let AsmString = !strconcat(opc, asm); 353 let Pattern = pattern; 354 let isPredicable = 0; 355 list<Predicate> Predicates = [IsARM]; 356} 357 358// Same as I except it can optionally modify CPSR. Note it's modeled as an input 359// operand since by default it's a zero register. It will become an implicit def 360// once it's "flipped". 361class sI<dag oops, dag iops, AddrMode am, int sz, 362 IndexMode im, Format f, InstrItinClass itin, 363 string opc, string asm, string cstr, 364 list<dag> pattern> 365 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 366 bits<4> p; // Predicate operand 367 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 368 let Inst{31-28} = p; 369 let Inst{20} = s; 370 371 let OutOperandList = oops; 372 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 373 let AsmString = !strconcat(opc, "${s}${p}", asm); 374 let Pattern = pattern; 375 list<Predicate> Predicates = [IsARM]; 376} 377 378// Special cases 379class XI<dag oops, dag iops, AddrMode am, int sz, 380 IndexMode im, Format f, InstrItinClass itin, 381 string asm, string cstr, list<dag> pattern> 382 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { 383 let OutOperandList = oops; 384 let InOperandList = iops; 385 let AsmString = asm; 386 let Pattern = pattern; 387 list<Predicate> Predicates = [IsARM]; 388} 389 390class AI<dag oops, dag iops, Format f, InstrItinClass itin, 391 string opc, string asm, list<dag> pattern> 392 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 393 opc, asm, "", pattern>; 394class AsI<dag oops, dag iops, Format f, InstrItinClass itin, 395 string opc, string asm, list<dag> pattern> 396 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 397 opc, asm, "", pattern>; 398class AXI<dag oops, dag iops, Format f, InstrItinClass itin, 399 string asm, list<dag> pattern> 400 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 401 asm, "", pattern>; 402class AInoP<dag oops, dag iops, Format f, InstrItinClass itin, 403 string opc, string asm, list<dag> pattern> 404 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 405 opc, asm, "", pattern>; 406 407// Ctrl flow instructions 408class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 409 string opc, string asm, list<dag> pattern> 410 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 411 opc, asm, "", pattern> { 412 let Inst{27-24} = opcod; 413} 414class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin, 415 string asm, list<dag> pattern> 416 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin, 417 asm, "", pattern> { 418 let Inst{27-24} = opcod; 419} 420 421// BR_JT instructions 422class JTI<dag oops, dag iops, InstrItinClass itin, 423 string asm, list<dag> pattern> 424 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin, 425 asm, "", pattern>; 426 427// Atomic load/store instructions 428class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 429 string opc, string asm, list<dag> pattern> 430 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 431 opc, asm, "", pattern> { 432 bits<4> Rt; 433 bits<4> Rn; 434 let Inst{27-23} = 0b00011; 435 let Inst{22-21} = opcod; 436 let Inst{20} = 1; 437 let Inst{19-16} = Rn; 438 let Inst{15-12} = Rt; 439 let Inst{11-0} = 0b111110011111; 440} 441class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 442 string opc, string asm, list<dag> pattern> 443 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin, 444 opc, asm, "", pattern> { 445 bits<4> Rd; 446 bits<4> Rt; 447 bits<4> addr; 448 let Inst{27-23} = 0b00011; 449 let Inst{22-21} = opcod; 450 let Inst{20} = 0; 451 let Inst{19-16} = addr; 452 let Inst{15-12} = Rd; 453 let Inst{11-4} = 0b11111001; 454 let Inst{3-0} = Rt; 455} 456class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern> 457 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> { 458 bits<4> Rt; 459 bits<4> Rt2; 460 bits<4> Rn; 461 let Inst{27-23} = 0b00010; 462 let Inst{22} = b; 463 let Inst{21-20} = 0b00; 464 let Inst{19-16} = Rn; 465 let Inst{15-12} = Rt; 466 let Inst{11-4} = 0b00001001; 467 let Inst{3-0} = Rt2; 468} 469 470// addrmode1 instructions 471class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 472 string opc, string asm, list<dag> pattern> 473 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 474 opc, asm, "", pattern> { 475 let Inst{24-21} = opcod; 476 let Inst{27-26} = 0b00; 477} 478class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 479 string opc, string asm, list<dag> pattern> 480 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 481 opc, asm, "", pattern> { 482 let Inst{24-21} = opcod; 483 let Inst{27-26} = 0b00; 484} 485class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, 486 string asm, list<dag> pattern> 487 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin, 488 asm, "", pattern> { 489 let Inst{24-21} = opcod; 490 let Inst{27-26} = 0b00; 491} 492 493// loads 494 495// LDR/LDRB/STR/STRB/... 496class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am, 497 Format f, InstrItinClass itin, string opc, string asm, 498 list<dag> pattern> 499 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm, 500 "", pattern> { 501 let Inst{27-25} = op; 502 let Inst{24} = 1; // 24 == P 503 // 23 == U 504 let Inst{22} = isByte; 505 let Inst{21} = 0; // 21 == W 506 let Inst{20} = isLd; 507} 508// Indexed load/stores 509class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops, 510 IndexMode im, Format f, InstrItinClass itin, string opc, 511 string asm, string cstr, list<dag> pattern> 512 : I<oops, iops, AddrMode2, 4, im, f, itin, 513 opc, asm, cstr, pattern> { 514 bits<4> Rt; 515 let Inst{27-26} = 0b01; 516 let Inst{24} = isPre; // P bit 517 let Inst{22} = isByte; // B bit 518 let Inst{21} = isPre; // W bit 519 let Inst{20} = isLd; // L bit 520 let Inst{15-12} = Rt; 521} 522class AI2stridx<bit isByte, bit isPre, dag oops, dag iops, 523 IndexMode im, Format f, InstrItinClass itin, string opc, 524 string asm, string cstr, list<dag> pattern> 525 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 526 pattern> { 527 // AM2 store w/ two operands: (GPR, am2offset) 528 // {13} 1 == Rm, 0 == imm12 529 // {12} isAdd 530 // {11-0} imm12/Rm 531 bits<14> offset; 532 bits<4> Rn; 533 let Inst{25} = offset{13}; 534 let Inst{23} = offset{12}; 535 let Inst{19-16} = Rn; 536 let Inst{11-0} = offset{11-0}; 537} 538// FIXME: Merge with the above class when addrmode2 gets used for STR, STRB 539// but for now use this class for STRT and STRBT. 540class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops, 541 IndexMode im, Format f, InstrItinClass itin, string opc, 542 string asm, string cstr, list<dag> pattern> 543 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 544 pattern> { 545 // AM2 store w/ two operands: (GPR, am2offset) 546 // {17-14} Rn 547 // {13} 1 == Rm, 0 == imm12 548 // {12} isAdd 549 // {11-0} imm12/Rm 550 bits<18> addr; 551 let Inst{25} = addr{13}; 552 let Inst{23} = addr{12}; 553 let Inst{19-16} = addr{17-14}; 554 let Inst{11-0} = addr{11-0}; 555} 556 557// addrmode3 instructions 558class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, 559 InstrItinClass itin, string opc, string asm, list<dag> pattern> 560 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 561 opc, asm, "", pattern> { 562 bits<14> addr; 563 bits<4> Rt; 564 let Inst{27-25} = 0b000; 565 let Inst{24} = 1; // P bit 566 let Inst{23} = addr{8}; // U bit 567 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 568 let Inst{21} = 0; // W bit 569 let Inst{20} = op20; // L bit 570 let Inst{19-16} = addr{12-9}; // Rn 571 let Inst{15-12} = Rt; // Rt 572 let Inst{11-8} = addr{7-4}; // imm7_4/zero 573 let Inst{7-4} = op; 574 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 575} 576 577class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 578 IndexMode im, Format f, InstrItinClass itin, string opc, 579 string asm, string cstr, list<dag> pattern> 580 : I<oops, iops, AddrMode3, 4, im, f, itin, 581 opc, asm, cstr, pattern> { 582 bits<4> Rt; 583 let Inst{27-25} = 0b000; 584 let Inst{24} = isPre; // P bit 585 let Inst{21} = isPre; // W bit 586 let Inst{20} = op20; // L bit 587 let Inst{15-12} = Rt; // Rt 588 let Inst{7-4} = op; 589} 590 591// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB 592// but for now use this class for LDRSBT, LDRHT, LDSHT. 593class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, 594 IndexMode im, Format f, InstrItinClass itin, string opc, 595 string asm, string cstr, list<dag> pattern> 596 : I<oops, iops, AddrMode3, 4, im, f, itin, 597 opc, asm, cstr, pattern> { 598 // {13} 1 == imm8, 0 == Rm 599 // {12-9} Rn 600 // {8} isAdd 601 // {7-4} imm7_4/zero 602 // {3-0} imm3_0/Rm 603 bits<14> addr; 604 bits<4> Rt; 605 let Inst{27-25} = 0b000; 606 let Inst{24} = isPre; // P bit 607 let Inst{23} = addr{8}; // U bit 608 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 609 let Inst{20} = op20; // L bit 610 let Inst{19-16} = addr{12-9}; // Rn 611 let Inst{15-12} = Rt; // Rt 612 let Inst{11-8} = addr{7-4}; // imm7_4/zero 613 let Inst{7-4} = op; 614 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 615 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3"; 616} 617 618class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops, 619 IndexMode im, Format f, InstrItinClass itin, string opc, 620 string asm, string cstr, list<dag> pattern> 621 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr, 622 pattern> { 623 // AM3 store w/ two operands: (GPR, am3offset) 624 bits<14> offset; 625 bits<4> Rt; 626 bits<4> Rn; 627 let Inst{27-25} = 0b000; 628 let Inst{23} = offset{8}; 629 let Inst{22} = offset{9}; 630 let Inst{19-16} = Rn; 631 let Inst{15-12} = Rt; // Rt 632 let Inst{11-8} = offset{7-4}; // imm7_4/zero 633 let Inst{7-4} = op; 634 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 635} 636 637// stores 638class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, 639 string opc, string asm, list<dag> pattern> 640 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin, 641 opc, asm, "", pattern> { 642 bits<14> addr; 643 bits<4> Rt; 644 let Inst{27-25} = 0b000; 645 let Inst{24} = 1; // P bit 646 let Inst{23} = addr{8}; // U bit 647 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 648 let Inst{21} = 0; // W bit 649 let Inst{20} = 0; // L bit 650 let Inst{19-16} = addr{12-9}; // Rn 651 let Inst{15-12} = Rt; // Rt 652 let Inst{11-8} = addr{7-4}; // imm7_4/zero 653 let Inst{7-4} = op; 654 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 655} 656 657// Pre-indexed stores 658class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin, 659 string opc, string asm, string cstr, list<dag> pattern> 660 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin, 661 opc, asm, cstr, pattern> { 662 let Inst{4} = 1; 663 let Inst{5} = 1; // H bit 664 let Inst{6} = 0; // S bit 665 let Inst{7} = 1; 666 let Inst{20} = 0; // L bit 667 let Inst{21} = 1; // W bit 668 let Inst{24} = 1; // P bit 669 let Inst{27-25} = 0b000; 670} 671class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin, 672 string opc, string asm, string cstr, list<dag> pattern> 673 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin, 674 opc, asm, cstr, pattern> { 675 let Inst{4} = 1; 676 let Inst{5} = 1; // H bit 677 let Inst{6} = 1; // S bit 678 let Inst{7} = 1; 679 let Inst{20} = 0; // L bit 680 let Inst{21} = 1; // W bit 681 let Inst{24} = 1; // P bit 682 let Inst{27-25} = 0b000; 683} 684 685// Post-indexed stores 686class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin, 687 string opc, string asm, string cstr, list<dag> pattern> 688 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin, 689 opc, asm, cstr,pattern> { 690 // {13} 1 == imm8, 0 == Rm 691 // {12-9} Rn 692 // {8} isAdd 693 // {7-4} imm7_4/zero 694 // {3-0} imm3_0/Rm 695 bits<14> addr; 696 bits<4> Rt; 697 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 698 let Inst{4} = 1; 699 let Inst{5} = 1; // H bit 700 let Inst{6} = 0; // S bit 701 let Inst{7} = 1; 702 let Inst{11-8} = addr{7-4}; // imm7_4/zero 703 let Inst{15-12} = Rt; // Rt 704 let Inst{19-16} = addr{12-9}; // Rn 705 let Inst{20} = 0; // L bit 706 let Inst{21} = 0; // W bit 707 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 708 let Inst{23} = addr{8}; // U bit 709 let Inst{24} = 0; // P bit 710 let Inst{27-25} = 0b000; 711} 712class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin, 713 string opc, string asm, string cstr, list<dag> pattern> 714 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin, 715 opc, asm, cstr, pattern> { 716 let Inst{4} = 1; 717 let Inst{5} = 1; // H bit 718 let Inst{6} = 1; // S bit 719 let Inst{7} = 1; 720 let Inst{20} = 0; // L bit 721 let Inst{21} = 0; // W bit 722 let Inst{24} = 0; // P bit 723 let Inst{27-25} = 0b000; 724} 725 726// addrmode4 instructions 727class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, 728 string asm, string cstr, list<dag> pattern> 729 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> { 730 bits<4> p; 731 bits<16> regs; 732 bits<4> Rn; 733 let Inst{31-28} = p; 734 let Inst{27-25} = 0b100; 735 let Inst{22} = 0; // S bit 736 let Inst{19-16} = Rn; 737 let Inst{15-0} = regs; 738} 739 740// Unsigned multiply, multiply-accumulate instructions. 741class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 742 string opc, string asm, list<dag> pattern> 743 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 744 opc, asm, "", pattern> { 745 let Inst{7-4} = 0b1001; 746 let Inst{20} = 0; // S bit 747 let Inst{27-21} = opcod; 748} 749class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 750 string opc, string asm, list<dag> pattern> 751 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 752 opc, asm, "", pattern> { 753 let Inst{7-4} = 0b1001; 754 let Inst{27-21} = opcod; 755} 756 757// Most significant word multiply 758class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 759 InstrItinClass itin, string opc, string asm, list<dag> pattern> 760 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 761 opc, asm, "", pattern> { 762 bits<4> Rd; 763 bits<4> Rn; 764 bits<4> Rm; 765 let Inst{7-4} = opc7_4; 766 let Inst{20} = 1; 767 let Inst{27-21} = opcod; 768 let Inst{19-16} = Rd; 769 let Inst{11-8} = Rm; 770 let Inst{3-0} = Rn; 771} 772// MSW multiple w/ Ra operand 773class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops, 774 InstrItinClass itin, string opc, string asm, list<dag> pattern> 775 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> { 776 bits<4> Ra; 777 let Inst{15-12} = Ra; 778} 779 780// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> 781class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 782 InstrItinClass itin, string opc, string asm, list<dag> pattern> 783 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin, 784 opc, asm, "", pattern> { 785 bits<4> Rn; 786 bits<4> Rm; 787 let Inst{4} = 0; 788 let Inst{7} = 1; 789 let Inst{20} = 0; 790 let Inst{27-21} = opcod; 791 let Inst{6-5} = bit6_5; 792 let Inst{11-8} = Rm; 793 let Inst{3-0} = Rn; 794} 795class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 796 InstrItinClass itin, string opc, string asm, list<dag> pattern> 797 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 798 bits<4> Rd; 799 let Inst{19-16} = Rd; 800} 801 802// AMulxyI with Ra operand 803class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 804 InstrItinClass itin, string opc, string asm, list<dag> pattern> 805 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 806 bits<4> Ra; 807 let Inst{15-12} = Ra; 808} 809// SMLAL* 810class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops, 811 InstrItinClass itin, string opc, string asm, list<dag> pattern> 812 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> { 813 bits<4> RdLo; 814 bits<4> RdHi; 815 let Inst{19-16} = RdHi; 816 let Inst{15-12} = RdLo; 817} 818 819// Extend instructions. 820class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin, 823 opc, asm, "", pattern> { 824 // All AExtI instructions have Rd and Rm register operands. 825 bits<4> Rd; 826 bits<4> Rm; 827 let Inst{15-12} = Rd; 828 let Inst{3-0} = Rm; 829 let Inst{7-4} = 0b0111; 830 let Inst{9-8} = 0b00; 831 let Inst{27-20} = opcod; 832} 833 834// Misc Arithmetic instructions. 835class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops, 836 InstrItinClass itin, string opc, string asm, list<dag> pattern> 837 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 838 opc, asm, "", pattern> { 839 bits<4> Rd; 840 bits<4> Rm; 841 let Inst{27-20} = opcod; 842 let Inst{19-16} = 0b1111; 843 let Inst{15-12} = Rd; 844 let Inst{11-8} = 0b1111; 845 let Inst{7-4} = opc7_4; 846 let Inst{3-0} = Rm; 847} 848 849// PKH instructions 850class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin, 851 string opc, string asm, list<dag> pattern> 852 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin, 853 opc, asm, "", pattern> { 854 bits<4> Rd; 855 bits<4> Rn; 856 bits<4> Rm; 857 bits<5> sh; 858 let Inst{27-20} = opcod; 859 let Inst{19-16} = Rn; 860 let Inst{15-12} = Rd; 861 let Inst{11-7} = sh; 862 let Inst{6} = tb; 863 let Inst{5-4} = 0b01; 864 let Inst{3-0} = Rm; 865} 866 867//===----------------------------------------------------------------------===// 868 869// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. 870class ARMPat<dag pattern, dag result> : Pat<pattern, result> { 871 list<Predicate> Predicates = [IsARM]; 872} 873class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> { 874 list<Predicate> Predicates = [IsARM, HasV5T]; 875} 876class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> { 877 list<Predicate> Predicates = [IsARM, HasV5TE]; 878} 879class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> { 880 list<Predicate> Predicates = [IsARM, HasV6]; 881} 882 883//===----------------------------------------------------------------------===// 884// Thumb Instruction Format Definitions. 885// 886 887class ThumbI<dag oops, dag iops, AddrMode am, int sz, 888 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 889 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 890 let OutOperandList = oops; 891 let InOperandList = iops; 892 let AsmString = asm; 893 let Pattern = pattern; 894 list<Predicate> Predicates = [IsThumb]; 895} 896 897// TI - Thumb instruction. 898class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern> 899 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 900 901// Two-address instructions 902class TIt<dag oops, dag iops, InstrItinClass itin, string asm, 903 list<dag> pattern> 904 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst", 905 pattern>; 906 907// tBL, tBX 32-bit instructions 908class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3, 909 dag oops, dag iops, InstrItinClass itin, string asm, 910 list<dag> pattern> 911 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>, 912 Encoding { 913 let Inst{31-27} = opcod1; 914 let Inst{15-14} = opcod2; 915 let Inst{12} = opcod3; 916} 917 918// BR_JT instructions 919class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, 920 list<dag> pattern> 921 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 922 923// Thumb1 only 924class Thumb1I<dag oops, dag iops, AddrMode am, int sz, 925 InstrItinClass itin, string asm, string cstr, list<dag> pattern> 926 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 927 let OutOperandList = oops; 928 let InOperandList = iops; 929 let AsmString = asm; 930 let Pattern = pattern; 931 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 932} 933 934class T1I<dag oops, dag iops, InstrItinClass itin, 935 string asm, list<dag> pattern> 936 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>; 937class T1Ix2<dag oops, dag iops, InstrItinClass itin, 938 string asm, list<dag> pattern> 939 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 940 941// Two-address instructions 942class T1It<dag oops, dag iops, InstrItinClass itin, 943 string asm, string cstr, list<dag> pattern> 944 : Thumb1I<oops, iops, AddrModeNone, 2, itin, 945 asm, cstr, pattern>; 946 947// Thumb1 instruction that can either be predicated or set CPSR. 948class Thumb1sI<dag oops, dag iops, AddrMode am, int sz, 949 InstrItinClass itin, 950 string opc, string asm, string cstr, list<dag> pattern> 951 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 952 let OutOperandList = !con(oops, (outs s_cc_out:$s)); 953 let InOperandList = !con(iops, (ins pred:$p)); 954 let AsmString = !strconcat(opc, "${s}${p}", asm); 955 let Pattern = pattern; 956 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 957} 958 959class T1sI<dag oops, dag iops, InstrItinClass itin, 960 string opc, string asm, list<dag> pattern> 961 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 962 963// Two-address instructions 964class T1sIt<dag oops, dag iops, InstrItinClass itin, 965 string opc, string asm, list<dag> pattern> 966 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, 967 "$Rn = $Rdn", pattern>; 968 969// Thumb1 instruction that can be predicated. 970class Thumb1pI<dag oops, dag iops, AddrMode am, int sz, 971 InstrItinClass itin, 972 string opc, string asm, string cstr, list<dag> pattern> 973 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 974 let OutOperandList = oops; 975 let InOperandList = !con(iops, (ins pred:$p)); 976 let AsmString = !strconcat(opc, "${p}", asm); 977 let Pattern = pattern; 978 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 979} 980 981class T1pI<dag oops, dag iops, InstrItinClass itin, 982 string opc, string asm, list<dag> pattern> 983 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>; 984 985// Two-address instructions 986class T1pIt<dag oops, dag iops, InstrItinClass itin, 987 string opc, string asm, list<dag> pattern> 988 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, 989 "$Rn = $Rdn", pattern>; 990 991class T1pIs<dag oops, dag iops, 992 InstrItinClass itin, string opc, string asm, list<dag> pattern> 993 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>; 994 995class Encoding16 : Encoding { 996 let Inst{31-16} = 0x0000; 997} 998 999// A6.2 16-bit Thumb instruction encoding 1000class T1Encoding<bits<6> opcode> : Encoding16 { 1001 let Inst{15-10} = opcode; 1002} 1003 1004// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding. 1005class T1General<bits<5> opcode> : Encoding16 { 1006 let Inst{15-14} = 0b00; 1007 let Inst{13-9} = opcode; 1008} 1009 1010// A6.2.2 Data-processing encoding. 1011class T1DataProcessing<bits<4> opcode> : Encoding16 { 1012 let Inst{15-10} = 0b010000; 1013 let Inst{9-6} = opcode; 1014} 1015 1016// A6.2.3 Special data instructions and branch and exchange encoding. 1017class T1Special<bits<4> opcode> : Encoding16 { 1018 let Inst{15-10} = 0b010001; 1019 let Inst{9-6} = opcode; 1020} 1021 1022// A6.2.4 Load/store single data item encoding. 1023class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { 1024 let Inst{15-12} = opA; 1025 let Inst{11-9} = opB; 1026} 1027class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative 1028 1029class T1BranchCond<bits<4> opcode> : Encoding16 { 1030 let Inst{15-12} = opcode; 1031} 1032 1033// Helper classes to encode Thumb1 loads and stores. For immediates, the 1034// following bits are used for "opA" (see A6.2.4): 1035// 1036// 0b0110 => Immediate, 4 bytes 1037// 0b1000 => Immediate, 2 bytes 1038// 0b0111 => Immediate, 1 byte 1039class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am, 1040 InstrItinClass itin, string opc, string asm, 1041 list<dag> pattern> 1042 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1043 T1LoadStore<0b0101, opcode> { 1044 bits<3> Rt; 1045 bits<8> addr; 1046 let Inst{8-6} = addr{5-3}; // Rm 1047 let Inst{5-3} = addr{2-0}; // Rn 1048 let Inst{2-0} = Rt; 1049} 1050class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am, 1051 InstrItinClass itin, string opc, string asm, 1052 list<dag> pattern> 1053 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>, 1054 T1LoadStore<opA, {opB,?,?}> { 1055 bits<3> Rt; 1056 bits<8> addr; 1057 let Inst{10-6} = addr{7-3}; // imm5 1058 let Inst{5-3} = addr{2-0}; // Rn 1059 let Inst{2-0} = Rt; 1060} 1061 1062// A6.2.5 Miscellaneous 16-bit instructions encoding. 1063class T1Misc<bits<7> opcode> : Encoding16 { 1064 let Inst{15-12} = 0b1011; 1065 let Inst{11-5} = opcode; 1066} 1067 1068// Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable. 1069class Thumb2I<dag oops, dag iops, AddrMode am, int sz, 1070 InstrItinClass itin, 1071 string opc, string asm, string cstr, list<dag> pattern> 1072 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1073 let OutOperandList = oops; 1074 let InOperandList = !con(iops, (ins pred:$p)); 1075 let AsmString = !strconcat(opc, "${p}", asm); 1076 let Pattern = pattern; 1077 list<Predicate> Predicates = [IsThumb2]; 1078 let DecoderNamespace = "Thumb2"; 1079} 1080 1081// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an 1082// input operand since by default it's a zero register. It will become an 1083// implicit def once it's "flipped". 1084// 1085// FIXME: This uses unified syntax so {s} comes before {p}. We should make it 1086// more consistent. 1087class Thumb2sI<dag oops, dag iops, AddrMode am, int sz, 1088 InstrItinClass itin, 1089 string opc, string asm, string cstr, list<dag> pattern> 1090 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1091 bits<1> s; // condition-code set flag ('1' if the insn should set the flags) 1092 let Inst{20} = s; 1093 1094 let OutOperandList = oops; 1095 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); 1096 let AsmString = !strconcat(opc, "${s}${p}", asm); 1097 let Pattern = pattern; 1098 list<Predicate> Predicates = [IsThumb2]; 1099 let DecoderNamespace = "Thumb2"; 1100} 1101 1102// Special cases 1103class Thumb2XI<dag oops, dag iops, AddrMode am, int sz, 1104 InstrItinClass itin, 1105 string asm, string cstr, list<dag> pattern> 1106 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1107 let OutOperandList = oops; 1108 let InOperandList = iops; 1109 let AsmString = asm; 1110 let Pattern = pattern; 1111 list<Predicate> Predicates = [IsThumb2]; 1112 let DecoderNamespace = "Thumb2"; 1113} 1114 1115class ThumbXI<dag oops, dag iops, AddrMode am, int sz, 1116 InstrItinClass itin, 1117 string asm, string cstr, list<dag> pattern> 1118 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> { 1119 let OutOperandList = oops; 1120 let InOperandList = iops; 1121 let AsmString = asm; 1122 let Pattern = pattern; 1123 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1124 let DecoderNamespace = "Thumb"; 1125} 1126 1127class T2I<dag oops, dag iops, InstrItinClass itin, 1128 string opc, string asm, list<dag> pattern> 1129 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1130class T2Ii12<dag oops, dag iops, InstrItinClass itin, 1131 string opc, string asm, list<dag> pattern> 1132 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>; 1133class T2Ii8<dag oops, dag iops, InstrItinClass itin, 1134 string opc, string asm, list<dag> pattern> 1135 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>; 1136class T2Iso<dag oops, dag iops, InstrItinClass itin, 1137 string opc, string asm, list<dag> pattern> 1138 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>; 1139class T2Ipc<dag oops, dag iops, InstrItinClass itin, 1140 string opc, string asm, list<dag> pattern> 1141 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>; 1142class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin, 1143 string opc, string asm, list<dag> pattern> 1144 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "", 1145 pattern> { 1146 bits<4> Rt; 1147 bits<4> Rt2; 1148 bits<13> addr; 1149 let Inst{31-25} = 0b1110100; 1150 let Inst{24} = P; 1151 let Inst{23} = addr{8}; 1152 let Inst{22} = 1; 1153 let Inst{21} = W; 1154 let Inst{20} = isLoad; 1155 let Inst{19-16} = addr{12-9}; 1156 let Inst{15-12} = Rt{3-0}; 1157 let Inst{11-8} = Rt2{3-0}; 1158 let Inst{7-0} = addr{7-0}; 1159} 1160 1161class T2sI<dag oops, dag iops, InstrItinClass itin, 1162 string opc, string asm, list<dag> pattern> 1163 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>; 1164 1165class T2XI<dag oops, dag iops, InstrItinClass itin, 1166 string asm, list<dag> pattern> 1167 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>; 1168class T2JTI<dag oops, dag iops, InstrItinClass itin, 1169 string asm, list<dag> pattern> 1170 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>; 1171 1172// Move to/from coprocessor instructions 1173class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern> 1174 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> { 1175 let Inst{31-28} = opc; 1176} 1177 1178// Two-address instructions 1179class T2XIt<dag oops, dag iops, InstrItinClass itin, 1180 string asm, string cstr, list<dag> pattern> 1181 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>; 1182 1183// T2Iidxldst - Thumb2 indexed load / store instructions. 1184class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre, 1185 dag oops, dag iops, 1186 AddrMode am, IndexMode im, InstrItinClass itin, 1187 string opc, string asm, string cstr, list<dag> pattern> 1188 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> { 1189 let OutOperandList = oops; 1190 let InOperandList = !con(iops, (ins pred:$p)); 1191 let AsmString = !strconcat(opc, "${p}", asm); 1192 let Pattern = pattern; 1193 list<Predicate> Predicates = [IsThumb2]; 1194 let DecoderNamespace = "Thumb2"; 1195 let Inst{31-27} = 0b11111; 1196 let Inst{26-25} = 0b00; 1197 let Inst{24} = signed; 1198 let Inst{23} = 0; 1199 let Inst{22-21} = opcod; 1200 let Inst{20} = load; 1201 let Inst{11} = 1; 1202 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed 1203 let Inst{10} = pre; // The P bit. 1204 let Inst{8} = 1; // The W bit. 1205 1206 bits<9> addr; 1207 let Inst{7-0} = addr{7-0}; 1208 let Inst{9} = addr{8}; // Sign bit 1209 1210 bits<4> Rt; 1211 bits<4> Rn; 1212 let Inst{15-12} = Rt{3-0}; 1213 let Inst{19-16} = Rn{3-0}; 1214} 1215 1216// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. 1217class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> { 1218 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T]; 1219} 1220 1221// T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode. 1222class T1Pat<dag pattern, dag result> : Pat<pattern, result> { 1223 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 1224} 1225 1226// T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode. 1227class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> { 1228 list<Predicate> Predicates = [IsThumb2, HasV6T2]; 1229} 1230 1231// T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode. 1232class T2Pat<dag pattern, dag result> : Pat<pattern, result> { 1233 list<Predicate> Predicates = [IsThumb2]; 1234} 1235 1236//===----------------------------------------------------------------------===// 1237 1238//===----------------------------------------------------------------------===// 1239// ARM VFP Instruction templates. 1240// 1241 1242// Almost all VFP instructions are predicable. 1243class VFPI<dag oops, dag iops, AddrMode am, int sz, 1244 IndexMode im, Format f, InstrItinClass itin, 1245 string opc, string asm, string cstr, list<dag> pattern> 1246 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1247 bits<4> p; 1248 let Inst{31-28} = p; 1249 let OutOperandList = oops; 1250 let InOperandList = !con(iops, (ins pred:$p)); 1251 let AsmString = !strconcat(opc, "${p}", asm); 1252 let Pattern = pattern; 1253 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1254 list<Predicate> Predicates = [HasVFP2]; 1255} 1256 1257// Special cases 1258class VFPXI<dag oops, dag iops, AddrMode am, int sz, 1259 IndexMode im, Format f, InstrItinClass itin, 1260 string asm, string cstr, list<dag> pattern> 1261 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> { 1262 bits<4> p; 1263 let Inst{31-28} = p; 1264 let OutOperandList = oops; 1265 let InOperandList = iops; 1266 let AsmString = asm; 1267 let Pattern = pattern; 1268 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1269 list<Predicate> Predicates = [HasVFP2]; 1270} 1271 1272class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin, 1273 string opc, string asm, list<dag> pattern> 1274 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin, 1275 opc, asm, "", pattern> { 1276 let PostEncoderMethod = "VFPThumb2PostEncoder"; 1277} 1278 1279// ARM VFP addrmode5 loads and stores 1280class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1281 InstrItinClass itin, 1282 string opc, string asm, list<dag> pattern> 1283 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1284 VFPLdStFrm, itin, opc, asm, "", pattern> { 1285 // Instruction operands. 1286 bits<5> Dd; 1287 bits<13> addr; 1288 1289 // Encode instruction operands. 1290 let Inst{23} = addr{8}; // U (add = (U == '1')) 1291 let Inst{22} = Dd{4}; 1292 let Inst{19-16} = addr{12-9}; // Rn 1293 let Inst{15-12} = Dd{3-0}; 1294 let Inst{7-0} = addr{7-0}; // imm8 1295 1296 // TODO: Mark the instructions with the appropriate subtarget info. 1297 let Inst{27-24} = opcod1; 1298 let Inst{21-20} = opcod2; 1299 let Inst{11-9} = 0b101; 1300 let Inst{8} = 1; // Double precision 1301 1302 // Loads & stores operate on both NEON and VFP pipelines. 1303 let D = VFPNeonDomain; 1304} 1305 1306class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, 1307 InstrItinClass itin, 1308 string opc, string asm, list<dag> pattern> 1309 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone, 1310 VFPLdStFrm, itin, opc, asm, "", pattern> { 1311 // Instruction operands. 1312 bits<5> Sd; 1313 bits<13> addr; 1314 1315 // Encode instruction operands. 1316 let Inst{23} = addr{8}; // U (add = (U == '1')) 1317 let Inst{22} = Sd{0}; 1318 let Inst{19-16} = addr{12-9}; // Rn 1319 let Inst{15-12} = Sd{4-1}; 1320 let Inst{7-0} = addr{7-0}; // imm8 1321 1322 // TODO: Mark the instructions with the appropriate subtarget info. 1323 let Inst{27-24} = opcod1; 1324 let Inst{21-20} = opcod2; 1325 let Inst{11-9} = 0b101; 1326 let Inst{8} = 0; // Single precision 1327 1328 // Loads & stores operate on both NEON and VFP pipelines. 1329 let D = VFPNeonDomain; 1330} 1331 1332// VFP Load / store multiple pseudo instructions. 1333class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr, 1334 list<dag> pattern> 1335 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain, 1336 cstr, itin> { 1337 let OutOperandList = oops; 1338 let InOperandList = !con(iops, (ins pred:$p)); 1339 let Pattern = pattern; 1340 list<Predicate> Predicates = [HasVFP2]; 1341} 1342 1343// Load / store multiple 1344class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1345 string asm, string cstr, list<dag> pattern> 1346 : VFPXI<oops, iops, AddrMode4, 4, im, 1347 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1348 // Instruction operands. 1349 bits<4> Rn; 1350 bits<13> regs; 1351 1352 // Encode instruction operands. 1353 let Inst{19-16} = Rn; 1354 let Inst{22} = regs{12}; 1355 let Inst{15-12} = regs{11-8}; 1356 let Inst{7-0} = regs{7-0}; 1357 1358 // TODO: Mark the instructions with the appropriate subtarget info. 1359 let Inst{27-25} = 0b110; 1360 let Inst{11-9} = 0b101; 1361 let Inst{8} = 1; // Double precision 1362} 1363 1364class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin, 1365 string asm, string cstr, list<dag> pattern> 1366 : VFPXI<oops, iops, AddrMode4, 4, im, 1367 VFPLdStMulFrm, itin, asm, cstr, pattern> { 1368 // Instruction operands. 1369 bits<4> Rn; 1370 bits<13> regs; 1371 1372 // Encode instruction operands. 1373 let Inst{19-16} = Rn; 1374 let Inst{22} = regs{8}; 1375 let Inst{15-12} = regs{12-9}; 1376 let Inst{7-0} = regs{7-0}; 1377 1378 // TODO: Mark the instructions with the appropriate subtarget info. 1379 let Inst{27-25} = 0b110; 1380 let Inst{11-9} = 0b101; 1381 let Inst{8} = 0; // Single precision 1382} 1383 1384// Double precision, unary 1385class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1386 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1387 string asm, list<dag> pattern> 1388 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1389 // Instruction operands. 1390 bits<5> Dd; 1391 bits<5> Dm; 1392 1393 // Encode instruction operands. 1394 let Inst{3-0} = Dm{3-0}; 1395 let Inst{5} = Dm{4}; 1396 let Inst{15-12} = Dd{3-0}; 1397 let Inst{22} = Dd{4}; 1398 1399 let Inst{27-23} = opcod1; 1400 let Inst{21-20} = opcod2; 1401 let Inst{19-16} = opcod3; 1402 let Inst{11-9} = 0b101; 1403 let Inst{8} = 1; // Double precision 1404 let Inst{7-6} = opcod4; 1405 let Inst{4} = opcod5; 1406} 1407 1408// Double precision, binary 1409class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1410 dag iops, InstrItinClass itin, string opc, string asm, 1411 list<dag> pattern> 1412 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1413 // Instruction operands. 1414 bits<5> Dd; 1415 bits<5> Dn; 1416 bits<5> Dm; 1417 1418 // Encode instruction operands. 1419 let Inst{3-0} = Dm{3-0}; 1420 let Inst{5} = Dm{4}; 1421 let Inst{19-16} = Dn{3-0}; 1422 let Inst{7} = Dn{4}; 1423 let Inst{15-12} = Dd{3-0}; 1424 let Inst{22} = Dd{4}; 1425 1426 let Inst{27-23} = opcod1; 1427 let Inst{21-20} = opcod2; 1428 let Inst{11-9} = 0b101; 1429 let Inst{8} = 1; // Double precision 1430 let Inst{6} = op6; 1431 let Inst{4} = op4; 1432} 1433 1434// Single precision, unary 1435class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1436 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1437 string asm, list<dag> pattern> 1438 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> { 1439 // Instruction operands. 1440 bits<5> Sd; 1441 bits<5> Sm; 1442 1443 // Encode instruction operands. 1444 let Inst{3-0} = Sm{4-1}; 1445 let Inst{5} = Sm{0}; 1446 let Inst{15-12} = Sd{4-1}; 1447 let Inst{22} = Sd{0}; 1448 1449 let Inst{27-23} = opcod1; 1450 let Inst{21-20} = opcod2; 1451 let Inst{19-16} = opcod3; 1452 let Inst{11-9} = 0b101; 1453 let Inst{8} = 0; // Single precision 1454 let Inst{7-6} = opcod4; 1455 let Inst{4} = opcod5; 1456} 1457 1458// Single precision unary, if no NEON. Same as ASuI except not available if 1459// NEON is enabled. 1460class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, 1461 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, 1462 string asm, list<dag> pattern> 1463 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm, 1464 pattern> { 1465 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1466} 1467 1468// Single precision, binary 1469class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops, 1470 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1471 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> { 1472 // Instruction operands. 1473 bits<5> Sd; 1474 bits<5> Sn; 1475 bits<5> Sm; 1476 1477 // Encode instruction operands. 1478 let Inst{3-0} = Sm{4-1}; 1479 let Inst{5} = Sm{0}; 1480 let Inst{19-16} = Sn{4-1}; 1481 let Inst{7} = Sn{0}; 1482 let Inst{15-12} = Sd{4-1}; 1483 let Inst{22} = Sd{0}; 1484 1485 let Inst{27-23} = opcod1; 1486 let Inst{21-20} = opcod2; 1487 let Inst{11-9} = 0b101; 1488 let Inst{8} = 0; // Single precision 1489 let Inst{6} = op6; 1490 let Inst{4} = op4; 1491} 1492 1493// Single precision binary, if no NEON. Same as ASbI except not available if 1494// NEON is enabled. 1495class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, 1496 dag iops, InstrItinClass itin, string opc, string asm, 1497 list<dag> pattern> 1498 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> { 1499 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1500 1501 // Instruction operands. 1502 bits<5> Sd; 1503 bits<5> Sn; 1504 bits<5> Sm; 1505 1506 // Encode instruction operands. 1507 let Inst{3-0} = Sm{4-1}; 1508 let Inst{5} = Sm{0}; 1509 let Inst{19-16} = Sn{4-1}; 1510 let Inst{7} = Sn{0}; 1511 let Inst{15-12} = Sd{4-1}; 1512 let Inst{22} = Sd{0}; 1513} 1514 1515// VFP conversion instructions 1516class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1517 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1518 list<dag> pattern> 1519 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> { 1520 let Inst{27-23} = opcod1; 1521 let Inst{21-20} = opcod2; 1522 let Inst{19-16} = opcod3; 1523 let Inst{11-8} = opcod4; 1524 let Inst{6} = 1; 1525 let Inst{4} = 0; 1526} 1527 1528// VFP conversion between floating-point and fixed-point 1529class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5, 1530 dag oops, dag iops, InstrItinClass itin, string opc, string asm, 1531 list<dag> pattern> 1532 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { 1533 // size (fixed-point number): sx == 0 ? 16 : 32 1534 let Inst{7} = op5; // sx 1535} 1536 1537// VFP conversion instructions, if no NEON 1538class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4, 1539 dag oops, dag iops, InstrItinClass itin, 1540 string opc, string asm, list<dag> pattern> 1541 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1542 pattern> { 1543 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP]; 1544} 1545 1546class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f, 1547 InstrItinClass itin, 1548 string opc, string asm, list<dag> pattern> 1549 : VFPAI<oops, iops, f, itin, opc, asm, pattern> { 1550 let Inst{27-20} = opcod1; 1551 let Inst{11-8} = opcod2; 1552 let Inst{4} = 1; 1553} 1554 1555class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1556 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1557 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>; 1558 1559class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1560 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1561 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>; 1562 1563class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1564 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1565 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>; 1566 1567class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, 1568 InstrItinClass itin, string opc, string asm, list<dag> pattern> 1569 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>; 1570 1571//===----------------------------------------------------------------------===// 1572 1573//===----------------------------------------------------------------------===// 1574// ARM NEON Instruction templates. 1575// 1576 1577class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1578 InstrItinClass itin, string opc, string dt, string asm, string cstr, 1579 list<dag> pattern> 1580 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1581 let OutOperandList = oops; 1582 let InOperandList = !con(iops, (ins pred:$p)); 1583 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1584 let Pattern = pattern; 1585 list<Predicate> Predicates = [HasNEON]; 1586} 1587 1588// Same as NeonI except it does not have a "data type" specifier. 1589class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f, 1590 InstrItinClass itin, string opc, string asm, string cstr, 1591 list<dag> pattern> 1592 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> { 1593 let OutOperandList = oops; 1594 let InOperandList = !con(iops, (ins pred:$p)); 1595 let AsmString = !strconcat(opc, "${p}", "\t", asm); 1596 let Pattern = pattern; 1597 list<Predicate> Predicates = [HasNEON]; 1598} 1599 1600class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1601 dag oops, dag iops, InstrItinClass itin, 1602 string opc, string dt, string asm, string cstr, list<dag> pattern> 1603 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, 1604 cstr, pattern> { 1605 let Inst{31-24} = 0b11110100; 1606 let Inst{23} = op23; 1607 let Inst{21-20} = op21_20; 1608 let Inst{11-8} = op11_8; 1609 let Inst{7-4} = op7_4; 1610 1611 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; 1612 1613 bits<5> Vd; 1614 bits<6> Rn; 1615 bits<4> Rm; 1616 1617 let Inst{22} = Vd{4}; 1618 let Inst{15-12} = Vd{3-0}; 1619 let Inst{19-16} = Rn{3-0}; 1620 let Inst{3-0} = Rm{3-0}; 1621} 1622 1623class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, 1624 dag oops, dag iops, InstrItinClass itin, 1625 string opc, string dt, string asm, string cstr, list<dag> pattern> 1626 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc, 1627 dt, asm, cstr, pattern> { 1628 bits<3> lane; 1629} 1630 1631class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> 1632 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1633 itin> { 1634 let OutOperandList = oops; 1635 let InOperandList = !con(iops, (ins pred:$p)); 1636 list<Predicate> Predicates = [HasNEON]; 1637} 1638 1639class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr, 1640 list<dag> pattern> 1641 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr, 1642 itin> { 1643 let OutOperandList = oops; 1644 let InOperandList = !con(iops, (ins pred:$p)); 1645 let Pattern = pattern; 1646 list<Predicate> Predicates = [HasNEON]; 1647} 1648 1649class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, 1650 string opc, string dt, string asm, string cstr, list<dag> pattern> 1651 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, 1652 pattern> { 1653 let Inst{31-25} = 0b1111001; 1654 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1655} 1656 1657class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, 1658 string opc, string asm, string cstr, list<dag> pattern> 1659 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm, 1660 cstr, pattern> { 1661 let Inst{31-25} = 0b1111001; 1662 let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; 1663} 1664 1665// NEON "one register and a modified immediate" format. 1666class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6, 1667 bit op5, bit op4, 1668 dag oops, dag iops, InstrItinClass itin, 1669 string opc, string dt, string asm, string cstr, 1670 list<dag> pattern> 1671 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { 1672 let Inst{23} = op23; 1673 let Inst{21-19} = op21_19; 1674 let Inst{11-8} = op11_8; 1675 let Inst{7} = op7; 1676 let Inst{6} = op6; 1677 let Inst{5} = op5; 1678 let Inst{4} = op4; 1679 1680 // Instruction operands. 1681 bits<5> Vd; 1682 bits<13> SIMM; 1683 1684 let Inst{15-12} = Vd{3-0}; 1685 let Inst{22} = Vd{4}; 1686 let Inst{24} = SIMM{7}; 1687 let Inst{18-16} = SIMM{6-4}; 1688 let Inst{3-0} = SIMM{3-0}; 1689} 1690 1691// NEON 2 vector register format. 1692class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1693 bits<5> op11_7, bit op6, bit op4, 1694 dag oops, dag iops, InstrItinClass itin, 1695 string opc, string dt, string asm, string cstr, list<dag> pattern> 1696 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> { 1697 let Inst{24-23} = op24_23; 1698 let Inst{21-20} = op21_20; 1699 let Inst{19-18} = op19_18; 1700 let Inst{17-16} = op17_16; 1701 let Inst{11-7} = op11_7; 1702 let Inst{6} = op6; 1703 let Inst{4} = op4; 1704 1705 // Instruction operands. 1706 bits<5> Vd; 1707 bits<5> Vm; 1708 1709 let Inst{15-12} = Vd{3-0}; 1710 let Inst{22} = Vd{4}; 1711 let Inst{3-0} = Vm{3-0}; 1712 let Inst{5} = Vm{4}; 1713} 1714 1715// Same as N2V except it doesn't have a datatype suffix. 1716class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, 1717 bits<5> op11_7, bit op6, bit op4, 1718 dag oops, dag iops, InstrItinClass itin, 1719 string opc, string asm, string cstr, list<dag> pattern> 1720 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> { 1721 let Inst{24-23} = op24_23; 1722 let Inst{21-20} = op21_20; 1723 let Inst{19-18} = op19_18; 1724 let Inst{17-16} = op17_16; 1725 let Inst{11-7} = op11_7; 1726 let Inst{6} = op6; 1727 let Inst{4} = op4; 1728 1729 // Instruction operands. 1730 bits<5> Vd; 1731 bits<5> Vm; 1732 1733 let Inst{15-12} = Vd{3-0}; 1734 let Inst{22} = Vd{4}; 1735 let Inst{3-0} = Vm{3-0}; 1736 let Inst{5} = Vm{4}; 1737} 1738 1739// NEON 2 vector register with immediate. 1740class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 1741 dag oops, dag iops, Format f, InstrItinClass itin, 1742 string opc, string dt, string asm, string cstr, list<dag> pattern> 1743 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1744 let Inst{24} = op24; 1745 let Inst{23} = op23; 1746 let Inst{11-8} = op11_8; 1747 let Inst{7} = op7; 1748 let Inst{6} = op6; 1749 let Inst{4} = op4; 1750 1751 // Instruction operands. 1752 bits<5> Vd; 1753 bits<5> Vm; 1754 bits<6> SIMM; 1755 1756 let Inst{15-12} = Vd{3-0}; 1757 let Inst{22} = Vd{4}; 1758 let Inst{3-0} = Vm{3-0}; 1759 let Inst{5} = Vm{4}; 1760 let Inst{21-16} = SIMM{5-0}; 1761} 1762 1763// NEON 3 vector register format. 1764 1765class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1766 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1767 string opc, string dt, string asm, string cstr, 1768 list<dag> pattern> 1769 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1770 let Inst{24} = op24; 1771 let Inst{23} = op23; 1772 let Inst{21-20} = op21_20; 1773 let Inst{11-8} = op11_8; 1774 let Inst{6} = op6; 1775 let Inst{4} = op4; 1776} 1777 1778class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, 1779 dag oops, dag iops, Format f, InstrItinClass itin, 1780 string opc, string dt, string asm, string cstr, list<dag> pattern> 1781 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1782 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1783 1784 // Instruction operands. 1785 bits<5> Vd; 1786 bits<5> Vn; 1787 bits<5> Vm; 1788 1789 let Inst{15-12} = Vd{3-0}; 1790 let Inst{22} = Vd{4}; 1791 let Inst{19-16} = Vn{3-0}; 1792 let Inst{7} = Vn{4}; 1793 let Inst{3-0} = Vm{3-0}; 1794 let Inst{5} = Vm{4}; 1795} 1796 1797class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1798 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1799 string opc, string dt, string asm, string cstr, 1800 list<dag> pattern> 1801 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1802 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1803 1804 // Instruction operands. 1805 bits<5> Vd; 1806 bits<5> Vn; 1807 bits<5> Vm; 1808 bit lane; 1809 1810 let Inst{15-12} = Vd{3-0}; 1811 let Inst{22} = Vd{4}; 1812 let Inst{19-16} = Vn{3-0}; 1813 let Inst{7} = Vn{4}; 1814 let Inst{3-0} = Vm{3-0}; 1815 let Inst{5} = lane; 1816} 1817 1818class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1819 bit op4, dag oops, dag iops, Format f, InstrItinClass itin, 1820 string opc, string dt, string asm, string cstr, 1821 list<dag> pattern> 1822 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4, 1823 oops, iops, f, itin, opc, dt, asm, cstr, pattern> { 1824 1825 // Instruction operands. 1826 bits<5> Vd; 1827 bits<5> Vn; 1828 bits<5> Vm; 1829 bits<2> lane; 1830 1831 let Inst{15-12} = Vd{3-0}; 1832 let Inst{22} = Vd{4}; 1833 let Inst{19-16} = Vn{3-0}; 1834 let Inst{7} = Vn{4}; 1835 let Inst{2-0} = Vm{2-0}; 1836 let Inst{5} = lane{1}; 1837 let Inst{3} = lane{0}; 1838} 1839 1840// Same as N3V except it doesn't have a data type suffix. 1841class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, 1842 bit op4, 1843 dag oops, dag iops, Format f, InstrItinClass itin, 1844 string opc, string asm, string cstr, list<dag> pattern> 1845 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { 1846 let Inst{24} = op24; 1847 let Inst{23} = op23; 1848 let Inst{21-20} = op21_20; 1849 let Inst{11-8} = op11_8; 1850 let Inst{6} = op6; 1851 let Inst{4} = op4; 1852 1853 // Instruction operands. 1854 bits<5> Vd; 1855 bits<5> Vn; 1856 bits<5> Vm; 1857 1858 let Inst{15-12} = Vd{3-0}; 1859 let Inst{22} = Vd{4}; 1860 let Inst{19-16} = Vn{3-0}; 1861 let Inst{7} = Vn{4}; 1862 let Inst{3-0} = Vm{3-0}; 1863 let Inst{5} = Vm{4}; 1864} 1865 1866// NEON VMOVs between scalar and core registers. 1867class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1868 dag oops, dag iops, Format f, InstrItinClass itin, 1869 string opc, string dt, string asm, list<dag> pattern> 1870 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain, 1871 "", itin> { 1872 let Inst{27-20} = opcod1; 1873 let Inst{11-8} = opcod2; 1874 let Inst{6-5} = opcod3; 1875 let Inst{4} = 1; 1876 // A8.6.303, A8.6.328, A8.6.329 1877 let Inst{3-0} = 0b0000; 1878 1879 let OutOperandList = oops; 1880 let InOperandList = !con(iops, (ins pred:$p)); 1881 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); 1882 let Pattern = pattern; 1883 list<Predicate> Predicates = [HasNEON]; 1884 1885 let PostEncoderMethod = "NEONThumb2DupPostEncoder"; 1886 1887 bits<5> V; 1888 bits<4> R; 1889 bits<4> p; 1890 bits<4> lane; 1891 1892 let Inst{31-28} = p{3-0}; 1893 let Inst{7} = V{4}; 1894 let Inst{19-16} = V{3-0}; 1895 let Inst{15-12} = R{3-0}; 1896} 1897class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1898 dag oops, dag iops, InstrItinClass itin, 1899 string opc, string dt, string asm, list<dag> pattern> 1900 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin, 1901 opc, dt, asm, pattern>; 1902class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1903 dag oops, dag iops, InstrItinClass itin, 1904 string opc, string dt, string asm, list<dag> pattern> 1905 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin, 1906 opc, dt, asm, pattern>; 1907class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, 1908 dag oops, dag iops, InstrItinClass itin, 1909 string opc, string dt, string asm, list<dag> pattern> 1910 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin, 1911 opc, dt, asm, pattern>; 1912 1913// Vector Duplicate Lane (from scalar to all elements) 1914class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops, 1915 InstrItinClass itin, string opc, string dt, string asm, 1916 list<dag> pattern> 1917 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> { 1918 let Inst{24-23} = 0b11; 1919 let Inst{21-20} = 0b11; 1920 let Inst{19-16} = op19_16; 1921 let Inst{11-7} = 0b11000; 1922 let Inst{6} = op6; 1923 let Inst{4} = 0; 1924 1925 bits<5> Vd; 1926 bits<5> Vm; 1927 bits<4> lane; 1928 1929 let Inst{22} = Vd{4}; 1930 let Inst{15-12} = Vd{3-0}; 1931 let Inst{5} = Vm{4}; 1932 let Inst{3-0} = Vm{3-0}; 1933} 1934 1935// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON 1936// for single-precision FP. 1937class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> { 1938 list<Predicate> Predicates = [HasNEON,UseNEONForFP]; 1939} 1940